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added enum masks and unknown regs

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This commit is contained in:
Patrick Mackinlay 2017-06-20 10:43:50 +07:00
parent ef6cc1eb4a
commit 5f6d2c5e53
2 changed files with 23 additions and 0 deletions
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3
src/mame/machine/interpro_srarb.cpp
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@ -25,6 +25,9 @@ DEVICE_ADDRESS_MAP_START(map, 32, interpro_srarb_device)
AM_RANGE(0x14, 0x17) AM_READWRITE(errdomhi_r, errdomhi_w) AM_RANGE(0x14, 0x17) AM_READWRITE(errdomhi_r, errdomhi_w)
AM_RANGE(0x18, 0x1b) AM_READWRITE(tmctrl_r, tmctrl_w) AM_RANGE(0x18, 0x1b) AM_READWRITE(tmctrl_r, tmctrl_w)
AM_RANGE(0x1c, 0x1f) AM_READWRITE8(unknown0_r, unknown0_w, 0x0000ff00) // boot code writes 0x10
AM_RANGE(0x20, 0x23) AM_READWRITE8(unknown1_r, unknown1_w, 0x0000ff00) // boot code writes 0x07
AM_RANGE(0x24, 0x27) AM_READWRITE(tmsrnem_r, tmsrnem_w) AM_RANGE(0x24, 0x27) AM_READWRITE(tmsrnem_r, tmsrnem_w)
AM_RANGE(0x28, 0x2b) AM_READWRITE(tmsrhog_r, tmsrhog_w) AM_RANGE(0x28, 0x2b) AM_READWRITE(tmsrhog_r, tmsrhog_w)
AM_RANGE(0x2c, 0x2f) AM_READWRITE(tmscale_r, tmscale_w) AM_RANGE(0x2c, 0x2f) AM_READWRITE(tmscale_r, tmscale_w)

20
src/mame/machine/interpro_srarb.h
View File

@ -15,6 +15,12 @@ public:
DECLARE_READ32_MEMBER(sdepid_r) { return sdepid; } DECLARE_READ32_MEMBER(sdepid_r) { return sdepid; }
DECLARE_WRITE32_MEMBER(sdepid_w) { sdepid = data; } DECLARE_WRITE32_MEMBER(sdepid_w) { sdepid = data; }
enum snapid_mask
{
SNAPID_GRANT = 0x0000000f,
SNAPID_HOGLOCK = 0x000000f0
};
DECLARE_READ32_MEMBER(snapid_r) { return snapid; } DECLARE_READ32_MEMBER(snapid_r) { return snapid; }
DECLARE_WRITE32_MEMBER(snapid_w) { snapid = data; } DECLARE_WRITE32_MEMBER(snapid_w) { snapid = data; }
DECLARE_READ32_MEMBER(prilo_r) { return prilo; } DECLARE_READ32_MEMBER(prilo_r) { return prilo; }
@ -27,8 +33,20 @@ public:
DECLARE_READ32_MEMBER(errdomhi_r) { return errdomhi; } DECLARE_READ32_MEMBER(errdomhi_r) { return errdomhi; }
DECLARE_WRITE32_MEMBER(errdomhi_w) { errdomhi = data; } DECLARE_WRITE32_MEMBER(errdomhi_w) { errdomhi = data; }
enum tmctrl_mask
{
TMCTRL_UNUSED = 0x00000007,
TMCTRL_ENNEM = 0x00000008,
TMCTRL_ENHOG = 0x00000010
};
DECLARE_READ32_MEMBER(tmctrl_r) { return tmctrl; } DECLARE_READ32_MEMBER(tmctrl_r) { return tmctrl; }
DECLARE_WRITE32_MEMBER(tmctrl_w) { tmctrl = data; } DECLARE_WRITE32_MEMBER(tmctrl_w) { tmctrl = data; }
DECLARE_READ8_MEMBER(unknown0_r) { return unknown0; }
DECLARE_WRITE8_MEMBER(unknown0_w) { unknown0 = data; }
DECLARE_READ8_MEMBER(unknown1_r) { return unknown1; }
DECLARE_WRITE8_MEMBER(unknown1_w) { unknown1 = data; }
DECLARE_READ32_MEMBER(tmsrnem_r) { return tmsrnem; } DECLARE_READ32_MEMBER(tmsrnem_r) { return tmsrnem; }
DECLARE_WRITE32_MEMBER(tmsrnem_w) { tmsrnem = data; } DECLARE_WRITE32_MEMBER(tmsrnem_w) { tmsrnem = data; }
DECLARE_READ32_MEMBER(tmsrhog_r) { return tmsrhog; } DECLARE_READ32_MEMBER(tmsrhog_r) { return tmsrhog; }
@ -44,6 +62,8 @@ private:
u32 sdepid, snapid, prilo, prihi; u32 sdepid, snapid, prilo, prihi;
u32 errdomlo, errdomhi; u32 errdomlo, errdomhi;
u32 tmctrl, tmsrnem, tmsrhog, tmscale; u32 tmctrl, tmsrnem, tmsrhog, tmscale;
u8 unknown0, unknown1;
}; };
// device type definition // device type definition