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Use emumem.h defines whenever possible

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This commit is contained in:
Giuseppe Gorgoglione 2016-08-11 02:15:50 +02:00
parent 2676e800e6
commit 5f912b42f6
33 changed files with 355 additions and 355 deletions
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6
src/mame/audio/hng64.cpp
View File

@ -110,7 +110,7 @@ READ32_MEMBER(hng64_state::hng64_soundram_r)
WRITE32_MEMBER( hng64_state::hng64_soundcpu_enable_w )
{
if (mem_mask&0xffff0000)
if (ACCESSING_BITS_16_31)
{
int cmd = data >> 16;
// I guess it's only one of the bits, the commands are inverse of each other
@ -132,9 +132,9 @@ WRITE32_MEMBER( hng64_state::hng64_soundcpu_enable_w )
}
}
if (mem_mask&0x0000ffff)
if (ACCESSING_BITS_0_15)
{
logerror("unknown hng64_soundcpu_enable_w %08x %08x\n", data, mem_mask);
logerror("unknown hng64_soundcpu_enable_w %08x %08x\n", data, mem_mask);
}
}

16
src/mame/drivers/astrafr.cpp
View File

@ -170,10 +170,10 @@ WRITE32_MEMBER(astrafr_state::astrafr_mem_w)
case 3:
address &= 0xfffff;
if (mem_mask&0xff000000) astra_fgpa_w(space, address+0, data >> 24);
if (mem_mask&0x00ff0000) astra_fgpa_w(space, address+1, data >> 16);
if (mem_mask&0x0000ff00) astra_fgpa_w(space, address+2, data >> 8);
if (mem_mask&0x000000ff) astra_fgpa_w(space, address+3, data >> 0);
if (ACCESSING_BITS_24_31) astra_fgpa_w(space, address+0, data >> 24);
if (ACCESSING_BITS_16_23) astra_fgpa_w(space, address+1, data >> 16);
if (ACCESSING_BITS_8_15) astra_fgpa_w(space, address+2, data >> 8);
if (ACCESSING_BITS_0_7) astra_fgpa_w(space, address+3, data >> 0);
break;
case 2:
@ -225,10 +225,10 @@ WRITE32_MEMBER(astrafr_state::astrafr_slave_mem_w)
case 3:
address &= 0xfffff;
if (mem_mask&0xff000000) astra_fgpa_slave_w(space, address+0, data >> 24);
if (mem_mask&0x00ff0000) astra_fgpa_slave_w(space, address+1, data >> 16);
if (mem_mask&0x0000ff00) astra_fgpa_slave_w(space, address+2, data >> 8);
if (mem_mask&0x000000ff) astra_fgpa_slave_w(space, address+3, data >> 0);
if (ACCESSING_BITS_24_31) astra_fgpa_slave_w(space, address+0, data >> 24);
if (ACCESSING_BITS_16_23) astra_fgpa_slave_w(space, address+1, data >> 16);
if (ACCESSING_BITS_8_15) astra_fgpa_slave_w(space, address+2, data >> 8);
if (ACCESSING_BITS_0_7) astra_fgpa_slave_w(space, address+3, data >> 0);
break;
case 2:

12
src/mame/drivers/bfm_sc4.cpp
View File

@ -205,12 +205,12 @@ READ16_MEMBER(sc4_state::sc4_mem_r)
if (addr < 0x0080)
{
UINT16 retvalue = 0x0000;
if (mem_mask&0xff00)
if (ACCESSING_BITS_8_15)
{
logerror("mem_mask&0xff00 unhandled\n");
}
if (mem_mask&0x00ff)
if (ACCESSING_BITS_0_7)
{
retvalue = read_input_matrix((addr & 0x00f0)>>4);
}
@ -381,12 +381,12 @@ WRITE16_MEMBER(sc4_state::sc4_mem_w)
if (addr < 0x0200)
{
if (mem_mask&0xff00)
if (ACCESSING_BITS_8_15)
{
logerror("lamp write mem_mask&0xff00 unhandled\n");
}
if (mem_mask&0x00ff)
if (ACCESSING_BITS_0_7)
{ // lamps
mux_output_w(space, (addr & 0x01f0)>>4, data);
}
@ -394,12 +394,12 @@ WRITE16_MEMBER(sc4_state::sc4_mem_w)
}
else if ((addr >= 0x1000) && (addr < 0x1200))
{
if (mem_mask&0xff00)
if (ACCESSING_BITS_8_15)
{
logerror("lamp write mem_mask&0xff00 unhandled\n");
}
if (mem_mask&0x00ff)
if (ACCESSING_BITS_0_7)
{ // lamps
mux_output2_w(space, (addr & 0x01f0)>>4, data);
}

2
src/mame/drivers/bfm_sc5.cpp
View File

@ -28,7 +28,7 @@ WRITE16_MEMBER( bfm_sc5_state::sc5_duart_w )
// clearly a duart of some kind, write patterns are the same as SC4 games
// printf("%s: duart_w %1x %04x %04x\n", machine().describe_context(), offset, data, mem_mask);
if (mem_mask &0xff00)
if (ACCESSING_BITS_8_15)
{
m_duart->write(space,offset,(data>>8)&0x00ff);
}

4
src/mame/drivers/cb2001.cpp
View File

@ -447,7 +447,7 @@ UINT32 cb2001_state::screen_update_cb2001(screen_device &screen, bitmap_rgb32 &b
is being executed incorrectly */
WRITE16_MEMBER(cb2001_state::cb2001_vidctrl_w)
{
if (mem_mask&0xff00) // video control?
if (ACCESSING_BITS_8_15) // video control?
{
printf("cb2001_vidctrl_w %04x %04x\n", data, mem_mask);
m_videobank = (data & 0x0800)>>11;
@ -458,7 +458,7 @@ WRITE16_MEMBER(cb2001_state::cb2001_vidctrl_w)
WRITE16_MEMBER(cb2001_state::cb2001_vidctrl2_w)
{
if (mem_mask&0xff00) // video control?
if (ACCESSING_BITS_8_15) // video control?
{
printf("cb2001_vidctrl2_w %04x %04x\n", data, mem_mask); // i think this switches to 'reels' mode
m_videomode = (data>>8) & 0x03; // which bit??

2
src/mame/drivers/cobra.cpp
View File

@ -1730,7 +1730,7 @@ READ32_MEMBER(cobra_state::sub_unk1_r)
WRITE32_MEMBER(cobra_state::sub_unk1_w)
{
/*
if (!(mem_mask & 0xff000000))
if (!ACCESSING_BITS_24_31)
{
printf("%02X", data >> 24);
ucount++;

6
src/mame/drivers/crystal.cpp
View File

@ -318,7 +318,7 @@ READ32_MEMBER(crystal_state::FlipCount_r)
WRITE32_MEMBER(crystal_state::FlipCount_w)
{
if (mem_mask & 0x00ff0000)
if (ACCESSING_BITS_16_23)
{
int fc = (data >> 16) & 0xff;
if (fc == 1)
@ -351,14 +351,14 @@ WRITE32_MEMBER(crystal_state::IntAck_w)
{
UINT32 IntPend = space.read_dword(0x01800c0c);
if (mem_mask & 0xff)
if (ACCESSING_BITS_0_7)
{
IntPend &= ~(1 << (data & 0x1f));
space.write_dword(0x01800c0c, IntPend);
if (!IntPend)
m_maincpu->set_input_line(SE3208_INT, CLEAR_LINE);
}
if (mem_mask & 0xff00)
if (ACCESSING_BITS_8_15)
m_IntHigh = (data >> 8) & 7;
}

4
src/mame/drivers/deco32.cpp
View File

@ -808,7 +808,7 @@ READ32_MEMBER( deco32_state::fghthist_protection_region_0_146_r )
{
UINT32 retdata = 0x0000ffff;
if (mem_mask & 0xffff0000)
if (ACCESSING_BITS_16_31)
{
mem_mask >>=16;
@ -826,7 +826,7 @@ READ32_MEMBER( deco32_state::fghthist_protection_region_0_146_r )
WRITE32_MEMBER( deco32_state::fghthist_protection_region_0_146_w )
{
if (mem_mask & 0xffff0000)
if (ACCESSING_BITS_16_31)
{
data >>=16;
mem_mask >>=16;

8
src/mame/drivers/deco_mlc.cpp
View File

@ -241,12 +241,12 @@ READ32_MEMBER( deco_mlc_state::mlc_spriteram_r )
{
UINT32 retdata = 0;
if (mem_mask & 0xffff0000)
if (ACCESSING_BITS_16_31)
{
retdata |= 0xffff0000;
}
if (mem_mask & 0x0000ffff)
if (ACCESSING_BITS_0_15)
{
retdata |= m_mlc_spriteram[offset];
}
@ -257,11 +257,11 @@ READ32_MEMBER( deco_mlc_state::mlc_spriteram_r )
WRITE32_MEMBER( deco_mlc_state::mlc_spriteram_w )
{
if (mem_mask & 0xffff0000)
if (ACCESSING_BITS_16_31)
{
}
if (mem_mask & 0x0000ffff)
if (ACCESSING_BITS_0_15)
{
data &=0x0000ffff;
COMBINE_DATA(&m_mlc_spriteram[offset]);

0
src/mame/drivers/divebomb.cpp Executable file → Normal file
View File

2
src/mame/drivers/dreambal.cpp
View File

@ -64,7 +64,7 @@ public:
logerror("dreambal_eeprom_w unhandled data %04x %04x\n",data&0x0fff8, mem_mask);
}
if (mem_mask&0x00ff)
if (ACCESSING_BITS_0_7)
{
m_eeprom->clk_write(data &0x2 ? ASSERT_LINE : CLEAR_LINE);
m_eeprom->di_write(data &0x1);

4
src/mame/drivers/gambl186.cpp
View File

@ -347,8 +347,8 @@ WRITE16_MEMBER(gambl186_state::upd_w)
// m_upd7759->reset_w(0);
// m_upd7759->reset_w(1);
// if (mem_mask&0x00ff) m_upd7759->port_w(space, 0, data & 0xff);
// if (mem_mask&0xff00) m_upd7759->port_w(space, 0, (data >> 8) & 0xff);
// if (ACCESSING_BITS_0_7) m_upd7759->port_w(space, 0, data & 0xff);
// if (ACCESSING_BITS_8_15) m_upd7759->port_w(space, 0, (data >> 8) & 0xff);
data = (data >> 8);
popmessage("sample index: %02x", data);

428
src/mame/drivers/gba.cpp
View File

File diff suppressed because it is too large Load Diff

2
src/mame/drivers/glass.cpp
View File

@ -388,7 +388,7 @@ WRITE16_MEMBER( glass_state::mainram_w )
{
// printf("%06x write %06x - %04x %04x\n", pc, (offset*2 + 0xfec000), data, mem_mask);
// several checks write here then expect it to appear mirrored, might be some kind of command + command ack
if (mem_mask & 0xff00) // sometimes mask 0xff00, but not in cases which poll for change
if (ACCESSING_BITS_8_15) // sometimes mask 0xff00, but not in cases which poll for change
{
mem_mask = 0x00ff;
data >>=8;

16
src/mame/drivers/juicebox.cpp
View File

@ -223,10 +223,10 @@ WRITE32_MEMBER(juicebox_state::s3c44b0_gpio_port_w)
READ32_MEMBER(juicebox_state::juicebox_nand_r)
{
UINT32 data = 0;
if (mem_mask & 0x000000FF) data = data | (smc_read() << 0);
if (mem_mask & 0x0000FF00) data = data | (smc_read() << 8);
if (mem_mask & 0x00FF0000) data = data | (smc_read() << 16);
if (mem_mask & 0xFF000000) data = data | (smc_read() << 24);
if (ACCESSING_BITS_0_7) data = data | (smc_read() << 0);
if (ACCESSING_BITS_8_15) data = data | (smc_read() << 8);
if (ACCESSING_BITS_16_23) data = data | (smc_read() << 16);
if (ACCESSING_BITS_24_31) data = data | (smc_read() << 24);
verboselog( 5, "juicebox_nand_r %08X %08X %08X\n", offset, mem_mask, data);
return data;
}
@ -234,10 +234,10 @@ READ32_MEMBER(juicebox_state::juicebox_nand_r)
WRITE32_MEMBER(juicebox_state::juicebox_nand_w)
{
verboselog( 5, "juicebox_nand_w %08X %08X %08X\n", offset, mem_mask, data);
if (mem_mask & 0x000000FF) smc_write((data >> 0) & 0xFF);
if (mem_mask & 0x0000FF00) smc_write((data >> 8) & 0xFF);
if (mem_mask & 0x00FF0000) smc_write((data >> 16) & 0xFF);
if (mem_mask & 0xFF000000) smc_write((data >> 24) & 0xFF);
if (ACCESSING_BITS_0_7) smc_write((data >> 0) & 0xFF);
if (ACCESSING_BITS_8_15) smc_write((data >> 8) & 0xFF);
if (ACCESSING_BITS_16_23) smc_write((data >> 16) & 0xFF);
if (ACCESSING_BITS_24_31) smc_write((data >> 24) & 0xFF);
}
// I2S

16
src/mame/drivers/mpu5.cpp
View File

@ -121,10 +121,10 @@ READ8_MEMBER(mpu5_state::asic_r8)
READ32_MEMBER(mpu5_state::asic_r32)
{
UINT32 retdata = 0;
if (mem_mask&0xff000000) retdata |= asic_r8(space,(offset*4)+0) <<24;
if (mem_mask&0x00ff0000) retdata |= asic_r8(space,(offset*4)+1) <<16;
if (mem_mask&0x0000ff00) retdata |= asic_r8(space,(offset*4)+2) <<8;
if (mem_mask&0x000000ff) retdata |= asic_r8(space,(offset*4)+3) <<0;
if (ACCESSING_BITS_24_31) retdata |= asic_r8(space,(offset*4)+0) <<24;
if (ACCESSING_BITS_16_23) retdata |= asic_r8(space,(offset*4)+1) <<16;
if (ACCESSING_BITS_8_15) retdata |= asic_r8(space,(offset*4)+2) <<8;
if (ACCESSING_BITS_0_7) retdata |= asic_r8(space,(offset*4)+3) <<0;
return retdata;
}
@ -255,10 +255,10 @@ WRITE8_MEMBER(mpu5_state::asic_w8)
WRITE32_MEMBER(mpu5_state::asic_w32)
{
if (mem_mask&0xff000000) asic_w8(space,(offset*4)+0, (data>>24)&0xff);
if (mem_mask&0x00ff0000) asic_w8(space,(offset*4)+1, (data>>16)&0xff);
if (mem_mask&0x0000ff00) asic_w8(space,(offset*4)+2, (data>>8) &0xff);
if (mem_mask&0x000000ff) asic_w8(space,(offset*4)+3, (data>>0) &0xff);
if (ACCESSING_BITS_24_31) asic_w8(space,(offset*4)+0, (data>>24)&0xff);
if (ACCESSING_BITS_16_23) asic_w8(space,(offset*4)+1, (data>>16)&0xff);
if (ACCESSING_BITS_8_15) asic_w8(space,(offset*4)+2, (data>>8) &0xff);
if (ACCESSING_BITS_0_7) asic_w8(space,(offset*4)+3, (data>>0) &0xff);
}

2
src/mame/drivers/namcos22.cpp
View File

@ -1582,7 +1582,7 @@ READ32_MEMBER(namcos22_state::namcos22_dspram_r)
WRITE32_MEMBER(namcos22_state::namcos22_dspram_w)
{
if (mem_mask & 0x00ff0000)
if (ACCESSING_BITS_16_23)
{
// only d0-23 are connected
mem_mask |= 0xff000000;

78
src/mame/drivers/ngen.cpp
View File

@ -283,32 +283,32 @@ WRITE16_MEMBER(ngen_state::peripheral_w)
case 0x0d:
case 0x0e:
case 0x0f:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_dmac->write(space,offset,data & 0xff);
break;
case 0x80: // DMA page offset?
case 0x81:
case 0x82:
case 0x83:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_dma_offset[offset-0x80] = data & 0xff;
break;
case 0xc0: // X-Bus modules reset
m_xbus_current = 0;
break;
case 0x10c:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_pic->write(space,0,data & 0xff);
break;
case 0x10d:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_pic->write(space,1,data & 0xff);
break;
case 0x110:
case 0x111:
case 0x112:
case 0x113:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_pit->write(space,offset-0x110,data & 0xff);
break;
case 0x141:
@ -316,19 +316,19 @@ WRITE16_MEMBER(ngen_state::peripheral_w)
COMBINE_DATA(&m_periph141);
break;
case 0x144:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_crtc->address_w(space,0,data & 0xff);
break;
case 0x145:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_crtc->register_w(space,0,data & 0xff);
break;
case 0x146:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_viduart->data_w(space,0,data & 0xff);
break;
case 0x147:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_viduart->control_w(space,0,data & 0xff);
break;
case 0x1a0: // serial?
@ -360,7 +360,7 @@ READ16_MEMBER(ngen_state::peripheral_r)
case 0x0d:
case 0x0e:
case 0x0f:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_dmac->read(space,offset);
logerror("DMA read offset %04x mask %04x returning %04x\n",offset,mem_mask,ret);
break;
@ -368,42 +368,42 @@ READ16_MEMBER(ngen_state::peripheral_r)
case 0x81:
case 0x82:
case 0x83:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_dma_offset[offset-0x80] & 0xff;
break;
case 0x10c:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_pic->read(space,0);
break;
case 0x10d:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_pic->read(space,1);
break;
case 0x110:
case 0x111:
case 0x112:
case 0x113:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_pit->read(space,offset-0x110);
break;
case 0x141:
ret = m_periph141;
break;
case 0x144:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_crtc->status_r(space,0);
break;
case 0x145:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_crtc->register_r(space,0);
break;
case 0x146:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_viduart->data_r(space,0);
break;
case 0x147: // keyboard UART
// expects bit 0 to be set (UART transmit ready)
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_viduart->status_r(space,0);
break;
case 0x1a0: // I/O control register?
@ -478,11 +478,11 @@ WRITE16_MEMBER(ngen_state::hfd_w)
case 0x00:
case 0x01:
case 0x02:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_fdc->write(space,offset,data & 0xff);
break;
case 0x03:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
{
m_fdc->write(space,offset,data & 0xff);
m_fdc_timer->write_clk0(1);
@ -490,22 +490,22 @@ WRITE16_MEMBER(ngen_state::hfd_w)
}
break;
case 0x04:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
fdc_control_w(space,0,data & 0xff);
break;
case 0x05:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
hdc_control_w(space,0,data & 0xff);
break;
case 0x07:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
disk_addr_ext(space,0,data & 0xff);
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_fdc_timer->write(space,offset-0x08,data & 0xff);
break;
case 0x10:
@ -516,7 +516,7 @@ WRITE16_MEMBER(ngen_state::hfd_w)
case 0x15:
case 0x16:
case 0x17:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_hdc->write(space,offset-0x10,data & 0xff);
logerror("WD1010 register %i write %02x mask %04x\n",offset-0x10,data & 0xff,mem_mask);
break;
@ -524,7 +524,7 @@ WRITE16_MEMBER(ngen_state::hfd_w)
case 0x19:
case 0x1a:
case 0x1b:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_hdc_timer->write(space,offset-0x18,data & 0xff);
break;
}
@ -539,11 +539,11 @@ READ16_MEMBER(ngen_state::hfd_r)
case 0x00:
case 0x01:
case 0x02:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_fdc->read(space,offset);
break;
case 0x03:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
{
ret = m_fdc->read(space,offset);
m_fdc_timer->write_clk0(1);
@ -554,7 +554,7 @@ READ16_MEMBER(ngen_state::hfd_r)
case 0x09:
case 0x0a:
case 0x0b:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_fdc_timer->read(space,offset-0x08);
break;
case 0x10:
@ -565,7 +565,7 @@ READ16_MEMBER(ngen_state::hfd_r)
case 0x15:
case 0x16:
case 0x17:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_hdc->read(space,offset-0x10);
logerror("WD1010 register %i read, mask %04x\n",offset-0x10,mem_mask);
break;
@ -573,7 +573,7 @@ READ16_MEMBER(ngen_state::hfd_r)
case 0x19:
case 0x1a:
case 0x1b:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_hdc_timer->read(space,offset-0x18);
break;
}
@ -769,12 +769,12 @@ READ16_MEMBER( ngen_state::b38_keyboard_r )
switch(offset)
{
case 0:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_viduart->data_r(space,0);
break;
case 1: // keyboard UART
// expects bit 0 to be set (UART transmit ready)
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_viduart->status_r(space,0);
break;
}
@ -786,11 +786,11 @@ WRITE16_MEMBER( ngen_state::b38_keyboard_w )
switch(offset)
{
case 0:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_viduart->data_w(space,0,data & 0xff);
break;
case 1:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_viduart->control_w(space,0,data & 0xff);
break;
}
@ -802,11 +802,11 @@ READ16_MEMBER( ngen_state::b38_crtc_r )
switch(offset)
{
case 0:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_crtc->register_r(space,0);
break;
case 1:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
ret = m_viduart->data_r(space,0);
break;
}
@ -818,11 +818,11 @@ WRITE16_MEMBER( ngen_state::b38_crtc_w )
switch(offset)
{
case 0:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_crtc->address_w(space,0,data & 0xff);
break;
case 1:
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
m_crtc->register_w(space,0,data & 0xff);
break;
}

4
src/mame/drivers/plygonet.cpp
View File

@ -236,13 +236,13 @@ WRITE32_MEMBER(polygonet_state::shared_ram_write)
}
/* write to the current dsp56k word */
if (mem_mask & 0xffff0000)
if (ACCESSING_BITS_16_31)
{
m_dsp56k_shared_ram_16[(offset<<1)] = (m_shared_ram[offset] & 0xffff0000) >> 16 ;
}
/* write to the next dsp56k word */
if (mem_mask & 0x0000ffff)
if (ACCESSING_BITS_0_15)
{
m_dsp56k_shared_ram_16[(offset<<1)+1] = (m_shared_ram[offset] & 0x0000ffff) ;
}

4
src/mame/drivers/segapico.cpp
View File

@ -330,8 +330,8 @@ WRITE16_MEMBER(pico_base_state::pico_68k_io_write )
m_sega_315_5641_pcm->reset_w(1);
m_sega_315_5641_pcm->start_w(1);
if (mem_mask&0x00ff) m_sega_315_5641_pcm->port_w(space,0,data&0xff);
if (mem_mask&0xff00) m_sega_315_5641_pcm->port_w(space,0,(data>>8)&0xff);*/
if (ACCESSING_BITS_0_7) m_sega_315_5641_pcm->port_w(space,0,data&0xff);
if (ACCESSING_BITS_8_15) m_sega_315_5641_pcm->port_w(space,0,(data>>8)&0xff);*/
break;
}

10
src/mame/drivers/segasp.cpp
View File

@ -79,14 +79,14 @@ G 171-8278G 315-6416 2x 512Mbit RMI
READ64_MEMBER(segasp_state::sp_bank_r)
{
if (mem_mask & U64(0xffffffff00000000))
if (ACCESSING_BITS_32_63)
return -1;
return m_sp_bank;
}
WRITE64_MEMBER(segasp_state::sp_bank_w)
{
if (mem_mask & U64(0xffffffff00000000))
if (ACCESSING_BITS_32_63)
return;
UINT16 bank = data & 0xffff;
if (bank != m_sp_bank)
@ -116,14 +116,14 @@ WRITE64_MEMBER(segasp_state::sn_93c46a_w)
READ64_MEMBER(segasp_state::sp_eeprom_r)
{
if (mem_mask & U64(0xffffffff00000000))
if (ACCESSING_BITS_32_63)
return -1;
return m_sp_eeprom->do_read() << 4;
}
WRITE64_MEMBER(segasp_state::sp_eeprom_w)
{
if (mem_mask & U64(0xffffffff00000000))
if (ACCESSING_BITS_32_63)
return;
m_sp_eeprom->di_write(data & 1);
m_sp_eeprom->cs_write((data & 2) ? ASSERT_LINE : CLEAR_LINE);
@ -144,7 +144,7 @@ READ64_MEMBER(segasp_state::sp_io_r)
int reg = offset * 2;
int shift = 0;
if (mem_mask & U64(0xffffffff00000000))
if (ACCESSING_BITS_32_63)
{
reg++;
shift = 32;

8
src/mame/drivers/supracan.cpp
View File

@ -1368,13 +1368,13 @@ WRITE16_MEMBER( supracan_state::_68k_soundram_w )
if(offset*2 < 0x500 && offset*2 >= 0x300)
{
if(mem_mask & 0xff00)
if(ACCESSING_BITS_8_15)
{
m_hack_68k_to_6502_access = true;
_6502_soundmem_w(mem, offset*2, data >> 8);
m_hack_68k_to_6502_access = false;
}
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
{
m_hack_68k_to_6502_access = true;
_6502_soundmem_w(mem, offset*2 + 1, data & 0xff);
@ -1392,13 +1392,13 @@ READ16_MEMBER( supracan_state::_68k_soundram_r )
if(offset*2 >= 0x300 && offset*2 < 0x500)
{
val = 0;
if(mem_mask & 0xff00)
if(ACCESSING_BITS_8_15)
{
m_hack_68k_to_6502_access = true;
val |= _6502_soundmem_r(mem, offset*2) << 8;
m_hack_68k_to_6502_access = false;
}
if(mem_mask & 0x00ff)
if(ACCESSING_BITS_0_7)
{
m_hack_68k_to_6502_access = true;
val |= _6502_soundmem_r(mem, offset*2 + 1);

0
src/mame/drivers/tek440x.cpp Executable file → Normal file
View File

16
src/mame/drivers/vegas.cpp
View File

@ -666,13 +666,13 @@ WRITE32_MEMBER( vegas_state::timekeeper_w )
{
if (m_cmos_unlocked)
{
if ((mem_mask & 0x000000ff) != 0)
if (ACCESSING_BITS_0_7)
m_timekeeper->write(space, offset * 4 + 0, data >> 0, 0xff);
if ((mem_mask & 0x0000ff00) != 0)
if (ACCESSING_BITS_8_15)
m_timekeeper->write(space, offset * 4 + 1, data >> 8, 0xff);
if ((mem_mask & 0x00ff0000) != 0)
if (ACCESSING_BITS_16_23)
m_timekeeper->write(space, offset * 4 + 2, data >> 16, 0xff);
if ((mem_mask & 0xff000000) != 0)
if (ACCESSING_BITS_24_31)
m_timekeeper->write(space, offset * 4 + 3, data >> 24, 0xff);
if (offset*4 >= 0x7ff0)
if (LOG_TIMEKEEPER) logerror("timekeeper_w(%04X & %08X) = %08X\n", offset*4, mem_mask, data);
@ -686,13 +686,13 @@ WRITE32_MEMBER( vegas_state::timekeeper_w )
READ32_MEMBER( vegas_state::timekeeper_r )
{
UINT32 result = 0xffffffff;
if ((mem_mask & 0x000000ff) != 0)
if (ACCESSING_BITS_0_7)
result = (result & ~0x000000ff) | (m_timekeeper->read(space, offset * 4 + 0, 0xff) << 0);
if ((mem_mask & 0x0000ff00) != 0)
if (ACCESSING_BITS_8_15)
result = (result & ~0x0000ff00) | (m_timekeeper->read(space, offset * 4 + 1, 0xff) << 8);
if ((mem_mask & 0x00ff0000) != 0)
if (ACCESSING_BITS_16_23)
result = (result & ~0x00ff0000) | (m_timekeeper->read(space, offset * 4 + 2, 0xff) << 16);
if ((mem_mask & 0xff000000) != 0)
if (ACCESSING_BITS_24_31)
result = (result & ~0xff000000) | (m_timekeeper->read(space, offset * 4 + 3, 0xff) << 24);
if (offset*4 >= 0x7ff0)
if (LOG_TIMEKEEPER) logerror("timekeeper_r(%04X & %08X) = %08X\n", offset*4, mem_mask, result);

2
src/mame/machine/apollo.cpp
View File

@ -276,7 +276,7 @@ WRITE16_MEMBER(apollo_state::apollo_csr_control_register_w)
}
}
cpu_control_register = (cpu_control_register & ~mem_mask) | (data & mem_mask);
COMBINE_DATA(&cpu_control_register);
output().set_value("internal_led_1", (cpu_control_register >> 15) & 1);
output().set_value("internal_led_2", (cpu_control_register >> 14) & 1);

32
src/mame/machine/bebox.cpp
View File

@ -622,28 +622,28 @@ READ64_MEMBER(bebox_state::scsi53c810_r )
{
int reg = offset*8;
UINT64 r = 0;
if (!(mem_mask & U64(0xff00000000000000))) {
if (!ACCESSING_BITS_56_63) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+0) << 56;
}
if (!(mem_mask & U64(0x00ff000000000000))) {
if (!ACCESSING_BITS_48_55) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+1) << 48;
}
if (!(mem_mask & U64(0x0000ff0000000000))) {
if (!ACCESSING_BITS_40_47) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+2) << 40;
}
if (!(mem_mask & U64(0x000000ff00000000))) {
if (!ACCESSING_BITS_32_39) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+3) << 32;
}
if (!(mem_mask & U64(0x00000000ff000000))) {
if (!ACCESSING_BITS_24_31) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+4) << 24;
}
if (!(mem_mask & U64(0x0000000000ff0000))) {
if (!ACCESSING_BITS_16_23) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+5) << 16;
}
if (!(mem_mask & U64(0x000000000000ff00))) {
if (!ACCESSING_BITS_8_15) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+6) << 8;
}
if (!(mem_mask & U64(0x00000000000000ff))) {
if (!ACCESSING_BITS_0_7) {
r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+7) << 0;
}
@ -654,28 +654,28 @@ READ64_MEMBER(bebox_state::scsi53c810_r )
WRITE64_MEMBER(bebox_state::scsi53c810_w )
{
int reg = offset*8;
if (!(mem_mask & U64(0xff00000000000000))) {
if (!ACCESSING_BITS_56_63) {
m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56);
}
if (!(mem_mask & U64(0x00ff000000000000))) {
if (!ACCESSING_BITS_48_55) {
m_lsi53c810->lsi53c810_reg_w(reg+1, data >> 48);
}
if (!(mem_mask & U64(0x0000ff0000000000))) {
if (!ACCESSING_BITS_40_47) {
m_lsi53c810->lsi53c810_reg_w(reg+2, data >> 40);
}
if (!(mem_mask & U64(0x000000ff00000000))) {
if (!ACCESSING_BITS_32_39) {
m_lsi53c810->lsi53c810_reg_w(reg+3, data >> 32);
}
if (!(mem_mask & U64(0x00000000ff000000))) {
if (!ACCESSING_BITS_24_31) {
m_lsi53c810->lsi53c810_reg_w(reg+4, data >> 24);
}
if (!(mem_mask & U64(0x0000000000ff0000))) {
if (!ACCESSING_BITS_16_23) {
m_lsi53c810->lsi53c810_reg_w(reg+5, data >> 16);
}
if (!(mem_mask & U64(0x000000000000ff00))) {
if (!ACCESSING_BITS_8_15) {
m_lsi53c810->lsi53c810_reg_w(reg+6, data >> 8);
}
if (!(mem_mask & U64(0x00000000000000ff))) {
if (!ACCESSING_BITS_0_7) {
m_lsi53c810->lsi53c810_reg_w(reg+7, data >> 0);
}
}

2
src/mame/machine/dc.cpp
View File

@ -271,7 +271,7 @@ int dc_state::decode_reg3216_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
//machine().debug_break();
}
if (mem_mask & U64(0x0000ffff00000000))
if (ACCESSING_BITS_32_47)
{
reg++;
*shift = 32;

4
src/mame/machine/m3comm.cpp
View File

@ -318,10 +318,10 @@ WRITE16_MEMBER(m3comm_device::ioregs_w)
send_size = (send_size >> 8) | (data << 8);
break;
case 0x88 / 2:
m_status0 = (m_status0 & ~mem_mask) | (data & mem_mask);
COMBINE_DATA(&m_status0);
break;
case 0x8A / 2:
m_status1 = (m_status1 & ~mem_mask) | (data & mem_mask);
COMBINE_DATA(&m_status1);
break;
case 0xC0 / 2:
m_commcpu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);

8
src/mame/machine/n64.cpp
View File

@ -2682,19 +2682,19 @@ READ32_MEMBER( n64_periphs::pif_ram_r )
WRITE32_MEMBER( n64_periphs::pif_ram_w )
{
if( mem_mask & 0xff000000 )
if( ACCESSING_BITS_24_31 )
{
pif_ram[offset*4+0] = ( data >> 24 ) & 0x000000ff;
}
if( mem_mask & 0x00ff0000 )
if( ACCESSING_BITS_16_23 )
{
pif_ram[offset*4+1] = ( data >> 16 ) & 0x000000ff;
}
if( mem_mask & 0x0000ff00 )
if( ACCESSING_BITS_8_15 )
{
pif_ram[offset*4+2] = ( data >> 8 ) & 0x000000ff;
}
if( mem_mask & 0x000000ff )
if( ACCESSING_BITS_0_7 )
{
pif_ram[offset*4+3] = ( data >> 0 ) & 0x000000ff;
}

2
src/mame/machine/segas32.cpp
View File

@ -104,7 +104,7 @@ WRITE16_MEMBER(segas32_state::sonic_level_load_protection)
{
UINT16 level;
//Perform write
m_system32_workram[CLEARED_LEVELS / 2] = (data & mem_mask) | (m_system32_workram[CLEARED_LEVELS / 2] & ~mem_mask);
COMBINE_DATA(&m_system32_workram[CLEARED_LEVELS / 2]);
//Refresh current level
if (m_system32_workram[CLEARED_LEVELS / 2] == 0)

4
src/mame/machine/stvprot.cpp
View File

@ -70,8 +70,8 @@ WRITE32_MEMBER ( stv_state::common_prot_w )
}
else if(offset == 2)
{
if (mem_mask&0xffff0000) m_cryptdevice->set_addr_low(data >> 16);
if (mem_mask&0x0000ffff) m_cryptdevice->set_addr_high(data&0xffff);
if (ACCESSING_BITS_16_31) m_cryptdevice->set_addr_low(data >> 16);
if (ACCESSING_BITS_0_15) m_cryptdevice->set_addr_high(data&0xffff);
}
else if(offset == 3)

2
src/mame/video/jaguar.cpp
View File

@ -543,7 +543,7 @@ READ32_MEMBER( jaguar_state::blitter_r )
WRITE32_MEMBER( jaguar_state::blitter_w )
{
COMBINE_DATA(&m_blitter_regs[offset]);
if ((offset == B_CMD) && (mem_mask & 0x0000ffff))
if ((offset == B_CMD) && ACCESSING_BITS_0_15)
{
m_blitter_status = 0;
int inner_count = m_blitter_regs[B_COUNT] & 0xffff;

4
src/mame/video/kaneko_tmap.cpp
View File

@ -315,7 +315,7 @@ WRITE16_MEMBER( kaneko_view2_tilemap_device::kaneko_tmap_regs_w )
/* some weird logic needed for Gals Panic on the EXPRO02 board */
WRITE16_MEMBER(kaneko_view2_tilemap_device::galsnew_vram_0_tilebank_w)
{
if (mem_mask & 0x00ff)
if (ACCESSING_BITS_0_7)
{
int val = (data & 0x00ff)<<8;
@ -329,7 +329,7 @@ WRITE16_MEMBER(kaneko_view2_tilemap_device::galsnew_vram_0_tilebank_w)
WRITE16_MEMBER(kaneko_view2_tilemap_device::galsnew_vram_1_tilebank_w)
{
if (mem_mask & 0x00ff)
if (ACCESSING_BITS_0_7)
{
int val = (data & 0x00ff)<<8;