From 602ff959466ff965494eddf9e47d65ece233e649 Mon Sep 17 00:00:00 2001
From: mahlemiut <mahlemiut@users.noreply.github.com>
Date: Sun, 7 Sep 2014 10:18:41 +0000
Subject: [PATCH] svga_s3: added CLKSYN test register (SR17), gets stock
 Trio64V2/DX BIOS to boot. (no whatsnew)

---
 src/emu/bus/isa/svga_s3.c | 2 +-
 src/emu/video/pc_vga.c    | 6 ++++++
 src/emu/video/pc_vga.h    | 1 +
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/emu/bus/isa/svga_s3.c b/src/emu/bus/isa/svga_s3.c
index d1d3d9b7423..d022e2e914d 100644
--- a/src/emu/bus/isa/svga_s3.c
+++ b/src/emu/bus/isa/svga_s3.c
@@ -16,7 +16,7 @@ ROM_START( s3_764 )
 	ROM_IGNORE( 0x8000 )
 
 	// The following are from Trio64V2/DX based cards
-	ROM_SYSTEM_BIOS( 1, "s3_9503", "PCI S3 9503-62 (S3 Trio64V2/DX)" )
+	ROM_SYSTEM_BIOS( 1, "trio64v2", "PCI S3 86C765 v1.03-08N (S3 Trio64V2/DX)" )
 	ROMX_LOAD("pci_9503-62_s3.bin", 0x00000, 0x8000, CRC(0e9d79d8) SHA1(274b5b98cc998f2783567000cdb12b14308bc290), ROM_BIOS(2) )
 
 	ROM_SYSTEM_BIOS( 2, "winner1k", "PCI Elsa Winner 1000/T2D 6.01.00 (S3 Trio64V2/DX)" )
diff --git a/src/emu/video/pc_vga.c b/src/emu/video/pc_vga.c
index 7fa0a5b33f6..4581d23bce7 100644
--- a/src/emu/video/pc_vga.c
+++ b/src/emu/video/pc_vga.c
@@ -2005,6 +2005,8 @@ void s3_vga_device::device_reset()
 	// Power-on strapping bits.  Sampled at reset, but can be modified later.
 	// These are just assumed defaults.
 	s3.strapping = 0x000f0b1e;
+	s3.sr10 = 0x42;
+	s3.sr11 = 0x41;
 }
 
 READ8_MEMBER(vga_device::mem_r)
@@ -3241,6 +3243,10 @@ UINT8 s3_vga_device::s3_seq_reg_read(UINT8 index)
 		case 0x15:
 			res = s3.sr15;
 			break;
+		case 0x17:
+			res = s3.sr17;  // CLKSYN test register
+			s3.sr17--;  // who knows what it should return, docs only say it defaults to 0, and is reserved for testing of the clock synthesiser
+			break;
 		}
 	}
 
diff --git a/src/emu/video/pc_vga.h b/src/emu/video/pc_vga.h
index 282ea401e9e..f74b98b9bb5 100644
--- a/src/emu/video/pc_vga.h
+++ b/src/emu/video/pc_vga.h
@@ -584,6 +584,7 @@ protected:
 		UINT8 sr12;   // DCLK PLL
 		UINT8 sr13;   // DCLK PLL
 		UINT8 sr15;   // CLKSYN control 2
+		UINT8 sr17;   // CLKSYN test
 		UINT8 clk_pll_r;  // individual DCLK PLL values
 		UINT8 clk_pll_m;
 		UINT8 clk_pll_n;