mirror of
https://github.com/holub/mame
synced 2025-05-31 18:11:50 +03:00
ucom4, upd7725: Removed MCFG. [Ryan Holtz]
This commit is contained in:
mooglyguy
parent
55c8bf8e0e
commit
6056c917ed
@ -11,39 +11,6 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
|
||||
// I/O ports setup
|
||||
#define MCFG_UCOM4_READ_A_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_read_a_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_READ_B_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_read_b_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_READ_C_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_read_c_callback(DEVCB_##_devcb);
|
||||
#define MCFG_UCOM4_WRITE_C_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_c_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_READ_D_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_read_d_callback(DEVCB_##_devcb);
|
||||
#define MCFG_UCOM4_WRITE_D_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_d_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_WRITE_E_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_e_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_WRITE_F_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_f_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_WRITE_G_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_g_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_WRITE_H_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_h_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_UCOM4_WRITE_I_CB(_devcb) \
|
||||
downcast<ucom4_cpu_device &>(*device).set_write_i_callback(DEVCB_##_devcb);
|
||||
|
||||
enum
|
||||
{
|
||||
NEC_UCOM4_PORTA = 0,
|
||||
@ -100,18 +67,18 @@ class ucom4_cpu_device : public cpu_device
|
||||
{
|
||||
public:
|
||||
// configuration helpers
|
||||
template <class Object> devcb_base &set_read_a_callback(Object &&cb) { return m_read_a.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_read_b_callback(Object &&cb) { return m_read_b.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_read_c_callback(Object &&cb) { return m_read_c.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_read_d_callback(Object &&cb) { return m_read_d.set_callback(std::forward<Object>(cb)); }
|
||||
auto read_a() { return m_read_a.bind(); }
|
||||
auto read_b() { return m_read_b.bind(); }
|
||||
auto read_c() { return m_read_c.bind(); }
|
||||
auto read_d() { return m_read_d.bind(); }
|
||||
|
||||
template <class Object> devcb_base &set_write_c_callback(Object &&cb) { return m_write_c.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_write_d_callback(Object &&cb) { return m_write_d.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_write_e_callback(Object &&cb) { return m_write_e.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_write_f_callback(Object &&cb) { return m_write_f.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_write_g_callback(Object &&cb) { return m_write_g.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_write_h_callback(Object &&cb) { return m_write_h.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_write_i_callback(Object &&cb) { return m_write_i.set_callback(std::forward<Object>(cb)); }
|
||||
auto write_c() { return m_write_c.bind(); }
|
||||
auto write_d() { return m_write_d.bind(); }
|
||||
auto write_e() { return m_write_e.bind(); }
|
||||
auto write_f() { return m_write_f.bind(); }
|
||||
auto write_g() { return m_write_g.bind(); }
|
||||
auto write_h() { return m_write_h.bind(); }
|
||||
auto write_i() { return m_write_i.bind(); }
|
||||
|
||||
protected:
|
||||
// construction/destruction
|
||||
|
||||
@ -28,57 +28,13 @@ enum
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
|
||||
#define MCFG_NECDSP_IN_INT_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_in_int_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_IN_SI_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_in_si_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_IN_SCK_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_in_sck_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_IN_SIEN_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_in_sien_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_IN_SOEN_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_in_soen_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_IN_DACK_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_in_dack_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_OUT_P0_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_out_p0_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_OUT_P1_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_out_p1_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_OUT_SO_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_out_so_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_OUT_SORQ_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_out_sorq_callback(DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_NECDSP_OUT_DRQ_CB(_devcb) \
|
||||
downcast<necdsp_device &>(*device).set_out_drq_callback(DEVCB_##_devcb);
|
||||
|
||||
|
||||
// ======================> necdsp_device
|
||||
|
||||
class necdsp_device : public cpu_device
|
||||
{
|
||||
public:
|
||||
template <class Object> devcb_base &set_in_int_callback(Object &&cb) { return m_in_int_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_in_si_callback(Object &&cb) { return m_in_si_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_in_sck_callback(Object &&cb) { return m_in_sck_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_in_sien_callback(Object &&cb) { return m_in_sien_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_in_soen_callback(Object &&cb) { return m_in_soen_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_in_dack_callback(Object &&cb) { return m_in_dack_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_out_p0_callback(Object &&cb) { return m_out_p0_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> devcb_base &set_out_p1_callback(Object &&cb) { return m_out_p1_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_out_so_callback(Object &&cb) { return m_out_so_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_out_sorq_callback(Object &&cb) { return m_out_sorq_cb.set_callback(std::forward<Object>(cb)); }
|
||||
//template <class Object> devcb_base &set_out_drq_callback(Object &&cb) { return m_out_drq_cb.set_callback(std::forward<Object>(cb)); }
|
||||
auto p0() { return m_out_p0_cb.bind(); }
|
||||
auto p1() { return m_out_p1_cb.bind(); }
|
||||
|
||||
uint8_t snesdsp_read(bool mode);
|
||||
void snesdsp_write(bool mode, uint8_t data);
|
||||
@ -192,7 +148,6 @@ private:
|
||||
memory_access_cache<2, -2, ENDIANNESS_BIG> *m_cache;
|
||||
|
||||
protected:
|
||||
// device callbacks
|
||||
devcb_read_line m_in_int_cb;
|
||||
//devcb_read8 m_in_si_cb;
|
||||
//devcb_read_line m_in_sck_cb;
|
||||
|
||||
@ -331,16 +331,16 @@ static const s16 ufombs_speaker_levels[] = { 0, 0x7fff, -0x8000, 0 };
|
||||
MACHINE_CONFIG_START(ufombs_state::ufombs)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D552, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, ufombs_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, ufombs_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, ufombs_state, speaker_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, ufombs_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, ufombs_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, ufombs_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, ufombs_state, plate_w))
|
||||
NEC_D552(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(ufombs_state::plate_w));
|
||||
m_maincpu->write_d().set(FUNC(ufombs_state::plate_w));
|
||||
m_maincpu->write_e().set(FUNC(ufombs_state::speaker_w));
|
||||
m_maincpu->write_f().set(FUNC(ufombs_state::grid_w));
|
||||
m_maincpu->write_g().set(FUNC(ufombs_state::grid_w));
|
||||
m_maincpu->write_h().set(FUNC(ufombs_state::grid_w));
|
||||
m_maincpu->write_i().set(FUNC(ufombs_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -477,16 +477,16 @@ static const s16 ssfball_speaker_levels[] = { 0, 0x7fff, -0x8000, 0 };
|
||||
MACHINE_CONFIG_START(ssfball_state::ssfball)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.3"))
|
||||
MCFG_UCOM4_READ_B_CB(READ8(*this, ssfball_state, input_b_r))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, ssfball_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, ssfball_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, ssfball_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, ssfball_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, ssfball_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, ssfball_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, ssfball_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set_ioport("IN.3");
|
||||
m_maincpu->read_b().set(FUNC(ssfball_state::input_b_r));
|
||||
m_maincpu->write_c().set(FUNC(ssfball_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(ssfball_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(ssfball_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(ssfball_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(ssfball_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(ssfball_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(ssfball_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -604,16 +604,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(bmsoccer_state::bmsoccer)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D552, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(READ8(*this, bmsoccer_state, input_a_r))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.2"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, bmsoccer_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, bmsoccer_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, bmsoccer_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, bmsoccer_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, bmsoccer_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, bmsoccer_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, bmsoccer_state, plate_w))
|
||||
NEC_D552(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set(FUNC(bmsoccer_state::input_a_r));
|
||||
m_maincpu->read_b().set_ioport("IN.2");
|
||||
m_maincpu->write_c().set(FUNC(bmsoccer_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(bmsoccer_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(bmsoccer_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(bmsoccer_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(bmsoccer_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(bmsoccer_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(bmsoccer_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -711,15 +711,15 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(bmsafari_state::bmsafari)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D552, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, bmsafari_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, bmsafari_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, bmsafari_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, bmsafari_state, speaker_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, bmsafari_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, bmsafari_state, plate_w))
|
||||
NEC_D552(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(bmsafari_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(bmsafari_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(bmsafari_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(bmsafari_state::speaker_w));
|
||||
m_maincpu->write_h().set(FUNC(bmsafari_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(bmsafari_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -860,16 +860,16 @@ static const s16 splasfgt_speaker_levels[] = { 0, 0x7fff, -0x8000, 0 };
|
||||
MACHINE_CONFIG_START(splasfgt_state::splasfgt)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.4"))
|
||||
MCFG_UCOM4_READ_B_CB(READ8(*this, splasfgt_state, input_b_r))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, splasfgt_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, splasfgt_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, splasfgt_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, splasfgt_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, splasfgt_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, splasfgt_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, splasfgt_state, grid_w))
|
||||
NEC_D553(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set_ioport("IN.4");
|
||||
m_maincpu->read_b().set(FUNC(splasfgt_state::input_b_r));
|
||||
m_maincpu->write_c().set(FUNC(splasfgt_state::plate_w));
|
||||
m_maincpu->write_d().set(FUNC(splasfgt_state::plate_w));
|
||||
m_maincpu->write_e().set(FUNC(splasfgt_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(splasfgt_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(splasfgt_state::grid_w));
|
||||
m_maincpu->write_h().set(FUNC(splasfgt_state::grid_w));
|
||||
m_maincpu->write_i().set(FUNC(splasfgt_state::grid_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -963,16 +963,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(bcclimbr_state::bcclimbr)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, bcclimbr_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, bcclimbr_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, bcclimbr_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, bcclimbr_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, bcclimbr_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, bcclimbr_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, bcclimbr_state, grid_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(bcclimbr_state::plate_w));
|
||||
m_maincpu->write_d().set(FUNC(bcclimbr_state::plate_w));
|
||||
m_maincpu->write_e().set(FUNC(bcclimbr_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(bcclimbr_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(bcclimbr_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(bcclimbr_state::grid_w));
|
||||
m_maincpu->write_i().set(FUNC(bcclimbr_state::grid_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -1085,13 +1085,13 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(tactix_state::tactix)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D557L, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(READ8(*this, tactix_state, input_r))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tactix_state, input_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tactix_state, leds_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tactix_state, input_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tactix_state, leds_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tactix_state, speaker_w))
|
||||
NEC_D557L(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set(FUNC(tactix_state::input_r));
|
||||
m_maincpu->write_c().set(FUNC(tactix_state::input_w));
|
||||
m_maincpu->write_d().set(FUNC(tactix_state::leds_w));
|
||||
m_maincpu->write_e().set(FUNC(tactix_state::input_w));
|
||||
m_maincpu->write_f().set(FUNC(tactix_state::leds_w));
|
||||
m_maincpu->write_g().set(FUNC(tactix_state::speaker_w));
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_ucom4_state, display_decay_tick, attotime::from_msec(1))
|
||||
config.set_default_layout(layout_tactix);
|
||||
@ -1179,16 +1179,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(invspace_state::invspace)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D552, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, invspace_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, invspace_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, invspace_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, invspace_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, invspace_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, invspace_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, invspace_state, grid_w))
|
||||
NEC_D552(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(invspace_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(invspace_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(invspace_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(invspace_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(invspace_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(invspace_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(invspace_state::grid_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -1294,16 +1294,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(efball_state::efball)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_READ_C_CB(IOPORT("IN.2"))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, efball_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, efball_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, efball_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, efball_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, efball_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, efball_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->read_c().set_ioport("IN.2");
|
||||
m_maincpu->write_d().set(FUNC(efball_state::plate_w));
|
||||
m_maincpu->write_e().set(FUNC(efball_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(efball_state::grid_w));
|
||||
m_maincpu->write_g().set(FUNC(efball_state::grid_w));
|
||||
m_maincpu->write_h().set(FUNC(efball_state::grid_w));
|
||||
m_maincpu->write_i().set(FUNC(efball_state::plate_w));
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_ucom4_state, display_decay_tick, attotime::from_msec(1))
|
||||
config.set_default_layout(layout_efball);
|
||||
@ -1394,16 +1394,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(galaxy2_state::galaxy2)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, galaxy2_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, galaxy2_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, galaxy2_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, galaxy2_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, galaxy2_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, galaxy2_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, galaxy2_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(galaxy2_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(galaxy2_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(galaxy2_state::grid_w));
|
||||
m_maincpu->write_f().set(FUNC(galaxy2_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(galaxy2_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(galaxy2_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(galaxy2_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -1512,16 +1512,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(astrocmd_state::astrocmd)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, astrocmd_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, astrocmd_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, astrocmd_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, astrocmd_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, astrocmd_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, astrocmd_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, astrocmd_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(astrocmd_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(astrocmd_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(astrocmd_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(astrocmd_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(astrocmd_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(astrocmd_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(astrocmd_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -1607,16 +1607,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(edracula_state::edracula)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, edracula_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, edracula_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, edracula_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, edracula_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, edracula_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, edracula_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, edracula_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(edracula_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(edracula_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(edracula_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(edracula_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(edracula_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(edracula_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(edracula_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -1694,10 +1694,10 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(mcompgin_state::mcompgin)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D650, 400_kHz_XTAL) // TDK FCR400K
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, mcompgin_state, lcd_w))
|
||||
NEC_D650(config, m_maincpu, 400_kHz_XTAL); // TDK FCR400K
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_e().set(FUNC(mcompgin_state::lcd_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_DEVICE_ADD("lcd", HLCD0530, 500) // C=0.01uF
|
||||
@ -1791,16 +1791,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(mvbfree_state::mvbfree)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, mvbfree_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, mvbfree_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, mvbfree_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, mvbfree_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, mvbfree_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, mvbfree_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, mvbfree_state, speaker_w))
|
||||
NEC_D553(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(mvbfree_state::plate_w));
|
||||
m_maincpu->write_d().set(FUNC(mvbfree_state::plate_w));
|
||||
m_maincpu->write_e().set(FUNC(mvbfree_state::grid_w));
|
||||
m_maincpu->write_f().set(FUNC(mvbfree_state::grid_w));
|
||||
m_maincpu->write_g().set(FUNC(mvbfree_state::grid_w));
|
||||
m_maincpu->write_h().set(FUNC(mvbfree_state::grid_w));
|
||||
m_maincpu->write_i().set(FUNC(mvbfree_state::speaker_w));
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_ucom4_state, display_decay_tick, attotime::from_msec(1))
|
||||
config.set_default_layout(layout_mvbfree);
|
||||
@ -1910,12 +1910,12 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(grobot9_state::grobot9)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D557L, 160000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(READ8(*this, grobot9_state, input_r))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, grobot9_state, input_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, grobot9_state, lamps_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, grobot9_state, lamps_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, grobot9_state, lamps_w))
|
||||
NEC_D557L(config, m_maincpu, 160000); // approximation
|
||||
m_maincpu->read_a().set(FUNC(grobot9_state::input_r));
|
||||
m_maincpu->write_c().set(FUNC(grobot9_state::input_w));
|
||||
m_maincpu->write_d().set(FUNC(grobot9_state::lamps_w));
|
||||
m_maincpu->write_e().set(FUNC(grobot9_state::lamps_w));
|
||||
m_maincpu->write_f().set(FUNC(grobot9_state::lamps_w));
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_ucom4_state, display_decay_tick, attotime::from_msec(1))
|
||||
config.set_default_layout(layout_grobot9);
|
||||
@ -2000,15 +2000,15 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(tccombat_state::tccombat)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D552, 400000) // approximation
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tccombat_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tccombat_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tccombat_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tccombat_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tccombat_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, tccombat_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, tccombat_state, grid_w))
|
||||
NEC_D552(config, m_maincpu, 400000); // approximation
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->write_c().set(FUNC(tccombat_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(tccombat_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(tccombat_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(tccombat_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(tccombat_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(tccombat_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(tccombat_state::grid_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -2156,16 +2156,16 @@ void tmtennis_state::machine_reset()
|
||||
MACHINE_CONFIG_START(tmtennis_state::tmtennis)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D552, 360000) // see set_clock
|
||||
MCFG_UCOM4_READ_A_CB(READ8(*this, tmtennis_state, input_r))
|
||||
MCFG_UCOM4_READ_B_CB(READ8(*this, tmtennis_state, input_r))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tmtennis_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tmtennis_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tmtennis_state, port_e_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tmtennis_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tmtennis_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, tmtennis_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, tmtennis_state, grid_w))
|
||||
NEC_D552(config, m_maincpu, 360000); // see set_clock
|
||||
m_maincpu->read_a().set(FUNC(tmtennis_state::input_r));
|
||||
m_maincpu->read_b().set(FUNC(tmtennis_state::input_r));
|
||||
m_maincpu->write_c().set(FUNC(tmtennis_state::plate_w));
|
||||
m_maincpu->write_d().set(FUNC(tmtennis_state::plate_w));
|
||||
m_maincpu->write_e().set(FUNC(tmtennis_state::port_e_w));
|
||||
m_maincpu->write_f().set(FUNC(tmtennis_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(tmtennis_state::grid_w));
|
||||
m_maincpu->write_h().set(FUNC(tmtennis_state::grid_w));
|
||||
m_maincpu->write_i().set(FUNC(tmtennis_state::grid_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -2264,16 +2264,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(tmpacman_state::tmpacman)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 430_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tmpacman_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tmpacman_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tmpacman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tmpacman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tmpacman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, tmpacman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, tmpacman_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 430_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(tmpacman_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(tmpacman_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(tmpacman_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(tmpacman_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(tmpacman_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(tmpacman_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(tmpacman_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -2366,16 +2366,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(tmscramb_state::tmscramb)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.1"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tmscramb_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tmscramb_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tmscramb_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tmscramb_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tmscramb_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, tmscramb_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, tmscramb_state, grid_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->read_b().set_ioport("IN.1");
|
||||
m_maincpu->write_c().set(FUNC(tmscramb_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(tmscramb_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(tmscramb_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(tmscramb_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(tmscramb_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(tmscramb_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(tmscramb_state::grid_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -2465,15 +2465,15 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(tcaveman_state::tcaveman)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(IOPORT("IN.0"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tcaveman_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tcaveman_state, grid_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tcaveman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tcaveman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tcaveman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, tcaveman_state, plate_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, tcaveman_state, plate_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set_ioport("IN.0");
|
||||
m_maincpu->write_c().set(FUNC(tcaveman_state::grid_w));
|
||||
m_maincpu->write_d().set(FUNC(tcaveman_state::grid_w));
|
||||
m_maincpu->write_e().set(FUNC(tcaveman_state::plate_w));
|
||||
m_maincpu->write_f().set(FUNC(tcaveman_state::plate_w));
|
||||
m_maincpu->write_g().set(FUNC(tcaveman_state::plate_w));
|
||||
m_maincpu->write_h().set(FUNC(tcaveman_state::plate_w));
|
||||
m_maincpu->write_i().set(FUNC(tcaveman_state::plate_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
@ -2596,16 +2596,16 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(alnchase_state::alnchase)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D553, 400_kHz_XTAL)
|
||||
MCFG_UCOM4_READ_A_CB(READ8(*this, alnchase_state, input_r))
|
||||
MCFG_UCOM4_READ_B_CB(IOPORT("IN.2"))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, alnchase_state, output_w))
|
||||
NEC_D553(config, m_maincpu, 400_kHz_XTAL);
|
||||
m_maincpu->read_a().set(FUNC(alnchase_state::input_r));
|
||||
m_maincpu->read_b().set_ioport("IN.2");
|
||||
m_maincpu->write_c().set(FUNC(alnchase_state::output_w));
|
||||
m_maincpu->write_d().set(FUNC(alnchase_state::output_w));
|
||||
m_maincpu->write_e().set(FUNC(alnchase_state::output_w));
|
||||
m_maincpu->write_f().set(FUNC(alnchase_state::output_w));
|
||||
m_maincpu->write_g().set(FUNC(alnchase_state::output_w));
|
||||
m_maincpu->write_h().set(FUNC(alnchase_state::output_w));
|
||||
m_maincpu->write_i().set(FUNC(alnchase_state::output_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SVG_ADD("screen", "svg")
|
||||
|
||||
@ -252,17 +252,17 @@ void tb303_state::machine_start()
|
||||
MACHINE_CONFIG_START(tb303_state::tb303)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", NEC_D650, TP2_HZ)
|
||||
MCFG_UCOM4_READ_A_CB(READ8(*this, tb303_state, input_r))
|
||||
MCFG_UCOM4_READ_B_CB(READ8(*this, tb303_state, input_r))
|
||||
MCFG_UCOM4_READ_C_CB(READ8(*this, tb303_state, ram_r))
|
||||
MCFG_UCOM4_WRITE_C_CB(WRITE8(*this, tb303_state, ram_w))
|
||||
MCFG_UCOM4_WRITE_D_CB(WRITE8(*this, tb303_state, ram_w))
|
||||
MCFG_UCOM4_WRITE_E_CB(WRITE8(*this, tb303_state, ram_w))
|
||||
MCFG_UCOM4_WRITE_F_CB(WRITE8(*this, tb303_state, ram_w))
|
||||
MCFG_UCOM4_WRITE_G_CB(WRITE8(*this, tb303_state, switch_w))
|
||||
MCFG_UCOM4_WRITE_H_CB(WRITE8(*this, tb303_state, switch_w))
|
||||
MCFG_UCOM4_WRITE_I_CB(WRITE8(*this, tb303_state, strobe_w))
|
||||
NEC_D650(config, m_maincpu, TP2_HZ);
|
||||
m_maincpu->read_a().set(FUNC(tb303_state::input_r));
|
||||
m_maincpu->read_b().set(FUNC(tb303_state::input_r));
|
||||
m_maincpu->read_c().set(FUNC(tb303_state::ram_r));
|
||||
m_maincpu->write_c().set(FUNC(tb303_state::ram_w));
|
||||
m_maincpu->write_d().set(FUNC(tb303_state::ram_w));
|
||||
m_maincpu->write_e().set(FUNC(tb303_state::ram_w));
|
||||
m_maincpu->write_f().set(FUNC(tb303_state::ram_w));
|
||||
m_maincpu->write_g().set(FUNC(tb303_state::switch_w));
|
||||
m_maincpu->write_h().set(FUNC(tb303_state::switch_w));
|
||||
m_maincpu->write_i().set(FUNC(tb303_state::strobe_w));
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("tp3_clock", tb303_state, tp3_clock, TP3_PERIOD)
|
||||
MCFG_TIMER_START_DELAY(TP3_PERIOD - TP3_LOW)
|
||||
|
||||
@ -380,11 +380,11 @@ MACHINE_CONFIG_START(tsispch_state::prose2k)
|
||||
/* TODO: the UPD7720 has a 10KHz clock to its INT pin */
|
||||
/* TODO: the UPD7720 has a 2MHz clock to its SCK pin */
|
||||
/* TODO: hook up p0, p1, int */
|
||||
MCFG_DEVICE_ADD("dsp", UPD7725, 8000000) /* VERIFIED clock, unknown divider; correct dsp type is UPD77P20 */
|
||||
MCFG_DEVICE_PROGRAM_MAP(dsp_prg_map)
|
||||
MCFG_DEVICE_DATA_MAP(dsp_data_map)
|
||||
MCFG_NECDSP_OUT_P0_CB(WRITELINE(*this, tsispch_state, dsp_to_8086_p0_w))
|
||||
MCFG_NECDSP_OUT_P1_CB(WRITELINE(*this, tsispch_state, dsp_to_8086_p1_w))
|
||||
UPD7725(config, m_dsp, 8000000); /* VERIFIED clock, unknown divider; correct dsp type is UPD77P20 */
|
||||
m_dsp->set_addrmap(AS_PROGRAM, &tsispch_state::dsp_prg_map);
|
||||
m_dsp->set_addrmap(AS_IO, &tsispch_state::dsp_data_map);
|
||||
m_dsp->p0().set(FUNC(tsispch_state::dsp_to_8086_p0_w));
|
||||
m_dsp->p1().set(FUNC(tsispch_state::dsp_to_8086_p1_w));
|
||||
|
||||
/* PIC 8259 */
|
||||
PIC8259(config, m_pic, 0);
|
||||
|
||||
@ -31,7 +31,7 @@ public:
|
||||
{ }
|
||||
|
||||
// devices
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ucom4_cpu_device> m_maincpu;
|
||||
optional_ioport_array<5> m_inp_matrix; // max 5
|
||||
output_finder<0x20, 0x20> m_out_x;
|
||||
output_finder<0x20> m_out_a;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user