mirror of
https://github.com/holub/mame
synced 2025-10-07 17:27:06 +03:00
Merge branch 'master' of https://github.com/mamedev/mame
This commit is contained in:
Lord-Nightmare
commit
6082fc6772
@ -403,6 +403,7 @@ BUSOBJS += $(BUSOBJ)/ieee488/c2031.o
|
||||
BUSOBJS += $(BUSOBJ)/ieee488/c2040.o
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||||
BUSOBJS += $(BUSOBJ)/ieee488/c2040fdc.o
|
||||
BUSOBJS += $(BUSOBJ)/ieee488/c8050.o
|
||||
BUSOBJS += $(BUSOBJ)/ieee488/c8050fdc.o
|
||||
BUSOBJS += $(BUSOBJ)/ieee488/c8280.o
|
||||
BUSOBJS += $(BUSOBJ)/ieee488/d9060.o
|
||||
BUSOBJS += $(BUSOBJ)/ieee488/softbox.o
|
||||
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||||
@ -9,15 +9,6 @@
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||||
|
||||
**********************************************************************/
|
||||
|
||||
/*
|
||||
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||||
TODO:
|
||||
|
||||
- writing starts in the middle of a byte
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||||
- 8050 PLL
|
||||
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||||
*/
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||||
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||||
#include "c2040fdc.h"
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||||
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||||
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||||
@ -35,7 +26,6 @@
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||||
//**************************************************************************
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||||
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||||
const device_type C2040_FDC = &device_creator<c2040_fdc_t>;
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||||
const device_type C8050_FDC = &device_creator<c8050_fdc_t>;
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||||
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||||
|
||||
//-------------------------------------------------
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||||
@ -67,31 +57,6 @@ const rom_entry *c2040_fdc_t::device_rom_region() const
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||||
// c2040_fdc_t - constructor
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||||
//-------------------------------------------------
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||||
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||||
c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
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||||
device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
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||||
m_write_sync(*this),
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m_write_ready(*this),
|
||||
m_write_error(*this),
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||||
m_gcr_rom(*this, "gcr"),
|
||||
m_floppy0(NULL),
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m_floppy1(NULL),
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m_mtr0(1),
|
||||
m_mtr1(1),
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m_stp0(0),
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m_stp1(0),
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m_ds(0),
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m_drv_sel(0),
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||||
m_mode_sel(0),
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m_rw_sel(0),
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||||
m_period(attotime::from_hz(clock))
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{
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cur_live.tm = attotime::never;
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cur_live.state = IDLE;
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cur_live.next_state = -1;
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cur_live.write_position = 0;
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cur_live.write_start_time = attotime::never;
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||||
}
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||||
c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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||||
device_t(mconfig, C2040_FDC, "C2040 FDC", tag, owner, clock, "c2040fdc", __FILE__),
|
||||
m_write_sync(*this),
|
||||
@ -118,9 +83,6 @@ c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char *tag, device_
|
||||
cur_live.drv_sel = m_drv_sel;
|
||||
}
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||||
|
||||
c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
|
||||
c2040_fdc_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__) { }
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -635,152 +597,3 @@ void c2040_fdc_t::set_floppy(floppy_image_device *floppy0, floppy_image_device *
|
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m_floppy0 = floppy0;
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m_floppy1 = floppy1;
|
||||
}
|
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void c8050_fdc_t::live_start()
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{
|
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cur_live.tm = machine().time();
|
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cur_live.state = RUNNING;
|
||||
cur_live.next_state = -1;
|
||||
|
||||
cur_live.shift_reg = 0;
|
||||
cur_live.shift_reg_write = 0;
|
||||
cur_live.cycle_counter = 0;
|
||||
cur_live.cell_counter = 0;
|
||||
cur_live.bit_counter = 0;
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cur_live.ds = m_ds;
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||||
cur_live.drv_sel = m_drv_sel;
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||||
cur_live.mode_sel = m_mode_sel;
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||||
cur_live.rw_sel = m_rw_sel;
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cur_live.pi = m_pi;
|
||||
|
||||
pll_reset(cur_live.tm, attotime::from_double(0));
|
||||
checkpoint_live = cur_live;
|
||||
pll_save_checkpoint();
|
||||
|
||||
live_run();
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_reset(const attotime &when, const attotime clock)
|
||||
{
|
||||
cur_pll.reset(when);
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||||
cur_pll.set_clock(clock);
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||||
}
|
||||
|
||||
void c8050_fdc_t::pll_save_checkpoint()
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||||
{
|
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checkpoint_pll = cur_pll;
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||||
}
|
||||
|
||||
void c8050_fdc_t::pll_retrieve_checkpoint()
|
||||
{
|
||||
cur_pll = checkpoint_pll;
|
||||
}
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||||
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||||
void c8050_fdc_t::checkpoint()
|
||||
{
|
||||
checkpoint_live = cur_live;
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pll_save_checkpoint();
|
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}
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|
||||
void c8050_fdc_t::rollback()
|
||||
{
|
||||
cur_live = checkpoint_live;
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pll_retrieve_checkpoint();
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}
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||||
void c8050_fdc_t::live_run(const attotime &limit)
|
||||
{
|
||||
if(cur_live.state == IDLE || cur_live.next_state != -1)
|
||||
return;
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||||
|
||||
for(;;) {
|
||||
switch(cur_live.state) {
|
||||
case RUNNING: {
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||||
bool syncpoint = false;
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||||
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||||
if (cur_live.tm > limit)
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return;
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||||
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int bit = get_next_bit(cur_live.tm, limit);
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if(bit < 0)
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return;
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||||
if (syncpoint) {
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commit(cur_live.tm);
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|
||||
cur_live.tm += m_period;
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live_delay(RUNNING_SYNCPOINT);
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return;
|
||||
}
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||||
|
||||
cur_live.tm += m_period;
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||||
break;
|
||||
}
|
||||
|
||||
case RUNNING_SYNCPOINT: {
|
||||
m_write_ready(cur_live.ready);
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||||
m_write_sync(cur_live.sync);
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||||
m_write_error(cur_live.error);
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||||
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cur_live.state = RUNNING;
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||||
checkpoint();
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||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
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||||
|
||||
int c8050_fdc_t::get_next_bit(attotime &tm, const attotime &limit)
|
||||
{
|
||||
return cur_pll.get_next_bit(tm, get_floppy(), limit);
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||||
}
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||||
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void c8050_fdc_t::stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp)
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{
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if (mtr) return;
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||||
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||||
int tracks = 0;
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||||
|
||||
switch (old_stp)
|
||||
{
|
||||
case 0: if (stp == 1) tracks++; else if (stp == 2) tracks--; break;
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||||
case 1: if (stp == 3) tracks++; else if (stp == 0) tracks--; break;
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||||
case 2: if (stp == 0) tracks++; else if (stp == 3) tracks--; break;
|
||||
case 3: if (stp == 2) tracks++; else if (stp == 1) tracks--; break;
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||||
}
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||||
|
||||
if (tracks == -1)
|
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{
|
||||
floppy->dir_w(1);
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floppy->stp_w(1);
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||||
floppy->stp_w(0);
|
||||
}
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||||
else if (tracks == 1)
|
||||
{
|
||||
floppy->dir_w(0);
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||||
floppy->stp_w(1);
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||||
floppy->stp_w(0);
|
||||
}
|
||||
|
||||
old_stp = stp;
|
||||
}
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||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::odd_hd_w )
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{
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||||
if (m_odd_hd != state)
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||||
{
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live_sync();
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m_odd_hd = cur_live.odd_hd = state;
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if (LOG) logerror("%s ODD HD %u\n", machine().time().as_string(), state);
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||||
m_floppy0->ss_w(!state);
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if (m_floppy1) m_floppy1->ss_w(!state);
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||||
checkpoint();
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live_run();
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||||
}
|
||||
}
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||||
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||||
WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
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{
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// TODO
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if (LOG) logerror("%s PULL SYNC %u\n", machine().time().as_string(), state);
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}
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||||
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||||
@ -18,10 +18,7 @@
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||||
#include "formats/d64_dsk.h"
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||||
#include "formats/d67_dsk.h"
|
||||
#include "formats/g64_dsk.h"
|
||||
#include "formats/d80_dsk.h"
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||||
#include "formats/d82_dsk.h"
|
||||
#include "imagedev/floppy.h"
|
||||
#include "machine/fdc_pll.h"
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||||
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||||
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||||
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||||
@ -50,7 +47,6 @@ class c2040_fdc_t : public device_t
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||||
{
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||||
public:
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||||
// construction/destruction
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||||
c2040_fdc_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
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||||
c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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||||
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||||
template<class _Object> static devcb_base &set_sync_wr_callback(device_t &device, _Object object) { return downcast<c2040_fdc_t &>(device).m_write_sync.set_callback(object); }
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@ -68,8 +64,6 @@ public:
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||||
DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
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DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; }
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DECLARE_READ_LINE_MEMBER( ready_r ) { return checkpoint_live.ready; }
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||||
DECLARE_READ_LINE_MEMBER( error_r ) { return checkpoint_live.error; }
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||||
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||||
void stp0_w(int stp);
|
||||
void stp1_w(int stp);
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||||
@ -147,9 +141,10 @@ protected:
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||||
emu_timer *t_gen;
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||||
|
||||
floppy_image_device* get_floppy();
|
||||
virtual void live_start();
|
||||
virtual void checkpoint();
|
||||
virtual void rollback();
|
||||
|
||||
void live_start();
|
||||
void checkpoint();
|
||||
void rollback();
|
||||
bool write_next_bit(bool bit, const attotime &limit);
|
||||
void start_writing(const attotime &tm);
|
||||
void commit(const attotime &tm);
|
||||
@ -157,43 +152,14 @@ protected:
|
||||
void live_delay(int state);
|
||||
void live_sync();
|
||||
void live_abort();
|
||||
virtual void live_run(const attotime &limit = attotime::never);
|
||||
void live_run(const attotime &limit = attotime::never);
|
||||
void get_next_edge(const attotime &when);
|
||||
virtual int get_next_bit(attotime &tm, const attotime &limit);
|
||||
int get_next_bit(attotime &tm, const attotime &limit);
|
||||
};
|
||||
|
||||
|
||||
// ======================> c8050_fdc_t
|
||||
|
||||
class c8050_fdc_t : public c2040_fdc_t
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( odd_hd_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
|
||||
|
||||
protected:
|
||||
fdc_pll_t cur_pll, checkpoint_pll;
|
||||
|
||||
void stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp);
|
||||
|
||||
virtual void live_start();
|
||||
virtual void checkpoint();
|
||||
virtual void rollback();
|
||||
void pll_reset(const attotime &when, const attotime clock);
|
||||
void pll_save_checkpoint();
|
||||
void pll_retrieve_checkpoint();
|
||||
virtual void live_run(const attotime &limit = attotime::never);
|
||||
virtual int get_next_bit(attotime &tm, const attotime &limit);
|
||||
};
|
||||
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type C2040_FDC;
|
||||
extern const device_type C8050_FDC;
|
||||
|
||||
|
||||
|
||||
|
||||
490
src/emu/bus/ieee488/c8050fdc.c
Normal file
490
src/emu/bus/ieee488/c8050fdc.c
Normal file
@ -0,0 +1,490 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Curt Coder
|
||||
/**********************************************************************
|
||||
|
||||
Commodore 8050 floppy disk controller emulation
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
#include "c8050fdc.h"
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// MACROS / CONSTANTS
|
||||
//**************************************************************************
|
||||
|
||||
#define LOG 0
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// DEVICE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
const device_type C8050_FDC = &device_creator<c8050_fdc_t>;
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// ROM( c8050_fdc )
|
||||
//-------------------------------------------------
|
||||
|
||||
ROM_START( c8050_fdc )
|
||||
ROM_REGION( 0x800, "gcr", 0)
|
||||
ROM_LOAD( "901467.uk6", 0x000, 0x800, CRC(a23337eb) SHA1(97df576397608455616331f8e837cb3404363fa2) )
|
||||
ROM_END
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// rom_region - device-specific ROM region
|
||||
//-------------------------------------------------
|
||||
|
||||
const rom_entry *c8050_fdc_t::device_rom_region() const
|
||||
{
|
||||
return ROM_NAME( c8050_fdc );
|
||||
}
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// LIVE DEVICE
|
||||
//**************************************************************************
|
||||
|
||||
//-------------------------------------------------
|
||||
// c8050_fdc_t - constructor
|
||||
//-------------------------------------------------
|
||||
|
||||
c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
|
||||
device_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__),
|
||||
m_write_sync(*this),
|
||||
m_write_ready(*this),
|
||||
m_write_error(*this),
|
||||
m_gcr_rom(*this, "gcr"),
|
||||
m_floppy0(NULL),
|
||||
m_floppy1(NULL),
|
||||
m_mtr0(1),
|
||||
m_mtr1(1),
|
||||
m_stp0(0),
|
||||
m_stp1(0),
|
||||
m_ds(0),
|
||||
m_drv_sel(0),
|
||||
m_mode_sel(0),
|
||||
m_rw_sel(0),
|
||||
m_period(attotime::from_hz(clock))
|
||||
{
|
||||
cur_live.tm = attotime::never;
|
||||
cur_live.state = IDLE;
|
||||
cur_live.next_state = -1;
|
||||
cur_live.drv_sel = m_drv_sel;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_start - device-specific startup
|
||||
//-------------------------------------------------
|
||||
|
||||
void c8050_fdc_t::device_start()
|
||||
{
|
||||
// resolve callbacks
|
||||
m_write_sync.resolve_safe();
|
||||
m_write_ready.resolve_safe();
|
||||
m_write_error.resolve_safe();
|
||||
|
||||
// allocate timer
|
||||
t_gen = timer_alloc(0);
|
||||
|
||||
// register for state saving
|
||||
save_item(NAME(m_mtr0));
|
||||
save_item(NAME(m_mtr1));
|
||||
save_item(NAME(m_stp0));
|
||||
save_item(NAME(m_stp1));
|
||||
save_item(NAME(m_ds));
|
||||
save_item(NAME(m_drv_sel));
|
||||
save_item(NAME(m_mode_sel));
|
||||
save_item(NAME(m_rw_sel));
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_reset - device-specific reset
|
||||
//-------------------------------------------------
|
||||
|
||||
void c8050_fdc_t::device_reset()
|
||||
{
|
||||
live_abort();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_timer - handler timer events
|
||||
//-------------------------------------------------
|
||||
|
||||
void c8050_fdc_t::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
{
|
||||
live_sync();
|
||||
live_run();
|
||||
}
|
||||
|
||||
floppy_image_device* c8050_fdc_t::get_floppy()
|
||||
{
|
||||
return cur_live.drv_sel ? m_floppy1 : m_floppy0;
|
||||
}
|
||||
|
||||
void c8050_fdc_t::stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp)
|
||||
{
|
||||
if (mtr) return;
|
||||
|
||||
int tracks = 0;
|
||||
|
||||
switch (old_stp)
|
||||
{
|
||||
case 0: if (stp == 1) tracks++; else if (stp == 2) tracks--; break;
|
||||
case 1: if (stp == 3) tracks++; else if (stp == 0) tracks--; break;
|
||||
case 2: if (stp == 0) tracks++; else if (stp == 3) tracks--; break;
|
||||
case 3: if (stp == 2) tracks++; else if (stp == 1) tracks--; break;
|
||||
}
|
||||
|
||||
if (tracks == -1)
|
||||
{
|
||||
floppy->dir_w(1);
|
||||
floppy->stp_w(1);
|
||||
floppy->stp_w(0);
|
||||
}
|
||||
else if (tracks == 1)
|
||||
{
|
||||
floppy->dir_w(0);
|
||||
floppy->stp_w(1);
|
||||
floppy->stp_w(0);
|
||||
}
|
||||
|
||||
old_stp = stp;
|
||||
}
|
||||
|
||||
void c8050_fdc_t::stp0_w(int stp)
|
||||
{
|
||||
if (m_stp0 != stp)
|
||||
{
|
||||
live_sync();
|
||||
this->stp_w(m_floppy0, m_mtr0, m_stp0, stp);
|
||||
checkpoint();
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
void c8050_fdc_t::stp1_w(int stp)
|
||||
{
|
||||
if (m_stp1 != stp)
|
||||
{
|
||||
live_sync();
|
||||
if (m_floppy1) this->stp_w(m_floppy1, m_mtr1, m_stp1, stp);
|
||||
checkpoint();
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
void c8050_fdc_t::ds_w(int ds)
|
||||
{
|
||||
if (m_ds != ds)
|
||||
{
|
||||
live_sync();
|
||||
m_ds = cur_live.ds = ds;
|
||||
checkpoint();
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
void c8050_fdc_t::set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1)
|
||||
{
|
||||
m_floppy0 = floppy0;
|
||||
m_floppy1 = floppy1;
|
||||
}
|
||||
|
||||
void c8050_fdc_t::live_start()
|
||||
{
|
||||
cur_live.tm = machine().time();
|
||||
cur_live.state = RUNNING;
|
||||
cur_live.next_state = -1;
|
||||
|
||||
cur_live.shift_reg = 0;
|
||||
cur_live.shift_reg_write = 0;
|
||||
cur_live.cycle_counter = 0;
|
||||
cur_live.cell_counter = 0;
|
||||
cur_live.bit_counter = 0;
|
||||
cur_live.ds = m_ds;
|
||||
cur_live.drv_sel = m_drv_sel;
|
||||
cur_live.mode_sel = m_mode_sel;
|
||||
cur_live.rw_sel = m_rw_sel;
|
||||
cur_live.pi = m_pi;
|
||||
|
||||
pll_reset(cur_live.tm, attotime::from_double(0));
|
||||
checkpoint_live = cur_live;
|
||||
pll_save_checkpoint();
|
||||
|
||||
live_run();
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_reset(const attotime &when, const attotime clock)
|
||||
{
|
||||
cur_pll.reset(when);
|
||||
cur_pll.set_clock(clock);
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_start_writing(const attotime &tm)
|
||||
{
|
||||
cur_pll.start_writing(tm);
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_commit(floppy_image_device *floppy, const attotime &tm)
|
||||
{
|
||||
cur_pll.commit(floppy, tm);
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_stop_writing(floppy_image_device *floppy, const attotime &tm)
|
||||
{
|
||||
cur_pll.stop_writing(floppy, tm);
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_save_checkpoint()
|
||||
{
|
||||
checkpoint_pll = cur_pll;
|
||||
}
|
||||
|
||||
void c8050_fdc_t::pll_retrieve_checkpoint()
|
||||
{
|
||||
cur_pll = checkpoint_pll;
|
||||
}
|
||||
|
||||
int c8050_fdc_t::pll_get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit)
|
||||
{
|
||||
return cur_pll.get_next_bit(tm, floppy, limit);
|
||||
}
|
||||
|
||||
bool c8050_fdc_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit)
|
||||
{
|
||||
return cur_pll.write_next_bit_prev_cell(bit, tm, floppy, limit);
|
||||
}
|
||||
|
||||
void c8050_fdc_t::checkpoint()
|
||||
{
|
||||
pll_commit(get_floppy(), cur_live.tm);
|
||||
checkpoint_live = cur_live;
|
||||
pll_save_checkpoint();
|
||||
}
|
||||
|
||||
void c8050_fdc_t::rollback()
|
||||
{
|
||||
cur_live = checkpoint_live;
|
||||
pll_retrieve_checkpoint();
|
||||
}
|
||||
|
||||
void c8050_fdc_t::live_sync()
|
||||
{
|
||||
if(!cur_live.tm.is_never()) {
|
||||
if(cur_live.tm > machine().time()) {
|
||||
rollback();
|
||||
live_run(machine().time());
|
||||
pll_commit(get_floppy(), cur_live.tm);
|
||||
} else {
|
||||
pll_commit(get_floppy(), cur_live.tm);
|
||||
if(cur_live.next_state != -1) {
|
||||
cur_live.state = cur_live.next_state;
|
||||
cur_live.next_state = -1;
|
||||
}
|
||||
if(cur_live.state == IDLE) {
|
||||
pll_stop_writing(get_floppy(), cur_live.tm);
|
||||
cur_live.tm = attotime::never;
|
||||
}
|
||||
}
|
||||
cur_live.next_state = -1;
|
||||
checkpoint();
|
||||
}
|
||||
}
|
||||
|
||||
void c8050_fdc_t::live_abort()
|
||||
{
|
||||
if(!cur_live.tm.is_never() && cur_live.tm > machine().time()) {
|
||||
rollback();
|
||||
live_run(machine().time());
|
||||
}
|
||||
|
||||
pll_stop_writing(get_floppy(), cur_live.tm);
|
||||
|
||||
cur_live.tm = attotime::never;
|
||||
cur_live.state = IDLE;
|
||||
cur_live.next_state = -1;
|
||||
|
||||
cur_live.ready = 1;
|
||||
cur_live.sync = 1;
|
||||
cur_live.error = 1;
|
||||
}
|
||||
|
||||
|
||||
void c8050_fdc_t::live_run(const attotime &limit)
|
||||
{
|
||||
if(cur_live.state == IDLE || cur_live.next_state != -1)
|
||||
return;
|
||||
|
||||
for(;;) {
|
||||
switch(cur_live.state) {
|
||||
case RUNNING: {
|
||||
bool syncpoint = false;
|
||||
|
||||
if (cur_live.tm > limit)
|
||||
return;
|
||||
|
||||
int bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
|
||||
if(bit < 0)
|
||||
return;
|
||||
|
||||
if (syncpoint) {
|
||||
live_delay(RUNNING_SYNCPOINT);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case RUNNING_SYNCPOINT: {
|
||||
m_write_ready(cur_live.ready);
|
||||
m_write_sync(cur_live.sync);
|
||||
m_write_error(cur_live.error);
|
||||
|
||||
cur_live.state = RUNNING;
|
||||
checkpoint();
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( c8050_fdc_t::read )
|
||||
{
|
||||
UINT8 e = checkpoint_live.e;
|
||||
offs_t i = checkpoint_live.i;
|
||||
|
||||
UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04);
|
||||
|
||||
if (LOG) logerror("%s VIA reads data %02x (%03x)\n", machine().time().as_string(), data, checkpoint_live.shift_reg);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( c8050_fdc_t::write )
|
||||
{
|
||||
if (m_pi != data)
|
||||
{
|
||||
live_sync();
|
||||
m_pi = cur_live.pi = data;
|
||||
checkpoint();
|
||||
if (LOG) logerror("%s PI %02x\n", machine().time().as_string(), data);
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::drv_sel_w )
|
||||
{
|
||||
if (m_drv_sel != state)
|
||||
{
|
||||
live_sync();
|
||||
m_drv_sel = cur_live.drv_sel = state;
|
||||
checkpoint();
|
||||
if (LOG) logerror("%s DRV SEL %u\n", machine().time().as_string(), state);
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::mode_sel_w )
|
||||
{
|
||||
if (m_mode_sel != state)
|
||||
{
|
||||
live_sync();
|
||||
m_mode_sel = cur_live.mode_sel = state;
|
||||
checkpoint();
|
||||
if (LOG) logerror("%s MODE SEL %u\n", machine().time().as_string(), state);
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::rw_sel_w )
|
||||
{
|
||||
if (m_rw_sel != state)
|
||||
{
|
||||
live_sync();
|
||||
m_rw_sel = cur_live.rw_sel = state;
|
||||
checkpoint();
|
||||
if (LOG) logerror("%s RW SEL %u\n", machine().time().as_string(), state);
|
||||
if (m_rw_sel) {
|
||||
pll_stop_writing(get_floppy(), machine().time());
|
||||
} else {
|
||||
pll_start_writing(machine().time());
|
||||
}
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::mtr0_w )
|
||||
{
|
||||
if (m_mtr0 != state)
|
||||
{
|
||||
live_sync();
|
||||
m_mtr0 = state;
|
||||
if (LOG) logerror("%s MTR0 %u\n", machine().time().as_string(), state);
|
||||
m_floppy0->mon_w(state);
|
||||
checkpoint();
|
||||
|
||||
if (!m_mtr0 || !m_mtr1) {
|
||||
if(cur_live.state == IDLE) {
|
||||
live_start();
|
||||
}
|
||||
} else {
|
||||
live_abort();
|
||||
}
|
||||
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::mtr1_w )
|
||||
{
|
||||
if (m_mtr1 != state)
|
||||
{
|
||||
live_sync();
|
||||
m_mtr1 = state;
|
||||
if (LOG) logerror("%s MTR1 %u\n", machine().time().as_string(), state);
|
||||
if (m_floppy1) m_floppy1->mon_w(state);
|
||||
checkpoint();
|
||||
|
||||
if (!m_mtr0 || !m_mtr1) {
|
||||
if(cur_live.state == IDLE) {
|
||||
live_start();
|
||||
}
|
||||
} else {
|
||||
live_abort();
|
||||
}
|
||||
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::odd_hd_w )
|
||||
{
|
||||
if (m_odd_hd != state)
|
||||
{
|
||||
live_sync();
|
||||
m_odd_hd = cur_live.odd_hd = state;
|
||||
if (LOG) logerror("%s ODD HD %u\n", machine().time().as_string(), state);
|
||||
m_floppy0->ss_w(!state);
|
||||
if (m_floppy1) m_floppy1->ss_w(!state);
|
||||
checkpoint();
|
||||
live_run();
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
|
||||
{
|
||||
// TODO
|
||||
if (LOG) logerror("%s PULL SYNC %u\n", machine().time().as_string(), state);
|
||||
}
|
||||
168
src/emu/bus/ieee488/c8050fdc.h
Normal file
168
src/emu/bus/ieee488/c8050fdc.h
Normal file
@ -0,0 +1,168 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Curt Coder
|
||||
/**********************************************************************
|
||||
|
||||
Commodore 8050 floppy disk controller emulation
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __C8050_FLOPPY__
|
||||
#define __C8050_FLOPPY__
|
||||
|
||||
#include "emu.h"
|
||||
#include "formats/d80_dsk.h"
|
||||
#include "formats/d82_dsk.h"
|
||||
#include "imagedev/floppy.h"
|
||||
#include "machine/fdc_pll.h"
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// INTERFACE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define MCFG_C8050_SYNC_CALLBACK(_write) \
|
||||
devcb = &c8050_fdc_t::set_sync_wr_callback(*device, DEVCB_##_write);
|
||||
|
||||
#define MCFG_C8050_READY_CALLBACK(_write) \
|
||||
devcb = &c8050_fdc_t::set_ready_wr_callback(*device, DEVCB_##_write);
|
||||
|
||||
#define MCFG_C8050_ERROR_CALLBACK(_write) \
|
||||
devcb = &c8050_fdc_t::set_error_wr_callback(*device, DEVCB_##_write);
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> c8050_fdc_t
|
||||
|
||||
class c8050_fdc_t : public device_t
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
template<class _Object> static devcb_base &set_sync_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_sync.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_ready.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_error_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_error.set_callback(object); }
|
||||
|
||||
DECLARE_READ8_MEMBER( read );
|
||||
DECLARE_WRITE8_MEMBER( write );
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( drv_sel_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( mode_sel_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rw_sel_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( mtr0_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( mtr1_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( odd_hd_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
|
||||
|
||||
DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
|
||||
DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; }
|
||||
|
||||
void stp0_w(int stp);
|
||||
void stp1_w(int stp);
|
||||
void ds_w(int ds);
|
||||
|
||||
void set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
// optional information overrides
|
||||
virtual const rom_entry *device_rom_region() const;
|
||||
|
||||
void stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp);
|
||||
|
||||
enum {
|
||||
IDLE,
|
||||
RUNNING,
|
||||
RUNNING_SYNCPOINT
|
||||
};
|
||||
|
||||
struct live_info {
|
||||
attotime tm;
|
||||
int state, next_state;
|
||||
int sync;
|
||||
int ready;
|
||||
int error;
|
||||
int ds;
|
||||
int drv_sel;
|
||||
int mode_sel;
|
||||
int rw_sel;
|
||||
int odd_hd;
|
||||
|
||||
attotime edge;
|
||||
UINT16 shift_reg;
|
||||
int cycle_counter;
|
||||
int cell_counter;
|
||||
int bit_counter;
|
||||
UINT8 e;
|
||||
offs_t i;
|
||||
|
||||
UINT8 pi;
|
||||
UINT16 shift_reg_write;
|
||||
};
|
||||
|
||||
devcb_write_line m_write_sync;
|
||||
devcb_write_line m_write_ready;
|
||||
devcb_write_line m_write_error;
|
||||
|
||||
required_memory_region m_gcr_rom;
|
||||
|
||||
floppy_image_device *m_floppy0;
|
||||
floppy_image_device *m_floppy1;
|
||||
|
||||
int m_mtr0;
|
||||
int m_mtr1;
|
||||
int m_stp0;
|
||||
int m_stp1;
|
||||
int m_ds;
|
||||
int m_drv_sel;
|
||||
int m_mode_sel;
|
||||
int m_rw_sel;
|
||||
int m_odd_hd;
|
||||
UINT8 m_pi;
|
||||
|
||||
attotime m_period;
|
||||
|
||||
live_info cur_live, checkpoint_live;
|
||||
fdc_pll_t cur_pll, checkpoint_pll;
|
||||
emu_timer *t_gen;
|
||||
|
||||
floppy_image_device* get_floppy();
|
||||
|
||||
void live_start();
|
||||
void checkpoint();
|
||||
void rollback();
|
||||
void pll_reset(const attotime &when, const attotime clock);
|
||||
void pll_start_writing(const attotime &tm);
|
||||
void pll_commit(floppy_image_device *floppy, const attotime &tm);
|
||||
void pll_stop_writing(floppy_image_device *floppy, const attotime &tm);
|
||||
int pll_get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit);
|
||||
bool pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit);
|
||||
void pll_save_checkpoint();
|
||||
void pll_retrieve_checkpoint();
|
||||
void live_delay(int state);
|
||||
void live_sync();
|
||||
void live_abort();
|
||||
void live_run(const attotime &limit = attotime::never);
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type C8050_FDC;
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@ -121,6 +121,7 @@ void i6300esb_lpc_device::device_reset()
|
||||
memset(mon_trp_rng, 0, sizeof(mon_trp_rng));
|
||||
mon_trp_msk = 0;
|
||||
nmi_sc = 0;
|
||||
gen_sta = 0x00;
|
||||
}
|
||||
|
||||
void i6300esb_lpc_device::reset_all_mappings()
|
||||
|
||||
@ -240,7 +240,8 @@ READ16_MEMBER( i82875p_host_device::toud_r)
|
||||
WRITE16_MEMBER(i82875p_host_device::toud_w)
|
||||
{
|
||||
COMBINE_DATA(&toud);
|
||||
logerror("%s: toud = %08x\n", tag(), 512*toud);
|
||||
toud &= ~7;
|
||||
logerror("%s: toud = %08x\n", tag(), toud << 16);
|
||||
remap_cb();
|
||||
}
|
||||
|
||||
@ -309,21 +310,27 @@ READ8_MEMBER( i82875p_host_device::capreg2_r)
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void i82875p_host_device::reset_all_mappings()
|
||||
{
|
||||
pci_host_device::reset_all_mappings();
|
||||
|
||||
toud = 0x0400;
|
||||
smram = 0x02;
|
||||
esmramc = 0x38;
|
||||
memset(pam, 0, sizeof(pam));
|
||||
}
|
||||
|
||||
void i82875p_host_device::device_reset()
|
||||
{
|
||||
pci_host_device::device_reset();
|
||||
|
||||
agpm = 0x00;
|
||||
fpllcont = 0x00;
|
||||
memset(pam, 0, sizeof(pam));
|
||||
smram = 0x02;
|
||||
esmramc = 0x38;
|
||||
agpctrl = 0x00000000;
|
||||
apsize = 0x00;
|
||||
attbase = 0x00000000;
|
||||
amtt = 0x10;
|
||||
lptt = 0x10;
|
||||
toud = 0x0400;
|
||||
mchcfg = 0x0000;
|
||||
errcmd = 0x0000;
|
||||
smicmd = 0x0000;
|
||||
@ -406,7 +413,6 @@ void i82875p_host_device::map_extra(UINT64 memory_window_start, UINT64 memory_wi
|
||||
|
||||
if((esmramc & 0x40) && (smram & 0x08))
|
||||
memory_space->install_ram (0xfeda0000, 0xfedbffff, &ram[0x000a0000/4]);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -20,6 +20,8 @@ public:
|
||||
void set_cpu_tag(const char *tag);
|
||||
void set_ram_size(int ram_size);
|
||||
|
||||
virtual void reset_all_mappings();
|
||||
|
||||
virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
|
||||
|
||||
|
||||
@ -63,6 +63,7 @@ pci_device::pci_device(const machine_config &mconfig, device_type type, const ch
|
||||
revision = 0x00;
|
||||
pclass = 0xffffff;
|
||||
subsystem_id = 0xffffffff;
|
||||
is_multifunction_device = false;
|
||||
}
|
||||
|
||||
void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subsystem_id)
|
||||
@ -194,9 +195,14 @@ READ8_MEMBER(pci_device::latency_timer_r)
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void pci_device::set_multifunction_device(bool enable)
|
||||
{
|
||||
is_multifunction_device = enable;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pci_device::header_type_r)
|
||||
{
|
||||
return 0x00;
|
||||
return is_multifunction_device ? 0x80 : 0x00;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pci_device::bist_r)
|
||||
@ -237,10 +243,6 @@ READ8_MEMBER(pci_device::capptr_r)
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void pci_device::scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root)
|
||||
{
|
||||
}
|
||||
|
||||
void pci_device::set_remap_cb(mapper_cb _remap_cb)
|
||||
{
|
||||
remap_cb = _remap_cb;
|
||||
@ -425,6 +427,9 @@ void pci_bridge_device::device_start()
|
||||
|
||||
for(int i=0; i<32*8; i++)
|
||||
if(sub_devices[i]) {
|
||||
if((i & 7) && sub_devices[i & ~7])
|
||||
sub_devices[i & ~7]->set_multifunction_device(true);
|
||||
|
||||
all_devices.append(sub_devices[i]);
|
||||
if(sub_devices[i] != this) {
|
||||
sub_devices[i]->remap_config_cb = cf_cb;
|
||||
@ -449,6 +454,8 @@ void pci_bridge_device::device_reset()
|
||||
|
||||
void pci_bridge_device::reset_all_mappings()
|
||||
{
|
||||
pci_device::reset_all_mappings();
|
||||
|
||||
for(int i=0; i != all_devices.count(); i++)
|
||||
if(all_devices[i] != this)
|
||||
all_devices[i]->reset_all_mappings();
|
||||
@ -784,9 +791,7 @@ void pci_host_device::device_start()
|
||||
memory_window_start = memory_window_end = memory_offset = 0;
|
||||
io_window_start = io_window_end = io_offset = 0;
|
||||
|
||||
for(int i=0; i != all_devices.count(); i++)
|
||||
if(all_devices[i] != this)
|
||||
all_devices[i]->reset_all_mappings();
|
||||
reset_all_mappings();
|
||||
}
|
||||
|
||||
void pci_host_device::device_reset()
|
||||
|
||||
@ -31,6 +31,7 @@ public:
|
||||
pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
|
||||
|
||||
void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subsystem_id);
|
||||
void set_multifunction_device(bool enable);
|
||||
|
||||
virtual void set_remap_cb(mapper_cb _remap_cb);
|
||||
virtual void reset_all_mappings();
|
||||
@ -109,12 +110,11 @@ protected:
|
||||
const UINT8 *expansion_rom;
|
||||
UINT32 expansion_rom_size;
|
||||
UINT32 expansion_rom_base;
|
||||
bool is_multifunction_device;
|
||||
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
static void scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root);
|
||||
|
||||
void skip_map_regs(int count);
|
||||
void add_map(UINT64 size, int flags, address_map_delegate &map);
|
||||
template <typename T> void add_map(UINT64 size, int flags, void (T::*map)(address_map &map, device_t &device), const char *name) {
|
||||
|
||||
@ -99,7 +99,6 @@ private:
|
||||
virtual void machine_reset();
|
||||
required_device<cpu_device> m_maincpu;
|
||||
UINT8 m_io[256];
|
||||
UINT8 m_counter;
|
||||
UINT8 m_6351_addr;
|
||||
};
|
||||
|
||||
|
||||
@ -16,7 +16,7 @@ G?A29 2001 Mocap Boxing
|
||||
G?A30 2002 Tsurugi
|
||||
GMA41 2001 Thrill Drive 2
|
||||
G?A45 2001 Boxing Mania
|
||||
GCB11 2001 Police 911 2 (USA) / Police 24/7 2 (World) / Keisatsukan Shinjuku 24ji 2 (Japan)
|
||||
G*B11 2001 Police 911 2 (USA) / Police 24/7 2 (World) / Keisatsukan Shinjuku 24ji 2 (Japan)
|
||||
G?B33 2001 Mocap Golf
|
||||
G?B41 2001 Jurassic Park 3
|
||||
G?B4x 2002 Xtrial Racing
|
||||
@ -79,9 +79,29 @@ MB81G163222-80 - Fujitsu MB81G163222-80 256k x 32-bit x 2 banks Synchronous Grap
|
||||
ADC0838 - National Semiconductor ADC0838 Serial I/O 8-Bit A/D Converters with Multiplexer Options (SOIC20 @ U13)
|
||||
DS2430 - Dallas DS2430 256-bits 1-Wire EEPROM. Has 256 bits x8 EEPROM (32 bytes), 64 bits x8 (8 bytes)
|
||||
one-time programmable application register and unique factory-lasered and tested 64-bit
|
||||
registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) (TO-92 @ U37)
|
||||
It appears the DS2430 is not protected from reading but the unique silicon serial number isn't
|
||||
included in the 40 byte dump.
|
||||
registration number (8-bit family code + 48-bit serial number + 8-bit CRC) (TO-92 @ U37)
|
||||
The OTP application register on the common DS2430 and the Police 911 2 DS2430 are not programmed
|
||||
(application register reads all 0xFF and the status register reads back 0xFF), so it's probably safe
|
||||
to assume they're not used on any of them.
|
||||
It appears the DS2430 is not protected from reading and the unique silicon serial number is
|
||||
included in the 40 byte dump. In the Police 911 2 NVRAM dump the serial number is located at both 0x002A and 0x1026
|
||||
so that means it is tied to the DS2430. If the serial number in the NVRAM and DS2430 match then they are
|
||||
paired. The same serial number is likely present in the CF card image and a compare is done there too.
|
||||
If they don't match the game requires an external DS2430 (i.e. dongle)
|
||||
When the lasered ROM is read from the DS2430, it comes out from LSB to MSB (family code, LSB of
|
||||
S/N->MSB of S/N, CRC)
|
||||
For Police 911 2 that is 0x14 0xB2 0xB7 0x4A 0x00 0x00 0x00 0x83
|
||||
Family code=0x14
|
||||
S/N=0x0000004AB7B2
|
||||
CRC=0x83
|
||||
In a DS2430 dump, the first 32 bytes is the EEPROM and the lasered ROM is 8 bytes and starts at 0x20h
|
||||
For Police 911 2 that is....
|
||||
00000000h CB 9B 56 EC A0 4C 87 53 51 46 28 E7 00 00 00 74
|
||||
00000010h 30 A9 C7 76 B9 85 A3 43 87 53 50 42 1A E7 FA CF
|
||||
00000020h 14 B2 B7 4A 00 00 00 83
|
||||
It may be possible to hand craft a DS2430 for a dongle-protected version of a game simply by using
|
||||
one of the existing DS2430 dumps and adjusting the serial number found in a dump of the NVRAM to pair them
|
||||
or adjusting the serial number in the NVRAM to match the serial number found in one of the dumped DS2430s.
|
||||
M48T58Y - ST Microelectronics M48T58Y Timekeeper RAM (DIP28 @ U39). When this dies (after 10 year lifespan)
|
||||
the game will complain with error RTC BAD then reset. The data inside the RTC can not be hand created
|
||||
(yet) so to revive the PCB the correct RTC data must be re-programmed to a new RTC and replaced
|
||||
@ -2299,7 +2319,7 @@ ROM_END
|
||||
ROM_START(p9112) /* dongle-protected version */
|
||||
VIPER_BIOS
|
||||
|
||||
ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00) /* plug-in male DIN5 dongle containing a DS2430 */
|
||||
ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00) /* plug-in male DIN5 dongle containing a DS2430. The sticker on the dongle says 'GCB11-UA' */
|
||||
ROM_LOAD("ds2430_p9112.u3", 0x00, 0x28, CRC(d745c6ee) SHA1(065C9D0DF1703B3BBB53A07F4923FDEE3B16F80E))
|
||||
|
||||
ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00) /* M48T58 Timekeeper NVRAM */
|
||||
@ -2564,7 +2584,7 @@ GAME(2001, p911uc, p911, viper, viper, viper_state, vipercf, ROT90, "K
|
||||
GAME(2001, p911kc, p911, viper, viper, viper_state, vipercf, ROT90, "Konami", "Police 911 (ver KAC)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2001, p911e, p911, viper, viper, viper_state, vipercf, ROT90, "Konami", "Police 24/7 (ver EAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2001, p911j, p911, viper, viper, viper_state, vipercf, ROT90, "Konami", "Keisatsukan Shinjuku 24ji (ver JAC)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2001, p9112, kviper, viper, viper, viper_state, vipercf, ROT90, "Konami", "Police 911 2 (ver UAD)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2001, p9112, kviper, viper, viper, viper_state, vipercf, ROT90, "Konami", "Police 911 2 (VER. UAA:B)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2003, popn9, kviper, viper, viper, viper_state, vipercf, ROT0, "Konami", "Pop'n Music 9 (ver JAB)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2001, sscopex, kviper, viper, viper, viper_state, vipercf, ROT0, "Konami", "Silent Scope EX (ver UAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
GAME(2001, sogeki, sscopex, viper, viper, viper_state, vipercf, ROT0, "Konami", "Sogeki (ver JAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
|
||||
|
||||
@ -7,12 +7,16 @@ Excalibur 64 kit computer, designed and sold in Australia by BGR Computers.
|
||||
Skeleton driver created on 2014-12-09.
|
||||
|
||||
Chips: Z80A, 8251, 8253, 8255, 6845
|
||||
We have Basic 1.1. Other known versions are 1.01, 2.1
|
||||
|
||||
Control W then Enter will switch between 40 and 80 characters per line.
|
||||
|
||||
ToDo:
|
||||
- Some keys can be connected to more than one position in the matrix. Need to
|
||||
determine the correct positions.
|
||||
- The position of the "Line Insert" key is unknown.
|
||||
- The video section has attributes and colour, none of this is done.
|
||||
- PCGEN command not working.
|
||||
- Colours are wrong (colour prom needs to be dumped)
|
||||
- Disk controller
|
||||
- Banking
|
||||
- The schematic shows the audio counter connected to 2MHz, but this produces
|
||||
@ -20,6 +24,8 @@ ToDo:
|
||||
- Serial
|
||||
- Parallel / Centronics
|
||||
- Need software
|
||||
- Pasting can drop a character or two at the start of a line.
|
||||
- Clock change for crtc
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
@ -45,10 +51,12 @@ public:
|
||||
, m_palette(*this, "palette")
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_cass(*this, "cassette")
|
||||
, m_crtc(*this, "crtc")
|
||||
, m_io_keyboard(*this, "KEY")
|
||||
{ }
|
||||
|
||||
DECLARE_DRIVER_INIT(excali64);
|
||||
DECLARE_PALETTE_INIT(excali64);
|
||||
DECLARE_WRITE8_MEMBER(ppib_w);
|
||||
DECLARE_READ8_MEMBER(ppic_r);
|
||||
DECLARE_WRITE8_MEMBER(ppic_w);
|
||||
@ -71,6 +79,7 @@ private:
|
||||
bool m_crtc_de;
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<cassette_image_device> m_cass;
|
||||
required_device<mc6845_device> m_crtc;
|
||||
required_ioport_array<8> m_io_keyboard;
|
||||
};
|
||||
|
||||
@ -96,55 +105,45 @@ ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START( excali64 )
|
||||
//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("LINEFEED") PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHAR(0x0a)//H
|
||||
//PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("REPT") PORT_CODE(KEYCODE_LALT)//0x11
|
||||
//PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Down)") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))//B
|
||||
//PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Up)") PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
|
||||
//PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Fire)") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(INSERT))
|
||||
//PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\\ |")PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|') PORT_CHAR(0x1c)
|
||||
//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Right)") PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
|
||||
//PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BRK") PORT_CODE(KEYCODE_NUMLOCK) PORT_CHAR(0x03)
|
||||
//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Left)") PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
|
||||
|
||||
PORT_START("KEY.0") /* line 0 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('R') PORT_CHAR(0x12)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('W') PORT_CHAR(0x17)
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') PORT_CHAR(0x12)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') PORT_CHAR(0x17)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('E') PORT_CHAR(0x05)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') PORT_CHAR(0x05)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CAPSLOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('A') PORT_CHAR(0x01)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('Q') PORT_CHAR(0x11)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') PORT_CHAR(0x01)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') PORT_CHAR(0x11)
|
||||
|
||||
PORT_START("KEY.1") /* line 1 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F3") PORT_CODE(KEYCODE_F3)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F2") PORT_CODE(KEYCODE_F2)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F4") PORT_CODE(KEYCODE_F4)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)//=
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED) // space
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F1") PORT_CODE(KEYCODE_F1)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) // F1
|
||||
|
||||
PORT_START("KEY.2") /* line 2 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(". >") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('M') PORT_CHAR(0x0d)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') PORT_CHAR(0x0d)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(", <") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('B') PORT_CHAR(0x02)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') PORT_CHAR(0x02)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED) //B
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('N') PORT_CHAR(0x0e)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') PORT_CHAR(0x0e)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //N
|
||||
|
||||
PORT_START("KEY.3") /* line 3 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("' \"") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x27) PORT_CHAR(0x22) PORT_CHAR(0x27)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('L') PORT_CHAR(0x0c)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') PORT_CHAR(0x0c)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0d)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("; :") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('J') PORT_CHAR(0x0a)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('G') PORT_CHAR(0x07)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('K') PORT_CHAR(0x0b)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('H') PORT_CHAR(0x08)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') PORT_CHAR(0x0a)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') PORT_CHAR(0x07)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') PORT_CHAR(0x0b)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHAR(0x08)
|
||||
|
||||
PORT_START("KEY.4") /* line 4 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4 $") PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
|
||||
@ -158,22 +157,22 @@ static INPUT_PORTS_START( excali64 )
|
||||
|
||||
PORT_START("KEY.5") /* line 5 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[ {") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{') PORT_CHAR(0x1b)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('O') PORT_CHAR(0x0f)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') PORT_CHAR(0x0f)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("] }") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}') PORT_CHAR(0x1d)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('P') PORT_CHAR(0x10)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('U') PORT_CHAR(0x15)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('T') PORT_CHAR(0x14)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('I') PORT_CHAR(0x09)//0x12
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('Y') PORT_CHAR(0x19)//0x14
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') PORT_CHAR(0x10)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') PORT_CHAR(0x15)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') PORT_CHAR(0x14)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') PORT_CHAR(0x09)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHAR(0x19)
|
||||
|
||||
PORT_START("KEY.6") /* line 6 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('F') PORT_CHAR(0x06)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('X') PORT_CHAR(0x18)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('V') PORT_CHAR(0x16)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('C') PORT_CHAR(0x03)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('D') PORT_CHAR(0x04)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('S') PORT_CHAR(0x13)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('Z') PORT_CHAR(0x1a)
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') PORT_CHAR(0x06)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') PORT_CHAR(0x18)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') PORT_CHAR(0x16)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') PORT_CHAR(0x03)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') PORT_CHAR(0x04)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') PORT_CHAR(0x13)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') PORT_CHAR(0x1a)
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //Z
|
||||
|
||||
PORT_START("KEY.7") /* line 7 */
|
||||
@ -234,11 +233,12 @@ WRITE8_MEMBER( excali64_state::ppic_w )
|
||||
|
||||
/*
|
||||
d0,1,2 : same as port50
|
||||
d7 : 2nd col
|
||||
d3 : 2nd colour set
|
||||
*/
|
||||
WRITE8_MEMBER( excali64_state::port70_w )
|
||||
{
|
||||
m_sys_status = data;
|
||||
m_crtc->set_unscaled_clock(BIT(data, 2) ? 2e6 : 1e6);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( excali64_state::video_w )
|
||||
@ -262,30 +262,105 @@ DRIVER_INIT_MEMBER( excali64_state, excali64 )
|
||||
m_p_videoram = memregion("videoram")->base();
|
||||
}
|
||||
|
||||
/* F4 Character Displayer */
|
||||
static const gfx_layout excali64_charlayout =
|
||||
{
|
||||
8, 12, /* 8 x 12 characters */
|
||||
256, /* 256 characters */
|
||||
1, /* 1 bits per pixel */
|
||||
{ 0 }, /* no bitplanes */
|
||||
/* x offsets */
|
||||
{ 7, 6, 5, 4, 3, 2, 1, 0 },
|
||||
/* y offsets */
|
||||
{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8, 10*8, 11*8 },
|
||||
8*16 /* every char takes 16 bytes */
|
||||
};
|
||||
|
||||
static GFXDECODE_START( excali64 )
|
||||
GFXDECODE_ENTRY( "chargen", 0x0000, excali64_charlayout, 0, 1 )
|
||||
GFXDECODE_END
|
||||
|
||||
// The colour names in the comments are what's needed, the current rgb values are mostly wrong
|
||||
PALETTE_INIT_MEMBER( excali64_state, excali64 )
|
||||
{
|
||||
// Colour Menu A
|
||||
palette.set_pen_color(0, 0x00, 0x00, 0x00); /* 0 Black */
|
||||
palette.set_pen_color(1, 0x7f, 0x00, 0x00); /* 1 Dark Red */
|
||||
palette.set_pen_color(2, 0xff, 0x00, 0x00); /* 2 Red */
|
||||
palette.set_pen_color(3, 0x00, 0x00, 0x00); /* 3 Pink */
|
||||
palette.set_pen_color(4, 0xbf, 0xbf, 0xbf); /* 4 Orange */
|
||||
palette.set_pen_color(5, 0x00, 0xff, 0xff); /* 5 Brown */
|
||||
palette.set_pen_color(6, 0xff, 0xff, 0x00); /* 6 Yellow */
|
||||
palette.set_pen_color(7, 0x7f, 0x7f, 0x00); /* 7 Dark Green */
|
||||
palette.set_pen_color(8, 0x00, 0x7f, 0x00); /* 8 Green */
|
||||
palette.set_pen_color(9, 0x00, 0xff, 0x00); /* 9 Bright Green */
|
||||
palette.set_pen_color(10, 0x00, 0x00, 0xff); /* 10 Light Blue */
|
||||
palette.set_pen_color(11, 0x00, 0x00, 0x7f); /* 11 Blue */
|
||||
palette.set_pen_color(12, 0xff, 0x00, 0xff); /* 12 Magenta */
|
||||
palette.set_pen_color(13, 0x7f, 0x00, 0x7f); /* 13 Purple */
|
||||
palette.set_pen_color(14, 0x80, 0x80, 0x80); /* 14 Dark Grey */
|
||||
palette.set_pen_color(15, 0xff, 0xff, 0xff); /* 15 White */
|
||||
// Colour Menu B
|
||||
palette.set_pen_color(16, 0x00, 0x00, 0x00); /* 0 Black */
|
||||
palette.set_pen_color(17, 0x7f, 0x00, 0x00); /* 1 Dark Red */
|
||||
palette.set_pen_color(18, 0xff, 0x00, 0x00); /* 2 Red */
|
||||
palette.set_pen_color(19, 0x80, 0x80, 0x80); /* 3 Flesh */
|
||||
palette.set_pen_color(20, 0x00, 0x00, 0xff); /* 4 Pink */
|
||||
palette.set_pen_color(21, 0xff, 0xff, 0x80); /* 5 Yellow Brown */
|
||||
palette.set_pen_color(22, 0x00, 0x00, 0x00); /* 6 Dark Brown */
|
||||
palette.set_pen_color(23, 0x00, 0xff, 0x00); /* 7 Dark Purple */
|
||||
palette.set_pen_color(24, 0xff, 0x80, 0xff); /* 8 Very Dark Green */
|
||||
palette.set_pen_color(25, 0x00, 0xff, 0xff); /* 9 Yellow Green */
|
||||
palette.set_pen_color(26, 0xff, 0x40, 0x40); /* 10 Grey Blue */
|
||||
palette.set_pen_color(27, 0xff, 0x00, 0x00); /* 11 Sky Blue */
|
||||
palette.set_pen_color(28, 0x00, 0x80, 0x80); /* 12 Very Pale Blue */
|
||||
palette.set_pen_color(29, 0xff, 0x00, 0xff); /* 13 Dark Grey */
|
||||
palette.set_pen_color(30, 0x80, 0xff, 0x80); /* 14 Light Grey */
|
||||
palette.set_pen_color(31, 0xff, 0xff, 0xff); /* 15 White */
|
||||
// Background
|
||||
palette.set_pen_color(32, 0x00, 0x00, 0x00); // 0 Black
|
||||
palette.set_pen_color(33, 0xff, 0x00, 0x00); // 1 Red
|
||||
palette.set_pen_color(34, 0x00, 0x00, 0xff); // 2 Blue
|
||||
palette.set_pen_color(35, 0xff, 0x00, 0xff); // 3 Magenta
|
||||
palette.set_pen_color(36, 0x00, 0xff, 0x00); // 4 Green
|
||||
palette.set_pen_color(37, 0xff, 0xff, 0x00); // 5 Yellow
|
||||
palette.set_pen_color(38, 0x00, 0xff, 0xff); // 6 Cyan
|
||||
palette.set_pen_color(39, 0xff, 0xff, 0xff); // 7 White
|
||||
|
||||
}
|
||||
|
||||
MC6845_UPDATE_ROW( excali64_state::update_row )
|
||||
{
|
||||
const rgb_t *palette = m_palette->palette()->entry_list_raw();
|
||||
UINT8 chr,gfx;
|
||||
UINT8 chr,gfx,col,bg,fg;
|
||||
UINT16 mem,x;
|
||||
UINT8 col_base = BIT(m_sys_status, 3) ? 16 : 0;
|
||||
UINT32 *p = &bitmap.pix32(y);
|
||||
|
||||
for (x = 0; x < x_count; x++)
|
||||
{
|
||||
UINT8 inv=0;
|
||||
if (x == cursor_x) inv=0xff;
|
||||
mem = (ma + x) & 0xfff;
|
||||
mem = (ma + x) & 0x7ff;
|
||||
chr = m_p_videoram[mem];
|
||||
gfx = m_p_chargen[(chr<<4) | ra] ^ inv;
|
||||
col = m_p_videoram[mem+0x800];
|
||||
fg = col_base + (col >> 4);
|
||||
bg = 32 + ((col >> 1) & 7);
|
||||
|
||||
if (BIT(col, 0) & BIT(chr, 7))
|
||||
gfx = m_p_videoram[0x800 + (chr<<4) + ra]; // hires definition
|
||||
else
|
||||
gfx = m_p_chargen[(chr<<4) | ra]; // normal character
|
||||
|
||||
gfx ^= ((x == cursor_x) ? 0xff : 0);
|
||||
|
||||
/* Display a scanline of a character */
|
||||
*p++ = palette[BIT(gfx, 0)];
|
||||
*p++ = palette[BIT(gfx, 1)];
|
||||
*p++ = palette[BIT(gfx, 2)];
|
||||
*p++ = palette[BIT(gfx, 3)];
|
||||
*p++ = palette[BIT(gfx, 4)];
|
||||
*p++ = palette[BIT(gfx, 5)];
|
||||
*p++ = palette[BIT(gfx, 6)];
|
||||
*p++ = palette[BIT(gfx, 7)];
|
||||
*p++ = palette[BIT(gfx, 0) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 1) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 2) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 3) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 4) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 5) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 6) ? fg : bg];
|
||||
*p++ = palette[BIT(gfx, 7) ? fg : bg];
|
||||
}
|
||||
}
|
||||
|
||||
@ -328,10 +403,13 @@ static MACHINE_CONFIG_START( excali64, excali64_state )
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_REFRESH_RATE(50)
|
||||
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
|
||||
MCFG_SCREEN_SIZE(80*8, 25*10)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 80*8-1, 0, 25*10-1)
|
||||
MCFG_SCREEN_SIZE(80*8, 24*12)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 80*8-1, 0, 24*12-1)
|
||||
MCFG_SCREEN_UPDATE_DEVICE("crtc", mc6845_device, screen_update)
|
||||
MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
|
||||
MCFG_PALETTE_ADD("palette", 40)
|
||||
MCFG_PALETTE_INIT_OWNER(excali64_state, excali64)
|
||||
//MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
|
||||
MCFG_GFXDECODE_ADD("gfxdecode", "palette", excali64)
|
||||
MCFG_MC6845_ADD("crtc", MC6845, "screen", XTAL_16MHz / 16) // 1MHz for lowres; 2MHz for highres
|
||||
MCFG_MC6845_SHOW_BORDER_AREA(false)
|
||||
MCFG_MC6845_CHAR_WIDTH(8)
|
||||
@ -346,16 +424,21 @@ static MACHINE_CONFIG_START( excali64, excali64_state )
|
||||
/* ROM definition */
|
||||
ROM_START( excali64 )
|
||||
ROM_REGION(0x10000, "maincpu", 0)
|
||||
ROM_LOAD( "rom_1.bin", 0x0000, 0x4000, CRC(e129a305) SHA1(e43ec7d040c2b2e548d22fd6bbc7df8b45a26e5a) )
|
||||
ROM_LOAD( "rom_2.bin", 0x2000, 0x2000, CRC(916d9f5a) SHA1(91c527cce963481b7bebf077e955ca89578bb553) )
|
||||
ROM_LOAD( "rom_1.ic17", 0x0000, 0x4000, CRC(e129a305) SHA1(e43ec7d040c2b2e548d22fd6bbc7df8b45a26e5a) )
|
||||
ROM_LOAD( "rom_2.ic24", 0x2000, 0x2000, CRC(916d9f5a) SHA1(91c527cce963481b7bebf077e955ca89578bb553) )
|
||||
// fix a bug that causes screen to be filled with 'p'
|
||||
ROM_FILL(0x4ee, 1, 0)
|
||||
ROM_FILL(0x4ef, 1, 8)
|
||||
ROM_FILL(0x4f6, 1, 0)
|
||||
ROM_FILL(0x4f7, 1, 8)
|
||||
|
||||
ROM_REGION(0x2000, "videoram", ROMREGION_ERASE00)
|
||||
|
||||
ROM_REGION(0x1000, "chargen", 0)
|
||||
ROM_LOAD( "genex_3.bin", 0x0000, 0x1000, CRC(b91619a9) SHA1(2ced636cb7b94ba9d329868d7ecf79963cefe9d9) )
|
||||
ROM_LOAD( "genex_3.ic43", 0x0000, 0x1000, CRC(b91619a9) SHA1(2ced636cb7b94ba9d329868d7ecf79963cefe9d9) )
|
||||
ROM_END
|
||||
|
||||
/* Driver */
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 1984, excali64, 0, 0, excali64, excali64, excali64_state, excali64, "BGR Computers", "Excalibur 64", GAME_IS_SKELETON )
|
||||
COMP( 1984, excali64, 0, 0, excali64, excali64, excali64_state, excali64, "BGR Computers", "Excalibur 64", GAME_NOT_WORKING )
|
||||
|
||||
@ -13,14 +13,13 @@
|
||||
|
||||
TODO:
|
||||
|
||||
- centronics
|
||||
- keyboard
|
||||
- expansion bus
|
||||
- Z80 card
|
||||
- Winchester DMA card (Xebec S1410 + Tandon TM502/TM603SE)
|
||||
- RAM cards
|
||||
- clock cards
|
||||
- floppy 8048
|
||||
- keyboard
|
||||
- hires graphics
|
||||
- brightness/contrast
|
||||
- MC6852
|
||||
@ -41,11 +40,11 @@
|
||||
//-------------------------------------------------
|
||||
|
||||
static ADDRESS_MAP_START( victor9k_mem, AS_PROGRAM, 8, victor9k_state )
|
||||
// AM_RANGE(0x00000, 0xdffff) AM_RAM
|
||||
AM_RANGE(0x00000, 0x1ffff) AM_RAM
|
||||
AM_RANGE(0x20000, 0xdffff) AM_NOP
|
||||
AM_RANGE(0xe0000, 0xe0001) AM_DEVREADWRITE(I8259A_TAG, pic8259_device, read, write)
|
||||
AM_RANGE(0xe0020, 0xe0023) AM_DEVREADWRITE(I8253_TAG, pit8253_device, read, write)
|
||||
AM_RANGE(0xe0040, 0xe0043) AM_DEVREADWRITE(UPD7201_TAG, upd7201_device, cd_ba_r, cd_ba_w)
|
||||
AM_RANGE(0xe0000, 0xe0001) AM_MIRROR(0x7f00) AM_DEVREADWRITE(I8259A_TAG, pic8259_device, read, write)
|
||||
AM_RANGE(0xe0020, 0xe0023) AM_MIRROR(0x7f00) AM_DEVREADWRITE(I8253_TAG, pit8253_device, read, write)
|
||||
AM_RANGE(0xe0040, 0xe0043) AM_MIRROR(0x7f00) AM_DEVREADWRITE(UPD7201_TAG, upd7201_device, cd_ba_r, cd_ba_w)
|
||||
AM_RANGE(0xe8000, 0xe8000) AM_MIRROR(0x7f00) AM_DEVREADWRITE(HD46505S_TAG, mc6845_device, status_r, address_w)
|
||||
AM_RANGE(0xe8001, 0xe8001) AM_MIRROR(0x7f00) AM_DEVREADWRITE(HD46505S_TAG, mc6845_device, register_r, register_w)
|
||||
AM_RANGE(0xe8020, 0xe802f) AM_MIRROR(0x7f00) AM_DEVREADWRITE(M6522_1_TAG, via6522_device, read, write)
|
||||
@ -56,7 +55,7 @@ static ADDRESS_MAP_START( victor9k_mem, AS_PROGRAM, 8, victor9k_state )
|
||||
AM_RANGE(0xe80c0, 0xe80cf) AM_MIRROR(0x7f00) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs6_r, cs6_w)
|
||||
AM_RANGE(0xe80e0, 0xe80ef) AM_MIRROR(0x7f00) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs7_r, cs7_w)
|
||||
AM_RANGE(0xf0000, 0xf0fff) AM_MIRROR(0x1000) AM_RAM AM_SHARE("video_ram")
|
||||
AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION(I8088_TAG, 0)
|
||||
AM_RANGE(0xf8000, 0xf9fff) AM_MIRROR(0x6000) AM_ROM AM_REGION(I8088_TAG, 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -169,7 +168,7 @@ WRITE_LINE_MEMBER( victor9k_state::ssda_irq_w )
|
||||
{
|
||||
m_ssda_irq = state;
|
||||
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
|
||||
}
|
||||
|
||||
|
||||
@ -190,6 +189,17 @@ WRITE8_MEMBER( victor9k_state::via1_pa_w )
|
||||
|
||||
*/
|
||||
|
||||
// centronics
|
||||
m_centronics->write_data0(BIT(data, 0));
|
||||
m_centronics->write_data1(BIT(data, 1));
|
||||
m_centronics->write_data2(BIT(data, 2));
|
||||
m_centronics->write_data3(BIT(data, 3));
|
||||
m_centronics->write_data4(BIT(data, 4));
|
||||
m_centronics->write_data5(BIT(data, 5));
|
||||
m_centronics->write_data6(BIT(data, 6));
|
||||
m_centronics->write_data7(BIT(data, 7));
|
||||
|
||||
// IEEE-488
|
||||
m_ieee488->dio_w(data);
|
||||
}
|
||||
|
||||
@ -211,8 +221,8 @@ WRITE8_MEMBER( victor9k_state::via1_pb_w )
|
||||
|
||||
bit description
|
||||
|
||||
PB0 DAV
|
||||
PB1 EOI
|
||||
PB0 DAV / DATA STROBE
|
||||
PB1 EOI / VFU?
|
||||
PB2 REN
|
||||
PB3 ATN
|
||||
PB4 IFC
|
||||
@ -222,6 +232,9 @@ WRITE8_MEMBER( victor9k_state::via1_pb_w )
|
||||
|
||||
*/
|
||||
|
||||
// centronics
|
||||
m_centronics->write_strobe(BIT(data, 0));
|
||||
|
||||
// IEEE-488
|
||||
m_ieee488->dav_w(BIT(data, 0));
|
||||
m_ieee488->eoi_w(BIT(data, 1));
|
||||
@ -241,7 +254,7 @@ WRITE_LINE_MEMBER( victor9k_state::via1_irq_w )
|
||||
{
|
||||
m_via1_irq = state;
|
||||
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( victor9k_state::via2_pa_w )
|
||||
@ -304,14 +317,6 @@ WRITE_LINE_MEMBER( victor9k_state::write_rib )
|
||||
}
|
||||
|
||||
|
||||
WRITE_LINE_MEMBER( victor9k_state::via2_irq_w )
|
||||
{
|
||||
m_via2_irq = state;
|
||||
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
bit description
|
||||
|
||||
@ -348,7 +353,7 @@ WRITE_LINE_MEMBER( victor9k_state::via3_irq_w )
|
||||
{
|
||||
m_via3_irq = state;
|
||||
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
|
||||
}
|
||||
|
||||
|
||||
@ -359,14 +364,14 @@ WRITE_LINE_MEMBER( victor9k_state::via3_irq_w )
|
||||
WRITE_LINE_MEMBER( victor9k_state::kbrdy_w )
|
||||
{
|
||||
//logerror("KBRDY %u\n", state);
|
||||
m_via2->write_cb1(state);
|
||||
|
||||
m_pic->ir6_w(state ? CLEAR_LINE : ASSERT_LINE);
|
||||
m_via2->write_cb1(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( victor9k_state::kbdata_w )
|
||||
{
|
||||
//logerror("KBDATA %u\n", state);
|
||||
|
||||
m_via2->write_cb2(state);
|
||||
m_via2->write_pa6(state);
|
||||
}
|
||||
@ -376,7 +381,7 @@ WRITE_LINE_MEMBER( victor9k_state::fdc_irq_w )
|
||||
{
|
||||
m_fdc_irq = state;
|
||||
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
|
||||
m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
|
||||
}
|
||||
|
||||
|
||||
@ -390,15 +395,10 @@ void victor9k_state::machine_start()
|
||||
save_item(NAME(m_brt));
|
||||
save_item(NAME(m_cont));
|
||||
save_item(NAME(m_via1_irq));
|
||||
save_item(NAME(m_via2_irq));
|
||||
save_item(NAME(m_via3_irq));
|
||||
save_item(NAME(m_fdc_irq));
|
||||
save_item(NAME(m_ssda_irq));
|
||||
|
||||
// memory banking
|
||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||
program.install_ram(0x00000, m_ram->size() - 1, m_ram->pointer());
|
||||
|
||||
// patch out SCP self test
|
||||
m_rom->base()[0x11ab] = 0xc3;
|
||||
|
||||
@ -422,6 +422,7 @@ void victor9k_state::machine_reset()
|
||||
}
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// MACHINE CONFIGURATION
|
||||
//**************************************************************************
|
||||
@ -446,7 +447,7 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
|
||||
|
||||
MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
|
||||
|
||||
MCFG_MC6845_ADD(HD46505S_TAG, HD6845, SCREEN_TAG, 1000000) // HD6845 == HD46505S
|
||||
MCFG_MC6845_ADD(HD46505S_TAG, HD6845, SCREEN_TAG, XTAL_30MHz/11) // HD6845 == HD46505S
|
||||
MCFG_MC6845_SHOW_BORDER_AREA(true)
|
||||
MCFG_MC6845_CHAR_WIDTH(10)
|
||||
MCFG_MC6845_UPDATE_ROW_CB(victor9k_state, crtc_update_row)
|
||||
@ -501,12 +502,17 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
|
||||
MCFG_DEVICE_ADD(M6522_2_TAG, VIA6522, XTAL_30MHz/30)
|
||||
MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via2_pa_w))
|
||||
MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via2_pb_w))
|
||||
MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via2_irq_w))
|
||||
MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE(I8259A_TAG, pic8259_device, ir6_w))
|
||||
|
||||
MCFG_DEVICE_ADD(M6522_3_TAG, VIA6522, XTAL_30MHz/30)
|
||||
MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via3_pb_w))
|
||||
MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via3_irq_w))
|
||||
|
||||
MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_devices, "printer")
|
||||
MCFG_CENTRONICS_BUSY_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb5))
|
||||
MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb6))
|
||||
MCFG_CENTRONICS_SELECT_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb7))
|
||||
|
||||
MCFG_RS232_PORT_ADD(RS232_A_TAG, default_rs232_devices, NULL)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rxa_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, dcda_w))
|
||||
@ -521,7 +527,7 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, ctsb_w))
|
||||
MCFG_RS232_DSR_HANDLER(DEVWRITELINE(M6522_2_TAG, via6522_device, write_pa5))
|
||||
|
||||
MCFG_DEVICE_ADD(VICTOR9K_KEYBOARD_TAG, VICTOR9K_KEYBOARD, 0)
|
||||
MCFG_DEVICE_ADD(KB_TAG, VICTOR9K_KEYBOARD, 0)
|
||||
MCFG_VICTOR9K_KBRDY_HANDLER(WRITELINE(victor9k_state, kbrdy_w))
|
||||
MCFG_VICTOR9K_KBDATA_HANDLER(WRITELINE(victor9k_state, kbdata_w))
|
||||
|
||||
@ -533,7 +539,6 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
|
||||
// internal ram
|
||||
MCFG_RAM_ADD(RAM_TAG)
|
||||
MCFG_RAM_DEFAULT_SIZE("128K")
|
||||
MCFG_RAM_EXTRA_OPTIONS("256K,384K,512K,640K,768K,896K")
|
||||
|
||||
// software list
|
||||
MCFG_SOFTWARE_LIST_ADD("flop_list", "victor9k_flop")
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#define __VICTOR9K__
|
||||
|
||||
#include "bus/rs232/rs232.h"
|
||||
#include "bus/centronics/ctronics.h"
|
||||
#include "cpu/i86/i86.h"
|
||||
#include "formats/victor9k_dsk.h"
|
||||
#include "imagedev/floppy.h"
|
||||
@ -47,7 +48,7 @@
|
||||
#define RS232_A_TAG "rs232a"
|
||||
#define RS232_B_TAG "rs232b"
|
||||
#define SCREEN_TAG "screen"
|
||||
#define VICTOR9K_KEYBOARD_TAG "victor9kb"
|
||||
#define KB_TAG "kb"
|
||||
#define FDC_TAG "fdc"
|
||||
|
||||
class victor9k_state : public driver_device
|
||||
@ -66,8 +67,9 @@ public:
|
||||
m_cvsd(*this, HC55516_TAG),
|
||||
m_crtc(*this, HD46505S_TAG),
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_kb(*this, VICTOR9K_KEYBOARD_TAG),
|
||||
m_kb(*this, KB_TAG),
|
||||
m_fdc(*this, FDC_TAG),
|
||||
m_centronics(*this, CENTRONICS_TAG),
|
||||
m_rs232a(*this, RS232_A_TAG),
|
||||
m_rs232b(*this, RS232_B_TAG),
|
||||
m_palette(*this, "palette"),
|
||||
@ -76,7 +78,6 @@ public:
|
||||
m_brt(0),
|
||||
m_cont(0),
|
||||
m_via1_irq(CLEAR_LINE),
|
||||
m_via2_irq(CLEAR_LINE),
|
||||
m_via3_irq(CLEAR_LINE),
|
||||
m_fdc_irq(CLEAR_LINE),
|
||||
m_ssda_irq(CLEAR_LINE)
|
||||
@ -95,6 +96,7 @@ public:
|
||||
required_device<ram_device> m_ram;
|
||||
required_device<victor9k_keyboard_device> m_kb;
|
||||
required_device<victor_9000_fdc_t> m_fdc;
|
||||
required_device<centronics_device> m_centronics;
|
||||
required_device<rs232_port_device> m_rs232a;
|
||||
required_device<rs232_port_device> m_rs232b;
|
||||
required_device<palette_device> m_palette;
|
||||
@ -115,7 +117,6 @@ public:
|
||||
DECLARE_WRITE8_MEMBER( via2_pb_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( write_ria );
|
||||
DECLARE_WRITE_LINE_MEMBER( write_rib );
|
||||
DECLARE_WRITE_LINE_MEMBER( via2_irq_w );
|
||||
|
||||
DECLARE_WRITE8_MEMBER( via3_pb_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( via3_irq_w );
|
||||
@ -136,7 +137,6 @@ public:
|
||||
|
||||
/* interrupts */
|
||||
int m_via1_irq;
|
||||
int m_via2_irq;
|
||||
int m_via3_irq;
|
||||
int m_fdc_irq;
|
||||
int m_ssda_irq;
|
||||
|
||||
@ -179,14 +179,14 @@ INPUT_PORTS_START( victor9k_keyboard )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
|
||||
PORT_START("Y6")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R)
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T)
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I)
|
||||
|
||||
PORT_START("Y7")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
@ -288,8 +288,8 @@ victor9k_keyboard_device::victor9k_keyboard_device(const machine_config &mconfig
|
||||
m_kbrdy_handler(*this),
|
||||
m_kbdata_handler(*this),
|
||||
m_y(0),
|
||||
m_kbrdy(1),
|
||||
m_kbdata(1),
|
||||
m_kbrdy(-1),
|
||||
m_kbdata(-1),
|
||||
m_kback(1)
|
||||
{
|
||||
}
|
||||
@ -373,7 +373,7 @@ WRITE8_MEMBER( victor9k_keyboard_device::kb_p1_w )
|
||||
m_y = data & 0x0f;
|
||||
}
|
||||
|
||||
//logerror("P1 %02x\n", data);
|
||||
//logerror("%s P1 %02x\n", machine().describe_context(), data);
|
||||
}
|
||||
|
||||
|
||||
@ -410,7 +410,7 @@ WRITE8_MEMBER( victor9k_keyboard_device::kb_p2_w )
|
||||
m_kbdata_handler(m_kbdata);
|
||||
}
|
||||
|
||||
//logerror("P2 %02x\n", data);
|
||||
//logerror("%s P2 %01x\n", machine().describe_context(), data&0x0f);
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user