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This commit is contained in:
Vas Crabb 2020-07-26 12:56:13 +10:00
parent fab7f87398
commit 60bd3086cc
103 changed files with 4409 additions and 4409 deletions
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54
hash/gba.xml
View File

@ -41517,19 +41517,19 @@ license:CC0
</dataarea>
</part>
</software>
<!-- hacked dumpd of protected games using 'Sintax' protection.
These games have a protection device which locks out certain ranges (and further reads) depending on the otherwised unused
upper address bits. Furthermore there is some kind of bootstrap mechanism to bypass the GBA protection.
The dumps are 'full address range' as to bypass the address lockouts, with the expected data for booting patched in.
These should be replaced with proper dumps of the flash ROM, with the lockout ranges documented and simulated
as things stand they have to be marked as 'bad' as they're not true archival quality dumps.
see http://hhug.me/?post=90 for details
These games have a protection device which locks out certain ranges (and further reads) depending on the otherwised unused
upper address bits. Furthermore there is some kind of bootstrap mechanism to bypass the GBA protection.
The dumps are 'full address range' as to bypass the address lockouts, with the expected data for booting patched in.
These should be replaced with proper dumps of the flash ROM, with the lockout ranges documented and simulated
as things stand they have to be marked as 'bad' as they're not true archival quality dumps.
see http://hhug.me/?post=90 for details
-->
<software name="rayman4">
<description>Rayman IV (Rayman - Sunshine of Trip) (unlicensed) (protection hacked)</description>
@ -41540,7 +41540,7 @@ license:CC0
<rom name="Rayman IV (Rayman - Sunshine of Trip) (Unl) (Eng) [YJ restored].gba" size="0x2000000" crc="d72c620f" sha1="0ef17374ee28f903127493bf47c14971aa6ed0b8" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="rayman4r" cloneof="rayman4">
<description>Rayman IV (Rayman - Puteshestviye Solnechnogo Sveta) (unlicensed) (Russian) (protection hacked)</description>
@ -41574,7 +41574,7 @@ license:CC0
<rom name="Super Mario DX (Unl) (Eng) [YJ restored].gba" size="0x2000000" crc="9255c170" sha1="2b7dce921497e10b43083040bc7a596369fc1b0e" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="chaojim" cloneof="smariodx">
<description>Chaoji Maliou DX (unlicensed) (Chinese) (protection hacked)</description>
@ -41608,7 +41608,7 @@ license:CC0
</dataarea>
</part>
</software>
<software name="poksaph"> <!-- unlicensed translation -->
<description>Pokemon - Sapphire Version (unlicensed) (protection hacked)</description>
<year>200?</year>
@ -41618,8 +41618,8 @@ license:CC0
<rom name="Pokemon - Sapphire Version (Unl) (Eng) [YJ restored].gba" size="0x2000000" crc="86a602ab" sha1="14051d159d7a1266b5bfecbfd52722fd3e0711bf" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="sonic3fs">
<description>Sonic 3 - Fighter Sonic (unlicensed) (protection hacked)</description>
<year>200?</year>
@ -41629,8 +41629,8 @@ license:CC0
<rom name="Sonic 3 - Fighter Sonic (Unl) (Eng) [YJ restored].gba" size="0x2000000" crc="8e0a9112" sha1="b3855ceae35152b8a98c882777f040ac2aa93926" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="tmnturt2">
<description>Teenage Mutant Ninja Turtles 2 (unlicensed) (protection hacked)</description>
<year>200?</year>
@ -41640,8 +41640,8 @@ license:CC0
<rom name="Teenage Mutant Ninja Turtles 2 (Unl) (Eng) [YJ restored].gba" size="0x2000000" crc="8ee6d3d5" sha1="cbcb99b4ee34d6d83c898a09083a655f7f9eecb1" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="lotr4">
<description>The Lord of the Rings IV - The Fellowship of the Ring (unlicensed) (protection hacked)</description>
<year>200?</year>
@ -41651,8 +41651,8 @@ license:CC0
<rom name="The Lord of the Rings IV - The Fellowship of the Ring (Unl) (Eng) [YJ restored].gba" size="0x2000000" crc="09c7c895" sha1="bf5f2ec4e7c7df834be9911d217af0d4490e3722" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="ultcje">
<description>Ultraman - Confrontation Between Justice And Evil (Ul'traman - Konfrontatsiya mezhdu spravedlivost'yu i zlom) (unlicensed) (Russian) (protection hacked)</description>
<year>200?</year>
@ -41662,8 +41662,8 @@ license:CC0
<rom name="Ultraman - Confrontation Between Justice And Evil (Unl) (Rus) [YJ restored].gba" size="0x2000000" crc="4683dbb5" sha1="08a9530ce82a76e1be5e408ae99bdd90c42748e9" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="xmanam">
<description>X-Man - Armour of Might (X-men) (unlicensed) (Russian) (protection hacked)</description>
<year>200?</year>
@ -41673,6 +41673,6 @@ license:CC0
<rom name="X-Man - Armour of Might (X-men) (Unl) (Rus) [YJ restored].gba" size="0x2000000" crc="e14c9b78" sha1="a894acc460efc9b9b03a7ce55e5a860b64473e13" status="baddump" />
</dataarea>
</part>
</software>
</software>
</softwarelist>

14
hash/ibm5150.xml
View File

@ -8175,7 +8175,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="bloodwyca" cloneof="bloodwyc">
<description>Bloodwych (Quest &amp; Glory Compilation) (Euro)</description>
<year>1991</year>
@ -8187,7 +8187,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="bluesbro">
<!-- Dumped via Kryoflux -->
<description>The Blues Brothers</description>
@ -8679,7 +8679,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="laurabw35" cloneof="laurabow">
<description>The Colonel's Bequest (3.5")</description>
<year>1989</year>
@ -8707,7 +8707,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="colossus4">
<description>Colossus Bridge 4</description>
<year>1988</year>
@ -10193,7 +10193,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="lsl2">
<description>Leisure Suit Larry Goes Looking for Love (in Several Wrong Places) (5.25")</description>
<year>1989</year>
@ -10865,7 +10865,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="martmemo">
<description>Martian Memorandum</description>
<year>1991</year>
@ -13108,7 +13108,7 @@ has been replaced with an all-zero block. -->
</dataarea>
</part>
</software>
<software name="ums2pe">
<description>UMS II: Nations at War - Planet Editor</description>
<year>1992</year>

6
hash/mobigo_cart.xml
View File

@ -535,7 +535,7 @@ license:CC0
</dataarea>
</part>
</software>
<!-- these have downloaded games on them, they do however appear to be tied to the machine that downloaded them, on other units they appear as blank -->
<software name="user1" supported="no">
<description>NAND User Cartridge (unknown data, set 1)</description>
@ -546,7 +546,7 @@ license:CC0
<rom name="80-201401.bin" size="0x8400000" crc="ea99f4d7" sha1="a9f8a7f05de21d971895e3385621112461a0a339"/>
</dataarea>
</part>
</software>
</software>
<software name="user2" supported="no">
<description>NAND User Cartridge (unknown data, set 2)</description>
@ -558,6 +558,6 @@ license:CC0
<rom name="80-201404_Console.bin" size="0x8400000" crc="ed3388f5" sha1="583d7eab0bf2a0e9bb90a28d1fdda701f0a7f32b"/>
</dataarea>
</part>
</software>
</software>
</softwarelist>

4
hash/sgi_mips_hdd.xml
View File

@ -9,9 +9,9 @@ license:CC0
IRIX requires a valid eaddr and high resolution mode. Before first boot,
enter the PROM command monitor and check printenv. If required settings are
missing, run
setenv -f eaddr 08:00:69:12:34:56
setenv -f eaddr 08:00:69:12:34:56
to set the Ethernet interface address, and
setenv monitor h
setenv monitor h
to enable high resolution mode (1280x1024), then power cycle.
Unless otherwise specified, all images are based on default installs of the

2
hash/tvgogo.xml
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@ -115,7 +115,7 @@ _(EU)__|__(US)__|____________|_____________________________________
</dataarea>
</part>
</software>
<software name="basketbalu" cloneof="basketbal" supported="no">
<description>Basketball (US)</description>
<year>2005</year>

4
hash/ut88.xml
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@ -22,8 +22,8 @@ These are for ut88 only - not for ut88mini
</software>
<!-- The only way to use this is to start in the debugger and load and run cpm256. Then g f800 to get back to the monitor.
Then load this tape in the usual manner, then G 100. It will start and expect to load another tape, but after that it
hangs. What is it supposed to do? -->
Then load this tape in the usual manner, then G 100. It will start and expect to load another tape, but after that it
hangs. What is it supposed to do? -->
<software name="chscom">
<description>Changer (v1.1) (CP/M)</description>
<year>19??</year>

6
hash/vsmilem_cart.xml
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@ -1012,8 +1012,8 @@ Language:
<rom name="vmotion80-084300.bin" size="0x0800000" crc="4d0dd939" sha1="b5411b036fa91daf56f654be4ce71b4ac15541ca" />
</dataarea>
</part>
</software>
</software>
<software name="soccerchmg" cloneof="soccerchm">
<description>Fußball Meisterschaft (Germany)</description>
<year>20??</year>
@ -1333,5 +1333,5 @@ Language:
</dataarea>
</part>
</software>
</softwarelist>

2
src/devices/bus/centronics/samdac.cpp
View File

@ -76,7 +76,7 @@ WRITE_LINE_MEMBER( centronics_samdac_device::input_strobe )
// raising edge, write to left channel
if (m_strobe == 0 && state == 1)
m_dac[0]->data_w(m_data[0]);
// failing edge, write to right channel
if (m_strobe == 1 && state == 0)
m_dac[1]->data_w(m_data[1]);

34
src/devices/bus/samcoupe/drive/drive.h
View File

@ -4,24 +4,24 @@
SAM Coupe Drive Slot
32-pin slot
32-pin slot
1A 0 VOLTS 1B WR
2A 0 VOLTS 2B A0
3A 0 VOLTS 3B A1
4A 0 VOLTS 4B D0
5A 0 VOLTS 5B D1
6A 0 VOLTS 6B D2
7A 0 VOLTS 7B D3
8A 0 VOLTS 8B D4
9A 0 VOLTS 9B D5
10A 0 VOLTS 10B D6
11A 0 VOLTS 11B D7
12A 0 VOLTS 12B 8 MHz
13A 0 VOLTS 13B RST
14A 0 VOLTS 14B N/C
15A 0 VOLTS 15B A2
16A 0 VOLTS 16B DISK 1 OR DISK 2
1A 0 VOLTS 1B WR
2A 0 VOLTS 2B A0
3A 0 VOLTS 3B A1
4A 0 VOLTS 4B D0
5A 0 VOLTS 5B D1
6A 0 VOLTS 6B D2
7A 0 VOLTS 7B D3
8A 0 VOLTS 8B D4
9A 0 VOLTS 9B D5
10A 0 VOLTS 10B D6
11A 0 VOLTS 11B D7
12A 0 VOLTS 12B 8 MHz
13A 0 VOLTS 13B RST
14A 0 VOLTS 14B N/C
15A 0 VOLTS 15B A2
16A 0 VOLTS 16B DISK 1 OR DISK 2
***************************************************************************/

66
src/devices/bus/samcoupe/expansion/expansion.h
View File

@ -4,40 +4,40 @@
SAM Coupe Expansion Slot
64-pin slot
64-pin slot
1A DBDIR 1C IORQL
2A RDL 2C MREQL
3A WRL 3C HALTL
4A BUSAKL 4C NMIL
5A WAITL 5C INTL
6A BUSREQL 6C CD1
7A RESETL 7C CD0
8A CM1L 8C CD7
9A REFRESHL 9C CD2
10A 0 VOLTS 10C +5 VOLTS
11A A0 11C CD6
12A A1 12C CD5
13A A2 13C CD3
14A A3 14C CD4
15A A4 15C CPU CLK
16A A5 16C A15
17A A6 17C A14
18A A7 18C A13
19A A8 19C A12
20A A9 20C A11
21A A10 21C DISK 2L
22A MSEINTL 22C ROMCSL
23A XMEML 23C EARMIC
24A 8 MHz 24C DISK 1L
25A RED 1 25C PRINTL
26A GREEN 1 26C BLUE 1
27A C SYNC 27C ROMCSRL
28A SPEN 28C AUDIO RIGHT
29A BLUE 0 29C AUDIO LEFT
30A RED 0 30C COMP VIDEO
31A BRIGHT 31C GREEN 0
32A +5 VOLTS 32C 0 VOLTS
1A DBDIR 1C IORQL
2A RDL 2C MREQL
3A WRL 3C HALTL
4A BUSAKL 4C NMIL
5A WAITL 5C INTL
6A BUSREQL 6C CD1
7A RESETL 7C CD0
8A CM1L 8C CD7
9A REFRESHL 9C CD2
10A 0 VOLTS 10C +5 VOLTS
11A A0 11C CD6
12A A1 12C CD5
13A A2 13C CD3
14A A3 14C CD4
15A A4 15C CPU CLK
16A A5 16C A15
17A A6 17C A14
18A A7 18C A13
19A A8 19C A12
20A A9 20C A11
21A A10 21C DISK 2L
22A MSEINTL 22C ROMCSL
23A XMEML 23C EARMIC
24A 8 MHz 24C DISK 1L
25A RED 1 25C PRINTL
26A GREEN 1 26C BLUE 1
27A C SYNC 27C ROMCSRL
28A SPEN 28C AUDIO RIGHT
29A BLUE 0 29C AUDIO LEFT
30A RED 0 30C COMP VIDEO
31A BRIGHT 31C GREEN 0
32A +5 VOLTS 32C 0 VOLTS
***************************************************************************/

18
src/devices/bus/samcoupe/mouse/mouseport.h
View File

@ -4,16 +4,16 @@
SAM Coupe Mouse Port
8-pin connector
8-pin connector
1 K3
2 K2
3 K1
4 K5
5 K4
6 MSEINT
7 RDMSEL
8 5V
1 K3
2 K2
3 K1
4 K5
5 K4
6 MSEINT
7 RDMSEL
8 5V
***************************************************************************/

6
src/devices/bus/spectrum/floppyone.cpp
View File

@ -8,7 +8,7 @@
FD1791-based floppy drive and printer interface with 4K RAM and 8K ROM
Was mainly designed as tape replacement, and sort of emulate how tapes works,
which allows to copy and use most of existing software and (not protected) games with no modification.
Doube-side drives considered as 2 separate floppies (0 and 4, 1 and 5 etc) probably to mimic tape sides A/B,
disks is password protected.
@ -20,7 +20,7 @@
SAVE "name" - save program
!FORMAT "diskname";"password";tracks - format disk, if disk was already formatted you'll be prompted for password.
!6=n - set text mode, 0 - regular 32-column, 3 - 64-column
!B=rs232delay, 0=use parallel printer (default)
!B=rs232delay, 0=use parallel printer (default)
There is more of special "!x=n" commands, but theirs functions is not known, manual is missing.
Some information about this device https://worldofspectrum.org/forums/discussion/42944/rocky-gush-floppy-drive-interface/p1
@ -114,7 +114,7 @@ void spectrum_flpone_device::device_add_mconfig(machine_config &config)
{
FD1791(config, m_fdc, 1_MHz_XTAL);
FLOPPY_CONNECTOR(config, "fdc:0", flpone_floppies, "525qd", spectrum_flpone_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:0", flpone_floppies, "525qd", spectrum_flpone_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:1", flpone_floppies, "525qd", spectrum_flpone_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:2", flpone_floppies, nullptr, spectrum_flpone_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:3", flpone_floppies, nullptr, spectrum_flpone_device::floppy_formats).enable_sound(true);

6
src/devices/bus/spectrum/floppyone.h
View File

@ -2,8 +2,8 @@
// copyright-holders:MetalliC
/*********************************************************************
FloppyOne DOS Interface
(c) 1984/5 R.P.Gush
FloppyOne DOS Interface
(c) 1984/5 R.P.Gush
*********************************************************************/
#ifndef MAME_BUS_SPECTRUM_FLPONE_H
@ -31,7 +31,7 @@ public:
spectrum_flpone_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
DECLARE_FLOPPY_FORMATS(floppy_formats);
DECLARE_INPUT_CHANGED_MEMBER(snapshot_button) { m_slot->nmi_w(newval ? ASSERT_LINE : CLEAR_LINE); };
DECLARE_INPUT_CHANGED_MEMBER(snapshot_button) { m_slot->nmi_w(newval ? ASSERT_LINE : CLEAR_LINE); };
protected:
// device-level overrides

10
src/devices/bus/spectrum/kempdisc.cpp
View File

@ -14,7 +14,7 @@
COPY - tape to disc transfer utility
FORMAT "discname": PRINT drive#, tracks#, sides#, steprate - format disc
Manual https://archive.org/download/World_of_Spectrum_June_2017_Mirror/World%20of%20Spectrum%20June%202017%20Mirror.zip/World%20of%20Spectrum%20June%202017%20Mirror/sinclair/hardware-info/k/KempstonDiscInterface_Manual.pdf
Manual https://archive.org/download/World_of_Spectrum_June_2017_Mirror/World%20of%20Spectrum%20June%202017%20Mirror.zip/World%20of%20Spectrum%20June%202017%20Mirror/sinclair/hardware-info/k/KempstonDiscInterface_Manual.pdf
Notes/TODO:
- schematics is missing, actual I/O ports decode might be not right
@ -79,7 +79,7 @@ void spectrum_kempdisc_device::device_add_mconfig(machine_config &config)
{
WD1770(config, m_fdc, 16_MHz_XTAL / 2);
FLOPPY_CONNECTOR(config, "fdc:0", kempdisc_floppies, "525qd", spectrum_kempdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:0", kempdisc_floppies, "525qd", spectrum_kempdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:1", kempdisc_floppies, "525qd", spectrum_kempdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:2", kempdisc_floppies, nullptr, spectrum_kempdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:3", kempdisc_floppies, nullptr, spectrum_kempdisc_device::floppy_formats).enable_sound(true);
@ -111,7 +111,7 @@ spectrum_kempdisc_device::spectrum_kempdisc_device(const machine_config &mconfig
, m_fdc(*this, "fdc")
, m_floppy(*this, "fdc:%u", 0)
, m_exp(*this, "exp")
// , m_control(0)
// , m_control(0)
{
}
@ -122,7 +122,7 @@ spectrum_kempdisc_device::spectrum_kempdisc_device(const machine_config &mconfig
void spectrum_kempdisc_device::device_start()
{
save_item(NAME(m_romcs));
// save_item(NAME(m_control));
// save_item(NAME(m_control));
}
//-------------------------------------------------
@ -175,7 +175,7 @@ void spectrum_kempdisc_device::iorq_w(offs_t offset, uint8_t data)
break;
}
// m_control = data;
// m_control = data;
m_fdc->set_floppy(floppy);
if (floppy) floppy->ss_w(BIT(data, 0));
if (data & 0xe0)

2
src/devices/bus/spectrum/kempdisc.h
View File

@ -56,7 +56,7 @@ protected:
required_device<spectrum_expansion_slot_device> m_exp;
int m_romcs;
// u8 m_control;
// u8 m_control;
};

4
src/devices/bus/spectrum/logitek.h
View File

@ -2,8 +2,8 @@
// copyright-holders:MetalliC
/*********************************************************************
Proceed 1 Interface
(c) 1984 Logitek
Proceed 1 Interface
(c) 1984 Logitek
*********************************************************************/
#ifndef MAME_BUS_SPECTRUM_LOGITEK_H

2
src/devices/bus/spectrum/sdi.cpp
View File

@ -1,4 +1,4 @@
// license:BSD-3-Clause
// license:BSD-3-Clause
// copyright-holders:MetalliC
/*********************************************************************

2
src/devices/bus/spectrum/sixword.cpp
View File

@ -150,7 +150,7 @@ void spectrum_swiftdisc_device::device_add_mconfig(machine_config &config)
m_fdc->intrq_wr_callback().set(DEVICE_SELF_OWNER, FUNC(spectrum_expansion_slot_device::nmi_w));
m_fdc->drq_wr_callback().set(DEVICE_SELF_OWNER, FUNC(spectrum_expansion_slot_device::nmi_w));
FLOPPY_CONNECTOR(config, "fdc:0", swiftdisc_floppies, "35dd", spectrum_swiftdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:0", swiftdisc_floppies, "35dd", spectrum_swiftdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:1", swiftdisc_floppies, "35dd", spectrum_swiftdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:2", swiftdisc_floppies, nullptr, spectrum_swiftdisc_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:3", swiftdisc_floppies, nullptr, spectrum_swiftdisc_device::floppy_formats).enable_sound(true);

2
src/devices/bus/spectrum/sixword.h
View File

@ -2,7 +2,7 @@
// copyright-holders:MetalliC
/*********************************************************************
SIXWORD Swift Disc Interface
SIXWORD Swift Disc Interface
*********************************************************************/
#ifndef MAME_BUS_SPECTRUM_SIXWORD_H

2
src/devices/bus/spectrum/speccydos.cpp
View File

@ -103,7 +103,7 @@ void spectrum_speccydos_device::device_add_mconfig(machine_config &config)
{
WD1770(config, m_fdc, 8_MHz_XTAL);
FLOPPY_CONNECTOR(config, "fdc:0", speccydos_floppies, "525dsqd", spectrum_speccydos_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:0", speccydos_floppies, "525dsqd", spectrum_speccydos_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:1", speccydos_floppies, "525dsqd", spectrum_speccydos_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:2", speccydos_floppies, nullptr, spectrum_speccydos_device::floppy_formats).enable_sound(true);
FLOPPY_CONNECTOR(config, "fdc:3", speccydos_floppies, nullptr, spectrum_speccydos_device::floppy_formats).enable_sound(true);

4
src/devices/cpu/gigatron/gigatron.cpp
View File

@ -115,7 +115,7 @@ void gigatron_cpu_device::device_start()
m_outx_cb.resolve_safe();
m_out_cb.resolve_safe();
m_ir_cb.resolve_safe(0);
reset_cpu();
}
@ -127,7 +127,7 @@ void gigatron_cpu_device::reset_cpu()
m_pc = 0;
m_npc = (m_pc + 1) & m_romMask;
m_ppc = 0;
m_inReg = 0xFF;
m_inReg = 0xFF;
m_outx = 0;
m_out = 0;
}

2
src/devices/cpu/gigatron/gigatron.h
View File

@ -50,7 +50,7 @@ protected:
// device_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
void reset_cpu();
void branchOp(uint8_t op, uint8_t mode, uint8_t bus, uint8_t d);

4
src/devices/machine/6821pia.cpp
View File

@ -229,7 +229,7 @@ uint8_t pia6821_device::get_in_a_value()
port_a_data = 0xff;
if (!m_logged_port_a_not_connected && (m_ddr_a != 0xff) &&
!machine().side_effects_disabled())
!machine().side_effects_disabled())
{
logerror("Warning! No port A read handler. Assuming pins 0x%02X not connected\n", m_ddr_a ^ 0xff);
m_logged_port_a_not_connected = true;
@ -279,7 +279,7 @@ uint8_t pia6821_device::get_in_b_value()
else
{
if (!m_logged_port_b_not_connected && (m_ddr_b != 0xff)
&& !machine().side_effects_disabled())
&& !machine().side_effects_disabled())
{
logerror("Error! No port B read handler. Three-state pins 0x%02X are undefined\n", m_ddr_b ^ 0xff);
m_logged_port_b_not_connected = true;

36
src/devices/machine/ibm21s850.cpp
View File

@ -12,12 +12,12 @@
#include "emu.h"
#include "ibm21s850.h"
#define LOG_READS (1 << 1)
#define LOG_WRITES (1 << 2)
#define LOG_UNKNOWNS (1 << 3)
#define LOG_ALL (LOG_READS | LOG_WRITES | LOG_UNKNOWNS)
#define LOG_READS (1 << 1)
#define LOG_WRITES (1 << 2)
#define LOG_UNKNOWNS (1 << 3)
#define LOG_ALL (LOG_READS | LOG_WRITES | LOG_UNKNOWNS)
#define VERBOSE (LOG_ALL)
#define VERBOSE (LOG_ALL)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(IBM21S850, ibm21s850_device, "ibm21s850", "IBM 21S850 IEEE-1394 1-Port PHY")
@ -52,12 +52,12 @@ void ibm21s85x_base_device::device_reset()
{
memset(m_regs, 0, 0x10);
m_regs[ROOT_OFFS] |= ROOT_MASK; // Root node
m_regs[GAP_COUNT_OFFS] |= 0x3f; // Initial reset value
m_regs[SPEED_OFFS] |= SPEED_400MBIT << SPEED_SHIFT; // 21S850 and 21S851 both indicate maximum 400Mb/s rate
m_regs[ENHANCED_REGS_OFFS] |= ENHANCED_REGS_MASK; // 21S850 and 21S851 both have an enhanced register map
m_regs[CABLE_PWR_OFFS] |= CABLE_PWR_MASK; // Cable is powered
m_regs[CONNECTION1_OFFS] |= CONNECTION1_MASK; // Port 1 connected
m_regs[ROOT_OFFS] |= ROOT_MASK; // Root node
m_regs[GAP_COUNT_OFFS] |= 0x3f; // Initial reset value
m_regs[SPEED_OFFS] |= SPEED_400MBIT << SPEED_SHIFT; // 21S850 and 21S851 both indicate maximum 400Mb/s rate
m_regs[ENHANCED_REGS_OFFS] |= ENHANCED_REGS_MASK; // 21S850 and 21S851 both have an enhanced register map
m_regs[CABLE_PWR_OFFS] |= CABLE_PWR_MASK; // Cable is powered
m_regs[CONNECTION1_OFFS] |= CONNECTION1_MASK; // Port 1 connected
m_regs[ARB_PHASE_OFFS] |= PHASE_BUS_RESET << ARB_PHASE_OFFS; // Power up in Bus Reset phase
power_on_reset();
@ -67,18 +67,18 @@ void ibm21s850_device::device_reset()
{
ibm21s85x_base_device::device_reset();
m_regs[NUM_PORTS_OFFS] |= 0x01; // 1 port available
m_regs[ENV_OFFS] |= 1 << ENV_SHIFT; // Cable PHY environment
m_regs[REG_COUNT_OFFS] |= 0x09; // 9 registers following the standard block on 21S850
m_regs[NUM_PORTS_OFFS] |= 0x01; // 1 port available
m_regs[ENV_OFFS] |= 1 << ENV_SHIFT; // Cable PHY environment
m_regs[REG_COUNT_OFFS] |= 0x09; // 9 registers following the standard block on 21S850
}
void ibm21s851_device::device_reset()
{
ibm21s85x_base_device::device_reset();
m_regs[NUM_PORTS_OFFS] |= 0x03; // 3 port available
m_regs[ENV_OFFS] |= 1 << ENV_SHIFT; // Cable PHY environment
m_regs[REG_COUNT_OFFS] |= 0x0b; // 11 registers following the standard block on 21S851
m_regs[NUM_PORTS_OFFS] |= 0x03; // 3 port available
m_regs[ENV_OFFS] |= 1 << ENV_SHIFT; // Cable PHY environment
m_regs[REG_COUNT_OFFS] |= 0x0b; // 11 registers following the standard block on 21S851
}
void ibm21s85x_base_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
@ -163,4 +163,4 @@ void ibm21s85x_base_device::write(offs_t offset, uint8_t data)
m_regs[offset] = data;
break;
}
}
}

234
src/devices/machine/ibm21s850.h
View File

@ -38,101 +38,101 @@ protected:
enum : uint32_t
{
PHYSICAL_ID_OFFS = 0,
PHYSICAL_ID_SHIFT = 2,
PHYSICAL_ID_MASK = 0xfc,
ROOT_OFFS = 0,
ROOT_MASK = 0x02,
CABLE_PWR_OFFS = 0,
CABLE_PWR_MASK = 0x01,
PHYSICAL_ID_OFFS = 0,
PHYSICAL_ID_SHIFT = 2,
PHYSICAL_ID_MASK = 0xfc,
ROOT_OFFS = 0,
ROOT_MASK = 0x02,
CABLE_PWR_OFFS = 0,
CABLE_PWR_MASK = 0x01,
ROOT_HOLD_OFFS = 1,
ROOT_HOLD_MASK = 0x80,
BUS_RESET_OFFS = 1,
BUS_RESET_MASK = 0x40,
GAP_COUNT_OFFS = 1,
GAP_COUNT_MASK = 0x3f,
ROOT_HOLD_OFFS = 1,
ROOT_HOLD_MASK = 0x80,
BUS_RESET_OFFS = 1,
BUS_RESET_MASK = 0x40,
GAP_COUNT_OFFS = 1,
GAP_COUNT_MASK = 0x3f,
SPEED_OFFS = 2,
SPEED_SHIFT = 6,
SPEED_MASK = 0xc0,
ENHANCED_REGS_OFFS = 2,
ENHANCED_REGS_MASK = 0x20,
NUM_PORTS_OFFS = 2,
NUM_PORTS_MASK = 0x1f,
SPEED_100MBIT = 0,
SPEED_200MBIT = 1,
SPEED_400MBIT = 2,
SPEED_RESERVED = 3,
SPEED_OFFS = 2,
SPEED_SHIFT = 6,
SPEED_MASK = 0xc0,
ENHANCED_REGS_OFFS = 2,
ENHANCED_REGS_MASK = 0x20,
NUM_PORTS_OFFS = 2,
NUM_PORTS_MASK = 0x1f,
SPEED_100MBIT = 0,
SPEED_200MBIT = 1,
SPEED_400MBIT = 2,
SPEED_RESERVED = 3,
ASTAT1_OFFS = 3,
ASTAT1_SHIFT = 6,
ASTAT1_MASK = 0xc0,
BSTAT1_OFFS = 3,
BSTAT1_SHIFT = 4,
BSTAT1_MASK = 0x30,
CHILD1_OFFS = 3,
CHILD1_MASK = 0x08,
CONNECTION1_OFFS = 3,
CONNECTION1_MASK = 0x04,
PEER_SPEED1_OFFS = 3,
PEER_SPEED1_MASK = 0x03,
ASTAT1_OFFS = 3,
ASTAT1_SHIFT = 6,
ASTAT1_MASK = 0xc0,
BSTAT1_OFFS = 3,
BSTAT1_SHIFT = 4,
BSTAT1_MASK = 0x30,
CHILD1_OFFS = 3,
CHILD1_MASK = 0x08,
CONNECTION1_OFFS = 3,
CONNECTION1_MASK = 0x04,
PEER_SPEED1_OFFS = 3,
PEER_SPEED1_MASK = 0x03,
LPS_OFFS = 11,
LPS_MASK = 0x80,
PHY_DELAY_OFFS = 11,
PHY_DELAY_SHIFT = 5,
PHY_DELAY_MASK = 0x60,
LPS_OFFS = 11,
LPS_MASK = 0x80,
PHY_DELAY_OFFS = 11,
PHY_DELAY_SHIFT = 5,
PHY_DELAY_MASK = 0x60,
CONFIG_MGR_CAP_OFFS = 11,
CONFIG_MGR_CAP_MASK = 0x10,
POWER_CLASS_OFFS = 11,
POWER_CLASS_SHIFT = 1,
POWER_CLASS_MASK = 0x0e,
POWER_CLASS_OFFS = 11,
POWER_CLASS_SHIFT = 1,
POWER_CLASS_MASK = 0x0e,
CMC_PIN_OFFS = 12,
CMC_PIN_MASK = 0x80,
CPS_INT_OFFS = 12,
CPS_INT_MASK = 0x40,
LP_TEST_ERR_OFFS = 12,
LP_TEST_ERR_MASK = 0x20,
ARB_PHASE_OFFS = 12,
ARB_PHASE_SHIFT = 3,
ARB_PHASE_MASK = 0x18,
ARB_STATE_OFFS = 12,
ARB_STATE_MASK = 0x07,
PHASE_BUS_RESET = 0,
PHASE_TREE_ID = 1,
PHASE_SELF_ID = 2,
PHASE_NORMAL = 3,
CMC_PIN_OFFS = 12,
CMC_PIN_MASK = 0x80,
CPS_INT_OFFS = 12,
CPS_INT_MASK = 0x40,
LP_TEST_ERR_OFFS = 12,
LP_TEST_ERR_MASK = 0x20,
ARB_PHASE_OFFS = 12,
ARB_PHASE_SHIFT = 3,
ARB_PHASE_MASK = 0x18,
ARB_STATE_OFFS = 12,
ARB_STATE_MASK = 0x07,
PHASE_BUS_RESET = 0,
PHASE_TREE_ID = 1,
PHASE_SELF_ID = 2,
PHASE_NORMAL = 3,
LP_TEST_EN_OFFS = 13,
LP_TEST_EN_MASK = 0x40,
ACK_ACCEL_EN_OFFS = 13,
ACK_ACCEL_EN_MASK = 0x08,
MULTISP_CONCAT_EN_OFFS = 13,
MULTISP_CONCAT_EN_MASK = 0x02,
MASK_LPS_OFFS = 13,
MASK_LPS_MASK = 0x01,
LP_TEST_EN_OFFS = 13,
LP_TEST_EN_MASK = 0x40,
ACK_ACCEL_EN_OFFS = 13,
ACK_ACCEL_EN_MASK = 0x08,
MULTISP_CONCAT_EN_OFFS = 13,
MULTISP_CONCAT_EN_MASK = 0x02,
MASK_LPS_OFFS = 13,
MASK_LPS_MASK = 0x01,
EN_TIMEOUT_OFFS = 14,
EN_TIMEOUT_MASK = 0x80,
IGNORE_UNPLUG_OFFS = 14,
IGNORE_UNPLUG_MASK = 0x40,
OVERRIDE_CMC_OFFS = 14,
OVERRIDE_CMC_MASK = 0x20,
SOFT_CMC_OFFS = 14,
SOFT_CMC_MASK = 0x10,
DISABLE_P1_OFFS = 14,
DISABLE_P1_MASK = 0x04,
EN_TIMEOUT_OFFS = 14,
EN_TIMEOUT_MASK = 0x80,
IGNORE_UNPLUG_OFFS = 14,
IGNORE_UNPLUG_MASK = 0x40,
OVERRIDE_CMC_OFFS = 14,
OVERRIDE_CMC_MASK = 0x20,
SOFT_CMC_OFFS = 14,
SOFT_CMC_MASK = 0x10,
DISABLE_P1_OFFS = 14,
DISABLE_P1_MASK = 0x04,
SOFT_POR_OFFS = 15,
SOFT_POR_MASK = 0x80,
SEND_PL_DIAG_OFFS = 15,
SEND_PL_DIAG_MASK = 0x20,
SOFT_POR_OFFS = 15,
SOFT_POR_MASK = 0x80,
SEND_PL_DIAG_OFFS = 15,
SEND_PL_DIAG_MASK = 0x20,
ACK_ACCEL_SYNC_OFFS = 15,
ACK_ACCEL_SYNC_MASK = 0x10,
ISBR_OFFS = 15,
ISBR_MASK = 0x08
ISBR_OFFS = 15,
ISBR_MASK = 0x08
};
uint8_t m_regs[16];
@ -151,11 +151,11 @@ private:
enum : uint32_t
{
ENV_OFFS = 4,
ENV_SHIFT = 6,
ENV_MASK = 0xc0,
REG_COUNT_OFFS = 4,
REG_COUNT_MASK = 0x3f
ENV_OFFS = 4,
ENV_SHIFT = 6,
ENV_MASK = 0xc0,
REG_COUNT_OFFS = 4,
REG_COUNT_MASK = 0x3f
};
};
@ -169,37 +169,37 @@ private:
enum : uint32_t
{
ASTAT2_OFFS = 4,
ASTAT2_SHIFT = 6,
ASTAT2_MASK = 0xc0,
BSTAT2_OFFS = 4,
BSTAT2_SHIFT = 4,
BSTAT2_MASK = 0x30,
CHILD2_OFFS = 4,
CHILD2_MASK = 0x08,
CONNECTION2_OFFS = 4,
CONNECTION2_MASK = 0x04,
PEER_SPEED2_OFFS = 4,
PEER_SPEED2_MASK = 0x03,
ASTAT2_OFFS = 4,
ASTAT2_SHIFT = 6,
ASTAT2_MASK = 0xc0,
BSTAT2_OFFS = 4,
BSTAT2_SHIFT = 4,
BSTAT2_MASK = 0x30,
CHILD2_OFFS = 4,
CHILD2_MASK = 0x08,
CONNECTION2_OFFS = 4,
CONNECTION2_MASK = 0x04,
PEER_SPEED2_OFFS = 4,
PEER_SPEED2_MASK = 0x03,
ASTAT3_OFFS = 5,
ASTAT3_SHIFT = 6,
ASTAT3_MASK = 0xc0,
BSTAT3_OFFS = 5,
BSTAT3_SHIFT = 4,
BSTAT3_MASK = 0x30,
CHILD3_OFFS = 5,
CHILD3_MASK = 0x08,
CONNECTION3_OFFS = 5,
CONNECTION3_MASK = 0x04,
PEER_SPEED3_OFFS = 5,
PEER_SPEED3_MASK = 0x03,
ASTAT3_OFFS = 5,
ASTAT3_SHIFT = 6,
ASTAT3_MASK = 0xc0,
BSTAT3_OFFS = 5,
BSTAT3_SHIFT = 4,
BSTAT3_MASK = 0x30,
CHILD3_OFFS = 5,
CHILD3_MASK = 0x08,
CONNECTION3_OFFS = 5,
CONNECTION3_MASK = 0x04,
PEER_SPEED3_OFFS = 5,
PEER_SPEED3_MASK = 0x03,
ENV_OFFS = 6,
ENV_SHIFT = 6,
ENV_MASK = 0xc0,
REG_COUNT_OFFS = 6,
REG_COUNT_MASK = 0x3f
ENV_OFFS = 6,
ENV_SHIFT = 6,
ENV_MASK = 0xc0,
REG_COUNT_OFFS = 6,
REG_COUNT_MASK = 0x3f
};
};

20
src/devices/machine/m68sfdc.cpp
View File

@ -210,7 +210,7 @@ u8 m68sfdc_device::read(offs_t offset)
data = (data & 0b11001100) >> 2 | (data & 0b00110011) << 2;
data = (data & 0b10101010) >> 1 | (data & 0b01010101) << 1;
return data;
}
// The 6821 address lines are swapped.
@ -251,7 +251,7 @@ void m68sfdc_device::write(offs_t offset, u8 data)
m_ssda_reg[(m_ssda_reg[0] >> 6) + 1] = data;
if (offset == 1 && (m_ssda_reg[0] & C1_AC_MASK) == C1_AC_C2 &&
(data & C2_PC_MASK) == C2_PC1 && m_enable_read)
(data & C2_PC_MASK) == C2_PC1 && m_enable_read)
{
// This a write to the 6852 CR2 register which enables
// the SM output (PC2 = 0, PC1 = 1), while the read
@ -267,7 +267,7 @@ void m68sfdc_device::write(offs_t offset, u8 data)
{
live_abort();
}
return;
}
@ -377,7 +377,7 @@ void m68sfdc_device::pia_pa_w(u8 data)
m_direction = direction;
update_floppy_selection();
u8 head_load = m_head_load1 && m_head_load2;
if (head_load != m_head_load)
{
@ -419,7 +419,7 @@ uint8_t m68sfdc_device::pia_pb_r()
if (m_write_protect_mode->read())
wpt = !wpt;
return (wpt << 4) | (m_crc << 7);
}
@ -448,7 +448,7 @@ void m68sfdc_device::pia_pb_w(u8 data)
if (m_floppy)
m_floppy->ss_w(m_select3_mode->read() ? m_select_3 : 0);
update_floppy_selection();
if (shift_crc_edge)
@ -669,7 +669,7 @@ void m68sfdc_device::live_run(attotime limit)
// 0xaa prefix check is an emulator hack for now to
// improve detection reliability.
if ((cur_live.shift_reg & 0xff) == sync &&
(cur_live.shift_reg >> 8) == 0xaa)
(cur_live.shift_reg >> 8) == 0xaa)
{
// Initialize the CRC. The hardware has an 8
// bit shift register to delay the bit stream
@ -713,7 +713,7 @@ void m68sfdc_device::live_run(attotime limit)
}
case SYNC_BYTE2:
m_ssda->receive_byte(flip_bits(cur_live.shift_reg & 0xff));
cur_live.bit_counter = 0;
cur_live.bit_counter = 0;
cur_live.state = READ;
checkpoint();
break;
@ -744,8 +744,8 @@ void m68sfdc_device::live_run(attotime limit)
// expected CRC end positions: address marks, and 128
// and 256 byte data sectors.
if (cur_live.bit_counter == (4 + 2) * 16 ||
cur_live.bit_counter == (128 + 2) * 16 ||
cur_live.bit_counter == (256 + 2) * 16)
cur_live.bit_counter == (128 + 2) * 16 ||
cur_live.bit_counter == (256 + 2) * 16)
{
m_crc = m_last_crc;
}

4
src/devices/machine/m68sfdc.h
View File

@ -26,7 +26,7 @@ public:
auto irq_handler() { return m_irq_handler.bind(); }
auto nmi_handler() { return m_nmi_handler.bind(); }
void set_floppies_4(floppy_connector*, floppy_connector*, floppy_connector*, floppy_connector*);
private:
@ -39,7 +39,7 @@ private:
devcb_write_line m_nmi_handler;
DECLARE_WRITE_LINE_MEMBER(handle_irq);
DECLARE_WRITE_LINE_MEMBER(handle_nmi);
uint8_t flip_bits(uint8_t data);
uint8_t pia_pa_r();
void pia_pa_w(u8 data);

6
src/devices/machine/pxa255.cpp
View File

@ -23,9 +23,9 @@
#define LOG_GPIO (1 << 6)
#define LOG_LCD_DMA (1 << 7)
#define LOG_LCD (1 << 8)
#define LOG_POWER (1 << 9)
#define LOG_RTC (1 << 10)
#define LOG_CLOCKS (1 << 11)
#define LOG_POWER (1 << 9)
#define LOG_RTC (1 << 10)
#define LOG_CLOCKS (1 << 11)
#define LOG_ALL (LOG_UNKNOWN | LOG_I2S | LOG_DMA | LOG_OSTIMER | LOG_INTC | LOG_GPIO | LOG_LCD_DMA | LOG_LCD | LOG_POWER | LOG_RTC | LOG_CLOCKS)
#define VERBOSE (LOG_ALL)

46
src/devices/machine/pxa255defs.h
View File

@ -220,11 +220,11 @@
*/
#define PXA255_RTC_BASE_ADDR (0x40900000)
#define PXA255_RCNR (PXA255_RTC_BASE_ADDR + 0x00000000)
#define PXA255_RTAR (PXA255_RTC_BASE_ADDR + 0x00000004)
#define PXA255_RTSR (PXA255_RTC_BASE_ADDR + 0x00000008)
#define PXA255_RTTR (PXA255_RTC_BASE_ADDR + 0x0000000c)
#define PXA255_RTC_BASE_ADDR (0x40900000)
#define PXA255_RCNR (PXA255_RTC_BASE_ADDR + 0x00000000)
#define PXA255_RTAR (PXA255_RTC_BASE_ADDR + 0x00000004)
#define PXA255_RTSR (PXA255_RTC_BASE_ADDR + 0x00000008)
#define PXA255_RTTR (PXA255_RTC_BASE_ADDR + 0x0000000c)
/*
@ -396,20 +396,20 @@
pg. 85 to 96, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_POWER_BASE_ADDR (0x40f00000)
#define PXA255_PMCR (PXA255_POWER_BASE_ADDR + 0x00000000)
#define PXA255_PSSR (PXA255_POWER_BASE_ADDR + 0x00000004)
#define PXA255_PSPR (PXA255_POWER_BASE_ADDR + 0x00000008)
#define PXA255_PWER (PXA255_POWER_BASE_ADDR + 0x0000000c)
#define PXA255_PRER (PXA255_POWER_BASE_ADDR + 0x00000010)
#define PXA255_PFER (PXA255_POWER_BASE_ADDR + 0x00000014)
#define PXA255_PEDR (PXA255_POWER_BASE_ADDR + 0x00000018)
#define PXA255_PCFR (PXA255_POWER_BASE_ADDR + 0x0000001c)
#define PXA255_PGSR0 (PXA255_POWER_BASE_ADDR + 0x00000020)
#define PXA255_PGSR1 (PXA255_POWER_BASE_ADDR + 0x00000024)
#define PXA255_PGSR2 (PXA255_POWER_BASE_ADDR + 0x00000028)
#define PXA255_RCSR (PXA255_POWER_BASE_ADDR + 0x00000030)
#define PXA255_PMFW (PXA255_POWER_BASE_ADDR + 0x00000034)
#define PXA255_POWER_BASE_ADDR (0x40f00000)
#define PXA255_PMCR (PXA255_POWER_BASE_ADDR + 0x00000000)
#define PXA255_PSSR (PXA255_POWER_BASE_ADDR + 0x00000004)
#define PXA255_PSPR (PXA255_POWER_BASE_ADDR + 0x00000008)
#define PXA255_PWER (PXA255_POWER_BASE_ADDR + 0x0000000c)
#define PXA255_PRER (PXA255_POWER_BASE_ADDR + 0x00000010)
#define PXA255_PFER (PXA255_POWER_BASE_ADDR + 0x00000014)
#define PXA255_PEDR (PXA255_POWER_BASE_ADDR + 0x00000018)
#define PXA255_PCFR (PXA255_POWER_BASE_ADDR + 0x0000001c)
#define PXA255_PGSR0 (PXA255_POWER_BASE_ADDR + 0x00000020)
#define PXA255_PGSR1 (PXA255_POWER_BASE_ADDR + 0x00000024)
#define PXA255_PGSR2 (PXA255_POWER_BASE_ADDR + 0x00000028)
#define PXA255_RCSR (PXA255_POWER_BASE_ADDR + 0x00000030)
#define PXA255_PMFW (PXA255_POWER_BASE_ADDR + 0x00000034)
/*
PXA255 Clock controller
@ -418,9 +418,9 @@
*/
#define PXA255_CLOCKS_BASE_ADDR (0x41300000)
#define PXA255_CCCR (PXA255_CLOCKS_BASE_ADDR + 0x00000000)
#define PXA255_CKEN (PXA255_CLOCKS_BASE_ADDR + 0x00000004)
#define PXA255_OSCC (PXA255_CLOCKS_BASE_ADDR + 0x00000008)
#define PXA255_CLOCKS_BASE_ADDR (0x41300000)
#define PXA255_CCCR (PXA255_CLOCKS_BASE_ADDR + 0x00000000)
#define PXA255_CKEN (PXA255_CLOCKS_BASE_ADDR + 0x00000004)
#define PXA255_OSCC (PXA255_CLOCKS_BASE_ADDR + 0x00000008)
#endif // MAME_MACHINE_PXA255DEFS

2
src/devices/machine/sa1110.cpp
View File

@ -11,7 +11,7 @@
#define LOG_UNKNOWN (1 << 1)
#define LOG_INTC (1 << 2)
#define LOG_POWER (1 << 3)
#define LOG_POWER (1 << 3)
#define LOG_ALL (LOG_UNKNOWN | LOG_INTC | LOG_POWER)
#define VERBOSE (LOG_ALL)

30
src/devices/machine/sa1110.h
View File

@ -44,23 +44,23 @@ protected:
enum
{
INTC_BASE_ADDR = 0x90050000,
REG_ICIP = (0x00000000 >> 2),
REG_ICMR = (0x00000004 >> 2),
REG_ICLR = (0x00000008 >> 2),
REG_ICCR = (0x0000000c >> 2),
REG_ICFP = (0x00000010 >> 2),
REG_ICPR = (0x00000020 >> 2),
INTC_BASE_ADDR = 0x90050000,
REG_ICIP = (0x00000000 >> 2),
REG_ICMR = (0x00000004 >> 2),
REG_ICLR = (0x00000008 >> 2),
REG_ICCR = (0x0000000c >> 2),
REG_ICFP = (0x00000010 >> 2),
REG_ICPR = (0x00000020 >> 2),
POWER_BASE_ADDR = 0x90020000,
REG_PMCR = (0x00000000 >> 2),
REG_PSSR = (0x00000004 >> 2),
REG_PSPR = (0x00000008 >> 2),
REG_PWER = (0x0000000c >> 2),
REG_PCFR = (0x00000010 >> 2),
REG_PPCR = (0x00000014 >> 2),
REG_PGSR = (0x00000018 >> 2),
REG_POSR = (0x0000001c >> 2)
REG_PMCR = (0x00000000 >> 2),
REG_PSSR = (0x00000004 >> 2),
REG_PSPR = (0x00000008 >> 2),
REG_PWER = (0x0000000c >> 2),
REG_PCFR = (0x00000010 >> 2),
REG_PPCR = (0x00000014 >> 2),
REG_PGSR = (0x00000018 >> 2),
REG_POSR = (0x0000001c >> 2)
};
struct intc_regs

14
src/devices/machine/tsb12lv01a.cpp
View File

@ -12,13 +12,13 @@
#include "emu.h"
#include "tsb12lv01a.h"
#define LOG_READS (1 << 1)
#define LOG_WRITES (1 << 2)
#define LOG_UNKNOWNS (1 << 3)
#define LOG_IRQS (1 << 4)
#define LOG_ALL (LOG_READS | LOG_WRITES | LOG_UNKNOWNS | LOG_IRQS)
#define LOG_READS (1 << 1)
#define LOG_WRITES (1 << 2)
#define LOG_UNKNOWNS (1 << 3)
#define LOG_IRQS (1 << 4)
#define LOG_ALL (LOG_READS | LOG_WRITES | LOG_UNKNOWNS | LOG_IRQS)
#define VERBOSE (LOG_ALL)
#define VERBOSE (LOG_ALL)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(TSB12LV01A, tsb12lv01a_device, "tsb12lv01a", "TSB12LV01A IEEE 1394 Link Controller")
@ -276,4 +276,4 @@ void tsb12lv01a_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
LOGMASKED(LOG_WRITES | LOG_UNKNOWNS, "%s: TSB12 Unknown write: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
break;
}
}
}

212
src/devices/machine/tsb12lv01a.h
View File

@ -46,128 +46,128 @@ private:
enum
{
NODE_ADDR_BUSNUM_SHIFT = 22,
NODE_ADDR_BUSNUM_MASK = 0xffc00000,
NODE_ADDR_NODENUM_SHIFT = 16,
NODE_ADDR_NODENUM_MASK = 0x003f0000,
NODE_ADDR_ROOT = 0x8000,
NODE_ADDR_ATACK_SHIFT = 4,
NODE_ADDR_ATACK_MASK = 0x000001f0,
NODE_ADDR_ACKV = 0x00000001,
NODE_ADDR_BUSNUM_MASK = 0xffc00000,
NODE_ADDR_NODENUM_SHIFT = 16,
NODE_ADDR_NODENUM_MASK = 0x003f0000,
NODE_ADDR_ROOT = 0x8000,
NODE_ADDR_ATACK_SHIFT = 4,
NODE_ADDR_ATACK_MASK = 0x000001f0,
NODE_ADDR_ACKV = 0x00000001,
CTRL_IDVAL = 0x80000000,
CTRL_RXSID = 0x40000000,
CTRL_BSYCTRL = 0x20000000,
CTRL_RAI = 0x10000000,
CTRL_RCVCYST = 0x08000000,
CTRL_TXAEN = 0x04000000,
CTRL_RXAEN = 0x02000000,
CTRL_TXIEN = 0x01000000,
CTRL_RXIEN = 0x00800000,
CTRL_ACKCEN = 0x00400000,
CTRL_RSTTX = 0x00200000,
CTRL_RSTRX = 0x00100000,
CTRL_CYMAS = 0x00000800,
CTRL_CYSRC = 0x00000400,
CTRL_CYTEN = 0x00000200,
CTRL_TRGEN = 0x00000100,
CTRL_IRP1EN = 0x00000080,
CTRL_IRP2EN = 0x00000040,
CTRL_FHBAD = 0x00000001,
CTRL_RW_BITS = CTRL_IDVAL | CTRL_RXSID | CTRL_BSYCTRL | CTRL_RAI | CTRL_RCVCYST |
CTRL_IDVAL = 0x80000000,
CTRL_RXSID = 0x40000000,
CTRL_BSYCTRL = 0x20000000,
CTRL_RAI = 0x10000000,
CTRL_RCVCYST = 0x08000000,
CTRL_TXAEN = 0x04000000,
CTRL_RXAEN = 0x02000000,
CTRL_TXIEN = 0x01000000,
CTRL_RXIEN = 0x00800000,
CTRL_ACKCEN = 0x00400000,
CTRL_RSTTX = 0x00200000,
CTRL_RSTRX = 0x00100000,
CTRL_CYMAS = 0x00000800,
CTRL_CYSRC = 0x00000400,
CTRL_CYTEN = 0x00000200,
CTRL_TRGEN = 0x00000100,
CTRL_IRP1EN = 0x00000080,
CTRL_IRP2EN = 0x00000040,
CTRL_FHBAD = 0x00000001,
CTRL_RW_BITS = CTRL_IDVAL | CTRL_RXSID | CTRL_BSYCTRL | CTRL_RAI | CTRL_RCVCYST |
CTRL_TXAEN | CTRL_RXAEN | CTRL_TXIEN | CTRL_RXIEN | CTRL_ACKCEN |
CTRL_CYMAS | CTRL_CYSRC | CTRL_CYTEN | CTRL_TRGEN | CTRL_IRP1EN |
CTRL_IRP2EN | CTRL_FHBAD,
INT_INT = 0x80000000,
INT_PHINT = 0x40000000,
INT_PHYRRX = 0x20000000,
INT_PHRST = 0x10000000,
INT_SIDCOMP = 0x08000000,
INT_TXRDY = 0x04000000,
INT_RXDTA = 0x02000000,
INT_CMDRST = 0x01000000,
INT_ACKRCV = 0x00800000,
INT_ITBADF = 0x00100000,
INT_ATBADF = 0x00080000,
INT_SNTRJ = 0x00020000,
INT_HDRDR = 0x00010000,
INT_TCERR = 0x00008000,
INT_INT = 0x80000000,
INT_PHINT = 0x40000000,
INT_PHYRRX = 0x20000000,
INT_PHRST = 0x10000000,
INT_SIDCOMP = 0x08000000,
INT_TXRDY = 0x04000000,
INT_RXDTA = 0x02000000,
INT_CMDRST = 0x01000000,
INT_ACKRCV = 0x00800000,
INT_ITBADF = 0x00100000,
INT_ATBADF = 0x00080000,
INT_SNTRJ = 0x00020000,
INT_HDRDR = 0x00010000,
INT_TCERR = 0x00008000,
INT_CYTMOUT = 0x00001000,
INT_CYSEC = 0x00000800,
INT_CYST = 0x00000400,
INT_CYDNE = 0x00000200,
INT_CYPND = 0x00000100,
INT_CYLST = 0x00000080,
INT_CARBFL = 0x00000040,
INT_ARBGP = 0x00000004,
INT_FRGP = 0x00000002,
INT_IARBFL = 0x00000001,
INT_CYSEC = 0x00000800,
INT_CYST = 0x00000400,
INT_CYDNE = 0x00000200,
INT_CYPND = 0x00000100,
INT_CYLST = 0x00000080,
INT_CARBFL = 0x00000040,
INT_ARBGP = 0x00000004,
INT_FRGP = 0x00000002,
INT_IARBFL = 0x00000001,
CYTMR_SEC_COUNT_SHIFT = 25,
CYTMR_SEC_COUNT_MASK = 0xfe000000,
CYTMR_SEC_COUNT_SHIFT = 25,
CYTMR_SEC_COUNT_MASK = 0xfe000000,
CYTMR_CYC_COUNT_SHIFT = 12,
CYTMR_CYC_COUNT_MASK = 0x01fff000,
CYTMR_CYC_OFFSET_SHIFT = 0,
CYTMR_CYC_OFFSET_MASK = 0x00000fff,
CYTMR_CYC_COUNT_MASK = 0x01fff000,
CYTMR_CYC_OFFSET_SHIFT = 0,
CYTMR_CYC_OFFSET_MASK = 0x00000fff,
ISOCH_PORT_TAG_SHIFT = 30,
ISOCH_PORT_TAG_MASK = 0xc0000000,
ISOCH_PORT_IRPORT1_SHIFT = 24,
ISOCH_PORT_IRPORT1_MASK = 0x3f000000,
ISOCH_PORT_TAG2_SHIFT = 22,
ISOCH_PORT_TAG2_MASK = 0x00c00000,
ISOCH_PORT_IRPORT2_SHIFT = 16,
ISOCH_PORT_IRPORT2_MASK = 0x003f0000,
ISOCH_PORT_MON_TAG = 0x00000001,
ISOCH_PORT_TAG_SHIFT = 30,
ISOCH_PORT_TAG_MASK = 0xc0000000,
ISOCH_PORT_IRPORT1_SHIFT = 24,
ISOCH_PORT_IRPORT1_MASK = 0x3f000000,
ISOCH_PORT_TAG2_SHIFT = 22,
ISOCH_PORT_TAG2_MASK = 0x00c00000,
ISOCH_PORT_IRPORT2_SHIFT = 16,
ISOCH_PORT_IRPORT2_MASK = 0x003f0000,
ISOCH_PORT_MON_TAG = 0x00000001,
FIFO_CTRL_CLRATF = 0x80000000,
FIFO_CTRL_CLRITF = 0x40000000,
FIFO_CTRL_CLRGRF = 0x20000000,
FIFO_CTRL_TRIG_SIZE_SHIFT = 18,
FIFO_CTRL_TRIG_SIZE_MASK = 0x07fc0000,
FIFO_CTRL_ATF_SIZE_SHIFT = 9,
FIFO_CTRL_ATF_SIZE_MASK = 0x0003fe00,
FIFO_CTRL_ITF_SIZE_SHIFT = 0,
FIFO_CTRL_ITF_SIZE_MASK = 0x000001ff,
FIFO_CTRL_RW_BITS = (FIFO_CTRL_TRIG_SIZE_MASK | FIFO_CTRL_ATF_SIZE_MASK | FIFO_CTRL_ITF_SIZE_MASK),
FIFO_CTRL_CLRATF = 0x80000000,
FIFO_CTRL_CLRITF = 0x40000000,
FIFO_CTRL_CLRGRF = 0x20000000,
FIFO_CTRL_TRIG_SIZE_SHIFT = 18,
FIFO_CTRL_TRIG_SIZE_MASK = 0x07fc0000,
FIFO_CTRL_ATF_SIZE_SHIFT = 9,
FIFO_CTRL_ATF_SIZE_MASK = 0x0003fe00,
FIFO_CTRL_ITF_SIZE_SHIFT = 0,
FIFO_CTRL_ITF_SIZE_MASK = 0x000001ff,
FIFO_CTRL_RW_BITS = (FIFO_CTRL_TRIG_SIZE_MASK | FIFO_CTRL_ATF_SIZE_MASK | FIFO_CTRL_ITF_SIZE_MASK),
PHY_RDPHY = 0x80000000,
PHY_WRPHY = 0x40000000,
PHY_PHYRGAD_SHIFT = 24,
PHY_PHYRGAD_MASK = 0x0f000000,
PHY_RDPHY = 0x80000000,
PHY_WRPHY = 0x40000000,
PHY_PHYRGAD_SHIFT = 24,
PHY_PHYRGAD_MASK = 0x0f000000,
PHY_PHYRGDATA_SHIFT = 16,
PHY_PHYRGDATA_MASK = 0x00ff0000,
PHY_PHYRXAD_SHIFT = 8,
PHY_PHYRXAD_MASK = 0x00000f00,
PHY_PHYRXDATA_SHIFT = 0,
PHY_PHYRXDATA_MASK = 0x000000ff,
PHY_RW_BITS = 0x0fff0fff,
PHY_PHYRGDATA_MASK = 0x00ff0000,
PHY_PHYRXAD_SHIFT = 8,
PHY_PHYRXAD_MASK = 0x00000f00,
PHY_PHYRXDATA_SHIFT = 0,
PHY_PHYRXDATA_MASK = 0x000000ff,
PHY_RW_BITS = 0x0fff0fff,
ATF_STATUS_FULL = 0x80000000,
ATF_STATUS_EMPTY = 0x40000000,
ATF_STATUS_CONERR = 0x20000000,
ATF_STATUS_ADRCLR = 0x10000000,
ATF_STATUS_CONTROL = 0x08000000,
ATF_STATUS_RAMTEST = 0x04000000,
ATF_STATUS_FULL = 0x80000000,
ATF_STATUS_EMPTY = 0x40000000,
ATF_STATUS_CONERR = 0x20000000,
ATF_STATUS_ADRCLR = 0x10000000,
ATF_STATUS_CONTROL = 0x08000000,
ATF_STATUS_RAMTEST = 0x04000000,
ATF_STATUS_ADRCOUNTER_SHIFT = 17,
ATF_STATUS_ADRCOUNTER_MASK = 0x03fe0000,
ATF_STATUS_ATFSPACE_SHIFT = 0,
ATF_STATUS_ATFSPACE_MASK = 0x000001ff,
ATF_STATUS_ADRCOUNTER_MASK = 0x03fe0000,
ATF_STATUS_ATFSPACE_SHIFT = 0,
ATF_STATUS_ATFSPACE_MASK = 0x000001ff,
ITF_STATUS_FULL = 0x80000000,
ITF_STATUS_EMPTY = 0x40000000,
ITF_STATUS_ITFSPACE_SHIFT = 0,
ITF_STATUS_ITFSPACE_MASK = 0x000001ff,
ITF_STATUS_FULL = 0x80000000,
ITF_STATUS_EMPTY = 0x40000000,
ITF_STATUS_ITFSPACE_SHIFT = 0,
ITF_STATUS_ITFSPACE_MASK = 0x000001ff,
GRF_STATUS_EMPTY = 0x80000000,
GRF_STATUS_CD = 0x40000000,
GRF_STATUS_PACCOM = 0x20000000,
GRF_STATUS_GRFTOTAL_SHIFT = 19,
GRF_STATUS_GRFTOTAL_MASK = 0x1ff80000,
GRF_STATUS_GRFSIZE_SHIFT = 9,
GRF_STATUS_GRFSIZE_MASK = 0x0007fe00,
GRF_STATUS_WRITECOUNT_SHIFT = 0,
GRF_STATUS_WRITECOUNT_MASK = 0x000001ff
GRF_STATUS_EMPTY = 0x80000000,
GRF_STATUS_CD = 0x40000000,
GRF_STATUS_PACCOM = 0x20000000,
GRF_STATUS_GRFTOTAL_SHIFT = 19,
GRF_STATUS_GRFTOTAL_MASK = 0x1ff80000,
GRF_STATUS_GRFSIZE_SHIFT = 9,
GRF_STATUS_GRFSIZE_MASK = 0x0007fe00,
GRF_STATUS_WRITECOUNT_SHIFT = 0,
GRF_STATUS_WRITECOUNT_MASK = 0x000001ff
};
uint32_t m_version;

142
src/devices/machine/v3021.cpp
View File

@ -8,89 +8,89 @@
Serial Real Time Clock
- Reference: https://www.emmicroelectronic.com/product/real-time-clocks-ic/v3021
- Reference: https://www.emmicroelectronic.com/product/real-time-clocks-ic/v3021
Pin assignment (SO8)
Pin assignment (SO8)
|-------------------------|
_|o |_
XI |_| |_| Vdd
| |
_| |_
XO |_| |_| WR
| V3021 |
_| |_
CS |_| |_| RD
| |
_| |_
Vss |_| |_| I/O
|-------------------------|
|-------------------------|
_|o |_
XI |_| |_| Vdd
| |
_| |_
XO |_| |_| WR
| V3021 |
_| |_
CS |_| |_| RD
| |
_| |_
Vss |_| |_| I/O
|-------------------------|
Pin description
Pin description
|-----|------|-----------------------------------------|
| Pin | Name | Description |
|-----|------|-----------------------------------------|
1 1 | XI | 32 kHz Crystal input |
|-----|------|-----------------------------------------|
1 2 | XO | 32 kHz Crystal output |
|-----|------|-----------------------------------------|
1 3 | CS | Chip select input |
|-----|------|-----------------------------------------|
1 4 | Vss | Ground supply |
|-----|------|-----------------------------------------|
1 5 | I/O | Data input and output |
|-----|------|-----------------------------------------|
1 6 | RD | Intel RD, Motorola DS (or tie to CS) |
|-----|------|-----------------------------------------|
1 7 | WR | Intel WR, Motorola R/W |
|-----|------|-----------------------------------------|
1 8 | Vdd | Positive supply |
|-----|------|-----------------------------------------|
|-----|------|-----------------------------------------|
| Pin | Name | Description |
|-----|------|-----------------------------------------|
1 1 | XI | 32 kHz Crystal input |
|-----|------|-----------------------------------------|
1 2 | XO | 32 kHz Crystal output |
|-----|------|-----------------------------------------|
1 3 | CS | Chip select input |
|-----|------|-----------------------------------------|
1 4 | Vss | Ground supply |
|-----|------|-----------------------------------------|
1 5 | I/O | Data input and output |
|-----|------|-----------------------------------------|
1 6 | RD | Intel RD, Motorola DS (or tie to CS) |
|-----|------|-----------------------------------------|
1 7 | WR | Intel WR, Motorola R/W |
|-----|------|-----------------------------------------|
1 8 | Vdd | Positive supply |
|-----|------|-----------------------------------------|
Register map (Unused bits are reserved)
Register map (Unused bits are reserved)
Address Bits Description
76543210
Data space
0 ---x---- Time set lock
---0---- Enable copy RAM to clock
---1---- Disable copy RAM to clock
----xx-- Test mode
----00-- Normal operation
----01-- All time keeping accelerated by 32
----10-- Parallel increment of all time data
Address Bits Description
76543210
Data space
0 ---x---- Time set lock
---0---- Enable copy RAM to clock
---1---- Disable copy RAM to clock
----xx-- Test mode
----00-- Normal operation
----01-- All time keeping accelerated by 32
----10-- Parallel increment of all time data
at 1 Hz with no carry over
----11-- Parallel increment of all time data
----11-- Parallel increment of all time data
at 32 Hz with no carry over
-------x Frequency measurement mode
-------x Frequency measurement mode
1 (Read only)
x------- Week number is changed
-x------ Weekday is changed
--x----- Year is changed
---x---- Month is changed
----x--- Day of month is changed
-----x-- Hours is changed
------x- Minutes is changed
-------x Seconds is changed
1 (Read only)
x------- Week number is changed
-x------ Weekday is changed
--x----- Year is changed
---x---- Month is changed
----x--- Day of month is changed
-----x-- Hours is changed
------x- Minutes is changed
-------x Seconds is changed
2 -xxxxxxx Seconds (BCD 00-59)
3 -xxxxxxx Minutes (BCD 00-59)
4 --xxxxxx Hours (BCD 00-23)
5 --xxxxxx Day of month (BCD 1-31)
6 ---xxxxx Month (BCD 01-12)
7 xxxxxxxx Year (BCD 00-99)
8 ----xxxx Week day (BCD 01-07)
9 -xxxxxxx Week number (BCD 00-52)
2 -xxxxxxx Seconds (BCD 00-59)
3 -xxxxxxx Minutes (BCD 00-59)
4 --xxxxxx Hours (BCD 00-23)
5 --xxxxxx Day of month (BCD 1-31)
6 ---xxxxx Month (BCD 01-12)
7 xxxxxxxx Year (BCD 00-99)
8 ----xxxx Week day (BCD 01-07)
9 -xxxxxxx Week number (BCD 00-52)
Address command space
e Copy RAM to clock
f Copy clock to RAM
Address command space
e Copy RAM to clock
f Copy clock to RAM
TODO:
- verify status bit (RAM 0x00)
- Support Week number correctly
TODO:
- verify status bit (RAM 0x00)
- Support Week number correctly
***************************************************************************/

6
src/devices/sound/ics2115.cpp
View File

@ -15,10 +15,10 @@
- Verify interrupt, envelope, timer period
- Verify unemulated registers
Changelog:
Changelog:
25th july 2020 [cam900]:
- Improve envelope behavior, Improve debugging registers, Fix ramping
25th july 2020 [cam900]:
- Improve envelope behavior, Improve debugging registers, Fix ramping
*/
#include "emu.h"

18
src/devices/sound/rp2c33_snd.cpp
View File

@ -2,17 +2,17 @@
// copyright-holders:cam900, Brad Smith, Brezza
/***************************************************************************
Ricoh RP2C33 Sound emulation
Ricoh RP2C33 Sound emulation
Based on:
- NSFplay github code by Brad Smith/Brezza
- Information from NESDev wiki
(https://wiki.nesdev.com/w/index.php/FDS_audio)
Based on:
- NSFplay github code by Brad Smith/Brezza
- Information from NESDev wiki
(https://wiki.nesdev.com/w/index.php/FDS_audio)
TODO:
- verify register behaviors
- verify unknown read, writes
- Lowpass filter?
TODO:
- verify register behaviors
- verify unknown read, writes
- Lowpass filter?
***************************************************************************/

2
src/devices/sound/rp2c33_snd.h
View File

@ -2,7 +2,7 @@
// copyright-holders:cam900, Brad Smith, Brezza
/***************************************************************************
Ricoh RP2C33 Sound emulation
Ricoh RP2C33 Sound emulation
***************************************************************************/

2
src/emu/debug/debugcmd.cpp
View File

@ -534,7 +534,7 @@ bool debugger_commands::validate_cpu_space_parameter(const char *param, int spac
/*-------------------------------------------------
validate_memory_region_parameter - validates
a parameter as a memory region name and
retrieves the given memory region
retrieves the given memory region
-------------------------------------------------*/
bool debugger_commands::validate_memory_region_parameter(const std::string &param, memory_region *&result)

2
src/lib/formats/fl1_dsk.h
View File

@ -4,7 +4,7 @@
formats/fl1_dsk.h
FloppyOne DOS disk images
FloppyOne DOS disk images
*********************************************************************/
#ifndef MAME_FORMATS_FL1_DSK_H

2
src/lib/formats/mdos_dsk.cpp
View File

@ -133,7 +133,7 @@ int mdos_format::find_size(io_generic *io, uint32_t form_factor)
if (!check_ascii(info.date, sizeof(info.date), "date"))
return -1;
if (!check_ascii(info.username, sizeof(info.username), "username"))
return -1;

2
src/lib/formats/swd_dsk.cpp
View File

@ -4,7 +4,7 @@
formats/swd_dsk.c
Swift Disc disk images
Swift Disc disk images
*********************************************************************/

2
src/lib/netlist/devices/nld_ne555.cpp
View File

@ -160,7 +160,7 @@ namespace netlist
#endif
m_overshoot = plib::clamp(m_overshoot(), nlconst::zero(), ovlimit);
//if (this->name() == "IC6_2")
// printf("%f %s %f %f %f\n", exec().time().as_double(), this->name().c_str(), m_overshoot(), m_R2.P()(), m_THRES());
// printf("%f %s %f %f %f\n", exec().time().as_double(), this->name().c_str(), m_overshoot(), m_R2.P()(), m_THRES());
m_RDIS.change_state([this]()
{
m_RDIS.set_R(nlconst::magic(R_ON));

2
src/lib/netlist/plib/pfunction.cpp
View File

@ -312,7 +312,7 @@ namespace plib {
opstk.pop();
}
//for (auto &e : postfix)
// printf("\t%s\n", e.c_str());
// printf("\t%s\n", e.c_str());
compile_postfix(inputs, postfix, expr);
}

2
src/lib/netlist/plib/pfunction.h
View File

@ -32,7 +32,7 @@ namespace plib {
LE,
GE,
IF,
NEG, // unary minus
NEG, // unary minus
POW,
LOG,
SIN,

4
src/lib/netlist/plib/pmath.h
View File

@ -442,8 +442,8 @@ namespace plib
template<class T>
constexpr const T& clamp( const T& v, const T& low, const T& high)
{
gsl_Expects(high >= low);
return (v < low) ? low : (high < v) ? high : v;
gsl_Expects(high >= low);
return (v < low) ? low : (high < v) ? high : v;
}
static_assert(noexcept(constants<double>::one()), "Not evaluated as constexpr");

2
src/mame/audio/cinemat.h
View File

@ -10,7 +10,7 @@
#include "netlist/nl_setup.h"
// log to cinemat.csv for nltool playback/analysis
#define ENABLE_NETLIST_LOGGING (0)
#define ENABLE_NETLIST_LOGGING (0)
class cinemat_audio_device : public device_t

10
src/mame/audio/cmi01a.cpp
View File

@ -477,11 +477,11 @@ void cmi01a_device::set_eclk(bool eclk)
tick_ediv();
}
// A B !(A && B) !A || !B
// 0 0 1 1
// 0 1 1 1
// 1 0 1 1
// 1 1 0 0
// A B !(A && B) !A || !B
// 0 0 1 1
// 0 1 1 1
// 1 0 1 1
// 1 1 0 0
const bool a = !m_load || !eclk;
const bool b = m_load || !m_ediv_out;

16
src/mame/audio/cmi01a.h
View File

@ -16,8 +16,8 @@
#define ENV_DIR_UP 0
#define ENV_DIR_DOWN 1
#define CHANNEL_STATUS_LOAD 1
#define CHANNEL_STATUS_RUN 2
#define CHANNEL_STATUS_LOAD 1
#define CHANNEL_STATUS_RUN 2
class cmi01a_device : public device_t, public device_sound_interface {
public:
@ -92,11 +92,11 @@ private:
uint8_t m_new_addr; // Flag
uint8_t m_vol_latch;
uint8_t m_flt_latch;
uint8_t m_rp;
uint8_t m_ws;
uint8_t m_rp;
uint8_t m_ws;
int m_dir;
int m_env_dir;
uint8_t m_env;
uint8_t m_env;
int m_pia0_cb2_state;
uint8_t m_bcas_q1_ticks;
@ -117,11 +117,11 @@ private:
bool m_tri;
bool m_pia1_ca2;
bool m_eclk;
bool m_eclk;
bool m_env_clk;
bool m_ediv_out;
bool m_ediv_out;
uint8_t m_ediv_rate;
uint8_t m_ediv_count;
uint8_t m_ediv_count;
uint16_t m_pitch;
uint8_t m_octave;

1110
src/mame/audio/nl_armora.cpp
View File

File diff suppressed because it is too large Load Diff

90
src/mame/audio/nl_barrier.cpp
View File

@ -42,9 +42,9 @@ NETLIST_START(barrier)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC)
@ -74,17 +74,17 @@ NETLIST_START(barrier)
RES(R17, RES_K(10))
RES(R18, RES_K(47))
RES(R19, 820)
// POT(R20, RES_K(10)) -- part of final amp (not emulated)
// RES(R21, 150) -- part of final amp (not emulated), not present on Space Wars
// RES(R22, 2.7) -- part of final amp (not emulated), not present on Space Wars
// RES(R23, 2.7) -- part of final amp (not emulated), not present on Space Wars
// POT(R20, RES_K(10)) -- part of final amp (not emulated)
// RES(R21, 150) -- part of final amp (not emulated), not present on Space Wars
// RES(R22, 2.7) -- part of final amp (not emulated), not present on Space Wars
// RES(R23, 2.7) -- part of final amp (not emulated), not present on Space Wars
RES(R24, RES_K(47))
RES(R25, 150)
RES(R26, RES_K(160))
RES(R27, 750)
// RES(R28, RES_K(150)) -- part of final amp (not emulated), illegible on Space Wars
// POT(R29, RES_K(10)) -- part of final amp (not emulated)
// RES(R30, 470) -- part of final amp (not emulated)
// RES(R28, RES_K(150)) -- part of final amp (not emulated), illegible on Space Wars
// POT(R29, RES_K(10)) -- part of final amp (not emulated)
// RES(R30, 470) -- part of final amp (not emulated)
RES(R31, 470)
RES(R32, RES_K(1))
RES(R33, RES_K(39))
@ -99,21 +99,21 @@ NETLIST_START(barrier)
CAP(C3, CAP_U(0.01))
CAP(C4, CAP_U(0.01))
CAP(C5, CAP_U(0.1))
// CAP(C6, CAP_U(4.7)) // not needed
// CAP(C6, CAP_U(4.7)) // not needed
CAP(C7, CAP_U(0.01))
CAP(C8, CAP_U(1))
CAP(C9, CAP_U(0.1))
CAP(C10, CAP_P(220))
CAP(C11, CAP_U(0.1))
// CAP(C12, CAP_U(0.01)) -- part of final amp (not emulated)
// CAP(C13, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C14, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C15, CAP_U(50)) -- not needed
// CAP(C16, CAP_U(2.2)) -- not needed
// CAP(C12, CAP_U(0.01)) -- part of final amp (not emulated)
// CAP(C13, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C14, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C15, CAP_U(50)) -- not needed
// CAP(C16, CAP_U(2.2)) -- not needed
CAP(C17, CAP_U(0.01))
CAP(C18, CAP_U(15))
// CAP(C19, CAP_U(50)) -- not needed
// CAP(C20, CAP_U(2.2)) -- not needed
// CAP(C19, CAP_U(50)) -- not needed
// CAP(C20, CAP_U(2.2)) -- not needed
CAP(C21, CAP_U(0.02))
CAP(C22, CAP_U(0.1))
@ -124,45 +124,45 @@ NETLIST_START(barrier)
D_1N914(CR5)
D_1N914(CR6)
Q_2N3906(Q1) // PNP
Q_2N3904(Q2) // NPN
Q_2N6426(Q3) // NPN Darlington
Q_2N6292(Q4) // NPN
Q_2N6107(Q5) // PNP
Q_2N6426(Q6) // NPN Darlington
Q_2N3904(Q7) // NPN
Q_2N3906(Q1) // PNP
Q_2N3904(Q2) // NPN
Q_2N6426(Q3) // NPN Darlington
Q_2N6292(Q4) // NPN
Q_2N6107(Q5) // PNP
Q_2N6426(Q6) // NPN Darlington
Q_2N3904(Q7) // NPN
TL081_DIP(U1) // Op. Amp.
TL081_DIP(U1) // Op. Amp.
NET_C(U1.4, I_VM15)
NET_C(U1.7, I_V15)
TTL_7406_DIP(U2) // Hex inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(U2) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(U2.7, GND)
NET_C(U2.14, I_V5)
TL081_DIP(U3) // Op. Amp.
TL081_DIP(U3) // Op. Amp.
NET_C(U3.4, I_VM15)
NET_C(U3.7, I_V15)
// TTL_7815_DIP(U4) // +15V Regulator -- not needed
// TTL_7815_DIP(U4) // +15V Regulator -- not needed
TL182_DIP(U5) // Analog switch
TL182_DIP(U5) // Analog switch
NET_C(U5.6, I_V15)
NET_C(U5.7, I_V5)
NET_C(U5.8, GND)
NET_C(U5.9, I_VM15)
// TL081_DIP(U6) // Op. Amp. -- part of final amp (not emulated)
// NET_C(U6.4, I_VM15)
// NET_C(U6.7, I_V15)
// TL081_DIP(U6) // Op. Amp. -- part of final amp (not emulated)
// NET_C(U6.4, I_VM15)
// NET_C(U6.7, I_V15)
// TTL_7915_DIP(U7) // -15V Regulator -- not needed
// TTL_7915_DIP(U7) // -15V Regulator -- not needed
TL081_DIP(U8) // Op. Amp.
TL081_DIP(U8) // Op. Amp.
NET_C(U8.4, I_VM15)
NET_C(U8.7, I_V15)
TL081_DIP(U9) // Op. Amp.
TL081_DIP(U9) // Op. Amp.
NET_C(U9.4, I_VM15)
NET_C(U9.7, I_V15)
@ -234,7 +234,7 @@ NETLIST_START(barrier)
NET_C(R24.2, U8.2, C10.1, R16.1)
NET_C(U8.3, GND)
NET_C(U8.6, R16.2, C10.2, R31.1, R38.1)
// NET_C(U8.6, R13.2) // Schems show noise source into summing amp -- wrong??
// NET_C(U8.6, R13.2) // Schems show noise source into summing amp -- wrong??
NET_C(R38.2, U5.14)
NET_C(I_OUT_2, U5.10)
NET_C(U5.13, C7.1)
@ -283,18 +283,18 @@ NETLIST_START(barrier)
#if (ENABLE_FRONTIERS)
// Separate each input into the summing network
OPTIMIZE_FRONTIER(R13.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R15.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R37.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R13.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R15.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R37.1, RES_M(1), 50)
// Decouple the Darlington BJTs from the sounds they enable
OPTIMIZE_FRONTIER(R27.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(R11.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(R27.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(R11.2, RES_M(1), 50)
// Decouple the noise source from the downstream filters
OPTIMIZE_FRONTIER(C3.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R24.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R38.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(C3.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R24.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R38.1, RES_M(1), 50)
#endif
NETLIST_END()

2586
src/mame/audio/nl_boxingb.cpp
View File

File diff suppressed because it is too large Load Diff

14
src/mame/audio/nl_cinemat_common.h
View File

@ -58,7 +58,7 @@
#define TTL_74LS163_DIP TTL_74163_DIP
#define TTL_74LS164_DIP TTL_74164_DIP
#define TTL_74LS191_DIP TTL_74191_DIP
#define TTL_74LS259_DIP TTL_9334_DIP // Seems to be pin-compatible
#define TTL_74LS259_DIP TTL_9334_DIP // Seems to be pin-compatible
#define TTL_74LS377_DIP TTL_74377_DIP
#define TTL_74LS393_DIP TTL_74393_DIP
@ -117,10 +117,10 @@ static NETLIST_START(_NE556_DIP)
A.THRESH, /* 1THRES |2 13| 2DISCH */ B.DISCH,
A.CONT, /* 1CONT |3 12| 2THRES */ B.THRESH,
A.RESET, /* 1RESET |4 NE556 11| 2CONT */ B.CONT,
A.OUT, /* 1OUT |5 10| 2RESET */ B.RESET,
A.OUT, /* 1OUT |5 10| 2RESET */ B.RESET,
A.TRIG, /* 1TRIG |6 9| 2OUT */ B.OUT,
A.GND, /* GND |7 8| 2TRIG */ B.TRIG
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -142,7 +142,7 @@ static NETLIST_START(_TL182_DIP)
PARAM(A.BASER, 270.0)
PARAM(B.BASER, 270.0)
RES(VR, 100)
RES(VR, 100)
NC_PIN(NC)
TTL_7406_GATE(AINV)
@ -183,7 +183,7 @@ static NETLIST_START(_Q_2N6426)
QBJT_EB(Q1, "NPN(IS=1.73583e-11 BF=831.056 NF=1.05532 VAF=957.147 IKF=0.101183 ISE=1.65383e-10 NE=1.59909 BR=2.763 NR=1.03428 VAR=4.18534 IKR=0.0674174 ISC=1.00007e-13 NC=2.00765 RB=22.2759 IRB=0.208089 RBM=22.2759 RE=0.0002 RC=0.001 XTB=2.12676 XTI=1.82449 EG=1.05 CJE=2.62709e-10 VJE=0.95 MJE=0.23 TF=1e-09 XTF=1 VTF=10 ITF=0.01 CJC=3.59851e-10 VJC=0.845279 MJC=0.23 XCJC=0.9 FC=0.5 TR=1e-07 PTF=0 KF=0 AF=1)")
QBJT_EB(Q2, "NPN(IS=1.73583e-11 BF=831.056 NF=1.05532 VAF=957.147 IKF=0.101183 ISE=1.65383e-10 NE=1.59909 BR=2.763 NR=1.03428 VAR=4.18534 IKR=0.0674174 ISC=1.00007e-13 NC=2.00765 RB=22.2759 IRB=0.208089 RBM=22.2759 RE=0.0002 RC=0.001 XTB=2.12676 XTI=1.82449 EG=1.05 CJE=2.62709e-10 VJE=0.95 MJE=0.23 TF=1e-09 XTF=1 VTF=10 ITF=0.01 CJC=0 VJC=0.845279 MJC=0.23 XCJC=0.9 FC=0.5 TR=1e-07 PTF=0 KF=0 AF=1)") // NPN
QBJT_EB(Q2, "NPN(IS=1.73583e-11 BF=831.056 NF=1.05532 VAF=957.147 IKF=0.101183 ISE=1.65383e-10 NE=1.59909 BR=2.763 NR=1.03428 VAR=4.18534 IKR=0.0674174 ISC=1.00007e-13 NC=2.00765 RB=22.2759 IRB=0.208089 RBM=22.2759 RE=0.0002 RC=0.001 XTB=2.12676 XTI=1.82449 EG=1.05 CJE=2.62709e-10 VJE=0.95 MJE=0.23 TF=1e-09 XTF=1 VTF=10 ITF=0.01 CJC=0 VJC=0.845279 MJC=0.23 XCJC=0.9 FC=0.5 TR=1e-07 PTF=0 KF=0 AF=1)") // NPN
DIODE(D1, "D(IS=1e-12 RS=10.8089 N=1.00809 XTI=3.00809 CJO=0 VJ=0.75 M=0.33 FC=0.5)")
RES(R1, RES_K(8))
@ -235,8 +235,8 @@ static NETLIST_START(_LM3900_DIP)
A.PLUS, /* 1IN+ |1 ++ 14| VCC */ A.VCC,
B.PLUS, /* 2IN+ |2 13| 3IN+ */ C.PLUS,
B.MINUS, /* 2IN- |3 12| 4IN+ */ D.PLUS,
B.OUT, /* 2OUT |4 LM3900 11| 4IN- */ D.MINUS,
A.OUT, /* 1OUT |5 10| 4OUT */ D.OUT,
B.OUT, /* 2OUT |4 LM3900 11| 4IN- */ D.MINUS,
A.OUT, /* 1OUT |5 10| 4OUT */ D.OUT,
A.MINUS, /* 1IN- |6 9| 3OUT */ C.OUT,
A.GND, /* GND |7 8| 3IN- */ C.MINUS
/* +--------------+ */

16
src/mame/audio/nl_gunfight.cpp
View File

@ -284,8 +284,8 @@ static NETLIST_START(gunfight_schematics)
// These all go to TTL ground at pin 7 of 7404 IC H6, rather than the
// ground used for the other sound circuits.
NET_C(GND,
R133.2, R233.2, R120.2, R220.2,
Q108.E, Q208.E, Q105.E, Q205.E)
R133.2, R233.2, R120.2, R220.2,
Q108.E, Q208.E, Q105.E, Q205.E)
NET_C(R134.2, R133.1, Q108.B)
NET_C(R234.2, R233.1, Q208.B)
@ -320,8 +320,8 @@ static NETLIST_START(gunfight_schematics)
// All connected to 16-volt power.
NET_C(I_V16.Q,
R132.1, R232.1, R119.1, R219.1,
Q107.E, Q207.E, Q104.E, Q204.E)
R132.1, R232.1, R119.1, R219.1,
Q107.E, Q207.E, Q104.E, Q204.E)
NET_C(R131.2, R132.2, Q107.B)
NET_C(R231.2, R232.2, Q207.B)
@ -796,11 +796,11 @@ NETLIST_START(gunfight)
// Power and ground connections for logic input devices:
NET_C(I_V5.Q,
I_LEFT_SHOT.VCC, I_RIGHT_SHOT.VCC,
I_LEFT_HIT.VCC, I_RIGHT_HIT.VCC)
I_LEFT_SHOT.VCC, I_RIGHT_SHOT.VCC,
I_LEFT_HIT.VCC, I_RIGHT_HIT.VCC)
NET_C(GND,
I_LEFT_SHOT.GND, I_RIGHT_SHOT.GND,
I_LEFT_HIT.GND, I_RIGHT_HIT.GND)
I_LEFT_SHOT.GND, I_RIGHT_SHOT.GND,
I_LEFT_HIT.GND, I_RIGHT_HIT.GND)
ALIAS(IN_LS, I_LEFT_SHOT.Q)
ALIAS(IN_RS, I_RIGHT_SHOT.Q)

146
src/mame/audio/nl_ripoff.cpp
View File

@ -53,12 +53,12 @@ NETLIST_START(ripoff)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_7, 0) // active high
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_7, 0) // active high
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND, I_OUT_7.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC, I_OUT_7.VCC)
@ -130,16 +130,16 @@ NETLIST_START(ripoff)
RES(R43, RES_K(10))
RES(R44, 330)
RES(R45, RES_K(27))
// RES(R46, RES_K(12)) -- part of final amp (not emulated)
// RES(R46, RES_K(12)) -- part of final amp (not emulated)
RES(R47, RES_K(1))
RES(R48, RES_K(2.7))
RES(R49, 470)
// POT(R50, RES_K()) -- listed as optional on schematics
// RES(R51, RES_K(1.5)) -- part of final amp (not emulated)
// RES(R52, 150) -- part of final amp (not emulated)
// RES(R53, RES_K(22)) -- part of final amp (not emulated)
// RES(R54, 150) -- part of final amp (not emulated)
// RES(R55, RES_K(39)) -- part of final amp (not emulated)
// POT(R50, RES_K()) -- listed as optional on schematics
// RES(R51, RES_K(1.5)) -- part of final amp (not emulated)
// RES(R52, 150) -- part of final amp (not emulated)
// RES(R53, RES_K(22)) -- part of final amp (not emulated)
// RES(R54, 150) -- part of final amp (not emulated)
// RES(R55, RES_K(39)) -- part of final amp (not emulated)
RES(R56, 150)
RES(R57, RES_K(2.7))
RES(R58, RES_M(1))
@ -189,19 +189,19 @@ NETLIST_START(ripoff)
CAP(C10, CAP_U(0.01))
CAP(C11, CAP_U(0.1))
CAP(C12, CAP_U(0.1))
// CAP(C13, CAP_U()) -- not used according to schematics
// CAP(C13, CAP_U()) -- not used according to schematics
CAP(C14, CAP_U(0.22))
CAP(C15, CAP_U(0.01))
CAP(C16, CAP_U(0.1))
CAP(C17, CAP_U(0.1))
CAP(C18, CAP_U(0.01))
CAP(C19, CAP_U(0.1))
// CAP(C20, CAP_U()) -- not used according to schematics
// CAP(C20, CAP_U()) -- not used according to schematics
CAP(C21, CAP_U(0.68))
// CAP(C22, CAP_U(0.005)) -- part of final amp (not emulated)
// CAP(C23, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C24, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C25, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C22, CAP_U(0.005)) -- part of final amp (not emulated)
// CAP(C23, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C24, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C25, CAP_P(470)) -- part of final amp (not emulated)
CAP(C26, CAP_U(0.1))
CAP(C27, CAP_U(0.1))
CAP(C28, CAP_U(0.01))
@ -209,16 +209,16 @@ NETLIST_START(ripoff)
CAP(C30, CAP_U(0.22))
CAP(C31, CAP_U(0.1))
CAP(C32, CAP_U(0.68))
// CAP(C33, CAP_U(0.1)) -- part of voltage converter (not emulated)
// CAP(C34, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C35, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C36, CAP_U()) -- part of voltage converter (not emulated)
// CAP(C37, CAP_U(0.1)) -- part of voltage converter (not emulated)
// CAP(C38, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C39, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C40, CAP_U()) -- part of voltage converter (not emulated)
// CAP(C41, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C42, CAP_U(0.1)) -- part of voltage converter (not emulated)
// CAP(C33, CAP_U(0.1)) -- part of voltage converter (not emulated)
// CAP(C34, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C35, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C36, CAP_U()) -- part of voltage converter (not emulated)
// CAP(C37, CAP_U(0.1)) -- part of voltage converter (not emulated)
// CAP(C38, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C39, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C40, CAP_U()) -- part of voltage converter (not emulated)
// CAP(C41, CAP_U(25)) -- part of voltage converter (not emulated)
// CAP(C42, CAP_U(0.1)) -- part of voltage converter (not emulated)
D_1N5240(D1)
D_1N914(D2)
@ -234,24 +234,24 @@ NETLIST_START(ripoff)
D_1N5240(D12)
D_1N5240(D13)
Q_2N3906(Q1) // PNP
Q_2N3906(Q2) // PNP
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3906(Q5) // PNP
// Q_2N6292(Q6) // PNP -- part of final amp (not emulated)
// Q_2N6107(Q7) // PNP -- part of final amp (not emulated)
Q_2N3904(Q8) // NPN
Q_2N3904(Q9) // NPN
Q_2N3904(Q10) // NPN
Q_2N3906(Q1) // PNP
Q_2N3906(Q2) // PNP
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3906(Q5) // PNP
// Q_2N6292(Q6) // PNP -- part of final amp (not emulated)
// Q_2N6107(Q7) // PNP -- part of final amp (not emulated)
Q_2N3904(Q8) // NPN
Q_2N3904(Q9) // NPN
Q_2N3904(Q10) // NPN
AMI_S2688(IC1) // Noise generator
AMI_S2688(IC1) // Noise generator
TL081_DIP(IC2) // Op. Amp.
TL081_DIP(IC2) // Op. Amp.
NET_C(IC2.7, I_V15)
NET_C(IC2.4, I_VM15)
CA3080_DIP(IC3) // Op. Amp.
CA3080_DIP(IC3) // Op. Amp.
NET_C(IC3.4, I_VM15)
NET_C(IC3.7, I_V15)
@ -259,74 +259,74 @@ NETLIST_START(ripoff)
LM555_DIP(IC5)
CA3080_DIP(IC6) // Op. Amp.
CA3080_DIP(IC6) // Op. Amp.
NET_C(IC6.4, I_VM15)
NET_C(IC6.7, I_V15)
TL081_DIP(IC7) // Op. Amp.
TL081_DIP(IC7) // Op. Amp.
NET_C(IC7.7, I_V15)
NET_C(IC7.4, I_VM15)
TTL_74LS164_DIP(IC8) // 8-bit Shift Reg.
TTL_74LS164_DIP(IC8) // 8-bit Shift Reg.
NET_C(IC8.7, GND)
NET_C(IC8.14, I_V5)
TTL_74LS377_DIP(IC9) // Octal D Flip Flop
TTL_74LS377_DIP(IC9) // Octal D Flip Flop
NET_C(IC9.10, GND)
NET_C(IC9.20, I_V5)
TTL_7406_DIP(IC10) // Hex inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(IC10) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(IC10.7, GND)
NET_C(IC10.14, I_V5)
LM555_DIP(IC11)
CA3080_DIP(IC12) // Op. Amp.
CA3080_DIP(IC12) // Op. Amp.
NET_C(IC12.4, I_VM15)
NET_C(IC12.7, I_V15)
LM555_DIP(IC13)
TL081_DIP(IC14) // Op. Amp.
TL081_DIP(IC14) // Op. Amp.
NET_C(IC14.7, I_V15)
NET_C(IC14.4, I_VM15)
TL081_DIP(IC15) // Op. Amp.
TL081_DIP(IC15) // Op. Amp.
NET_C(IC15.7, I_V15)
NET_C(IC15.4, I_VM15)
TL081_DIP(IC16) // Op. Amp.
TL081_DIP(IC16) // Op. Amp.
NET_C(IC16.7, I_V15)
NET_C(IC16.4, I_VM15)
TL081_DIP(IC17) // Op. Amp.
TL081_DIP(IC17) // Op. Amp.
NET_C(IC17.7, I_V15)
NET_C(IC17.4, I_VM15)
TTL_74LS393_DIP(IC18) // Dual 4 Bit B.C.
TTL_74LS393_DIP(IC18) // Dual 4 Bit B.C.
NET_C(IC18.7, GND)
NET_C(IC18.14, I_V5)
TL081_DIP(IC19) // Op. Amp.
TL081_DIP(IC19) // Op. Amp.
NET_C(IC19.7, I_V15)
NET_C(IC19.4, I_VM15)
TL081_DIP(IC20) // Op. Amp.
TL081_DIP(IC20) // Op. Amp.
NET_C(IC20.7, I_V15)
NET_C(IC20.4, I_VM15)
TL081_DIP(IC21) // Op. Amp.
TL081_DIP(IC21) // Op. Amp.
NET_C(IC21.7, I_V15)
NET_C(IC21.4, I_VM15)
TTL_74LS393_DIP(IC22) // Dual 4 Bit B.C.
TTL_74LS393_DIP(IC22) // Dual 4 Bit B.C.
NET_C(IC22.7, GND)
NET_C(IC22.14, I_V5)
// TTL_7915_DIP(IC23) // -15V Regulator -- not emulated
// TTL_7815_DIP(IC24) // +15V Regulator -- not emulated
// TTL_7915_DIP(IC23) // -15V Regulator -- not emulated
// TTL_7815_DIP(IC24) // +15V Regulator -- not emulated
TTL_7414_DIP(IC25) // Hex Inverter
TTL_7414_DIP(IC25) // Hex Inverter
NET_C(IC25.7, GND)
NET_C(IC25.14, I_V5)
@ -335,7 +335,7 @@ NETLIST_START(ripoff)
//
NET_C(I_OUT_7, R7.1, IC4.2)
NET_C(IC4.8, IC4.4, I_V5) // pin 4 not documented in schematics
NET_C(IC4.8, IC4.4, I_V5) // pin 4 not documented in schematics
NET_C(R7.2, I_V5)
NET_C(R8.2, I_V5)
NET_C(R8.1, IC4.6, IC4.7, C6.1)
@ -402,7 +402,7 @@ NETLIST_START(ripoff)
NET_C(IC10.4, R27.2, R28.1)
NET_C(IC9.6, IC10.5)
NET_C(IC10.6, R29.2, R30.1)
NET_C(R29.1, R27.1, R25.1, D1.K, R23.1) // also R50.2 if present
NET_C(R29.1, R27.1, R25.1, D1.K, R23.1) // also R50.2 if present
NET_C(R23.2, I_V15)
NET_C(D1.A, GND)
NET_C(R26.2, R28.2, R30.2, R76.1, IC19.2) // also R50.1 if present
@ -671,31 +671,31 @@ NETLIST_START(ripoff)
//
NET_C(GND, IC9.17, IC9.18, IC10.9, IC22.12, IC22.13)
NET_C(GND, IC14.2, IC14.3, IC15.2, IC15.3) // part of final amp
NET_C(GND, IC14.2, IC14.3, IC15.2, IC15.3) // part of final amp
//
// Unconnected outputs
//
HINT(IC9.16, NC) // Q6
HINT(IC9.19, NC) // Q7
HINT(IC10.8, NC) // QD
HINT(IC22.11, NC) // Q0
HINT(IC22.10, NC) // Q1
HINT(IC22.9, NC) // Q2
HINT(IC22.8, NC) // Q3
HINT(IC9.16, NC) // Q6
HINT(IC9.19, NC) // Q7
HINT(IC10.8, NC) // QD
HINT(IC22.11, NC) // Q0
HINT(IC22.10, NC) // Q1
HINT(IC22.9, NC) // Q2
HINT(IC22.8, NC) // Q3
#if (ENABLE_FRONTIERS)
//
// Split explosion/beep/motor from other sources
//
OPTIMIZE_FRONTIER(R45.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(IC7.3, RES_M(1), 50)
OPTIMIZE_FRONTIER(R45.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(IC7.3, RES_M(1), 50)
//
// Split noise generator from consumers
//
OPTIMIZE_FRONTIER(R1.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R1.1, RES_M(1), 50)
#endif
NETLIST_END()

2000
src/mame/audio/nl_solarq.cpp
View File

File diff suppressed because it is too large Load Diff

104
src/mame/audio/nl_spacewar.cpp
View File

@ -36,13 +36,13 @@ NETLIST_START(spacewar)
SOLVER(Solver, 1000)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
// PARAM(Solver.MIN_TS_TS, 2e-5)
// PARAM(Solver.MIN_TS_TS, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC)
@ -64,7 +64,7 @@ NETLIST_START(spacewar)
RES(R9, RES_K(39))
RES(R10, RES_K(2.2))
RES(R11, 470)
// RES(R12, 0) -- not present on Space Wars
// RES(R12, 0) -- not present on Space Wars
RES(R13, RES_K(8.2))
RES(R14, RES_K(120))
RES(R15, RES_K(20))
@ -72,17 +72,17 @@ NETLIST_START(spacewar)
RES(R17, RES_K(10))
RES(R18, RES_K(47))
RES(R19, 820)
// POT(R20, RES_K(10)) -- part of final amp (not emulated)
// RES(R21, 150) -- part of final amp (not emulated), not present on Space Wars
// RES(R22, 2.7) -- part of final amp (not emulated), not present on Space Wars
// RES(R23, 2.7) -- part of final amp (not emulated), not present on Space Wars
// POT(R20, RES_K(10)) -- part of final amp (not emulated)
// RES(R21, 150) -- part of final amp (not emulated), not present on Space Wars
// RES(R22, 2.7) -- part of final amp (not emulated), not present on Space Wars
// RES(R23, 2.7) -- part of final amp (not emulated), not present on Space Wars
RES(R24, RES_K(47))
RES(R25, 150)
RES(R26, RES_K(160))
RES(R27, 750)
// RES(R28, RES_K(68)) -- part of final amp (not emulated), illegible on Space Wars
// POT(R29, RES_K(10)) -- part of final amp (not emulated)
// RES(R30, 750) -- part of final amp (not emulated)
// RES(R28, RES_K(68)) -- part of final amp (not emulated), illegible on Space Wars
// POT(R29, RES_K(10)) -- part of final amp (not emulated)
// RES(R30, 750) -- part of final amp (not emulated)
RES(R31, 470)
RES(R32, RES_K(1))
RES(R33, RES_K(39))
@ -91,7 +91,7 @@ NETLIST_START(spacewar)
RES(R36, RES_M(1))
RES(R37, RES_K(10))
RES(R38, RES_K(10))
// RES(R39, RES_K(120))
// RES(R39, RES_K(120))
RES(R40, RES_K(120))
RES(R41, RES_K(20))
RES(R42, RES_K(1))
@ -102,21 +102,21 @@ NETLIST_START(spacewar)
CAP(C3, CAP_U(0.01))
CAP(C4, CAP_U(0.01))
CAP(C5, CAP_U(0.1))
// CAP(C6, CAP_U(4.7)) // not needed
// CAP(C7, 0) // not present
// CAP(C6, CAP_U(4.7)) // not needed
// CAP(C7, 0) // not present
CAP(C8, CAP_U(1))
CAP(C9, CAP_U(0.1))
CAP(C10, CAP_P(220))
CAP(C11, CAP_U(0.1))
// CAP(C12, CAP_U(0.01)) -- part of final amp (not emulated)
// CAP(C13, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C14, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C15, CAP_U(50)) -- not needed
// CAP(C16, CAP_U(2.2)) -- not needed
// CAP(C12, CAP_U(0.01)) -- part of final amp (not emulated)
// CAP(C13, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C14, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C15, CAP_U(50)) -- not needed
// CAP(C16, CAP_U(2.2)) -- not needed
CAP(C17, CAP_U(0.01))
CAP(C18, CAP_U(33))
// CAP(C19, CAP_U(50)) -- not needed
// CAP(C20, CAP_U(2.2)) -- not needed
// CAP(C19, CAP_U(50)) -- not needed
// CAP(C20, CAP_U(2.2)) -- not needed
CAP(C21, CAP_U(0.02))
CAP(C22, CAP_U(0.1))
CAP(C23, CAP_U(0.1))
@ -129,49 +129,49 @@ NETLIST_START(spacewar)
D_1N914(CR5)
D_1N914(CR6)
Q_2N3906(Q1) // PNP
Q_2N3904(Q2) // NPN
Q_2N6426(Q3) // NPN Darlington
Q_2N6292(Q4) // NPN
Q_2N6107(Q5) // PNP
Q_2N6426(Q6) // NPN Darlington
Q_2N3904(Q7) // NPN
Q_2N3906(Q1) // PNP
Q_2N3904(Q2) // NPN
Q_2N6426(Q3) // NPN Darlington
Q_2N6292(Q4) // NPN
Q_2N6107(Q5) // PNP
Q_2N6426(Q6) // NPN Darlington
Q_2N3904(Q7) // NPN
TL081_DIP(U1) // Op. Amp.
TL081_DIP(U1) // Op. Amp.
NET_C(U1.4, I_VM15)
NET_C(U1.7, I_V15)
TTL_7406_DIP(U2) // Hex inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(U2) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(U2.7, GND)
NET_C(U2.14, I_V5)
TL081_DIP(U3) // Op. Amp.
TL081_DIP(U3) // Op. Amp.
NET_C(U3.4, I_VM15)
NET_C(U3.7, I_V15)
// TTL_7815_DIP(U4) // +15V Regulator -- not needed
// TTL_7815_DIP(U4) // +15V Regulator -- not needed
TL182_DIP(U5) // Analog switch
TL182_DIP(U5) // Analog switch
NET_C(U5.6, I_V15)
NET_C(U5.7, I_V5)
NET_C(U5.8, GND)
NET_C(U5.9, I_VM15)
// TL081_DIP(U6) // Op. Amp. -- part of final amp (not emulated)
// NET_C(U6.4, I_VM15)
// NET_C(U6.7, I_V15)
// TL081_DIP(U6) // Op. Amp. -- part of final amp (not emulated)
// NET_C(U6.4, I_VM15)
// NET_C(U6.7, I_V15)
// TTL_7915_DIP(U7) // -15V Regulator -- not needed
// TTL_7915_DIP(U7) // -15V Regulator -- not needed
TL081_DIP(U8) // Op. Amp.
TL081_DIP(U8) // Op. Amp.
NET_C(U8.4, I_VM15)
NET_C(U8.7, I_V15)
TL081_DIP(U9) // Op. Amp.
TL081_DIP(U9) // Op. Amp.
NET_C(U9.4, I_VM15)
NET_C(U9.7, I_V15)
TL182_DIP(U10) // Analog switch
TL182_DIP(U10) // Analog switch
NET_C(U10.6, I_V15)
NET_C(U10.7, I_V5)
NET_C(U10.8, GND)
@ -296,19 +296,19 @@ NETLIST_START(spacewar)
#if (ENABLE_FRONTIERS)
// Separate each input into the summing network
OPTIMIZE_FRONTIER(R13.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R15.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R41.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R37.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R13.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R15.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R41.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R37.1, RES_M(1), 50)
// Decouple the Darlington BJTs from the sounds they enable
OPTIMIZE_FRONTIER(R27.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R11.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(R27.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R11.2, RES_M(1), 50)
// Decouple the noise source from the downstream filters
OPTIMIZE_FRONTIER(C3.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R24.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R38.2, RES_M(1), 50)
OPTIMIZE_FRONTIER(C3.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R24.1, RES_M(1), 50)
OPTIMIZE_FRONTIER(R38.2, RES_M(1), 50)
#endif
NETLIST_END()

280
src/mame/audio/nl_speedfrk.cpp
View File

@ -39,12 +39,12 @@ NETLIST_START(speedfrk)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 1) // active low
TTL_INPUT(I_OUT_1, 1) // active low
TTL_INPUT(I_OUT_2, 1) // active low
TTL_INPUT(I_OUT_3, 1) // active low
TTL_INPUT(I_OUT_4, 1) // active low
TTL_INPUT(I_OUT_7, 1) // active low
TTL_INPUT(I_OUT_0, 1) // active low
TTL_INPUT(I_OUT_1, 1) // active low
TTL_INPUT(I_OUT_2, 1) // active low
TTL_INPUT(I_OUT_3, 1) // active low
TTL_INPUT(I_OUT_4, 1) // active low
TTL_INPUT(I_OUT_7, 1) // active low
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND, I_OUT_7.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC, I_OUT_7.VCC)
@ -53,162 +53,162 @@ NETLIST_START(speedfrk)
ANALOG_INPUT(I_V5, 5)
// RES(R1, 2.7)
// RES(R2, 2.7)
// RES(R3, 2.7)
// RES(R4, 2.7)
// RES(R5, 150) // PCB verified
// RES(R6, 150)
// RES(R7, RES_K(10)) // PCB verified
// RES(R8, RES_K(68)) // PCB verified
// RES(R9, RES_K(2.2)) // PCB verified
// RES(R10, 820) // PCB verified
// RES(R11, RES_K(47)) // PCB verified
// RES(R12, RES_K(1)) ??
// RES(R1, 2.7)
// RES(R2, 2.7)
// RES(R3, 2.7)
// RES(R4, 2.7)
// RES(R5, 150) // PCB verified
// RES(R6, 150)
// RES(R7, RES_K(10)) // PCB verified
// RES(R8, RES_K(68)) // PCB verified
// RES(R9, RES_K(2.2)) // PCB verified
// RES(R10, 820) // PCB verified
// RES(R11, RES_K(47)) // PCB verified
// RES(R12, RES_K(1)) ??
RES(R13, 150)
RES(R14, RES_K(2.2)) // PCB verified
RES(R15, RES_K(10)) // PCB verified
RES(R16, RES_K(2.2)) // PCB verified
RES(R17, RES_K(1)) // PCB verified
RES(R18, RES_K(8.2)) // PCB verified
RES(R19, RES_K(3.9)) // PCB verified
RES(R20, RES_K(4.7)) // PCB verified
RES(R21, RES_K(3.3)) // PCB verified
RES(R22, RES_K(10)) // PCB verified
RES(R23, RES_K(4.7)) // PCB verified
RES(R14, RES_K(2.2)) // PCB verified
RES(R15, RES_K(10)) // PCB verified
RES(R16, RES_K(2.2)) // PCB verified
RES(R17, RES_K(1)) // PCB verified
RES(R18, RES_K(8.2)) // PCB verified
RES(R19, RES_K(3.9)) // PCB verified
RES(R20, RES_K(4.7)) // PCB verified
RES(R21, RES_K(3.3)) // PCB verified
RES(R22, RES_K(10)) // PCB verified
RES(R23, RES_K(4.7)) // PCB verified
RES(R24, RES_K(10))
RES(R25, RES_K(18)) // PCB verified
RES(R26, RES_K(18)) // PCB verified
RES(R27, RES_K(6.8)) // PCB verified
RES(R28, RES_K(10)) // PCB verified
RES(R29, RES_K(2.2)) // PCB verified
RES(R30, 330) // PCB verified
RES(R31, 330) // PCB verified
RES(R32, RES_K(1)) // PCB verified
RES(R33, RES_K(1)) // PCB verified
RES(R34, RES_K(1)) // PCB verified
// RES(R35, 0) // PCB verified: not populated
RES(R36, RES_K(1)) // PCB verified
RES(R37, RES_K(1)) // PCB verified
RES(R38, RES_K(1)) // PCB verified
RES(R39, RES_K(1)) // PCB verified
RES(R40, RES_K(1)) // PCB verified
RES(R41, RES_K(1)) // PCB verified
RES(R42, RES_K(1)) // PCB verified
RES(R43, RES_K(1)) // PCB verified
RES(R44, RES_K(30)) // PCB verified
RES(R45, RES_K(4.7)) // PCB verified
RES(R46, RES_K(10)) // PCB verified
RES(R25, RES_K(18)) // PCB verified
RES(R26, RES_K(18)) // PCB verified
RES(R27, RES_K(6.8)) // PCB verified
RES(R28, RES_K(10)) // PCB verified
RES(R29, RES_K(2.2)) // PCB verified
RES(R30, 330) // PCB verified
RES(R31, 330) // PCB verified
RES(R32, RES_K(1)) // PCB verified
RES(R33, RES_K(1)) // PCB verified
RES(R34, RES_K(1)) // PCB verified
// RES(R35, 0) // PCB verified: not populated
RES(R36, RES_K(1)) // PCB verified
RES(R37, RES_K(1)) // PCB verified
RES(R38, RES_K(1)) // PCB verified
RES(R39, RES_K(1)) // PCB verified
RES(R40, RES_K(1)) // PCB verified
RES(R41, RES_K(1)) // PCB verified
RES(R42, RES_K(1)) // PCB verified
RES(R43, RES_K(1)) // PCB verified
RES(R44, RES_K(30)) // PCB verified
RES(R45, RES_K(4.7)) // PCB verified
RES(R46, RES_K(10)) // PCB verified
// CAP(C4, CAP_U(4.7))
// CAP(C5, CAP_U(4.7))
// CAP(C4, CAP_U(4.7))
// CAP(C5, CAP_U(4.7))
CAP(C12, CAP_U(0.001))
CAP(C13, CAP_U(0.001))
CAP(C17, CAP_U(0.02))
CAP(C20, CAP_U(0.1))
CAP(C23, CAP_U(0.1))
// CAP(C1, CAP_U(50))
// CAP(C2, CAP_U(50))
// CAP(C3, CAP_U(4.7))
// CAP(C6, CAP_U(0.002))
// CAP(C7, CAP_U(0.002))
// CAP(C8, CAP_U(0.01))
// CAP(C9, CAP_U(0.1))
// CAP(C10, CAP_U(0.1))
// CAP(C11, CAP_U(0.02))
// CAP(C1, CAP_U(50))
// CAP(C2, CAP_U(50))
// CAP(C3, CAP_U(4.7))
// CAP(C6, CAP_U(0.002))
// CAP(C7, CAP_U(0.002))
// CAP(C8, CAP_U(0.01))
// CAP(C9, CAP_U(0.1))
// CAP(C10, CAP_U(0.1))
// CAP(C11, CAP_U(0.02))
// D_1N914B(CR1) // OK
// D_1N914B(CR2) // OK
D_1N914B(CR3) // OK
// D_1N914B(CR1) // OK
// D_1N914B(CR2) // OK
D_1N914B(CR3) // OK
// Q_2N6292(Q1) // NPN
// Q_2N6107(Q2) // PNP
Q_2N3904(Q3) // NPN
// Q_2N3904(Q3) // NPN -- unknown type
// Q_2N6292(Q1) // NPN
// Q_2N6107(Q2) // PNP
Q_2N3904(Q3) // NPN
// Q_2N3904(Q3) // NPN -- unknown type
TTL_74LS04_DIP(U2) // Hex Inverting Gates
TTL_74LS04_DIP(U2) // Hex Inverting Gates
NET_C(U2.7, GND)
NET_C(U2.14, I_V5)
TL081_DIP(U3) // Op. Amp.
TL081_DIP(U3) // Op. Amp.
NET_C(U3.4, GND)
NET_C(U3.7, I_V5)
TTL_74LS163_DIP(U4) // Synchronous 4-Bit Counters
TTL_74LS163_DIP(U4) // Synchronous 4-Bit Counters
NET_C(U4.8, GND)
NET_C(U4.16, I_V5)
TTL_74LS107_DIP(U5) // DUAL J-K FLIP-FLOPS WITH CLEAR
TTL_74LS107_DIP(U5) // DUAL J-K FLIP-FLOPS WITH CLEAR
NET_C(U5.7, GND)
NET_C(U5.14, I_V5)
TTL_74LS08_DIP(U6) // Quad 2-Input AND Gates
TTL_74LS08_DIP(U6) // Quad 2-Input AND Gates
NET_C(U6.7, GND)
NET_C(U6.14, I_V5)
TTL_74LS163_DIP(U7) // Synchronous 4-Bit Counters
TTL_74LS163_DIP(U7) // Synchronous 4-Bit Counters
NET_C(U7.8, GND)
NET_C(U7.16, I_V5)
TTL_74LS163_DIP(U8) // Synchronous 4-Bit Counters
TTL_74LS163_DIP(U8) // Synchronous 4-Bit Counters
NET_C(U8.8, GND)
NET_C(U8.16, I_V5)
TTL_74LS163_DIP(U9) // Synchronous 4-Bit Counters
TTL_74LS163_DIP(U9) // Synchronous 4-Bit Counters
NET_C(U9.8, GND)
NET_C(U9.16, I_V5)
// TTL_7915_DIP(U8) // -15V Regulator -- not needed
// TTL_7815_DIP(U9) // +15V Regulator -- not needed
// TTL_7915_DIP(U8) // -15V Regulator -- not needed
// TTL_7815_DIP(U9) // +15V Regulator -- not needed
TTL_74LS04_DIP(U10) // Hex Inverting Gates
TTL_74LS04_DIP(U10) // Hex Inverting Gates
NET_C(U10.7, GND)
NET_C(U10.14, I_V5)
TTL_74LS08_DIP(U11) // Quad 2-Input AND Gates
TTL_74LS08_DIP(U11) // Quad 2-Input AND Gates
NET_C(U11.7, GND)
NET_C(U11.14, I_V5)
TTL_74LS75_DIP(U12) // 4-Bit Bistable Latches with Complementary Outputs
TTL_74LS75_DIP(U12) // 4-Bit Bistable Latches with Complementary Outputs
NET_C(U12.12, GND)
NET_C(U12.5, I_V5)
TTL_74LS164_DIP(U13) // 8-bit parallel-out serial shift registers
TTL_74LS164_DIP(U13) // 8-bit parallel-out serial shift registers
NET_C(U13.7, GND)
NET_C(U13.14, I_V5)
TTL_74LS164_DIP(U14) // 8-bit parallel-out serial shift registers
TTL_74LS164_DIP(U14) // 8-bit parallel-out serial shift registers
NET_C(U14.7, GND)
NET_C(U14.14, I_V5)
TTL_74LS163_DIP(U15) // Synchronous 4-Bit Counters
TTL_74LS163_DIP(U15) // Synchronous 4-Bit Counters
NET_C(U15.8, GND)
NET_C(U15.16, I_V5)
TTL_74LS107_DIP(U17) // DUAL J-K FLIP-FLOPS WITH CLEAR
TTL_74LS107_DIP(U17) // DUAL J-K FLIP-FLOPS WITH CLEAR
NET_C(U17.7, GND)
NET_C(U17.14, I_V5)
TTL_74LS393_DIP(U18) // Dual 4-Stage Binary Counter
TTL_74LS393_DIP(U18) // Dual 4-Stage Binary Counter
NET_C(U18.7, GND)
NET_C(U18.14, I_V5)
TTL_74LS86_DIP(U19) // Quad 2-Input XOR Gates
TTL_74LS86_DIP(U19) // Quad 2-Input XOR Gates
NET_C(U19.7, GND)
NET_C(U19.14, I_V5)
TTL_74LS164_DIP(U20) // 8-bit parallel-out serial shift registers
TTL_74LS164_DIP(U20) // 8-bit parallel-out serial shift registers
NET_C(U20.7, GND)
NET_C(U20.14, I_V5)
LM555_DIP(U22) // 5-5-5 Timer
LM555_DIP(U22) // 5-5-5 Timer
TTL_74LS163_DIP(U23) // Dual 4-Stage Binary Counter
TTL_74LS163_DIP(U23) // Dual 4-Stage Binary Counter
NET_C(U23.8, GND)
NET_C(U23.16, I_V5)
TTL_74LS164_DIP(U24) // 8-bit parallel-out serial shift registers
TTL_74LS164_DIP(U24) // 8-bit parallel-out serial shift registers
NET_C(U24.7, GND)
NET_C(U24.14, I_V5)
@ -267,7 +267,7 @@ NETLIST_START(speedfrk)
NET_C(U4.6, R36.1)
NET_C(U4.4, U4.5, GND)
NET_C(U4.14, U18.1, U6.13, U7.2)
NET_C(U4.10, I_V5) // need to verify
NET_C(U4.10, I_V5) // need to verify
NET_C(U18.6, U18.13)
NET_C(U18.2, U18.12, GND)
@ -296,7 +296,7 @@ NETLIST_START(speedfrk)
NET_C(U19.11, U20.1)
NET_C(U20.9, R42.1)
// NET_C(R42.2, I_V5)
// NET_C(R42.2, I_V5)
NET_C(U20.2, U19.3)
NET_C(U20.12, U19.1)
NET_C(U20.13, U19.4)
@ -308,7 +308,7 @@ NETLIST_START(speedfrk)
NET_C(U24.13, R44.1, U11.12, U11.9, U11.5, U11.2)
NET_C(U23.1, U23.3, U23.5, U23.7, R40.2)
NET_C(U23.10, R40.2) // need to verify
NET_C(U23.10, R40.2) // need to verify
NET_C(R40.1, I_V5)
NET_C(U23.4, U23.6, GND)
NET_C(U23.9, U19.8, U17.9)
@ -401,51 +401,51 @@ NETLIST_START(speedfrk)
// Unconnected outputs
//
HINT(U4.11, NC) // Q3
HINT(U4.12, NC) // Q2
HINT(U4.13, NC) // Q1
HINT(U5.5, NC) // Q2
HINT(U7.14, NC) // Q0
HINT(U8.11, NC) // Q3
HINT(U8.12, NC) // Q2
HINT(U8.13, NC) // Q1
HINT(U8.14, NC) // Q0
HINT(U9.11, NC) // Q3
HINT(U9.12, NC) // Q2
HINT(U9.13, NC) // Q1
HINT(U9.14, NC) // Q0
HINT(U10.2, NC) // QQ1 -- part of 2MHz clock gen
HINT(U10.4, NC) // QQ2 -- part of 2MHz clock gen
HINT(U10.6, NC) // QQ3 -- part of 2MHz clock gen
HINT(U12.1, NC) // QQ0
HINT(U12.8, NC) // QQ3
HINT(U12.11, NC) // QQ2
HINT(U12.14, NC) // QQ1
HINT(U15.11, NC) // Q3
HINT(U15.12, NC) // Q2
HINT(U15.13, NC) // Q1
HINT(U15.14, NC) // Q0
HINT(U17.2, NC) // QQ1
HINT(U17.6, NC) // QQ2
HINT(U18.3, NC) // Q0
HINT(U18.4, NC) // Q1
HINT(U18.5, NC) // Q2
HINT(U18.9, NC) // Q2
HINT(U20.3, NC) // Q0
HINT(U20.4, NC) // Q1
HINT(U20.5, NC) // Q2
HINT(U20.6, NC) // Q3
HINT(U20.10, NC) // Q4
HINT(U20.11, NC) // Q5
HINT(U23.11, NC) // Q3
HINT(U23.12, NC) // Q2
HINT(U23.13, NC) // Q1
HINT(U23.14, NC) // Q0
HINT(U24.3, NC) // Q0
HINT(U24.4, NC) // Q1
HINT(U24.5, NC) // Q2
HINT(U24.6, NC) // Q3
HINT(U24.10, NC) // Q4
HINT(U24.11, NC) // Q5
HINT(U4.11, NC) // Q3
HINT(U4.12, NC) // Q2
HINT(U4.13, NC) // Q1
HINT(U5.5, NC) // Q2
HINT(U7.14, NC) // Q0
HINT(U8.11, NC) // Q3
HINT(U8.12, NC) // Q2
HINT(U8.13, NC) // Q1
HINT(U8.14, NC) // Q0
HINT(U9.11, NC) // Q3
HINT(U9.12, NC) // Q2
HINT(U9.13, NC) // Q1
HINT(U9.14, NC) // Q0
HINT(U10.2, NC) // QQ1 -- part of 2MHz clock gen
HINT(U10.4, NC) // QQ2 -- part of 2MHz clock gen
HINT(U10.6, NC) // QQ3 -- part of 2MHz clock gen
HINT(U12.1, NC) // QQ0
HINT(U12.8, NC) // QQ3
HINT(U12.11, NC) // QQ2
HINT(U12.14, NC) // QQ1
HINT(U15.11, NC) // Q3
HINT(U15.12, NC) // Q2
HINT(U15.13, NC) // Q1
HINT(U15.14, NC) // Q0
HINT(U17.2, NC) // QQ1
HINT(U17.6, NC) // QQ2
HINT(U18.3, NC) // Q0
HINT(U18.4, NC) // Q1
HINT(U18.5, NC) // Q2
HINT(U18.9, NC) // Q2
HINT(U20.3, NC) // Q0
HINT(U20.4, NC) // Q1
HINT(U20.5, NC) // Q2
HINT(U20.6, NC) // Q3
HINT(U20.10, NC) // Q4
HINT(U20.11, NC) // Q5
HINT(U23.11, NC) // Q3
HINT(U23.12, NC) // Q2
HINT(U23.13, NC) // Q1
HINT(U23.14, NC) // Q0
HINT(U24.3, NC) // Q0
HINT(U24.4, NC) // Q1
HINT(U24.5, NC) // Q2
HINT(U24.6, NC) // Q3
HINT(U24.10, NC) // Q4
HINT(U24.11, NC) // Q5
NETLIST_END()

310
src/mame/audio/nl_starcas.cpp
View File

@ -49,14 +49,14 @@
// once for War of the Worlds
//
#define VARIANT_STARCASTLE 0
#define VARIANT_WOTW 1
#define VARIANT_STARCASTLE 0
#define VARIANT_WOTW 1
#define SOUND_VARIANT (VARIANT_STARCASTLE)
#define SOUND_VARIANT (VARIANT_STARCASTLE)
#include "nl_starcas.cpp"
#undef SOUND_VARIANT
#define SOUND_VARIANT (VARIANT_WOTW)
#define SOUND_VARIANT (VARIANT_WOTW)
#include "nl_starcas.cpp"
@ -82,12 +82,12 @@ NETLIST_START(wotw)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active low
TTL_INPUT(I_OUT_1, 1) // active low
TTL_INPUT(I_OUT_2, 1) // active low
TTL_INPUT(I_OUT_3, 1) // active low
TTL_INPUT(I_OUT_4, 0) // active low
TTL_INPUT(I_OUT_7, 0) // active low
TTL_INPUT(I_OUT_0, 0) // active low
TTL_INPUT(I_OUT_1, 1) // active low
TTL_INPUT(I_OUT_2, 1) // active low
TTL_INPUT(I_OUT_3, 1) // active low
TTL_INPUT(I_OUT_4, 0) // active low
TTL_INPUT(I_OUT_7, 0) // active low
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND, I_OUT_7.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC, I_OUT_7.VCC)
@ -99,31 +99,31 @@ NETLIST_START(wotw)
ANALOG_INPUT(I_VM15, -15)
RES(R1, RES_K(1))
RES(R2, 160)
RES(R3, RES_K(1))
RES(R4, RES_K(1))
RES(R5, RES_K(2))
RES(R6, RES_K(2))
RES(R7, RES_K(4.7))
RES(R8, RES_K(3.3))
RES(R9, 820)
RES(R10, RES_M(3.3))
RES(R11, RES_M(3.3))
RES(R12, RES_M(5.1))
RES(R13, RES_M(1.6))
RES(R14, RES_K(2))
RES(R15, RES_K(18))
RES(R16, RES_K(10))
RES(R17, RES_K(10))
RES(R18, RES_K(91))
RES(R19, RES_K(10))
RES(R20, RES_K(1))
RES(R21, RES_K(2))
RES(R22, RES_K(1))
RES(R24, RES_K(200))
RES(R25, RES_K(30))
RES(R26, RES_K(200))
RES(R27, RES_K(51))
RES(R2, 160)
RES(R3, RES_K(1))
RES(R4, RES_K(1))
RES(R5, RES_K(2))
RES(R6, RES_K(2))
RES(R7, RES_K(4.7))
RES(R8, RES_K(3.3))
RES(R9, 820)
RES(R10, RES_M(3.3))
RES(R11, RES_M(3.3))
RES(R12, RES_M(5.1))
RES(R13, RES_M(1.6))
RES(R14, RES_K(2))
RES(R15, RES_K(18))
RES(R16, RES_K(10))
RES(R17, RES_K(10))
RES(R18, RES_K(91))
RES(R19, RES_K(10))
RES(R20, RES_K(1))
RES(R21, RES_K(2))
RES(R22, RES_K(1))
RES(R24, RES_K(200))
RES(R25, RES_K(30))
RES(R26, RES_K(200))
RES(R27, RES_K(51))
RES(R28, RES_M(1))
RES(R29, 430)
RES(R30, 560)
@ -148,61 +148,61 @@ NETLIST_START(wotw)
RES(R49, RES_K(20))
RES(R50, RES_K(1))
RES(R51, RES_K(12))
RES(R52, RES_K(4.7))
RES(R52, RES_K(4.7))
RES(R53, RES_K(1))
RES(R54, RES_K(39))
RES(R55, RES_K(12))
RES(R56, RES_K(1))
RES(R57, RES_K(100))
RES(R58, RES_K(18))
RES(R58, RES_K(18))
RES(R59, RES_K(15))
RES(R60, RES_K(7.5))
RES(R61, 430)
RES(R62, 430)
RES(R63, RES_K(4.7))
RES(R63, RES_K(4.7))
RES(R64, RES_K(1))
RES(R65, RES_K(39))
RES(R66, RES_K(12))
RES(R67, RES_K(1))
RES(R68, RES_K(100))
RES(R69, RES_K(6.8))
RES(R70, RES_K(18))
RES(R70, RES_K(18))
RES(R71, RES_K(47))
RES(R72, 390)
RES(R73, 390)
RES(R74, RES_K(4.7))
RES(R74, RES_K(4.7))
RES(R75, RES_K(2.7))
RES(R76, RES_K(4.7))
RES(R76, RES_K(4.7))
RES(R77, RES_K(39))
RES(R78, RES_K(12))
RES(R79, RES_K(1))
RES(R80, RES_K(200))
RES(R81, RES_K(300))
RES(R82, RES_K(240))
RES(R80, RES_K(200))
RES(R81, RES_K(300))
RES(R82, RES_K(240))
RES(R83, 200)
RES(R84, 200)
RES(R85, RES_K(4.7))
RES(R85, RES_K(4.7))
RES(R86, RES_K(2.7))
RES(R87, RES_K(4.7))
RES(R87, RES_K(4.7))
RES(R88, RES_K(1))
RES(R89, RES_K(1.8))
RES(R90, RES_K(3.9))
RES(R90, RES_K(3.9))
RES(R91, RES_K(39))
RES(R92, RES_K(12))
RES(R93, 620)
RES(R94, RES_K(360))
RES(R94, RES_K(360))
RES(R95, RES_K(27))
RES(R96, RES_K(33))
RES(R96, RES_K(33))
RES(R97, 47)
RES(R98, 47)
RES(R99, RES_K(4.7))
RES(R99, RES_K(4.7))
RES(R100, RES_K(2.7))
RES(R101, RES_K(4.7))
RES(R101, RES_K(4.7))
RES(R102, RES_K(39))
RES(R103, RES_K(12))
RES(R104, RES_K(1))
RES(R105, RES_K(36))
RES(R106, RES_K(36))
RES(R105, RES_K(36))
RES(R106, RES_K(36))
RES(R107, RES_K(8.2))
RES(R108, RES_K(47))
RES(R109, RES_K(22))
@ -217,64 +217,64 @@ NETLIST_START(wotw)
RES(R118, RES_K(820))
RES(R119, RES_K(100))
// RES(R120, RES_K(390)) -- part of final amp (not emulated)
// RES(R121, RES_K(15)) -- part of final amp (not emulated)
// RES(R122, 150) -- part of final amp (not emulated)
// RES(R123, RES_K(22)) -- part of final amp (not emulated)
// RES(R124, 150) -- part of final amp (not emulated)
// RES(R121, RES_K(15)) -- part of final amp (not emulated)
// RES(R122, 150) -- part of final amp (not emulated)
// RES(R123, RES_K(22)) -- part of final amp (not emulated)
// RES(R124, 150) -- part of final amp (not emulated)
RES(R125, RES_K(8.2))
RES(R126, RES_K(20))
RES(R127, RES_K(30))
RES(R127, RES_K(30))
POT(R128, RES_K(10))
PARAM(R128.DIAL, 0.500000)
// CAP(C2, CAP_U(25)) // electrolytic
// CAP(C4, CAP_U(25)) // electrolytic
// CAP(C5, CAP_U(25)) // electrolytic
// CAP(C7, CAP_U(25)) // electrolytic
// CAP(C9, CAP_U(25)) // electrolytic
CAP(C11, CAP_U(0.68)) // film
CAP(C12, CAP_U(0.001)) // disk
CAP(C13, CAP_U(0.0022)) // film
CAP(C14, CAP_U(0.1)) // film
CAP(C15, CAP_U(0.1)) // film
CAP(C16, CAP_U(0.1)) // disk*
CAP(C17, CAP_U(100)) // electrolytic
CAP(C18, CAP_U(0.1)) // film
CAP(C19, CAP_U(0.1)) // disk*
CAP(C20, CAP_U(0.1)) // film
CAP(C21, CAP_U(0.01)) // disk
CAP(C22, CAP_U(0.68)) // film
CAP(C23, CAP_U(0.001)) // disk
CAP(C24, CAP_U(0.0047)) // film
CAP(C25, CAP_U(0.1)) // film
CAP(C26, CAP_U(0.1)) // film
CAP(C27, CAP_U(2.2)) // electrolytic
CAP(C28, CAP_U(0.22)) // film
CAP(C29, CAP_U(0.1)) // film
CAP(C30, CAP_U(4.7)) // electrolytic
CAP(C31, CAP_U(0.1)) // film
CAP(C32, CAP_U(0.01)) // film
CAP(C33, CAP_U(0.68)) // film
CAP(C34, CAP_U(3.3)) // electrolytic
CAP(C35, CAP_U(0.22)) // film
CAP(C36, CAP_U(0.33)) // film
CAP(C37, CAP_U(0.47)) // film
CAP(C38, CAP_U(0.01)) // disk
CAP(C39, CAP_U(0.68)) // film
CAP(C40, CAP_U(0.1)) // film
CAP(C41, CAP_U(0.01)) // disk
CAP(C42, CAP_U(0.1)) // film
// CAP(C43, CAP_U(0.68)) // film -- part of final amp (not emulated)
// CAP(C44, CAP_P(470)) // disk -- part of final amp (not emulated)
// CAP(C45, CAP_P(470)) // disk -- part of final amp (not emulated)
// CAP(C46, CAP_P(470)) // disk -- part of final amp (not emulated)
// CAP(C47, CAP_U(0.005)) // disk -- part of final amp (not emulated)
CAP(C48, CAP_U(0.33)) // film
// CAP(C2, CAP_U(25)) // electrolytic
// CAP(C4, CAP_U(25)) // electrolytic
// CAP(C5, CAP_U(25)) // electrolytic
// CAP(C7, CAP_U(25)) // electrolytic
// CAP(C9, CAP_U(25)) // electrolytic
CAP(C11, CAP_U(0.68)) // film
CAP(C12, CAP_U(0.001)) // disk
CAP(C13, CAP_U(0.0022)) // film
CAP(C14, CAP_U(0.1)) // film
CAP(C15, CAP_U(0.1)) // film
CAP(C16, CAP_U(0.1)) // disk*
CAP(C17, CAP_U(100)) // electrolytic
CAP(C18, CAP_U(0.1)) // film
CAP(C19, CAP_U(0.1)) // disk*
CAP(C20, CAP_U(0.1)) // film
CAP(C21, CAP_U(0.01)) // disk
CAP(C22, CAP_U(0.68)) // film
CAP(C23, CAP_U(0.001)) // disk
CAP(C24, CAP_U(0.0047)) // film
CAP(C25, CAP_U(0.1)) // film
CAP(C26, CAP_U(0.1)) // film
CAP(C27, CAP_U(2.2)) // electrolytic
CAP(C28, CAP_U(0.22)) // film
CAP(C29, CAP_U(0.1)) // film
CAP(C30, CAP_U(4.7)) // electrolytic
CAP(C31, CAP_U(0.1)) // film
CAP(C32, CAP_U(0.01)) // film
CAP(C33, CAP_U(0.68)) // film
CAP(C34, CAP_U(3.3)) // electrolytic
CAP(C35, CAP_U(0.22)) // film
CAP(C36, CAP_U(0.33)) // film
CAP(C37, CAP_U(0.47)) // film
CAP(C38, CAP_U(0.01)) // disk
CAP(C39, CAP_U(0.68)) // film
CAP(C40, CAP_U(0.1)) // film
CAP(C41, CAP_U(0.01)) // disk
CAP(C42, CAP_U(0.1)) // film
// CAP(C43, CAP_U(0.68)) // film -- part of final amp (not emulated)
// CAP(C44, CAP_P(470)) // disk -- part of final amp (not emulated)
// CAP(C45, CAP_P(470)) // disk -- part of final amp (not emulated)
// CAP(C46, CAP_P(470)) // disk -- part of final amp (not emulated)
// CAP(C47, CAP_U(0.005)) // disk -- part of final amp (not emulated)
CAP(C48, CAP_U(0.33)) // film
// D_1N4003(D1) // not needed
// D_1N4003(D2) // not needed
// D_1N4003(D3) // not needed
// D_1N4003(D4) // not needed
// D_1N4003(D1) // not needed
// D_1N4003(D2) // not needed
// D_1N4003(D3) // not needed
// D_1N4003(D4) // not needed
D_1N5240B(D5)
D_1N5236B(D6)
D_1N914B(D7)
@ -282,121 +282,121 @@ NETLIST_START(wotw)
D_1N914B(D9)
D_1N914B(D10)
Q_2N3904(Q1) // NPN
Q_2N3904(Q2) // NPN
Q_2N3906(Q3) // PNP
Q_2N3904(Q4) // NPN
Q_2N3904(Q5) // NPN
Q_2N3906(Q6) // PNP
Q_2N3906(Q7) // PNP
Q_2N3906(Q8) // PNP
Q_2N3906(Q9) // PNP
Q_2N3906(Q10) // PNP
Q_2N3906(Q11) // PNP
Q_2N3906(Q12) // PNP
Q_2N3906(Q13) // PNP
Q_2N3906(Q14) // PNP
Q_2N3906(Q15) // PNP
Q_2N3906(Q16) // PNP
// Q_2N6107(Q17) // PNP -- part of final amp (not emulated)
// Q_2N6292(Q18) // NPN -- part of final amp (not emulated)
Q_2N3904(Q1) // NPN
Q_2N3904(Q2) // NPN
Q_2N3906(Q3) // PNP
Q_2N3904(Q4) // NPN
Q_2N3904(Q5) // NPN
Q_2N3906(Q6) // PNP
Q_2N3906(Q7) // PNP
Q_2N3906(Q8) // PNP
Q_2N3906(Q9) // PNP
Q_2N3906(Q10) // PNP
Q_2N3906(Q11) // PNP
Q_2N3906(Q12) // PNP
Q_2N3906(Q13) // PNP
Q_2N3906(Q14) // PNP
Q_2N3906(Q15) // PNP
Q_2N3906(Q16) // PNP
// Q_2N6107(Q17) // PNP -- part of final amp (not emulated)
// Q_2N6292(Q18) // NPN -- part of final amp (not emulated)
TTL_7414_DIP(IC1) // Hex Inverter
TTL_7414_DIP(IC1) // Hex Inverter
NET_C(IC1.7, GND)
NET_C(IC1.14, I_V5)
TTL_74LS164_DIP(IC2) // 8-bit Shift Reg.
TTL_74LS164_DIP(IC2) // 8-bit Shift Reg.
NET_C(IC2.7, GND)
NET_C(IC2.14, I_V5)
TTL_74LS377_DIP(IC3) // Octal D Flip Flop
TTL_74LS377_DIP(IC3) // Octal D Flip Flop
NET_C(IC3.10, GND)
NET_C(IC3.20, I_V5)
// TTL_7815_DIP(IC4) // +15V Regulator -- not needed
// TTL_7915_DIP(IC5) // -15V Regulator -- not needed
// TTL_7815_DIP(IC4) // +15V Regulator -- not needed
// TTL_7915_DIP(IC5) // -15V Regulator -- not needed
TTL_7406_DIP(IC6) // Hex Inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(IC6) // Hex Inverter -- currently using a clone of 7416, no open collector behavior
NET_C(IC6.7, GND)
NET_C(IC6.14, I_V5)
TL081_DIP(IC7) // Op. Amp.
TL081_DIP(IC7) // Op. Amp.
NET_C(IC7.7, I_V15)
NET_C(IC7.4, I_VM15)
TL081_DIP(IC8) // Op. Amp.
TL081_DIP(IC8) // Op. Amp.
NET_C(IC8.7, I_V15)
NET_C(IC8.4, I_VM15)
#if (!HLE_BACKGROUND_VCO)
LM566_DIP(IC9) // 566 VCO
LM566_DIP(IC9) // 566 VCO
#endif
TTL_74LS163_DIP(IC10) // Binary Counter (schems say can sub a 74161)
TTL_74LS163_DIP(IC10) // Binary Counter (schems say can sub a 74161)
NET_C(IC10.8, GND)
NET_C(IC10.16, I_V5)
TTL_74LS163_DIP(IC11) // Binary Counter (schems say can sub a 74161)
TTL_74LS163_DIP(IC11) // Binary Counter (schems say can sub a 74161)
NET_C(IC11.8, GND)
NET_C(IC11.16, I_V5)
TTL_74LS393_DIP(IC12) // Dual 4 Bit B.C.
TTL_74LS393_DIP(IC12) // Dual 4 Bit B.C.
NET_C(IC12.7, GND)
NET_C(IC12.14, I_V5)
TTL_74LS393_DIP(IC13) // Dual 4 Bit B.C.
TTL_74LS393_DIP(IC13) // Dual 4 Bit B.C.
NET_C(IC13.7, GND)
NET_C(IC13.14, I_V5)
AMI_S2688(IC14) // Noise generator
AMI_S2688(IC14) // Noise generator
TL081_DIP(IC15) // Op. Amp.
TL081_DIP(IC15) // Op. Amp.
NET_C(IC15.7, I_V15)
NET_C(IC15.4, I_VM15)
LM555_DIP(IC16) // Timer
LM555_DIP(IC16) // Timer
#if (!HLE_LASER_VCO)
LM566_DIP(IC17) // 566 VCO
LM566_DIP(IC17) // 566 VCO
#endif
CA3080_DIP(IC18) // Trnscndt. Op. Amp.
CA3080_DIP(IC18) // Trnscndt. Op. Amp.
NET_C(IC18.7, I_V15)
NET_C(IC18.4, I_VM15)
CA3080_DIP(IC19) // Trnscndt. Op. Amp.
CA3080_DIP(IC19) // Trnscndt. Op. Amp.
NET_C(IC19.7, I_V15)
NET_C(IC19.4, I_VM15)
CA3080_DIP(IC20) // Trnscndt. Op. Amp.
CA3080_DIP(IC20) // Trnscndt. Op. Amp.
NET_C(IC20.7, I_V15)
NET_C(IC20.4, I_VM15)
CA3080_DIP(IC21) // Trnscndt. Op. Amp.
CA3080_DIP(IC21) // Trnscndt. Op. Amp.
NET_C(IC21.7, I_V15)
NET_C(IC21.4, I_VM15)
CA3080_DIP(IC22) // Trnscndt. Op. Amp.
CA3080_DIP(IC22) // Trnscndt. Op. Amp.
NET_C(IC22.7, I_V15)
NET_C(IC22.4, I_VM15)
LM555_DIP(IC23) // Timer
LM555_DIP(IC23) // Timer
LM555_DIP(IC24) // Timer
LM555_DIP(IC24) // Timer
// TL081_DIP(IC25) // Op. Amp. -- part of final amp (not emulated)
// NET_C(IC25.7, I_V15)
// NET_C(IC25.4, I_VM15)
// TL081_DIP(IC25) // Op. Amp. -- part of final amp (not emulated)
// NET_C(IC25.7, I_V15)
// NET_C(IC25.4, I_VM15)
TL081_DIP(IC26) // Op. Amp.
TL081_DIP(IC26) // Op. Amp.
NET_C(IC26.7, I_V15)
NET_C(IC26.4, I_VM15)
TL081_DIP(IC27) // Op. Amp.
TL081_DIP(IC27) // Op. Amp.
NET_C(IC27.7, I_V15)
NET_C(IC27.4, I_VM15)
TTL_74LS107_DIP(IC28) // Dual J-K Flip Flop
TTL_74LS107_DIP(IC28) // Dual J-K Flip Flop
NET_C(IC28.7, GND)
NET_C(IC28.14, I_V5)
@ -796,12 +796,12 @@ NETLIST_START(wotw)
//
// Disconnect noise source from consumers
//
OPTIMIZE_FRONTIER(IC15.3, RES_M(1), 50)
OPTIMIZE_FRONTIER(IC15.3, RES_M(1), 50)
//
// Split noise outputs from output outputs before the mixer
//
OPTIMIZE_FRONTIER(IC26.3, RES_M(1), 50)
OPTIMIZE_FRONTIER(IC26.3, RES_M(1), 50)
#endif
NETLIST_END()

182
src/mame/audio/nl_starhawk.cpp
View File

@ -49,12 +49,12 @@ NETLIST_START(starhawk)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_7, 0) // active high
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_7, 0) // active high
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND, I_OUT_7.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC, I_OUT_7.VCC)
@ -84,19 +84,19 @@ NETLIST_START(starhawk)
RES(R17, RES_K(510))
RES(R18, RES_K(10))
RES(R19, RES_K(33))
// RES(R20, 150) -- part of final amp (not emulated)
// RES(R21, RES_K(22)) -- part of final amp (not emulated)
// RES(R20, 150) -- part of final amp (not emulated)
// RES(R21, RES_K(22)) -- part of final amp (not emulated)
RES(R22, RES_K(1))
// RES(R23, RES_K(10)) -- part of final amp (not emulated)
// RES(R24, 150) -- part of final amp (not emulated)
// POT(R25, RES_K(100))-- part of final amp (not emulated)
// RES(R23, RES_K(10)) -- part of final amp (not emulated)
// RES(R24, 150) -- part of final amp (not emulated)
// POT(R25, RES_K(100))-- part of final amp (not emulated)
RES(R26, RES_K(1))
RES(R27, RES_K(1))
RES(R28, RES_K(510))
RES(R29, RES_K(10)) // PCB verified
// RES(R30, ???)
RES(R31, RES_K(47)) // PCB verified
RES(R32, RES_M(3.3)) // PCB verified
RES(R29, RES_K(10)) // PCB verified
// RES(R30, ???)
RES(R31, RES_K(47)) // PCB verified
RES(R32, RES_M(3.3)) // PCB verified
RES(R33, RES_M(1))
RES(R34, RES_K(47))
RES(R35, RES_M(1))
@ -126,30 +126,30 @@ NETLIST_START(starhawk)
RES(R59, RES_K(39))
RES(R60, RES_K(82))
// CAP(C1, CAP_U(2.2))
// CAP(C2, CAP_U(2.2))
// CAP(C3, CAP_U(3.3))
// CAP(C4, CAP_U(3.3))
// CAP(C1, CAP_U(2.2))
// CAP(C2, CAP_U(2.2))
// CAP(C3, CAP_U(3.3))
// CAP(C4, CAP_U(3.3))
CAP(C5, CAP_P(100))
CAP(C6, CAP_U(3.3))
CAP(C7, CAP_U(0.01))
CAP(C8, CAP_U(1))
CAP(C9, CAP_U(0.022))
CAP(C10, CAP_U(0.15)) // 15?
CAP(C10, CAP_U(0.15)) // 15?
CAP(C11, CAP_U(0.15))
CAP(C12, CAP_U(15))
CAP(C13, CAP_U(0.0033))
CAP(C14, CAP_U(0.0047))
CAP(C15, CAP_U(1))
// CAP(C16, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C16, CAP_P(470)) -- part of final amp (not emulated)
CAP(C17, CAP_U(22))
// CAP(C18, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C19, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C18, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C19, CAP_P(470)) -- part of final amp (not emulated)
CAP(C20, CAP_U(1))
#if (SLOW_SHIP_WOBBLE)
CAP(C21, CAP_U(22)) // discovered by accident, makes HLE analysis easier
CAP(C21, CAP_U(22)) // discovered by accident, makes HLE analysis easier
#else
CAP(C21, CAP_U(0.22)) // PCB verified
CAP(C21, CAP_U(0.22)) // PCB verified
#endif
CAP(C22, CAP_U(0.1))
CAP(C23, CAP_U(0.0027))
@ -157,8 +157,8 @@ NETLIST_START(starhawk)
CAP(C25, CAP_U(0.0027))
CAP(C26, CAP_U(1))
CAP(C27, CAP_U(0.1))
// CAP(C39, CAP_U(1))
// CAP(C40, CAP_U(1))
// CAP(C39, CAP_U(1))
// CAP(C40, CAP_U(1))
D_1N914(CR1)
D_1N914(CR2)
@ -171,118 +171,118 @@ NETLIST_START(starhawk)
D_1N914(CR9)
D_1N914(CR10)
Q_2N3906(Q1) // PNP
// Q_2N6292(Q2) // NPN -- part of final amp (not emulated)
// Q_2N6107(Q3) // PNP -- part of final amp (not emulated)
Q_2N3906(Q1) // PNP
// Q_2N6292(Q2) // NPN -- part of final amp (not emulated)
// Q_2N6107(Q3) // PNP -- part of final amp (not emulated)
#if (!HLE_LAZER_VCOS)
Q_2N3904(Q4) // NPN
Q_2N3904(Q5) // NPN
Q_2N3904(Q4) // NPN
Q_2N3904(Q5) // NPN
#endif
TL182_DIP(IC3A) // Analog switch
TL182_DIP(IC3A) // Analog switch
NET_C(IC3A.6, I_V15)
NET_C(IC3A.7, I_V5)
NET_C(IC3A.8, GND)
NET_C(IC3A.9, I_VM15)
// TTL_7815_DIP(IC2D) // +15V Regulator -- not needed
// TTL_7915_DIP(IC2C) // -15V Regulator -- not needed
// TTL_7815_DIP(IC2D) // +15V Regulator -- not needed
// TTL_7915_DIP(IC2C) // -15V Regulator -- not needed
TL081_DIP(IC4A) // Op. Amp.
TL081_DIP(IC4A) // Op. Amp.
NET_C(IC4A.4, I_VM15)
NET_C(IC4A.7, I_V15)
TL081_DIP(IC4B) // Op. Amp.
TL081_DIP(IC4B) // Op. Amp.
NET_C(IC4B.4, I_VM15)
NET_C(IC4B.7, I_V15)
// TL081_DIP(IC4C) // Op. Amp. -- part of final amp (not emulated)
// NET_C(IC4C.4, I_VM15)
// NET_C(IC4C.7, I_V15)
// TL081_DIP(IC4C) // Op. Amp. -- part of final amp (not emulated)
// NET_C(IC4C.4, I_VM15)
// NET_C(IC4C.7, I_V15)
TTL_74LS393_DIP(IC4E) // Dual 4-Stage Binary Counter
TTL_74LS393_DIP(IC4E) // Dual 4-Stage Binary Counter
NET_C(IC4E.7, GND)
NET_C(IC4E.14, I_V5)
TL081_DIP(IC5A) // Op. Amp.
TL081_DIP(IC5A) // Op. Amp.
NET_C(IC5A.4, I_VM15)
NET_C(IC5A.7, I_V15)
TL081_DIP(IC5B) // Op. Amp.
TL081_DIP(IC5B) // Op. Amp.
NET_C(IC5B.4, I_VM15)
NET_C(IC5B.7, I_V15)
LM556_DIP(IC5D)
PROM_74S287_DIP(IC5E) // 1024-bit PROM -- dump needed
PROM_74S287_DIP(IC5E) // 1024-bit PROM -- dump needed
PARAM(IC5E.A.ROM, "2085.5e8e")
NET_C(IC5E.8, GND)
NET_C(IC5E.16, I_V5)
CA3080_DIP(IC6A) // Trnscndt. Op. Amp.
CA3080_DIP(IC6A) // Trnscndt. Op. Amp.
NET_C(IC6A.7, I_V15)
NET_C(IC6A.4, I_VM15)
TL081_DIP(IC6B) // Op. Amp.
TL081_DIP(IC6B) // Op. Amp.
NET_C(IC6B.4, I_VM15)
NET_C(IC6B.7, I_V15)
TTL_74LS04_DIP(IC6C) // Hex Inverting Gates
TTL_74LS04_DIP(IC6C) // Hex Inverting Gates
NET_C(IC6C.7, GND)
NET_C(IC6C.14, I_V5)
LM556_DIP(IC6D)
TL081_DIP(IC6E) // Op. Amp.
TL081_DIP(IC6E) // Op. Amp.
NET_C(IC6E.4, I_VM15)
NET_C(IC6E.7, I_V15)
TL081_DIP(IC6F) // Op. Amp.
TL081_DIP(IC6F) // Op. Amp.
NET_C(IC6F.4, I_VM15)
NET_C(IC6F.7, I_V15)
TTL_7406_DIP(IC7C) // Hex inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(IC7C) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(IC7C.7, GND)
NET_C(IC7C.14, I_V5)
TTL_74LS393_DIP(IC7E) // Dual 4-Stage Binary Counter
TTL_74LS393_DIP(IC7E) // Dual 4-Stage Binary Counter
NET_C(IC7E.7, GND)
NET_C(IC7E.14, I_V5)
TTL_74LS164_DIP(IC8C) // 8-bit Shift Reg.
TTL_74LS164_DIP(IC8C) // 8-bit Shift Reg.
NET_C(IC8C.7, GND)
NET_C(IC8C.14, I_V5)
TTL_74LS164_DIP(IC8D) // 8-bit Shift Reg.
TTL_74LS164_DIP(IC8D) // 8-bit Shift Reg.
NET_C(IC8D.7, GND)
NET_C(IC8D.14, I_V5)
PROM_74S287_DIP(IC8E) // 1024-bit PROM -- dump needed
PROM_74S287_DIP(IC8E) // 1024-bit PROM -- dump needed
PARAM(IC8E.A.ROM, "2085.5e8e")
NET_C(IC8E.8, GND)
NET_C(IC8E.16, I_V5)
TTL_74LS164_DIP(IC9C) // 8-bit Shift Reg.
TTL_74LS164_DIP(IC9C) // 8-bit Shift Reg.
NET_C(IC9C.7, GND)
NET_C(IC9C.14, I_V5)
TTL_74LS164_DIP(IC9D) // 8-bit Shift Reg.
TTL_74LS164_DIP(IC9D) // 8-bit Shift Reg.
NET_C(IC9D.7, GND)
NET_C(IC9D.14, I_V5)
TTL_74LS163_DIP(IC9E) // Binary Counter (schems say can sub a 74161)
TTL_74LS163_DIP(IC9E) // Binary Counter (schems say can sub a 74161)
NET_C(IC9E.8, GND)
NET_C(IC9E.16, I_V5)
TTL_74LS86_DIP(IC10C) // Quad 2-Input XOR Gates
TTL_74LS86_DIP(IC10C) // Quad 2-Input XOR Gates
NET_C(IC10C.7, GND)
NET_C(IC10C.14, I_V5)
TTL_74LS21_DIP(IC10D) // Dual 4-Input AND Gates
TTL_74LS21_DIP(IC10D) // Dual 4-Input AND Gates
NET_C(IC10D.7, GND)
NET_C(IC10D.14, I_V5)
TTL_74LS393_DIP(IC10E) // Dual 4-Stage Binary Counter
TTL_74LS393_DIP(IC10E) // Dual 4-Stage Binary Counter
NET_C(IC10E.7, GND)
NET_C(IC10E.14, I_V5)
@ -603,38 +603,38 @@ NETLIST_START(starhawk)
// Unconnected outputs
//
HINT(IC4E.9, NC) // Q3
HINT(IC4E.9, NC) // Q3
#if (HLE_LAZER_VCOS)
HINT(IC6C.8, NC) // QD
HINT(IC6C.12, NC) // QF
HINT(IC6C.8, NC) // QD
HINT(IC6C.12, NC) // QF
#endif
HINT(IC7C.4, NC) // QB
HINT(IC7C.6, NC) // QC
HINT(IC7E.9, NC) // Q3
HINT(IC8C.4, NC) // Q1
HINT(IC8C.5, NC) // Q2
HINT(IC8C.6, NC) // Q3
HINT(IC8C.10, NC) // Q4
HINT(IC8C.11, NC) // Q5
HINT(IC8C.12, NC) // Q6
HINT(IC8D.5, NC) // Q2
HINT(IC8D.6, NC) // Q3
HINT(IC8D.10, NC) // Q4
HINT(IC8D.11, NC) // Q5
HINT(IC8D.12, NC) // Q6
HINT(IC9C.3, NC) // Q0
HINT(IC9C.4, NC) // Q1
HINT(IC9C.5, NC) // Q2
HINT(IC9C.6, NC) // Q3
HINT(IC9C.11, NC) // Q5
HINT(IC9D.3, NC) // Q0
HINT(IC9D.4, NC) // Q1
HINT(IC9D.5, NC) // Q2
HINT(IC9D.6, NC) // Q3
HINT(IC9D.11, NC) // Q5
HINT(IC9E.11, NC) // Q3
HINT(IC9E.12, NC) // Q2
HINT(IC9E.13, NC) // Q1
HINT(IC9E.14, NC) // Q0
HINT(IC7C.4, NC) // QB
HINT(IC7C.6, NC) // QC
HINT(IC7E.9, NC) // Q3
HINT(IC8C.4, NC) // Q1
HINT(IC8C.5, NC) // Q2
HINT(IC8C.6, NC) // Q3
HINT(IC8C.10, NC) // Q4
HINT(IC8C.11, NC) // Q5
HINT(IC8C.12, NC) // Q6
HINT(IC8D.5, NC) // Q2
HINT(IC8D.6, NC) // Q3
HINT(IC8D.10, NC) // Q4
HINT(IC8D.11, NC) // Q5
HINT(IC8D.12, NC) // Q6
HINT(IC9C.3, NC) // Q0
HINT(IC9C.4, NC) // Q1
HINT(IC9C.5, NC) // Q2
HINT(IC9C.6, NC) // Q3
HINT(IC9C.11, NC) // Q5
HINT(IC9D.3, NC) // Q0
HINT(IC9D.4, NC) // Q1
HINT(IC9D.5, NC) // Q2
HINT(IC9D.6, NC) // Q3
HINT(IC9D.11, NC) // Q5
HINT(IC9E.11, NC) // Q3
HINT(IC9E.12, NC) // Q2
HINT(IC9E.13, NC) // Q1
HINT(IC9E.14, NC) // Q0
NETLIST_END()

92
src/mame/audio/nl_sundance.cpp
View File

@ -44,12 +44,12 @@ NETLIST_START(sundance)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 1) // active low
TTL_INPUT(I_OUT_1, 1) // active low
TTL_INPUT(I_OUT_2, 1) // active low
TTL_INPUT(I_OUT_3, 1) // active low
TTL_INPUT(I_OUT_4, 1) // active low
TTL_INPUT(I_OUT_7, 1) // active low
TTL_INPUT(I_OUT_0, 1) // active low
TTL_INPUT(I_OUT_1, 1) // active low
TTL_INPUT(I_OUT_2, 1) // active low
TTL_INPUT(I_OUT_3, 1) // active low
TTL_INPUT(I_OUT_4, 1) // active low
TTL_INPUT(I_OUT_7, 1) // active low
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND, I_OUT_7.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC, I_OUT_7.VCC)
@ -124,9 +124,9 @@ NETLIST_START(sundance)
RES(R62, RES_K(2.7))
RES(R63, RES_K(2.7))
RES(R64, 470)
// RES(R65, 150) -- part of final amp (not emulated)
// RES(R66, RES_K(22)) -- part of final amp (not emulated)
// RES(R67, 150) -- part of final amp (not emulated)
// RES(R65, 150) -- part of final amp (not emulated)
// RES(R66, RES_K(22)) -- part of final amp (not emulated)
// RES(R67, 150) -- part of final amp (not emulated)
RES(R68, 330)
RES(R69, RES_K(390))
RES(R70, RES_K(15))
@ -134,9 +134,9 @@ NETLIST_START(sundance)
RES(R72, RES_K(68))
RES(R73, RES_K(2.7))
RES(R74, RES_K(2.7))
// RES(R75, RES_K(10)) -- part of final amp (not emulated)
// POT(R76, RES_K(100)) -- part of final amp (not emulated)
// PARAM(R76.DIAL, 0.500000) -- part of final amp (not emulated)
// RES(R75, RES_K(10)) -- part of final amp (not emulated)
// POT(R76, RES_K(100)) -- part of final amp (not emulated)
// PARAM(R76.DIAL, 0.500000) -- part of final amp (not emulated)
RES(R77, 330)
RES(R78, RES_K(220))
@ -155,11 +155,11 @@ NETLIST_START(sundance)
CAP(C13, CAP_U(0.001))
CAP(C14, CAP_U(0.005))
CAP(C15, CAP_U(10))
// CAP(C16, CAP_U(3.3)) -- not needed
// CAP(C17, CAP_U(3.3)) -- not needed
// CAP(C18, CAP_U(3.3)) -- not needed
// CAP(C19, CAP_U(3.3)) -- not needed
// CAP(C20, CAP_U(3.3)) -- not needed
// CAP(C16, CAP_U(3.3)) -- not needed
// CAP(C17, CAP_U(3.3)) -- not needed
// CAP(C18, CAP_U(3.3)) -- not needed
// CAP(C19, CAP_U(3.3)) -- not needed
// CAP(C20, CAP_U(3.3)) -- not needed
CAP(C21, CAP_U(0.1))
CAP(C22, CAP_U(0.005))
CAP(C23, CAP_U(0.1))
@ -171,39 +171,39 @@ NETLIST_START(sundance)
CAP(C29, CAP_U(0.1))
CAP(C30, CAP_U(0.01))
CAP(C31, CAP_U(0.1))
// CAP(C32, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C33, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C34, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C32, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C33, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C34, CAP_P(470)) -- part of final amp (not emulated)
CAP(C35, CAP_U(0.15))
CAP(C36, CAP_U(0.1))
CAP(C37, CAP_U(0.01))
CAP(C38, CAP_U(0.1))
CAP(C39, CAP_U(1))
D_1N5240(D1)
D_1N914(D2)
D_1N914(D3)
D_1N5240(D1)
D_1N914(D2)
D_1N914(D3)
Q_2N3904(Q1) // NPN
Q_2N3904(Q2) // NPN
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3906(Q5) // PNP
Q_2N3906(Q6) // PNP
// Q_2N6292(Q7) // NPN -- part of final amp (not emulated)
// Q_2N6107(Q9) // PNP -- part of final amp (not emulated)
Q_2N3906(Q8) // PNP
Q_2N3906(Q10) // PNP
Q_2N3904(Q1) // NPN
Q_2N3904(Q2) // NPN
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3906(Q5) // PNP
Q_2N3906(Q6) // PNP
// Q_2N6292(Q7) // NPN -- part of final amp (not emulated)
// Q_2N6107(Q9) // PNP -- part of final amp (not emulated)
Q_2N3906(Q8) // PNP
Q_2N3906(Q10) // PNP
TL081_DIP(IC1) // Op. Amp.
// NET_C(IC1.7, I_V15) // (indirectly via R5)
TL081_DIP(IC1) // Op. Amp.
// NET_C(IC1.7, I_V15) // (indirectly via R5)
NET_C(IC1.4, I_VM15)
TL081_DIP(IC2) // Op. Amp.
TL081_DIP(IC2) // Op. Amp.
NET_C(IC2.7, I_V15)
NET_C(IC2.4, I_VM15)
TL081_DIP(IC3) // Op. Amp.
TL081_DIP(IC3) // Op. Amp.
NET_C(IC3.7, I_V15)
NET_C(IC3.4, I_VM15)
@ -211,12 +211,12 @@ NETLIST_START(sundance)
NET_C(IC4.7, GND)
NET_C(IC4.14, I_V15)
// TTL_7815_DIP(IC5) // +15V Regulator -- not needed
// TTL_7915_DIP(IC6) // -15V Regulator -- not needed
// TTL_7815_DIP(IC5) // +15V Regulator -- not needed
// TTL_7915_DIP(IC6) // -15V Regulator -- not needed
LM555_DIP(IC7)
TL081_DIP(IC8) // Op. Amp.
TL081_DIP(IC8) // Op. Amp.
NET_C(IC8.7, I_V15)
NET_C(IC8.4, I_VM15)
@ -234,7 +234,7 @@ NETLIST_START(sundance)
NET_C(IC12.7, I_V15)
NET_C(IC12.4, I_VM15)
TTL_74LS125_DIP(IC13) // Quad 3-state buffer
TTL_74LS125_DIP(IC13) // Quad 3-state buffer
NET_C(IC13.7, GND)
NET_C(IC13.14, I_V5)
@ -256,7 +256,7 @@ NETLIST_START(sundance)
NET_C(IC19.7, I_V15)
NET_C(IC19.4, I_VM15)
TL081_DIP(IC20) // Op. Amp.
TL081_DIP(IC20) // Op. Amp.
NET_C(IC20.7, I_V15)
NET_C(IC20.4, I_VM15)
@ -303,7 +303,7 @@ NETLIST_START(sundance)
NET_C(I_OUT_1, R2.1, IC11.2)
NET_C(R2.2, I_V5)
NET_C(IC11.8, IC11.4, I_V5) // -- IC11.4 not documented
NET_C(IC11.8, IC11.4, I_V5) // -- IC11.4 not documented
NET_C(IC11.3, R35.1)
NET_C(IC11.1, GND)
NET_C(R34.1, I_V5)
@ -365,7 +365,7 @@ NETLIST_START(sundance)
NET_C(R25.1, IC7.6, IC7.7, C7.1)
NET_C(C7.2, IC7.1, GND)
NET_C(R24.2, I_V5)
NET_C(R25.2, IC7.8, IC7.4, I_V5) // IC7.4 -- not documented
NET_C(R25.2, IC7.8, IC7.4, I_V5) // IC7.4 -- not documented
NET_C(IC7.3, Q4.E)
NET_C(Q4.B, R26.2)
NET_C(R26.1, GND)
@ -476,8 +476,8 @@ NETLIST_START(sundance)
// Unconnected pins
//
NET_C(GND, IC20.2, IC20.3) // part of final amp
NET_C(GND, IC20.2, IC20.3) // part of final amp
// NET_C(GND, IC6.3, IC28.8, IC28.9, IC28.10, IC28.11)
// NET_C(GND, IC6.3, IC28.8, IC28.9, IC28.10, IC28.11)
NETLIST_END()

120
src/mame/audio/nl_tailg.cpp
View File

@ -49,11 +49,11 @@ NETLIST_START(tailg)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC)
@ -134,12 +134,12 @@ NETLIST_START(tailg)
RES(R68, RES_K(20))
RES(R69, RES_K(30))
RES(R70, 470)
// RES(R71, 150) -- part of final amp (not emulated)
// RES(R72, RES_K(22)) -- part of final amp (not emulated)
// RES(R73, 150) -- part of final amp (not emulated)
// RES(R74, RES_K(47)) -- part of final amp (not emulated)
// POT(R75, RES_K(100)) -- part of final amp (not emulated)
// PARAM(R75.DIAL, 0.5) -- part of final amp (not emulated)
// RES(R71, 150) -- part of final amp (not emulated)
// RES(R72, RES_K(22)) -- part of final amp (not emulated)
// RES(R73, 150) -- part of final amp (not emulated)
// RES(R74, RES_K(47)) -- part of final amp (not emulated)
// POT(R75, RES_K(100)) -- part of final amp (not emulated)
// PARAM(R75.DIAL, 0.5) -- part of final amp (not emulated)
RES(R76, RES_K(47))
RES(R77, RES_K(47))
RES(R78, RES_K(2.7))
@ -183,13 +183,13 @@ NETLIST_START(tailg)
CAP(C31, CAP_U(0.05))
CAP(C32, CAP_U(0.1))
CAP(C33, CAP_U(0.1))
// CAP(C34, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C35, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C36, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C37, CAP_U(3.3))
// CAP(C38, CAP_U(3.3))
// CAP(C39, CAP_U(3.3))
// CAP(C40, CAP_U(3.3))
// CAP(C34, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C35, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C36, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C37, CAP_U(3.3))
// CAP(C38, CAP_U(3.3))
// CAP(C39, CAP_U(3.3))
// CAP(C40, CAP_U(3.3))
CAP(C41, CAP_U(0.005))
CAP(C42, CAP_U(0.1))
CAP(C43, CAP_U(10))
@ -205,64 +205,64 @@ NETLIST_START(tailg)
D_1N914(D8)
D_1N914(D9)
Q_2N3904(Q1) // NPN
Q_2N3904(Q2) // NPN
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3906(Q5) // PNP
// Q_2N6292(Q6) // NPN -- part of final amp (not emulated)
// Q_2N6107(Q7) // PNP -- part of final amp (not emulated)
Q_2N3906(Q8) // PNP
Q_2N3904(Q1) // NPN
Q_2N3904(Q2) // NPN
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3906(Q5) // PNP
// Q_2N6292(Q6) // NPN -- part of final amp (not emulated)
// Q_2N6107(Q7) // PNP -- part of final amp (not emulated)
Q_2N3906(Q8) // PNP
TL081_DIP(IC1) // Op. Amp.
// NET_C(IC1.7, I_V15) // (indirectly via R5)
TL081_DIP(IC1) // Op. Amp.
// NET_C(IC1.7, I_V15) // (indirectly via R5)
NET_C(IC1.4, I_VM15)
TL081_DIP(IC2) // Op. Amp.
TL081_DIP(IC2) // Op. Amp.
NET_C(IC2.4, I_VM15)
NET_C(IC2.7, I_V15)
TL081_DIP(IC3) // Op. Amp.
TL081_DIP(IC3) // Op. Amp.
NET_C(IC3.4, I_VM15)
NET_C(IC3.7, I_V15)
TTL_74LS125_DIP(IC4) // Quad 3-state Buffers
TTL_74LS125_DIP(IC4) // Quad 3-state Buffers
NET_C(IC4.7, GND)
NET_C(IC4.14, I_V5)
TTL_7404_DIP(IC5) // Hex Inverting Gates
TTL_7404_DIP(IC5) // Hex Inverting Gates
NET_C(IC5.7, GND)
NET_C(IC5.14, I_V5)
TTL_7406_DIP(IC6) // Hex inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(IC6) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(IC6.7, GND)
NET_C(IC6.14, I_V5)
TL081_DIP(IC7) // Op. Amp.
TL081_DIP(IC7) // Op. Amp.
NET_C(IC7.4, I_VM15)
NET_C(IC7.7, I_V15)
TTL_74LS393_DIP(IC8) // Dual 4-Stage Binary Counter
TTL_74LS393_DIP(IC8) // Dual 4-Stage Binary Counter
NET_C(IC8.7, GND)
NET_C(IC8.14, I_V5)
TL081_DIP(IC9) // Op. Amp.
TL081_DIP(IC9) // Op. Amp.
NET_C(IC9.4, I_VM15)
NET_C(IC9.7, I_V15)
CA3080_DIP(IC10) // Op. Amp.
CA3080_DIP(IC10) // Op. Amp.
NET_C(IC10.4, I_VM15)
NET_C(IC10.7, I_V15)
TL081_DIP(IC11) // Op. Amp.
TL081_DIP(IC11) // Op. Amp.
NET_C(IC11.4, I_VM15)
NET_C(IC11.7, I_V15)
TTL_74LS123_DIP(IC12) // Retriggerable Monostable Multivibrators
TTL_74LS123_DIP(IC12) // Retriggerable Monostable Multivibrators
NET_C(IC12.8, GND)
NET_C(IC12.16, I_V5)
CA3080_DIP(IC13) // Op. Amp.
CA3080_DIP(IC13) // Op. Amp.
NET_C(IC13.4, I_VM15)
NET_C(IC13.7, I_V15)
@ -274,18 +274,18 @@ NETLIST_START(tailg)
LM555_DIP(IC17)
TTL_74LS393_DIP(IC18) // Dual 4-Stage Binary Counter
TTL_74LS393_DIP(IC18) // Dual 4-Stage Binary Counter
NET_C(IC18.7, GND)
NET_C(IC18.14, I_V5)
TL081_DIP(IC19) // Op. Amp.
TL081_DIP(IC19) // Op. Amp.
NET_C(IC19.4, I_VM15)
NET_C(IC19.7, I_V15)
// TTL_7915_DIP(IC20) // -15V Regulator -- not needed
// TTL_7815_DIP(IC21) // +15V Regulator -- not needed
// TTL_7915_DIP(IC20) // -15V Regulator -- not needed
// TTL_7815_DIP(IC21) // +15V Regulator -- not needed
CA3080_DIP(IC22) // Op. Amp.
CA3080_DIP(IC22) // Op. Amp.
NET_C(IC22.4, I_VM15)
NET_C(IC22.7, I_V15)
@ -673,26 +673,26 @@ NETLIST_START(tailg)
// Unconnected inputs
//
NET_C(GND, IC19.2, IC19.3) // part of final amp
NET_C(GND, IC19.2, IC19.3) // part of final amp
NET_C(GND, IC5.9, IC5.11, IC5.13, IC6.9, IC6.11, IC6.13)
//
// Unconnected outputs
//
HINT(IC5.8, NC) // QC
HINT(IC5.10, NC) // QD
HINT(IC5.12, NC) // QE
HINT(IC6.8, NC) // QC
HINT(IC6.10, NC) // QD
HINT(IC6.12, NC) // QE
HINT(IC12.4, NC) // /QA
HINT(IC12.5, NC) // QB
HINT(IC18.3, NC) // Q0A
HINT(IC18.5, NC) // Q2A
HINT(IC18.9, NC) // Q2B
HINT(IC18.10, NC) // Q1B
HINT(IC23.11, NC) // Q6
HINT(IC23.12, NC) // Q7
HINT(IC5.8, NC) // QC
HINT(IC5.10, NC) // QD
HINT(IC5.12, NC) // QE
HINT(IC6.8, NC) // QC
HINT(IC6.10, NC) // QD
HINT(IC6.12, NC) // QE
HINT(IC12.4, NC) // /QA
HINT(IC12.5, NC) // QB
HINT(IC18.3, NC) // Q0A
HINT(IC18.5, NC) // Q2A
HINT(IC18.9, NC) // Q2B
HINT(IC18.10, NC) // Q1B
HINT(IC23.11, NC) // Q6
HINT(IC23.12, NC) // Q7
NETLIST_END()

100
src/mame/audio/nl_warrior.cpp
View File

@ -39,11 +39,11 @@ NETLIST_START(warrior)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
TTL_INPUT(I_OUT_0, 0) // active high
TTL_INPUT(I_OUT_1, 0) // active high
TTL_INPUT(I_OUT_2, 0) // active high
TTL_INPUT(I_OUT_3, 0) // active high
TTL_INPUT(I_OUT_4, 0) // active high
NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND)
NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC)
@ -112,11 +112,11 @@ NETLIST_START(warrior)
RES(R56, RES_K(2.7))
RES(R57, RES_K(820))
RES(R58, 470)
// RES(R59, 150) -- part of final amp (not emulated)
// RES(R60, RES_K(2.2)) -- part of final amp (not emulated)
// RES(R61, 150) -- part of final amp (not emulated)
// RES(R62, RES_K(47)) -- part of final amp (not emulated)
// POT(R63, RES_K(100)) -- part of final amp (not emulated)
// RES(R59, 150) -- part of final amp (not emulated)
// RES(R60, RES_K(2.2)) -- part of final amp (not emulated)
// RES(R61, 150) -- part of final amp (not emulated)
// RES(R62, RES_K(47)) -- part of final amp (not emulated)
// POT(R63, RES_K(100)) -- part of final amp (not emulated)
CAP(C1, CAP_U(0.1))
CAP(C2, CAP_U(0.1))
@ -136,14 +136,14 @@ NETLIST_START(warrior)
CAP(C16, CAP_U(0.01))
CAP(C17, CAP_U(15))
CAP(C18, CAP_U(4.7))
CAP(C19, CAP_U(0.22)) // 22?
CAP(C19, CAP_U(0.22)) // 22?
CAP(C20, CAP_U(0.1))
CAP(C21, CAP_U(0.1))
// CAP(C22, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C23, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C24, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C25, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C26, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C22, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C23, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C24, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C25, CAP_U(3.3)) -- part of voltage converter (not emulated)
// CAP(C26, CAP_U(3.3)) -- part of voltage converter (not emulated)
CAP(C27, CAP_U(0.047))
CAP(C28, CAP_U(0.01))
CAP(C29, CAP_U(0.47))
@ -155,9 +155,9 @@ NETLIST_START(warrior)
CAP(C35, CAP_U(0.05))
CAP(C36, CAP_U(0.01))
CAP(C37, CAP_U(0.1))
// CAP(C38, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C39, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C40, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C38, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C39, CAP_P(470)) -- part of final amp (not emulated)
// CAP(C40, CAP_P(470)) -- part of final amp (not emulated)
D_1N5240(D1)
D_1N914(D2)
@ -165,76 +165,76 @@ NETLIST_START(warrior)
D_1N914(D4)
D_1N914(D5)
Q_2N3906(Q1) // PNP
Q_2N3906(Q2) // PNP
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3904(Q5) // NPN
// Q_2N5878(Q6) // NPN -- part of final amp (not emulated)
// Q_2N5876(Q7) // PNP -- part of final amp (not emulated)
Q_2N3906(Q1) // PNP
Q_2N3906(Q2) // PNP
Q_2N3906(Q3) // PNP
Q_2N3906(Q4) // PNP
Q_2N3904(Q5) // NPN
// Q_2N5878(Q6) // NPN -- part of final amp (not emulated)
// Q_2N5876(Q7) // PNP -- part of final amp (not emulated)
TL081_DIP(IC1) // Op. Amp.
TL081_DIP(IC1) // Op. Amp.
NET_C(IC1.7, I_V15)
NET_C(IC1.4, I_VM15)
CA3080_DIP(IC2) // Op. Amp.
CA3080_DIP(IC2) // Op. Amp.
NET_C(IC2.4, I_VM15)
NET_C(IC2.7, I_V15)
CA3080_DIP(IC3) // Op. Amp.
CA3080_DIP(IC3) // Op. Amp.
NET_C(IC3.4, I_VM15)
NET_C(IC3.7, I_V15)
LM555_DIP(IC4)
TL081_DIP(IC5) // Op. Amp.
// NET_C(IC5.7, I_V15) // (indirectly via R15)
TL081_DIP(IC5) // Op. Amp.
// NET_C(IC5.7, I_V15) // (indirectly via R15)
NET_C(IC5.4, I_VM15)
TL081_DIP(IC6) // Op. Amp.
TL081_DIP(IC6) // Op. Amp.
NET_C(IC6.4, I_VM15)
NET_C(IC6.7, I_V15)
TL081_DIP(IC7) // Op. Amp.
TL081_DIP(IC7) // Op. Amp.
NET_C(IC7.4, I_VM15)
NET_C(IC7.7, I_V15)
TTL_74LS125_DIP(IC8) // Quad 3-state Buffers
TTL_74LS125_DIP(IC8) // Quad 3-state Buffers
NET_C(IC8.7, GND)
NET_C(IC8.14, I_V5)
LM555_DIP(IC9)
// TTL_7815_DIP(IC10) // +15V Regulator -- not emulated
// TTL_7915_DIP(IC11) // -15V Regulator -- not emulated
// TTL_7815_DIP(IC10) // +15V Regulator -- not emulated
// TTL_7915_DIP(IC11) // -15V Regulator -- not emulated
LM555_DIP(IC12)
CA3080_DIP(IC13) // Op. Amp.
CA3080_DIP(IC13) // Op. Amp.
NET_C(IC13.4, I_VM15)
NET_C(IC13.7, I_V15)
TTL_74121_DIP(IC14) // Monostable multivibrators with Schmitt-trigger inputs
TTL_74121_DIP(IC14) // Monostable multivibrators with Schmitt-trigger inputs
NET_C(IC14.7, GND)
NET_C(IC14.14, I_V5)
TTL_7406_DIP(IC15) // Hex inverter -- currently using a clone of 7416, no open collector behavior
TTL_7406_DIP(IC15) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(IC15.7, GND)
NET_C(IC15.14, I_V5)
TL081_DIP(IC16) // Op. Amp.
TL081_DIP(IC16) // Op. Amp.
NET_C(IC16.4, I_VM15)
NET_C(IC16.7, I_V15)
LM555_DIP(IC17)
CA3080_DIP(IC18) // Op. Amp.
CA3080_DIP(IC18) // Op. Amp.
NET_C(IC18.4, I_VM15)
NET_C(IC18.7, I_V15)
// TL081_DIP(IC19) // Op. Amp. -- part of final amp (not emulated)
// NET_C(IC19.4, I_VM15)
// NET_C(IC19.7, I_V15)
// TL081_DIP(IC19) // Op. Amp. -- part of final amp (not emulated)
// NET_C(IC19.4, I_VM15)
// NET_C(IC19.7, I_V15)
#if (HLE_NOISE_GEN)
//
@ -285,7 +285,7 @@ NETLIST_START(warrior)
//
NET_C(I_OUT_2, R11.1, IC4.2)
NET_C(R11.2, R12.2, IC4.8, IC4.4, I_V5) // IC4.4 not listed
NET_C(R11.2, R12.2, IC4.8, IC4.4, I_V5) // IC4.4 not listed
NET_C(R12.1, IC4.6, IC4.7, C7.1)
NET_C(C7.2, GND)
NET_C(IC4.1, GND)
@ -480,11 +480,11 @@ NETLIST_START(warrior)
//
/*
HINT(IC5.4, NC) // Q1
HINT(IC5.6, NC) // Q2
HINT(IC5.8, NC) // Q3
HINT(IC5.10, NC) // Q4
HINT(IC5.12, NC) // Q5
HINT(IC5.4, NC) // Q1
HINT(IC5.6, NC) // Q2
HINT(IC5.8, NC) // Q3
HINT(IC5.10, NC) // Q4
HINT(IC5.12, NC) // Q5
*/
NETLIST_END()

14
src/mame/audio/s11c_bg.cpp
View File

@ -380,13 +380,13 @@ void s11c_bg_device::bg_cvsd_digit_clock_clear_w(uint8_t data)
}
/*
Rom mapping for the 4 banking bits:
3 2 1 0
r q 0 0 - U4, A15 q, A16 r
r q 0 1 - U19, A15 q, A16 r
r q 1 0 - U20, A15 q, A16 r
x x 1 1 - open bus
for ease of loading the roms, we swap the bits to the order '1 0 3 2'
Rom mapping for the 4 banking bits:
3 2 1 0
r q 0 0 - U4, A15 q, A16 r
r q 0 1 - U19, A15 q, A16 r
r q 1 0 - U20, A15 q, A16 r
x x 1 1 - open bus
for ease of loading the roms, we swap the bits to the order '1 0 3 2'
*/
void s11c_bg_device::bgbank_w(uint8_t data)
{

2
src/mame/drivers/astrof.cpp
View File

@ -1067,7 +1067,7 @@ ROM_START( astroff )
ROM_REGION( 0x0020, "proms", 0 )
ROM_LOAD( "im5610-82s123.2f", 0x0000, 0x0020, CRC(61329fd1) SHA1(15782d8757d4dda5a8b97815e94c90218f0e08dd) )
ROM_END
ROM_START( abattle )
ROM_REGION( 0x10000, "maincpu", 0 )

18
src/mame/drivers/bigkarnk_ms.cpp
View File

@ -346,7 +346,7 @@ private:
void bigkarnkm_map(address_map &map);
void sound_map(address_map &map);
void soundrom_map(address_map &map);
uint16_t vram1_r(offs_t offset, uint16_t mem_mask);
uint16_t vram2_r(offs_t offset, uint16_t mem_mask);
uint16_t vram3_r(offs_t offset, uint16_t mem_mask);
@ -358,7 +358,7 @@ private:
TILE_GET_INFO_MEMBER(get_tile_info_tilemap1);
TILE_GET_INFO_MEMBER(get_tile_info_tilemap2);
TILE_GET_INFO_MEMBER(get_tile_info_tilemap3);
tilemap_t *m_bg_tilemap1;
tilemap_t *m_bg_tilemap2;
tilemap_t *m_bg_tilemap3;
@ -382,7 +382,7 @@ TILE_GET_INFO_MEMBER(bigkarnk_ms_state::get_tile_info_tilemap1)
{
int tile = m_videoram1[tile_index*2];
int attr = m_videoram1[(tile_index*2)+1] & 0x1f;
// int fx = (m_videoram1[(tile_index*2)+1] & 0xc0)>>6;
// int fx = (m_videoram1[(tile_index*2)+1] & 0xc0)>>6;
// we rearranged the tile order for the 16x16 deode, so have to swap back here
tile = ((tile & 0x300) >> 8) | ((tile & 0xff) << 2) | (tile & 0xfc00);
@ -492,7 +492,7 @@ void bigkarnk_ms_state::bigkarnkm_map(address_map &map)
map(0x400002, 0x400003).portr("IN1");
map(0x400006, 0x400007).portr("IN2");
map(0x400008, 0x400009).portr("IN3");
map(0x40000c, 0x40000d).noprw();
map(0x40000e, 0x40000e).w(m_soundlatch, FUNC(generic_latch_8_device::write));
@ -514,7 +514,7 @@ uint32_t bigkarnk_ms_state::screen_update(screen_device &screen, bitmap_ind16 &b
m_bg_tilemap2->set_scrollx(0, 112-(m_scrollregs[0]-0x2));
m_bg_tilemap2->set_scrolly(0, -m_scrollregs[1]);
m_bg_tilemap1->set_scrollx(0, 112-(m_scrollregs[2]));
m_bg_tilemap1->set_scrolly(0, -m_scrollregs[3]);
@ -607,7 +607,7 @@ static INPUT_PORTS_START( bigkarnkm )
PORT_DIPSETTING( 0x00a0, DEF_STR( 1C_6C ) )
PORT_DIPSETTING( 0x0000, "Free Play (if Coin A too)" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("IN3")
PORT_DIPNAME( 0x0007, 0x0006, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:8,7,6")
PORT_DIPSETTING( 0x0007, "0" )
@ -691,7 +691,7 @@ WRITE_LINE_MEMBER(bigkarnk_ms_state::splash_msm5205_int)
void bigkarnk_ms_state::sound_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).m(m_soundrom, FUNC(address_map_bank_device::amap8));
map(0xe000, 0xe000).w(FUNC(bigkarnk_ms_state::splash_adpcm_control_w));
@ -700,7 +700,7 @@ void bigkarnk_ms_state::sound_map(address_map &map)
map(0xe800, 0xe801).rw("ymsnd", FUNC(ym3812_device::read), FUNC(ym3812_device::write));
map(0xf000, 0xf7ff).ram();
map(0xf800, 0xf800).r(m_soundlatch, FUNC(generic_latch_8_device::read));
map(0xf800, 0xf800).r(m_soundlatch, FUNC(generic_latch_8_device::read));
}
void bigkarnk_ms_state::soundrom_map(address_map &map)
@ -718,7 +718,7 @@ void bigkarnk_ms_state::bigkarnkm(machine_config &config)
Z80(config, m_soundcpu, 16_MHz_XTAL/4);
m_soundcpu->set_addrmap(AS_PROGRAM, &bigkarnk_ms_state::sound_map);
m_soundcpu->set_periodic_int(FUNC(bigkarnk_ms_state::nmi_line_pulse), attotime::from_hz(60*64));
m_soundcpu->set_periodic_int(FUNC(bigkarnk_ms_state::nmi_line_pulse), attotime::from_hz(60*64));
ADDRESS_MAP_BANK(config, m_soundrom).set_map(&bigkarnk_ms_state::soundrom_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x4000);

66
src/mame/drivers/bingor.cpp
View File

@ -799,70 +799,70 @@ void bingor_state::vip2000(machine_config &config)
// I doubt we need to load the EEPROMs
ROM_START( bingor1 ) // Strings: Big Roll / Bingo Roll / 1991 AWR / 1992 Rosenauer Electronic Austria.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_START( bingor1 ) // Strings: Big Roll / Bingo Roll / 1991 AWR / 1992 Rosenauer Electronic Austria.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "bingo v 29.4.99 l.bin", 0x00000, 0x08000, CRC(b6773bff) SHA1(74e375662730e002e05186bd77098fa0d8e43ade) )
ROM_LOAD16_BYTE( "bingo v 29.4.99 h.bin", 0x00001, 0x08000, CRC(0e18f90a) SHA1(0743302e675f01f8ad42ac2e67ecb1c1bf870ae7) )
// gfx roms on this one are twice the size of the others
ROM_REGION16_LE( 0x20000, "gfx", 0 ) // blitter data?
ROM_REGION16_LE( 0x20000, "gfx", 0 ) // blitter data?
ROM_LOAD16_BYTE( "bingo turbo l.bin", 0x000000, 0x10000, CRC(86b10566) SHA1(5f74b250ced3574feffdc40b6ed013ec5a0c2c97) )
ROM_LOAD16_BYTE( "bingo turbo h.bin", 0x000001, 0x10000, CRC(7e18f9d7) SHA1(519b65d6812a3762e3215f4918c834d5a444b28a) )
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_LOAD( "pic16c54b.bin", 0x000, 0x200, CRC(21e8a699) SHA1(8a22292fa3669105d52a9d681d5be345fcfe6607) )
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "bingor1_24c04a.bin", 0x000000, 0x200, CRC(b169df46) SHA1(ebafc81c6918aae9daa6b90df16161751cfd2590) )
ROM_END
ROM_START( bingor2 ) // Strings: Euro Bingo / 1988-1992 Rosenauer Electronic Austria.
ROM_REGION16_LE( 0x20000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_START( bingor2 ) // Strings: Euro Bingo / 1988-1992 Rosenauer Electronic Austria.
ROM_REGION16_LE( 0x20000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "bingo roll vip2 v26.02.02_l.bin", 0x00000, 0x10000, CRC(40df6ee8) SHA1(1e90ef906e47f95ebde85b6dd32fdfe50c0564fc) )
ROM_LOAD16_BYTE( "bingo roll vip2 v26.02.02_h.bin", 0x00001, 0x10000, CRC(9154c183) SHA1(a4060294295a9b8df07ce9fcfeefcf009e129817) )
ROM_REGION16_LE( 0x20000, "gfx", 0 ) // blitter data?
ROM_REGION16_LE( 0x20000, "gfx", 0 ) // blitter data?
ROM_LOAD16_BYTE( "bingo roll grafik l.bin", 0x000000, 0x10000, CRC(3e753e13) SHA1(011b5f530e54332be194830c0a1d2ec31425017a) )
ROM_LOAD16_BYTE( "bingo roll grafik h.bin", 0x000001, 0x10000, CRC(4eec39ad) SHA1(4201d5ec207d30dcac9813dd6866d2b61c168e75) )
ROM_REGION( 0x20000, "pic", 0 ) // protection
ROM_REGION( 0x20000, "pic", 0 ) // protection
ROM_LOAD( "pic16c54c.bin", 0x000, 0x200, CRC(21e8a699) SHA1(8a22292fa3669105d52a9d681d5be345fcfe6607) )
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "bingor2_24c04a.bin", 0x000000, 0x200, CRC(a7c87036) SHA1(f7d6161bbfdcdc50212f6b71eb2cbbbb18548cc6) )
ROM_END
ROM_START( bingor3 ) // Strings: 1995-1997 Paloma Elektronik / 2002 Paloma Elektronik / Play Star Austria 0316/821193.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_START( bingor3 ) // Strings: 1995-1997 Paloma Elektronik / 2002 Paloma Elektronik / Play Star Austria 0316/821193.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "bellstar vip2l 27.07_1.bin", 0x00000, 0x08000, CRC(0115bca7) SHA1(0b692b46bc6641296861666f00ec0475dc7296a1) )
ROM_LOAD16_BYTE( "bellstar vip2l 27.07_2.bin", 0x00001, 0x08000, CRC(c689aa69) SHA1(fb1f477654909f156c30a6be29f84962f4edb1c3) )
ROM_REGION16_LE( 0x20000, "gfx", ROMREGION_ERASE00 ) // blitter data?
ROM_REGION16_LE( 0x20000, "gfx", ROMREGION_ERASE00 ) // blitter data?
ROM_LOAD16_BYTE( "bsg-11.10.02_l.bin", 0x000000, 0x08000, CRC(a8b22477) SHA1(92d638f0f188a43f14487989cf42195311fb2c35) ) //half size?
ROM_LOAD16_BYTE( "bsg-11.10.02_h.bin", 0x000001, 0x08000, CRC(969d201c) SHA1(7705ceb383ef122538ebf8046041d1c24ec9b9a4) )
ROM_REGION( 0x20000, "pic", 0 ) // protection
ROM_REGION( 0x20000, "pic", 0 ) // protection
ROM_LOAD( "pic16c54c.bin", 0x000, 0x400, CRC(5a507be6) SHA1(f4fbfb7e7516eecab32d96b3a34ad88395edac9e) )
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "bingor3_24c04a.bin", 0x000000, 0x200, CRC(7a5eb172) SHA1(12d2fc96049427ef1a8acf47242b41b2095d28b6) )
ROM_LOAD( "bingor3_24c04a_alt.bin", 0x000000, 0x200, CRC(fcff2d26) SHA1(aec1ddd38149404741a057c74bf84bfb4a8e4aa1) )
ROM_END
// this is a mix of 2 of the other sets.. I don't know if it's correct
ROM_START( bingor4 ) // Strings: 1995-1997 Paloma Elektronik / 2002 Paloma Elektronik / Play Star Austria 0316/821193 / CBA Design, Lyon France.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_START( bingor4 ) // Strings: 1995-1997 Paloma Elektronik / 2002 Paloma Elektronik / Play Star Austria 0316/821193 / CBA Design, Lyon France.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "01.bin", 0x00000, 0x08000, CRC(0115bca7) SHA1(0b692b46bc6641296861666f00ec0475dc7296a1) )
ROM_LOAD16_BYTE( "02.bin", 0x00001, 0x08000, CRC(c689aa69) SHA1(fb1f477654909f156c30a6be29f84962f4edb1c3) )
ROM_REGION16_LE( 0x20000, "gfx", 0 ) // blitter data?
ROM_REGION16_LE( 0x20000, "gfx", 0 ) // blitter data?
ROM_LOAD16_BYTE( "bingo roll grafik l.bin", 0x000000, 0x10000, CRC(3e753e13) SHA1(011b5f530e54332be194830c0a1d2ec31425017a) )
ROM_LOAD16_BYTE( "bingo roll grafik h.bin", 0x000001, 0x10000, CRC(4eec39ad) SHA1(4201d5ec207d30dcac9813dd6866d2b61c168e75) )
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_LOAD( "pic16c54c.bin", 0x000, 0x200, CRC(21e8a699) SHA1(8a22292fa3669105d52a9d681d5be345fcfe6607) )
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "bingor4_24c04a.bin", 0x000000, 0x200, CRC(38cf70a9) SHA1(ba9a1640200963e2d58d761edc13a24fa5ef44c2) )
ROM_END
@ -873,19 +873,19 @@ ROM_END
*/
ROM_START( bingor5 ) // BellStar V3. Strings: 1995-1997 Paloma Elektronik / 2002 Paloma Elektronik / Play Star Austria 0316/821193 / CBA Design, Lyon France.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_START( bingor5 ) // BellStar V3. Strings: 1995-1997 Paloma Elektronik / 2002 Paloma Elektronik / Play Star Austria 0316/821193 / CBA Design, Lyon France.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "bellstar_v3_v.3.6.02_l.bin", 0x00000, 0x08000, CRC(56b84a5d) SHA1(1bda4fb972b4f0f0575089b545bf15dfea859948) )
ROM_LOAD16_BYTE( "bellstar_v3_v.3.6.02_h.bin", 0x00001, 0x08000, CRC(d6945bb8) SHA1(b620f1b547be03c4609bff8d06111d0ea425bae8) )
ROM_REGION16_LE( 0x20000, "gfx", ROMREGION_ERASE00 ) // blitter data?
ROM_REGION16_LE( 0x20000, "gfx", ROMREGION_ERASE00 ) // blitter data?
ROM_LOAD16_BYTE( "b.s.grafik_11.10.02_l.bin", 0x000000, 0x08000, CRC(a8b22477) SHA1(92d638f0f188a43f14487989cf42195311fb2c35) ) //half size?
ROM_LOAD16_BYTE( "b.s.grafik_11.10.02_h.bin", 0x000001, 0x08000, CRC(969d201c) SHA1(7705ceb383ef122538ebf8046041d1c24ec9b9a4) )
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_LOAD( "pic16c54c.bin", 0x000, 0x400, CRC(5a507be6) SHA1(f4fbfb7e7516eecab32d96b3a34ad88395edac9e) )
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "bingor5_24c04a.bin", 0x000000, 0x200, CRC(fcff2d26) SHA1(aec1ddd38149404741a057c74bf84bfb4a8e4aa1) )
ROM_END
@ -896,32 +896,32 @@ ROM_END
Same PCB layout as bingor3,
but 2x crystals:
1x 16 MHz. (sub board)
1x 10 MHz. (main board)
1x MP690P
*/
ROM_START( bingor6 ) // Strings: 1988-1992 AWR Hard & Soft Austria.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_START( bingor6 ) // Strings: 1988-1992 AWR Hard & Soft Austria.
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "bingo_l.bin", 0x00000, 0x08000, CRC(78df905d) SHA1(197c5a795bdda964db780dd3b9c0f9b76197a610) )
ROM_LOAD16_BYTE( "bingo_h.bin", 0x00001, 0x08000, CRC(f25958fd) SHA1(8a8c061accc4c2fa8475188a1281518e63fb456d) )
ROM_REGION16_LE( 0x20000, "gfx", ROMREGION_ERASE00 ) // blitter data?
ROM_REGION16_LE( 0x20000, "gfx", ROMREGION_ERASE00 ) // blitter data?
ROM_LOAD16_BYTE( "turbo_l.bin", 0x000000, 0x10000, CRC(86b10566) SHA1(5f74b250ced3574feffdc40b6ed013ec5a0c2c97) )
ROM_LOAD16_BYTE( "turbo_h.bin", 0x000001, 0x10000, CRC(7e18f9d7) SHA1(519b65d6812a3762e3215f4918c834d5a444b28a) )
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_REGION( 0x20000, "pic", 0 ) // protection?
ROM_LOAD( "pic16c54rc.bin", 0x000, 0x400, NO_DUMP )
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "bingor6_24c04a.bin", 0x000000, 0x200, CRC(9d271c5f) SHA1(8ac5c4848fb8d9a156ba760324022839fefcbb72) )
ROM_END
ROM_START( vip2000 )
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "vipbios8l.bin", 0x00000, 0x08000, CRC(a4c2b351) SHA1(bb718584bfe32b9ed27fadfd89b4094d4bbd6d7f) )
ROM_LOAD16_BYTE( "vipbios8h.bin", 0x00001, 0x08000, CRC(7c42c5ee) SHA1(c419a834ddb245363bacfe70d31cff7c2d4a2d03) )

18
src/mame/drivers/bloodbro_ms.cpp
View File

@ -120,7 +120,7 @@ uint32_t bloodbro_ms_state::screen_update(screen_device &screen, bitmap_ind16 &b
int ypos = attr0 & 0x00ff;
int xpos = (attr1 & 0xff00)>>8;
xpos |= (attr2 & 0x8000) ? 0x100 : 0x000;
xpos |= (attr2 & 0x8000) ? 0x100 : 0x000;
ypos = (0xff - ypos);
@ -152,13 +152,13 @@ static const gfx_layout tiles16x16x4_layout =
/*
static const gfx_layout tiles8x8x4_layout =
{
8,8,
RGN_FRAC(1,1),
4,
{ 0,8,16,24 },
{ 0,1,2,3,4,5,6,7 },
{ STEP8(0,32) },
16 * 16
8,8,
RGN_FRAC(1,1),
4,
{ 0,8,16,24 },
{ 0,1,2,3,4,5,6,7 },
{ STEP8(0,32) },
16 * 16
};
*/
@ -256,7 +256,7 @@ ROM_START( bloodbrom )
ROM_LOAD32_BYTE( "4-3-b_bb4b2.ic16", 0x00002, 0x20000, CRC(f25dd182) SHA1(eff29970c7b898744b08a151f9e17b68ce77e78d) )
ROM_LOAD32_BYTE( "4-3-b_bb4b3.ic15", 0x00001, 0x20000, CRC(3efcb6aa) SHA1(0a162285d08e171e946147e0725db879643ae113) )
ROM_LOAD32_BYTE( "4-3-b_bb4b4.ic14", 0x00000, 0x20000, CRC(6b5254fa) SHA1(1e9e3096e5f29554fb8f8cb0df0e5157f940f8c9) )
// ROMs for frontmost tile layer (text) are missing?
ROM_REGION( 0x80000, "gfx3", 0 ) // on another MOD 4/3 board
ROM_LOAD32_BYTE( "text.ic17", 0x00003, 0x20000, NO_DUMP )

2
src/mame/drivers/cinemat.cpp
View File

@ -1094,7 +1094,7 @@ void cinemat_state::speedfrk(machine_config &config)
{
cinemat_nojmi_8k(config);
SPEED_FREAK_AUDIO(config, "soundboard", 0).configure_latch_inputs(*m_outlatch);
// m_outlatch->q_out_cb<1>().set(FUNC(cinemat_state::speedfrk_start_led_w));
// m_outlatch->q_out_cb<1>().set(FUNC(cinemat_state::speedfrk_start_led_w));
}
void cinemat_state::starhawk(machine_config &config)

4
src/mame/drivers/cmi.cpp
View File

@ -1685,7 +1685,7 @@ void cmi_state::cmi02_w(offs_t offset, uint8_t data)
m_hp_int = 0;
m_maincpu1_irq_merger->in_w<1>(0);
//if (m_lp_int == 0)
// m_maincpu1->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
// m_maincpu1->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
m_i8214[2]->b_sgs_w(~(data & 0xf));
break;
@ -1723,7 +1723,7 @@ void cmi_state::i8214_cpu1_w(uint8_t data)
m_maincpu1_irq_merger->in_w<0>(0);
m_lp_int = 0;
//if (m_hp_int == 0)
// m_maincpu1->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
// m_maincpu1->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
m_i8214[0]->b_sgs_w(~(data & 0xf));
}

10
src/mame/drivers/ddenlovr.cpp
View File

@ -5393,7 +5393,7 @@ static INPUT_PORTS_START( animaljr )
PORT_DIPSETTING( 0x0c, "Level 5" )
PORT_DIPSETTING( 0x04, "Level 6" )
PORT_DIPSETTING( 0x00, "unknown Level (00)" )
PORT_DIPSETTING( 0x10, "unknown Level (10)" )
PORT_DIPSETTING( 0x10, "unknown Level (10)" )
PORT_DIPNAME( 0xe0, 0xe0, "Game Hit Probability" ) PORT_DIPLOCATION("DSWA:6,7,8") // manual lists 6 valid settings
PORT_DIPSETTING( 0x40, "1/15" )
PORT_DIPSETTING( 0x60, "1/10" )
@ -5430,16 +5430,16 @@ static INPUT_PORTS_START( animaljr )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
PORT_START("DSW3")
PORT_DIPNAME( 0x01, 0x01, "Unknown A-9 (debug?)" ) PORT_DIPLOCATION("DSWA:9") // manual lists 'unused, MUST remain OFF'
PORT_DIPNAME( 0x01, 0x01, "Unknown A-9 (debug?)" ) PORT_DIPLOCATION("DSWA:9") // manual lists 'unused, MUST remain OFF'
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, "Tickets" ) PORT_DIPLOCATION("DSWA:10")
PORT_DIPNAME( 0x02, 0x02, "Tickets" ) PORT_DIPLOCATION("DSWA:10")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, "Unknown B-9 (debug?)" ) PORT_DIPLOCATION("DSWB:9") // manual lists 'unused, should remain OFF'
PORT_DIPNAME( 0x04, 0x04, "Unknown B-9 (debug?)" ) PORT_DIPLOCATION("DSWB:9") // manual lists 'unused, should remain OFF'
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW ) PORT_DIPLOCATION("DSWB:10")
PORT_SERVICE( 0x08, IP_ACTIVE_LOW ) PORT_DIPLOCATION("DSWB:10")
PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END

4
src/mame/drivers/exidyttl.cpp
View File

@ -195,7 +195,7 @@ ROM_END
ROM_START( destdrby )
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
ROM_REGION( 0x0400, "roms", ROMREGION_ERASE00)
ROM_LOAD( "82s123-31.a11", 0x0000, 0x0020, CRC(f304a1fb) SHA1(0f029274bb99723ebcc271d761e1500ca50b2738) )
ROM_LOAD( "82s123-32.c12", 0x0000, 0x0020, CRC(f8dbd779) SHA1(55bdaf9eb1ba6185e20512c4874ebb625861508e) )
@ -253,7 +253,7 @@ ROM_START( deathrac )
ROM_LOAD( "6331-31.a11", 0x0000, 0x0020, CRC(f304a1fb) SHA1(0f029274bb99723ebcc271d761e1500ca50b2738) )
ROM_LOAD( "6331-32.c12", 0x0000, 0x0020, CRC(f8dbd779) SHA1(55bdaf9eb1ba6185e20512c4874ebb625861508e) )
ROM_LOAD( "6331-33.p14", 0x0000, 0x0020, CRC(2e83bf80) SHA1(02fcc1e879c06759a21ef4f004fe7aa790814112) )
// Note: Image for 36 has all zeros in the second half, which is unused.
// Note: Image for 36 has all zeros in the second half, which is unused.
// Other roms in this series (34,35) all have duplicate content in the second half
ROM_LOAD( "6331-36.e7", 0x0000, 0x0020, CRC(bb743b79) SHA1(8eb73782bcea7dbba7b75db32307e562248691bb) )
ROM_LOAD( "6331-35.g7", 0x0000, 0x0020, CRC(5ed8cdd2) SHA1(d193d819ad634c43d648ce49073799b4df6dfd2f) )

8
src/mame/drivers/exorciser.cpp
View File

@ -191,7 +191,7 @@ private:
u8 main_r(offs_t offset);
void main_w(offs_t offset, u8 data);
u8 prom_r(offs_t offset);
required_device<m6800_cpu_device> m_maincpu;
required_device<address_map_bank_device> m_bankdev;
required_device<input_merger_device> m_mainirq;
@ -258,7 +258,7 @@ void exorciser_state::mem_map(address_map &map)
// Disk driver code.
map(0xe800, 0xebff).rom().region("68fdc2", 0);
// Disk driver unit
map(0xec00, 0xec07).rw(m_fdc, FUNC(m68sfdc_device::read), FUNC(m68sfdc_device::write));
@ -270,7 +270,7 @@ void exorciser_state::mem_map(address_map &map)
// EXBUG
map(0xf000, 0xfbff).rom().region("exbug", 0);
map(0xfcf4, 0xfcf5).mirror(0x0002).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write));
map(0xfcf8, 0xfcfb).rw(m_pia_dbg, FUNC(pia6821_device::read), FUNC(pia6821_device::write));
@ -403,7 +403,7 @@ WRITE_LINE_MEMBER(exorciser_state::write_f13_clock)
u8 exorciser_state::main_r(offs_t offset)
{
if (offset == m_stop_address && m_stop_enabled &&
!machine().side_effects_disabled())
!machine().side_effects_disabled())
{
m_pia_dbg->cb1_w(CLEAR_LINE);
m_pia_dbg->cb1_w(ASSERT_LINE);

22
src/mame/drivers/funworld.cpp
View File

@ -6088,13 +6088,13 @@ ROM_END
The following two sets have the same program
but different graphics system.
Both sets have graphics ROMs data interleaved
inside the second half of a 16bit 27C210 EPROM.
The second set has some 8bits data in the first half.
Not clear if it's for obfuscation or just are the missing
logo graphics tiles.
The program looks original. The former sets programs
have differents offsets patched and moved blocks respect
this new program.
@ -6110,15 +6110,15 @@ ROM_START( jolyjokro )
ROM_REGION( 0x10000, "gfxpool", 0 )
ROM_LOAD( "impera2.bin", 0x0000, 0x10000, CRC(aa86dba6) SHA1(fe189dde83bd855f4a0b34b20c161a9addc15017) )
ROM_CONTINUE( 0x0000, 0x10000) // discarding 1nd empty half (0000-ffff)
ROM_CONTINUE( 0x0000, 0x10000) // discarding 1nd empty half (0000-ffff)
ROM_REGION( 0x10000, "gfx1", 0 )
ROM_FILL( 0x0000, 0x10000, 0xff) // deinterleaved GFX data will be placed here
ROM_FILL( 0x0000, 0x10000, 0xff) // deinterleaved GFX data will be placed here
ROM_REGION( 0x0800, "nvram", 0 ) // default NVRAM
ROM_REGION( 0x0800, "nvram", 0 ) // default NVRAM
ROM_LOAD( "jolyjokro_nvram.bin", 0x0000, 0x0800, CRC(1f69e567) SHA1(86695ca6f9f93c6badd092410611d8061edf8efa) )
ROM_REGION( 0x0200, "proms", 0 ) // PLD address the 2nd half
ROM_REGION( 0x0200, "proms", 0 ) // PLD address the 2nd half
ROM_LOAD( "1_impera_color_ii.bin", 0x0000, 0x0200, CRC(9d62f9f5) SHA1(68300c25c7eaa13a3fdbf91ab0711d0bc530543d) )
ROM_END
@ -6128,15 +6128,15 @@ ROM_START( jolyjokrp )
ROM_REGION( 0x10000, "gfxpool", 0 )
ROM_LOAD( "9c_1ff1.bin", 0x00000, 0x10000, CRC(4b8f0821) SHA1(0821eed07f5e98b66d87a3079756dad72ffe9665) )
ROM_CONTINUE( 0x00000, 0x10000) // discarding 1nd half (0000-ffff), but has some data. maybe the missing impera logo?
ROM_CONTINUE( 0x00000, 0x10000) // discarding 1nd half (0000-ffff), but has some data. maybe the missing impera logo?
ROM_REGION( 0x10000, "gfx1", 0 )
ROM_FILL( 0x0000, 0x10000, 0xff) // deinterleaved GFX data will be placed here
ROM_FILL( 0x0000, 0x10000, 0xff) // deinterleaved GFX data will be placed here
ROM_REGION( 0x0800, "nvram", 0 ) // default NVRAM
ROM_REGION( 0x0800, "nvram", 0 ) // default NVRAM
ROM_LOAD( "jolyjokrp_nvram.bin", 0x0000, 0x0800, CRC(c8706e75) SHA1(421420b1ee82615faf290d1204342cdde776ffaf) )
ROM_REGION( 0x0200, "proms", 0 ) // PLD address the 2nd half
ROM_REGION( 0x0200, "proms", 0 ) // PLD address the 2nd half
ROM_LOAD( "impera_color_ii.bin", 0x0000, 0x0200, CRC(9d62f9f5) SHA1(68300c25c7eaa13a3fdbf91ab0711d0bc530543d) )
ROM_END
@ -7923,7 +7923,7 @@ void funworld_state::init_impera16()
*****************************/
int j = 0;
for (int i = 0; i < size; i += 2)
{
gfx8rom[j] = gfx16rom[i];

12
src/mame/drivers/galpanic_ms.cpp
View File

@ -20,7 +20,7 @@
MOD 4/3 - Tilemap board, has logic + 4 tilemap ROMs, long thin sub-board (CAR-0484/1 SOLD) with no chips, just routing along one edge
-- does the sound board have a MSM5205 or not?
-- does the sound board have a MSM5205 or not?
*/
@ -237,8 +237,8 @@ void galspanic_ms_state::sound_map(address_map &map)
//map(0x8000, 0xbfff).m(m_soundrom, FUNC(address_map_bank_device::amap8));
// map(0xe000, 0xe000).w(FUNC(galspanic_ms_state::splash_adpcm_control_w));
// map(0xe400, 0xe400).w(FUNC(galspanic_ms_state::splash_adpcm_data_w));
// map(0xe000, 0xe000).w(FUNC(galspanic_ms_state::splash_adpcm_control_w));
// map(0xe400, 0xe400).w(FUNC(galspanic_ms_state::splash_adpcm_data_w));
map(0xa000, 0xa001).rw(m_ym1, FUNC(ym2203_device::read), FUNC(ym2203_device::write)).mirror(0x0008);
map(0xa002, 0xa003).rw(m_ym2, FUNC(ym2203_device::read), FUNC(ym2203_device::write)).mirror(0x0008);
@ -307,7 +307,7 @@ uint32_t galspanic_ms_state::screen_update(screen_device &screen, bitmap_ind16 &
m_bg_tilemap2->set_scrollx(0, 64+m_scrollram[0x400/2]);
m_bg_tilemap2->set_scrolly(0, 48-m_scrollram[0x402/2]);
m_bg_tilemap2->draw(screen, bitmap, cliprect, 0, 0);
// TODO, convert to device, share between Modualar System games
@ -326,7 +326,7 @@ uint32_t galspanic_ms_state::screen_update(screen_device &screen, bitmap_ind16 &
int ypos = attr0 & 0x00ff;
int xpos = (attr1 & 0xff00)>>8;
xpos |= (attr2 & 0x8000) ? 0x100 : 0x000;
xpos |= (attr2 & 0x8000) ? 0x100 : 0x000;
ypos = (0xff - ypos);
@ -465,7 +465,7 @@ void galspanic_ms_state::newquiz(machine_config &config)
Z80(config, m_soundcpu, 16_MHz_XTAL/4);
m_soundcpu->set_addrmap(AS_PROGRAM, &galspanic_ms_state::sound_map);
// m_soundcpu->set_periodic_int(FUNC(galspanic_ms_state::nmi_line_pulse), attotime::from_hz(60*64)); // no NMI here, just retn
// m_soundcpu->set_periodic_int(FUNC(galspanic_ms_state::nmi_line_pulse), attotime::from_hz(60*64)); // no NMI here, just retn
ADDRESS_MAP_BANK(config, m_soundrom).set_map(&galspanic_ms_state::soundrom_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x4000);

16
src/mame/drivers/gigatron.cpp
View File

@ -51,7 +51,7 @@ private:
void data_map(address_map &map);
uint16_t m_lc; //Lights Changed
//Video Generation stuff
uint8_t m_out;
uint8_t m_row;
@ -62,10 +62,10 @@ private:
void video_draw(u8 data);
uint8_t inputs();
void port_outx(uint8_t data);
std::unique_ptr<bitmap_ind16> m_bitmap_render;
std::unique_ptr<bitmap_ind16> m_bitmap_buffer;
required_device<gigatron_cpu_device> m_maincpu;
required_device<dac_byte_interface> m_dac;
required_ioport m_io_inputs;
@ -85,26 +85,26 @@ void gigatron_state::video_draw(u8 data)
{
uint8_t out = data;
uint8_t falling = m_out & ~out;
if (falling & VSYNC)
{
m_row = 0;
m_pixel = 0;
}
if (falling & HSYNC)
{
m_col = 0;
m_row++;
}
m_out = out;
if ((out & (VSYNC | HSYNC)) != (VSYNC | HSYNC))
{
return;
}
if((m_row >= 0 && m_row < 480) && (m_col >= 0 && m_col < 640))
{
//uint16_t *dest;

86
src/mame/drivers/goldnpkr.cpp
View File

@ -1497,8 +1497,8 @@ TILE_GET_INFO_MEMBER(goldnpkr_state::get_bg_tile_info)
int attr = m_colorram[tile_index];
int code = ((attr & 1) << 8) | m_videoram[tile_index];
int bank = (attr & 0x02) >> 1; // bit 1 switch the gfx banks
int color = (attr & 0x3c) >> 2; // bits 2-3-4-5 for color
int bank = (attr & 0x02) >> 1; // bit 1 switch the gfx banks
int color = (attr & 0x3c) >> 2; // bits 2-3-4-5 for color
tileinfo.set(bank, code, color, 0);
}
@ -1515,8 +1515,8 @@ TILE_GET_INFO_MEMBER(goldnpkr_state::wcrdxtnd_get_bg_tile_info)
int attr = m_colorram[tile_index];
int code = ((attr & 1) << 8) | m_videoram[tile_index];
int bank = (attr & 0x03) + ((attr & 0xc0) >> 4); // bits 0, 1, 6 & 7 switch the gfx banks
int color = (attr & 0x3c) >> 2; // bits 2-3-4-5 for color
int bank = (attr & 0x03) + ((attr & 0xc0) >> 4); // bits 0, 1, 6 & 7 switch the gfx banks
int color = (attr & 0x3c) >> 2; // bits 2-3-4-5 for color
tileinfo.set(bank, code, color, 0);
}
@ -1747,7 +1747,7 @@ void goldnpkr_state::super21p_palette(palette_device &palette) const
*/
uint8_t goldnpkr_state::goldnpkr_mux_port_r()
{
switch( m_mux_data & 0xf0 ) // bits 4-7
switch( m_mux_data & 0xf0 ) // bits 4-7
{
// normal selector writes 7F-BF-DF-EF
case 0x10: return ioport("IN0-0")->read();
@ -1767,9 +1767,9 @@ uint8_t goldnpkr_state::goldnpkr_mux_port_r()
uint8_t goldnpkr_state::pottnpkr_mux_port_r()
{
uint8_t pa_0_4 = 0xff, pa_7; // temporary placeholder for bits 0 to 4 & 7
uint8_t pa_0_4 = 0xff, pa_7; // temporary placeholder for bits 0 to 4 & 7
switch( m_mux_data & 0xf0 ) // bits 4-7
switch( m_mux_data & 0xf0 ) // bits 4-7
{
case 0x10: return ioport("IN0-0")->read();
case 0x20: return ioport("IN0-1")->read();
@ -1777,7 +1777,7 @@ uint8_t goldnpkr_state::pottnpkr_mux_port_r()
case 0x80: return ioport("IN0-3")->read();
}
pa_7 = (m_pia0_PA_data >> 7) & 1; // to do: bit PA5 to pin CB1
pa_7 = (m_pia0_PA_data >> 7) & 1; // to do: bit PA5 to pin CB1
return ( (pa_0_4 & 0x3f) | (pa_7 << 6) | (pa_7 << 7) ) ;
}
@ -1785,7 +1785,7 @@ uint8_t goldnpkr_state::pottnpkr_mux_port_r()
void goldnpkr_state::mux_w(uint8_t data)
{
//logerror("mux_w: %2x\n",data);
m_mux_data = data ^ 0xff; // inverted
m_mux_data = data ^ 0xff; // inverted
}
void goldnpkr_state::mux_port_w(uint8_t data)
@ -1881,11 +1881,11 @@ void goldnpkr_state::lamps_a_w(uint8_t data)
*/
data = data ^ 0xff;
m_lamps[0] = BIT(data, 0); // lamp 0
m_lamps[1] = BIT(data, 1); // lamp 1
m_lamps[2] = BIT(data, 2); // lamp 2
m_lamps[3] = BIT(data, 3); // lamp 3
m_lamps[4] = BIT(data, 4); // lamp 4
m_lamps[0] = BIT(data, 0); // lamp 0
m_lamps[1] = BIT(data, 1); // lamp 1
m_lamps[2] = BIT(data, 2); // lamp 2
m_lamps[3] = BIT(data, 3); // lamp 3
m_lamps[4] = BIT(data, 4); // lamp 4
machine().bookkeeping().coin_counter_w(0, data & 0x40); // counter 1
machine().bookkeeping().coin_counter_w(1, data & 0x80); // counter 2
@ -1958,7 +1958,7 @@ void goldnpkr_state::goldnpkr_map(address_map &map)
map(0x0848, 0x084b).rw("pia1", FUNC(pia6821_device::read), FUNC(pia6821_device::write));
map(0x1000, 0x13ff).ram().w(FUNC(goldnpkr_state::goldnpkr_videoram_w)).share("videoram");
map(0x1800, 0x1bff).ram().w(FUNC(goldnpkr_state::goldnpkr_colorram_w)).share("colorram");
map(0x2000, 0x7fff).rom(); // superdbl uses 0x2000..0x3fff address space
map(0x2000, 0x7fff).rom(); // superdbl uses 0x2000..0x3fff address space
}
void goldnpkr_state::witchcdj_map(address_map &map)
@ -2033,9 +2033,9 @@ void goldnpkr_state::wildcard_map(address_map &map)
map(0x1000, 0x13ff).ram().w(FUNC(goldnpkr_state::goldnpkr_videoram_w)).share("videoram");
map(0x1800, 0x1bff).ram().w(FUNC(goldnpkr_state::goldnpkr_colorram_w)).share("colorram");
map(0x2000, 0x2000).portr("SW2");
map(0x2200, 0x27ff).rom(); // for VK set
map(0x2800, 0x2fff).ram(); // for VK set
map(0x3000, 0xffff).rom(); // for VK set. bootleg starts from 4000
map(0x2200, 0x27ff).rom(); // for VK set
map(0x2800, 0x2fff).ram(); // for VK set
map(0x3000, 0xffff).rom(); // for VK set. bootleg starts from 4000
}
/*
@ -2052,9 +2052,9 @@ void goldnpkr_state::wcrdxtnd_map(address_map &map)
map(0x1000, 0x13ff).ram().w(FUNC(goldnpkr_state::goldnpkr_videoram_w)).share("videoram");
map(0x1800, 0x1bff).ram().w(FUNC(goldnpkr_state::goldnpkr_colorram_w)).share("colorram");
map(0x2000, 0x2000).portr("SW2");
map(0x2200, 0x27ff).rom(); // for VK hardware
map(0x2200, 0x27ff).rom(); // for VK hardware
map(0x2800, 0x2fff).ram().share("nvram"); // Dallas ds1210 + battery backed RAM
map(0x3000, 0xffff).rom(); // for VK hardware. bootleg starts from 4000
map(0x3000, 0xffff).rom(); // for VK hardware. bootleg starts from 4000
}
/*
@ -2206,7 +2206,7 @@ static INPUT_PORTS_START( goldnpkr )
PORT_START("IN0-3")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Learn Mode") PORT_CODE(KEYCODE_F2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("D-31") PORT_CODE(KEYCODE_E) // O.A.R? (D-31 in schematics)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("D-31") PORT_CODE(KEYCODE_E) // O.A.R? (D-31 in schematics)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(3) PORT_NAME("Coupon (Note In)")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(3) PORT_NAME("Coin In")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("Weight (Coupon In)")
@ -2490,16 +2490,16 @@ static INPUT_PORTS_START( animpkr )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_DIPNAME( 0x10, 0x00, "High Pair (11-13)" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPNAME( 0x10, 0x00, "High Pair (11-13)" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, "50hz/60hz" ) PORT_DIPLOCATION("SW1:2")
PORT_DIPNAME( 0x20, 0x00, "50hz/60hz" ) PORT_DIPLOCATION("SW1:2")
PORT_DIPSETTING( 0x20, "50hz" )
PORT_DIPSETTING( 0x00, "60hz" )
PORT_DIPNAME( 0x40, 0x00, "Payout Mode" ) PORT_DIPLOCATION("SW1:3")
PORT_DIPNAME( 0x40, 0x00, "Payout Mode" ) PORT_DIPLOCATION("SW1:3")
PORT_DIPSETTING( 0x40, "Manual" )
PORT_DIPSETTING( 0x00, "Auto" )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:4")
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:4")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
@ -2573,7 +2573,7 @@ static INPUT_PORTS_START( ngold)
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, "Minimal Hand" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPNAME( 0x10, 0x00, "Minimal Hand" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x00, "Pair of Aces" )
PORT_DIPSETTING( 0x10, "Double Pair" )
PORT_DIPNAME( 0x20, 0x00, "50hz/60hz" ) PORT_DIPLOCATION("SW1:2")
@ -2644,7 +2644,7 @@ static INPUT_PORTS_START( ngoldb) // only coinage changes against ngold...
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, "Minimal Hand" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPNAME( 0x10, 0x00, "Minimal Hand" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x00, "Pair of Aces" )
PORT_DIPSETTING( 0x10, "Double Pair" )
PORT_DIPNAME( 0x20, 0x00, "50hz/60hz" ) PORT_DIPLOCATION("SW1:2")
@ -2738,10 +2738,10 @@ SW4 OFF ON OFF ON
switches 1+2+5+6 = OFF
switches 7+8 = ON
*/
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:1") // OFF by default
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:1") // OFF by default
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") // OFF by default
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") // OFF by default
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x0c, 0x04, "Percentage" ) PORT_DIPLOCATION("SW1:3,4")
@ -2749,16 +2749,16 @@ SW4 OFF ON OFF ON
PORT_DIPSETTING( 0x04, "50%" )
PORT_DIPSETTING( 0x08, "60%" )
PORT_DIPSETTING( 0x00, "70%" )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:5") // OFF by default
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:5") // OFF by default
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:6") // OFF by default
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:6") // OFF by default
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:7") // ON by default
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:7") // ON by default
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:8") // ON by default
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:8") // ON by default
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@ -4559,7 +4559,7 @@ static const discrete_555_desc goldnpkr_555_vco_desc =
static const discrete_dac_r1_ladder dac_goldnpkr_ladder =
{
3, // size of ladder
{RES_K(30), RES_K(15), RES_K(7.5)}, // elements
{RES_K(30), RES_K(15), RES_K(7.5)}, // elements
/* external vBias doesn't seems to be accurate.
using the 555 internal values sound better.
@ -4703,7 +4703,7 @@ void goldnpkr_state::goldnpkr_base(machine_config &config)
screen.set_visarea(0*8, 32*8-1, 0*8, 29*8-1); // From MC6845 init, registers 01 & 06.
screen.set_screen_update(FUNC(goldnpkr_state::screen_update_goldnpkr));
mc6845_device &crtc(MC6845(config, "crtc", CPU_CLOCK)); // 68B45 or 6845s @ CPU clock
mc6845_device &crtc(MC6845(config, "crtc", CPU_CLOCK)); // 68B45 or 6845s @ CPU clock
crtc.set_screen("screen");
crtc.set_show_border_area(false);
crtc.set_char_width(8);
@ -5109,7 +5109,7 @@ void blitz_state::megadpkr(machine_config &config)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&blitz_state::megadpkr_banked_map).set_data_width(8).set_addr_width(16).set_stride(0x4000);
M68705P5(config, m_mcu, CPU_CLOCK); // unknown
M68705P5(config, m_mcu, CPU_CLOCK); // unknown
m_mcu->portb_w().set(FUNC(blitz_state::mcu_portb_w));
m_mcu->portc_w().set(FUNC(blitz_state::mcu_portc_w));
@ -5302,7 +5302,7 @@ ROM_END
RB confirmed the dump. There are other games with double sized roms and identical halves.
*/
ROM_START( pottnpkr ) // golden poker style game. code is intended to start at $6000. is potten's poker the real name?
ROM_START( pottnpkr ) // golden poker style game. code is intended to start at $6000. is potten's poker the real name?
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD( "ic13_3.bin", 0x2000, 0x1000, CRC(23c975cd) SHA1(1d32a9ba3aa996287a823558b9d610ab879a29e8) )
ROM_LOAD( "ic14_4.bin", 0x3000, 0x1000, CRC(86a03aab) SHA1(0c4e8699b9fc9943de1fa0a364e043b3878636dc) )
@ -6416,8 +6416,8 @@ ROM_START( witchcdg )
ROM_LOAD( "1.b1", 0x2000, 0x1000, CRC(8a17d1a7) SHA1(488e4eae287b05923bd6b378574e91cfe49d8c24) ) // cards deck gfx, bitplane3
ROM_REGION( 0x3000, "gfx1", 0 )
ROM_FILL( 0x0000, 0x2000, 0x00000 ) // filling the R-G bitplanes
ROM_COPY( "gfx2", 0x2800, 0x2000, 0x0800 ) // srctag, srcoffs, offset, length
ROM_FILL( 0x0000, 0x2000, 0x00000 ) // filling the R-G bitplanes
ROM_COPY( "gfx2", 0x2800, 0x2000, 0x0800 ) // srctag, srcoffs, offset, length
ROM_REGION( 0x0100, "proms", 0 )
// ROM_LOAD( "82s129.7d", 0x0000, 0x0100, CRC(7f31066b) SHA1(15420780ec6b2870fc4539ec3afe4f0c58eedf12) ) // original PCB PROM
@ -6519,7 +6519,7 @@ ROM_START( witchgme )
ROM_LOAD( "3.5a", 0x2000, 0x1000, CRC(8a17d1a7) SHA1(488e4eae287b05923bd6b378574e91cfe49d8c24) ) // char ROM
ROM_REGION( 0x3000, "gfx1", 0 )
ROM_FILL( 0x0000, 0x2000, 0x0000 ) // filling the R-G bitplanes
ROM_FILL( 0x0000, 0x2000, 0x0000 ) // filling the R-G bitplanes
ROM_COPY( "gfx2", 0x2800, 0x2000, 0x0800 ) // srctag, srcoffs, offset, length
ROM_REGION( 0x0100, "proms", 0 )
@ -11455,7 +11455,7 @@ ROM_START( pokermon )
ROM_END
ROM_START( pokersis )
ROM_REGION( 0x10000, "maincpu", 0 ) // seems to contains 4 selectable programs, but vectors lack of sense
ROM_REGION( 0x10000, "maincpu", 0 ) // seems to contains 4 selectable programs, but vectors lack of sense
ROM_LOAD( "gsub1.bin", 0x0000, 0x10000, CRC(d585dd64) SHA1(acc371aa8c6c9d1ae784e62eae9c90fd05fad0fc) )
ROM_REGION( 0x18000, "gfx", 0 )
@ -11507,12 +11507,12 @@ ROM_END
The game looks like a poker game using rockets instead of cards.
But the game also has graphics tiles for 4 characters:
- pig
- duck
- donkey
- mouse
Duck and mouse are very close to Disney's characters Donald Duck
and Mickey Mouse.

2
src/mame/drivers/kas89.cpp
View File

@ -274,7 +274,7 @@ void kas89_state::machine_start()
save_item(NAME(m_main_nmi_enable));
save_item(NAME(m_leds_mux_selector));
save_item(NAME(m_leds_mux_data));
save_item(NAME(m_outdata));
save_item(NAME(m_outdata));
}
void kas89_state::machine_reset()

2
src/mame/drivers/lft_chiptune.cpp
View File

@ -12,7 +12,7 @@
#include "sound/volt_reg.h"
#include "speaker.h"
#define MASTER_CLOCK 8000000
#define MASTER_CLOCK 8000000
class lft_chiptune_state : public driver_device
{

2
src/mame/drivers/lft_craft.cpp
View File

@ -14,7 +14,7 @@
#include "emupal.h"
#include "speaker.h"
#define MASTER_CLOCK 20000000
#define MASTER_CLOCK 20000000
#define VISIBLE_CYCLES 480
#define HSYNC_CYCLES 155

2
src/mame/drivers/lft_phasor.cpp
View File

@ -14,7 +14,7 @@
#include "emupal.h"
#include "speaker.h"
#define MASTER_CLOCK 17734470
#define MASTER_CLOCK 17734470
#define SAMPLES_PER_FRAME (355255)

8
src/mame/drivers/magicard.cpp
View File

@ -25,7 +25,7 @@
* Puzzle Me!, Impera, 199?.
* unknown 'TE06', Impera, 199?.
* Lucky 7 (Impera), Impera, 199?.
*******************************************************************************
@ -987,7 +987,7 @@ ROM_START( magicardw )
ROM_REGION( 0x80000, "maincpu", 0 ) // 68070 Code & GFX
ROM_LOAD16_WORD_SWAP( "am27c4096.bin", 0x00000, 0x80000, CRC(d9e2a4ec) SHA1(b3000ded242fa25709c90b9b2541c9d1d5cabebb) )
ROM_REGION( 0x0200, "pic16c54", 0 ) // protected
ROM_REGION( 0x0200, "pic16c54", 0 ) // protected
ROM_LOAD("pic16c54a.bin", 0x0000, 0x0200, NO_DUMP )
ROM_END
@ -1114,14 +1114,14 @@ ROM_START( unkte06 )
ROM_REGION( 0x80000, "maincpu", 0 ) // 68070 Code & GFX
ROM_LOAD16_WORD_SWAP( "m27c4002.bin", 0x00000, 0x80000, CRC(229a504f) SHA1(8033e9b4cb55f2364bf4606375ef9ac05fc715fe) )
ROM_REGION( 0x0200, "pic16c54", 0 ) // protected
ROM_REGION( 0x0200, "pic16c54", 0 ) // protected
ROM_LOAD("pic16c54.bin", 0x0000, 0x0200, NO_DUMP )
ROM_END
/*
Lucky 7
Impera
*/
ROM_START( lucky7i )
ROM_REGION( 0x80000, "maincpu", 0 ) // 68070 Code & GFX

2
src/mame/drivers/midvunit.cpp
View File

@ -1671,7 +1671,7 @@ ROM_END
Some Off Road Challenge PCBs were all EPROMs, most seemed to have mask ROMs for the data ROMs
Mask ROMs have been seen in two formats:
-------------------------------- --------------------------------
-------------------------------- --------------------------------
| MIDWAY GAMES INC | | MIDWAY GAMES INC |
| OFFROAD CHALLENGE | | OFFROAD CHALLENGE |
) 5341-15511-01 | ) 5341-15510-01 |

14
src/mame/drivers/midzeus.cpp
View File

@ -41,10 +41,10 @@ The Grid v1.2 10/18/2000
#include "crusnexo.lh"
#define LOG_FIREWIRE (1 << 1)
#define LOG_DISK (1 << 2)
#define LOG_DISK_JR (1 << 3)
#define LOG_UNKNOWN (1 << 4)
#define LOG_FIREWIRE (1 << 1)
#define LOG_DISK (1 << 2)
#define LOG_DISK_JR (1 << 3)
#define LOG_UNKNOWN (1 << 4)
#define VERBOSE (LOG_FIREWIRE)
#include "logmacro.h"
@ -114,9 +114,9 @@ private:
void update_firewire_irq();
uint32_t m_disk_asic[0x10];
int m_fw_int_enable;
int m_fw_int;
uint32_t m_disk_asic[0x10];
int m_fw_int_enable;
int m_fw_int;
required_device<zeus2_device> m_zeus;
required_device<tsb12lv01a_device> m_fw_link;

42
src/mame/drivers/monkey_king_3b.cpp
View File

@ -28,39 +28,39 @@ built-in games, and a SD card for additional games.
The RS-70 is notable for having a debug UART on the USB port
(serial TX on D+, 115200). It prints the following messages on boot:
EXEC: Executing 'boot' with 0 args (ZLib ON)...
EXEC: Loading 'boot' at 0x18000000...
EXEC: Loaded 372272 bytes of 2097152 available.
EXEC: Executing 'boot' with 0 args (ZLib ON)...
EXEC: Loading 'boot' at 0x18000000...
EXEC: Loaded 372272 bytes of 2097152 available.
This is different from the serial output that this emulation model
currently produces. Perhaps one of the unimplemented IO is causing
it to go into some kind of debug mode. The log output produced by
this machine is:
Modes:0x00000000
PUT: Setting joystick to mode 0x0, timer to 250us
Modes:0x00000000
PUT: Setting joystick to mode 0x0, timer to 250us
******************************************************
MK FIRMWARE INFORMATION
Mode: 0xB4
Build Time: May 8 2019 14:09:21
CPU Clock: 240MHz
TFS Start: 0x8070000
Video Buf: 0x6000000
Stack Top: 0x3001EE8
IWRAM Size: 32kB
EVRAM Size: 16384kB
Heap Size: 6144kB at 0x18200000
Video Mode: 0
Video Size: 1280x720x16bpp
******************************************************
******************************************************
MK FIRMWARE INFORMATION
Mode: 0xB4
Build Time: May 8 2019 14:09:21
CPU Clock: 240MHz
TFS Start: 0x8070000
Video Buf: 0x6000000
Stack Top: 0x3001EE8
IWRAM Size: 32kB
EVRAM Size: 16384kB
Heap Size: 6144kB at 0x18200000
Video Mode: 0
Video Size: 1280x720x16bpp
******************************************************
There are other strings in the ROM that imply there may be more serial
debug possibilities.
TODO:
implement everything
add dumps of more Monkey King systems
implement everything
add dumps of more Monkey King systems
*/
#include "emu.h"

8
src/mame/drivers/nes_clone.cpp
View File

@ -416,11 +416,11 @@ void nes_clone_vtvppong_state::init_vtvppong()
{
for (int i = 0; i < len; i++)
{
int newaddr = bitswap<18>(i, 17, 16, 15, 13, 14, 12,
11, 10, 9, 8,
7, 6, 5, 4,
int newaddr = bitswap<18>(i, 17, 16, 15, 13, 14, 12,
11, 10, 9, 8,
7, 6, 5, 4,
3, 2, 1, 0);
buffer[i] = src[newaddr];
}
std::copy(buffer.begin(), buffer.end(), &src[0]);

2
src/mame/drivers/nes_sh6578.cpp
View File

@ -5,7 +5,7 @@
SH6578 NES clone hardware
enhanced NES, different to VT / OneBus systems
"UMC 1997.2 A35551S" on CPU die (maxx6in1)
"UMC 1997.2 A35551S" on CPU die (maxx6in1)
video rendering is changed significantly compared to NES so not using NES PPU device
has 256x256 pixel pages, attributes are stored next to tile numbers (not in their own table after them) etc.

2
src/mame/drivers/raiden_ms.cpp
View File

@ -482,7 +482,7 @@ void raiden_ms_state::raidenm(machine_config &config)
PALETTE(config, m_palette).set_format(palette_device::xBGR_444, 0x400);
GFXDECODE(config, "gfxdecode", "palette", gfx_raiden_ms);
GENERIC_LATCH_8(config, m_soundlatch);
/* sound hardware */

2
src/mame/drivers/seattle.cpp
View File

@ -755,7 +755,7 @@ const uint8_t seattle_state::translate49[7] = { 0x8, 0xc, 0xe, 0xf, 0x3, 0x1, 0x
*************************************/
CUSTOM_INPUT_MEMBER(seattle_state::blitz_49way_r)
{
return (translate49[m_io_49way_y[1]->read() >> 4] << 12) | (translate49[m_io_49way_x[1]->read() >> 4] << 8) |
return (translate49[m_io_49way_y[1]->read() >> 4] << 12) | (translate49[m_io_49way_x[1]->read() >> 4] << 8) |
(translate49[m_io_49way_y[0]->read() >> 4] << 4) | (translate49[m_io_49way_x[0]->read() >> 4] << 0);
}

4
src/mame/drivers/spg2xx.cpp
View File

@ -677,7 +677,7 @@ static INPUT_PORTS_START( totspies )
PORT_MODIFY("P2")
PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
// unit also has a 'select' button next to 'OK' and while test mode shows it onscreen too, it doesn't get tested, so probably isn't connected to anything?
PORT_MODIFY("P3")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("OK")
@ -1782,7 +1782,7 @@ CONS( 2006, ablkickb, 0, 0, ablkickb, ablkickb, spg2xx_game_albkickb_
CONS( 2007, lxspidaj, 0, 0, spg2xx_pal,lxspidaj, spg2xx_game_albkickb_state, init_ablkickb, "Lexibook", "Spider-Man Super TV Air Jet (Lexibook Junior, JG6000SP)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
CONS( 2006, totspies, 0, 0, spg2xx_pal,totspies, spg2xx_game_state, empty_init, "Senario / Marathon - Mystery Animation Inc.", "Totally Spies! (France)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
CONS( 2006, totspies, 0, 0, spg2xx_pal,totspies, spg2xx_game_state, empty_init, "Senario / Marathon - Mystery Animation Inc.", "Totally Spies! (France)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
CONS( 2006, fordrace, 0, 0, fordrace, fordrace, spg2xx_game_fordrace_state, empty_init, "Excalibur Electronics", "Ford Racing", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )

4
src/mame/drivers/spg2xx_shredmjr.cpp
View File

@ -147,7 +147,7 @@ void shredmjr_game_state::taikeegr(machine_config &config)
{
SPG24X(config, m_maincpu, XTAL(27'000'000), m_screen);
m_maincpu->set_addrmap(AS_PROGRAM, &shredmjr_game_state::mem_map_4m);
spg2xx_base(config);
m_maincpu->porta_in().set_ioport("P1");
@ -230,7 +230,7 @@ CONS( 2007, shredmjr, taikeegr, 0, shredmjr, taikeegr, shredmjr_ga
// doesn't have a Senario logo ingame, but does on box.
CONS( 200?, guitarst, 0, 0, taikeegr, taikeegr, shredmjr_game_state, init_taikeegr, "Senario", "Guitar Star (US, Senario, NTSC)", MACHINE_IMPERFECT_TIMING | MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS ) // ^
// this one has a different song selection (same as one in the alt undumped Rockstar Guitar / Guitar Rock. It was sold as a different product, so hasn't been set as a clone.
// this one has a different song selection (same as one in the alt undumped Rockstar Guitar / Guitar Rock. It was sold as a different product, so hasn't been set as a clone.
// Unit found in Ireland "imported by Cathay Product Sourcing Ltd." on the box, with address in Ireland
// ITEM #01109 on instruction sheet, no manufacturer named on either box or instructions
CONS( 200?, guitarstp, 0, 0, taikeegrp, guitarstp,shredmjr_game_state, init_taikeegr, "<unknown>", "Guitar Star (Europe, PAL)", MACHINE_IMPERFECT_TIMING | MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS ) // ^

20
src/mame/drivers/spg2xx_wiwi.cpp
View File

@ -148,7 +148,7 @@ void spg2xx_game_marc250_state::machine_start()
m_pulse_timer2->adjust(attotime::never);
// hack, makes x-racer3 and some others more stable, TODO: find out what is really wrong
m_maincpu->set_clock_scale(2.0000f);
m_maincpu->set_clock_scale(2.0000f);
}
@ -288,7 +288,7 @@ void spg2xx_game_marc101_state::porta_w(offs_t offset, uint16_t data, uint16_t m
// 00 - wait a while
// 01 - set 0x0400 in port a high
// 02 - clear 0x0400 in port a
// 07 - measure number of times 0x2000 on port a changes, with min/max acceptable values and a timeout
// 07 - measure number of times 0x2000 on port a changes, with min/max acceptable values and a timeout
// ff - failure (causes blank screen / shutdown + inf loop)
if ((data & 0x0400) != (m_prev_porta & 0x0400))
{
@ -307,7 +307,7 @@ uint16_t spg2xx_game_marc250_state::porta_r()
uint16_t ret = m_io_p1->read() &~ 0x6000;
ret |= m_toggle ? 0x2000 : 0x0000;
ret |= m_toggle2 ? 0x4000 : 0x0000;
// printf("porta %04x\n", ret);
// printf("porta %04x\n", ret);
return ret;
}
@ -681,7 +681,7 @@ void spg2xx_game_marc101_state::portb_w(offs_t offset, uint16_t data, uint16_t m
(mem_mask & 0x0001) ? ((data & 0x0001) ? '1' : '0') : 'x');
}
if (m_maincpu->pc() < 0x2000)
{
// bit 0x1000 isn't set as an output, but clearly needs to be treated as one
@ -728,14 +728,14 @@ void spg2xx_game_marc250_state::init_m527()
}
}
// pass maze road
//rom[((12 * 0x800000) / 2) | 0x0284b5] = 0x0003;
// learn numbers
//rom[((13 * 0x800000) / 2) | 0x00c055] = 0x0003;
// bowling
//rom[((17 * 0x800000) / 2) | 0x015e58] = 0x0003;
// cliff overhang / gym dancing
// cliff overhang / gym dancing
//rom[((18 * 0x800000) / 2) | 0x01cab4] = 0x0003;
rom[((18 * 0x800000) / 2) | 0x021e25] = 0xffff; // secondary 'turn off'
// jump chess
@ -792,8 +792,8 @@ void spg2xx_game_marc250_state::portb_w(offs_t offset, uint16_t data, uint16_t m
// bank 12 = (used) (doesn't boot)
// bank 13 = (used) (doesn't boot)
// bank 14 = (used) 'ROM 18 64M'
// bank 15 = (unused) 'ROM 18 64M' (dupe)
// bank 15 = (unused) 'ROM 18 64M' (dupe)
// bank 16 = (used) 'ROM 16 64M' (error)
// bank 17 = (used) (plays music)
// bank 18 = (used) (doesn't boot)
@ -802,7 +802,7 @@ void spg2xx_game_marc250_state::portb_w(offs_t offset, uint16_t data, uint16_t m
// bank 21 = (used)
// bank 22 = (used)
// bank 23 = (used)
// bank 24 = (used)
// bank 25 = (used)
// bank 26 = (used)
@ -886,7 +886,7 @@ ROM_END
ROM_START( marc250 )
ROM_REGION( 0x10000000, "maincpu", ROMREGION_ERASE00 )
ROM_LOAD16_WORD_SWAP( "m527.u6", 0x0000000, 0x10000000, CRC(4b856cab) SHA1(41c66bbdb0bb1442d7e11da18e9e6b20048445ba) )
ROM_END
ROM_END
ROM_START( guitrbus )
ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASE00 )

18
src/mame/drivers/splash_ms.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:David Haywood
/*
Splash (Modular System)
Splash (Modular System)
*/
@ -103,7 +103,7 @@ private:
void subrambank_map(address_map& map);
void subrombank_map(address_map& map);
void descramble_16x16tiles(uint8_t* src, int len);
};
@ -118,13 +118,13 @@ uint16_t splashms_state::unknown_0x40000c_r()
void splashms_state::sub_rambankselect_w(uint8_t data)
{
// logerror("sub_rambankselect_w %02x\n", data);
// logerror("sub_rambankselect_w %02x\n", data);
m_subram->set_bank(data&0x7);
}
void splashms_state::sub_rombankselect_w(uint8_t data)
{
// logerror("sub_rombankselect_w %02x\n", data);
// logerror("sub_rombankselect_w %02x\n", data);
m_subrom->set_bank(data & 0x7f);
}
@ -180,7 +180,7 @@ TILE_GET_INFO_MEMBER(splashms_state::get_tile_info_tilemap2)
uint32_t splashms_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
// bitmap.fill(0, cliprect);
// bitmap.fill(0, cliprect);
for (int y = 0; y < 256; y++)
{
@ -305,7 +305,7 @@ void splashms_state::sound_map(address_map &map)
map(0xe800, 0xe801).rw("ymsnd", FUNC(ym3812_device::read), FUNC(ym3812_device::write));
map(0xf000, 0xf7ff).ram();
map(0xf800, 0xf800).r(m_soundlatch, FUNC(generic_latch_8_device::read));
map(0xf800, 0xf800).r(m_soundlatch, FUNC(generic_latch_8_device::read));
}
void splashms_state::machine_start()
@ -468,7 +468,7 @@ void splashms_state::splashms(machine_config &config)
Z80(config, m_soundcpu, 16_MHz_XTAL/4);
m_soundcpu->set_addrmap(AS_PROGRAM, &splashms_state::sound_map);
m_soundcpu->set_periodic_int(FUNC(splashms_state::nmi_line_pulse), attotime::from_hz(60*64));
m_soundcpu->set_periodic_int(FUNC(splashms_state::nmi_line_pulse), attotime::from_hz(60*64));
/* video hardware */
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
@ -540,8 +540,8 @@ ROM_START( splashms )
ROM_LOAD32_BYTE( "8_sp_837.ic37", 0x000000, 0x010000, CRC(3b544131) SHA1(e7fd97cb24b84739f2481efb1d232f86df4a3d8d) ) // 1xxxxxxxxxxxxxxx = 0xFF
ROM_LOAD32_BYTE( "8_sp_830.ic30", 0x000001, 0x010000, CRC(09bb675b) SHA1(49c41ccfce1b0077c430c6bb38bc858aeaf87fb8) ) // has some garbage in the blank space of the paired ROMs
ROM_LOAD32_BYTE( "8_sp_822.ic22", 0x000002, 0x010000, CRC(621fcf26) SHA1(a7ff6b12fbbea1bba7c4a397a82ac2fb5c09558a) ) // 1xxxxxxxxxxxxxxx = 0xFF
ROM_LOAD32_BYTE( "8_sp_815.ic15", 0x000003, 0x010000, CRC(5641b621) SHA1(e71df1ab5c9b2254495d99657477b52e8843d128) ) // 1xxxxxxxxxxxxxxx = 0xFF
ROM_LOAD32_BYTE( "8_sp_815.ic15", 0x000003, 0x010000, CRC(5641b621) SHA1(e71df1ab5c9b2254495d99657477b52e8843d128) ) // 1xxxxxxxxxxxxxxx = 0xFF
ROM_REGION( 0x080000, "sprites", ROMREGION_ERASEFF | ROMREGION_INVERT )
ROM_LOAD32_BYTE( "5-1_sp_524.ic24", 0x000000, 0x010000, CRC(841c24c1) SHA1(70cb26033999f8184c51849e00bfcb2270f646e8) )
ROM_LOAD32_BYTE( "5-1_sp_518.ic18", 0x000001, 0x010000, CRC(499cb813) SHA1(4d22e58530ff8a85b7ffc8ae1ab5986215986b49) )

44
src/mame/drivers/truco.cpp
View File

@ -204,9 +204,9 @@
#include "speaker.h"
#define MASTER_CLOCK XTAL(12'000'000) // confirmed
#define CPU_CLOCK (MASTER_CLOCK/16) // guess
#define CRTC_CLOCK (MASTER_CLOCK/8) // guess
#define MASTER_CLOCK XTAL(12'000'000) // confirmed
#define CPU_CLOCK (MASTER_CLOCK/16) // guess
#define CRTC_CLOCK (MASTER_CLOCK/8) // guess
/*******************************************
@ -233,7 +233,7 @@ WRITE_LINE_MEMBER(truco_state::pia_ca2_w)
void truco_state::portb_w(uint8_t data)
{
m_dac->write(BIT(data, 7)); // Isolated the bit for Delta-Sigma DAC
m_dac->write(BIT(data, 7)); // Isolated the bit for Delta-Sigma DAC
if (data & 0x7f)
logerror("Port B writes: %2x\n", data);
@ -256,9 +256,9 @@ WRITE_LINE_MEMBER(truco_state::pia_irqb_w)
void truco_state::main_map(address_map &map)
{
map(0x0000, 0x17ff).ram(); // General purpose RAM
map(0x1800, 0x7bff).ram().share("videoram"); // Video RAM
map(0x7c00, 0x7fff).ram().share("battery_ram"); // Battery backed RAM
map(0x0000, 0x17ff).ram(); // General purpose RAM
map(0x1800, 0x7bff).ram().share("videoram"); // Video RAM
map(0x7c00, 0x7fff).ram().share("battery_ram"); // Battery backed RAM
map(0x8000, 0x8003).rw("pia0", FUNC(pia6821_device::read), FUNC(pia6821_device::write));
map(0x8004, 0x8004).w("crtc", FUNC(mc6845_device::address_w));
map(0x8005, 0x8005).rw("crtc", FUNC(mc6845_device::register_r), FUNC(mc6845_device::register_w));
@ -266,7 +266,7 @@ void truco_state::main_map(address_map &map)
}
/*
CRTC MC6845 initialization routine at $a506 only set the first 14 registers (data at $a4e2)
Register: 00 01 02 03 04 05 06 07 08 09 10 11 12 13
Value: 0x5f 0x40 0x4d 0x06 0x0f 0x04 0x0c 0x0e 0x00 0x0f 0x00 0x00 0x00 0xc0
@ -278,17 +278,17 @@ void truco_state::main_map(address_map &map)
*******************************************/
static INPUT_PORTS_START( truco )
PORT_START("P1") // IN0
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S17 (P2 START)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S14 (SERVICE SW)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA C26 (P2 SELECT)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S16 (COIN2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S15 (TILT SW)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) // Connected to JAMMA C22 (P1 BUTTON1)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) // Connected to JAMMA C18/21 (JOY UP & JOY RIGHT)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) // Connected to JAMMA C19/20 (JOY DOWN & JOY LEFT)
PORT_START("P1") // IN0
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S17 (P2 START)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S14 (SERVICE SW)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA C26 (P2 SELECT)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S16 (COIN2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Connected to JAMMA S15 (TILT SW)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) // Connected to JAMMA C22 (P1 BUTTON1)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) // Connected to JAMMA C18/21 (JOY UP & JOY RIGHT)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) // Connected to JAMMA C19/20 (JOY DOWN & JOY LEFT)
PORT_START("COIN") // IN1
PORT_START("COIN") // IN1
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
@ -298,7 +298,7 @@ static INPUT_PORTS_START( truco )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("JMPRS") // JP1-2
PORT_START("JMPRS") // JP1-2
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
PORT_DIPSETTING ( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING ( 0x00, DEF_STR( On ) )
@ -397,7 +397,7 @@ void truco_state::truco(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &truco_state::main_map);
m_maincpu->set_vblank_int("screen", FUNC(truco_state::interrupt));
WATCHDOG_TIMER(config, m_watchdog).set_time(attotime::from_msec(1600)); // 1.6 seconds
WATCHDOG_TIMER(config, m_watchdog).set_time(attotime::from_msec(1600)); // 1.6 seconds
pia6821_device &pia(PIA6821(config, "pia0", 0));
pia.readpa_handler().set_ioport("P1");
@ -411,14 +411,14 @@ void truco_state::truco(machine_config &config)
// video hardware
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_refresh_hz(60);
screen.set_vblank_time(ATTOSECONDS_IN_USEC(2500)); // not accurate
screen.set_vblank_time(ATTOSECONDS_IN_USEC(2500)); // not accurate
screen.set_size(256, 192);
screen.set_visarea(0, 256-1, 0, 192-1);
screen.set_screen_update(FUNC(truco_state::screen_update));
PALETTE(config, "palette", FUNC(truco_state::truco_palette), 16);
mc6845_device &crtc(MC6845(config, "crtc", CRTC_CLOCK)); // identified as UM6845
mc6845_device &crtc(MC6845(config, "crtc", CRTC_CLOCK)); // identified as UM6845
crtc.set_screen("screen");
crtc.set_show_border_area(false);
crtc.set_char_width(4);

8
src/mame/drivers/vegas.cpp
View File

@ -1138,8 +1138,8 @@ CUSTOM_INPUT_MEMBER(vegas_state::gauntleg_p12_r)
}
else {
// 49 way joysticks
return (translate49[m_io_49way_x[1]->read() >> 4] << 12) | (translate49[m_io_49way_y[1]->read() >> 4] << 8) |
(translate49[m_io_49way_x[0]->read() >> 4] << 4) | (translate49[m_io_49way_y[0]->read() >> 4] << 0);
return (translate49[m_io_49way_x[1]->read() >> 4] << 12) | (translate49[m_io_49way_y[1]->read() >> 4] << 8) |
(translate49[m_io_49way_x[0]->read() >> 4] << 4) | (translate49[m_io_49way_y[0]->read() >> 4] << 0);
}
}
@ -1154,8 +1154,8 @@ CUSTOM_INPUT_MEMBER(vegas_state::gauntleg_p34_r)
}
else {
// 49 way joysticks
return (translate49[m_io_49way_x[3]->read() >> 4] << 12) | (translate49[m_io_49way_y[3]->read() >> 4] << 8) |
(translate49[m_io_49way_x[2]->read() >> 4] << 4) | (translate49[m_io_49way_y[2]->read() >> 4] << 0);
return (translate49[m_io_49way_x[3]->read() >> 4] << 12) | (translate49[m_io_49way_y[3]->read() >> 4] << 8) |
(translate49[m_io_49way_x[2]->read() >> 4] << 4) | (translate49[m_io_49way_y[2]->read() >> 4] << 0);
}
}

8
src/mame/drivers/vsmile.cpp
View File

@ -333,10 +333,10 @@ ROM_START( vsmilem )
/* This ROM doesn't show the 'Motion' logo at all, but was dumped from a Motion unit
Console says "Vtech V.Smile V-motion Active Learning System"
"FCC ID 62R-0788, IC 1135D-0788" "53-36600-056-080"
melted into plastic "VT8281"
The PCB has the code 35-078800-001-103_708979-2.
Console says "Vtech V.Smile V-motion Active Learning System"
"FCC ID 62R-0788, IC 1135D-0788" "53-36600-056-080"
melted into plastic "VT8281"
The PCB has the code 35-078800-001-103_708979-2.
*/
ROM_SYSTEM_BIOS( 1, "bios1", "bios1" )
ROMX_LOAD( "vmotionbios.bin", 0x000000, 0x200000, CRC(427087ea) SHA1(dc9eaa55f4a0047b6069ef73beea86d26f0f5394), ROM_GROUPWORD | ROM_REVERSE | ROM_BIOS(1) ) // from a US unit

2
src/mame/drivers/vt1682.cpp
View File

@ -6130,7 +6130,7 @@ CONS( 200?, itvg48, exsprt48, 0, vt1682_exsportp, exsprt48, vt1682_exspo
// This has a different selection of games to the above, Dancing as extra under Music, Doesn't have Poker under Brain, Ball Shoot instead of 'Noshery' under Arcade
// imported by Cathay Product Sourcing Ltd. (Ireland) no other manufacturer information on box, not sure if Xing is name of manufacturer or product
CONS( 200?, xing48, 0, 0, vt1682_exsportp, exsprt48, vt1682_exsport_state, regular_init, "Xing", "Xing Wireless Interactive TV Game 'Wi TV Zone' 48-in-1 (Europe, PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // ^
CONS( 200?, xing48, 0, 0, vt1682_exsportp, exsprt48, vt1682_exsport_state, regular_init, "Xing", "Xing Wireless Interactive TV Game 'Wi TV Zone' 48-in-1 (Europe, PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // ^
/*
The above was also released in the US as Excite Sports Wireless Interactive TV Game - 48-in-1 with an almost identical box to exsprt48 unit, but with the different games noted.

50
src/mame/includes/midzeus.h
View File

@ -149,20 +149,20 @@ protected:
optional_ioport m_io_keypad;
output_finder<7> m_digits;
emu_timer * m_display_irq_off_timer;
uint8_t m_crusnexo_leds_select;
uint32_t m_disk_asic_jr[0x10];
emu_timer * m_display_irq_off_timer;
uint8_t m_crusnexo_leds_select;
uint32_t m_disk_asic_jr[0x10];
uint8_t m_cmos_protected;
uint8_t m_cmos_protected;
emu_timer * m_timer[2];
emu_timer * m_timer[2];
private:
uint32_t m_gun_control;
uint8_t m_gun_irq_state;
emu_timer * m_gun_timer[2];
int32_t m_gun_x[2], m_gun_y[2];
uint8_t m_keypad_select;
uint32_t m_gun_control;
uint8_t m_gun_irq_state;
emu_timer * m_gun_timer[2];
int32_t m_gun_x[2], m_gun_y[2];
uint8_t m_keypad_select;
void exit_handler();
void zeus_pointer_w(uint32_t which, uint32_t data, bool logit);
@ -186,22 +186,22 @@ private:
void waveram_plot_check_depth_nowrite(int y, int x, uint16_t color, uint16_t depth);
std::unique_ptr<midzeus_renderer> m_poly;
uint8_t m_log_fifo;
uint8_t m_log_fifo;
uint32_t m_zeus_fifo[20];
uint8_t m_zeus_fifo_words;
int16_t m_zeus_matrix[3][3];
int32_t m_zeus_point[3];
int16_t m_zeus_light[3];
void * m_zeus_renderbase;
uint32_t m_zeus_palbase;
uint32_t m_zeus_unkbase;
int m_zeus_enable_logging;
uint32_t m_zeus_objdata;
rectangle m_zeus_cliprect;
uint32_t m_zeus_fifo[20];
uint8_t m_zeus_fifo_words;
int16_t m_zeus_matrix[3][3];
int32_t m_zeus_point[3];
int16_t m_zeus_light[3];
void * m_zeus_renderbase;
uint32_t m_zeus_palbase;
uint32_t m_zeus_unkbase;
int m_zeus_enable_logging;
uint32_t m_zeus_objdata;
rectangle m_zeus_cliprect;
std::unique_ptr<uint32_t[]> m_waveram[2];
int m_yoffs;
int m_texel_width;
int m_is_mk4b;
int m_yoffs;
int m_texel_width;
int m_is_mk4b;
};

2
src/mame/layout/v4addlad.lay
View File

@ -496,7 +496,7 @@ license:CC0
</bezel>
<bezel name="LADDER" element="LADDER">
<bounds x="127" y="142" width="16" height="16" />
</bezel>
</bezel>
<bezel name="lamp126" element="matrixlamp" state="0">
<bounds x="145" y="140" width="20" height="20"/>
</bezel>

2
src/mame/layout/v4barqst.lay
View File

@ -304,7 +304,7 @@ license:CC0
<bounds x="2" y="2" width="16" height="8" />
</text>
</element>
<element name="START" defstate="0">
<rect state ="0">
<bounds x="0" y="0" width="20" height="10" />

8
src/mame/layout/v4strike.lay
View File

@ -201,7 +201,7 @@ license:CC0
<bounds x="0" y="0" width="16" height="8" />
</text>
</element>
<element name="COLLECT" defstate="0">
<rect state ="0">
<bounds x="0" y="0" width="16" height="10" />
@ -452,14 +452,14 @@ license:CC0
<bezel name="lamp51" element="FREEZE" inputtag="ORANGE1" inputmask="0x10">
<bounds x="250" y="560" width="50" height="50" />
</bezel>
<bezel name="lamp35" element="GO" inputtag="ORANGE1" inputmask="0x40">
<bounds x="300" y="560" width="50" height="50" />
</bezel>
<screen index="0">
<bounds x="50" y="260" width="504" height="296" />
</screen>
</view>
</mamelayout>

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