mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
Added fccpu20 to Miniforce as a VME card
This commit is contained in:
Joakim Larsson Edstrom
parent
19a9122748
commit
615b815259
@ -1499,6 +1499,8 @@ if (BUSES["VME"]~=null) then
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MAME_DIR .. "src/devices/bus/vme/vme_mzr8300.h",
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MAME_DIR .. "src/devices/bus/vme/vme_mvme350.cpp",
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MAME_DIR .. "src/devices/bus/vme/vme_mvme350.h",
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MAME_DIR .. "src/devices/bus/vme/vme_fccpu20.cpp",
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MAME_DIR .. "src/devices/bus/vme/vme_fccpu20.h",
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MAME_DIR .. "src/devices/bus/vme/vme_fcisio.cpp",
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MAME_DIR .. "src/devices/bus/vme/vme_fcisio.h",
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MAME_DIR .. "src/devices/bus/vme/vme_fcscsi.cpp",
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290
src/devices/bus/vme/vme_fccpu20.cpp
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290
src/devices/bus/vme/vme_fccpu20.cpp
Normal file
@ -0,0 +1,290 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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/***************************************************************************
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*/
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#include "emu.h"
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#include "cpu/m68000/m68000.h"
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#include "bus/rs232/rs232.h"
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#include "machine/68230pit.h"
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#include "machine/68153bim.h"
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#include "machine/68561mpcc.h"
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#include "machine/clock.h"
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#include "vme_fccpu20.h"
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#define LOG_GENERAL 0x01
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#define LOG_SETUP 0x02
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#define LOG_PRINTF 0x04
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#define LOG_INT 0x08
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#define VERBOSE 0 //(LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
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#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0)
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#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0)
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#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__)
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#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
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#define LOGINT(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
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#if VERBOSE & LOG_PRINTF
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#define logerror printf
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#endif
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#ifdef _MSC_VER
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#define FUNCNAME __func__
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#else
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#define FUNCNAME __PRETTY_FUNCTION__
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#endif
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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const device_type VME_FCCPU20 = &device_creator<vme_fccpu20_card_device>;
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#define CPU_CLOCK XTAL_20MHz /* HCJ */
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#define DUSCC_CLOCK XTAL_14_7456MHz /* HCJ */
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static ADDRESS_MAP_START (cpu20_mem, AS_PROGRAM, 32, vme_fccpu20_card_device)
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
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AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
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AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* RAM installed in machine start */
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AM_RANGE (0xff040000, 0xff04ffff) AM_RAM /* RAM installed in machine start */
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AM_RANGE (0xff000000, 0xff00ffff) AM_ROM AM_REGION("roms", 0x0000)
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AM_RANGE (0xff800000, 0xff80001f) AM_DEVREADWRITE8("mpcc", mpcc68561_device, read, write, 0xffffffff)
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AM_RANGE (0xff800200, 0xff80021f) AM_DEVREADWRITE8("mpcc2", mpcc68561_device, read, write, 0xffffffff)
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// AM_RANGE (0xff800200, 0xff8003ff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xff00ff00)
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AM_RANGE (0xff800600, 0xff80061f) AM_DEVREADWRITE8("mpcc3", mpcc68561_device, read, write, 0xffffffff)
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AM_RANGE (0xff800800, 0xff80080f) AM_DEVREADWRITE8("bim", bim68153_device, read, write, 0xff00ff00)
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// AM_RANGE (0xff800a00, 0xff800a0f) AM_DEVREADWRITE8("rtc", rtc_device, read, write, 0x00ff00ff)
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AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0xffffffff)
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ADDRESS_MAP_END
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/*
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* Machine configuration
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*/
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static MACHINE_CONFIG_FRAGMENT (fccpu20)
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/* basic machine hardware */
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MCFG_CPU_ADD ("maincpu", M68020, XTAL_16MHz) /* Crytstal not verified */
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MCFG_CPU_PROGRAM_MAP (cpu20_mem)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("bim", bim68153_device, iack)
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// MCFG_VME_DEVICE_ADD("vme")
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// MCFG_VME_SLOT_ADD ("vme", "vme1", fccpu20_vme_cards, nullptr)
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/* PIT Parallel Interface and Timer device, assumed strapped for on board clock */
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MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_32MHz / 4) /* Crystal not verified */
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MCFG_PIT68230_PA_INPUT_CB(READ8(vme_fccpu20_card_device, pita_r))
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MCFG_PIT68230_PB_INPUT_CB(READ8(vme_fccpu20_card_device, pitb_r))
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MCFG_PIT68230_PC_INPUT_CB(READ8(vme_fccpu20_card_device, pitc_r))
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MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("bim", bim68153_device, int2_w))
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/* BIM */
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MCFG_MC68153_ADD("bim", XTAL_32MHz / 8)
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MCFG_BIM68153_OUT_INT_CB(WRITELINE(vme_fccpu20_card_device, bim_irq_callback))
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/*INT0 - Abort switch */
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/*INT1 - MPCC@8.064 MHz aswell */
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/*INT2 - PI/T timer */
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/*INT3 - SYSFAIL/IRQVMX/ACFAIL/MPCC2/3 */
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/* MPCC */
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#define RS232P1_TAG "rs232p1"
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#define RS232P2_TAG "rs232p2"
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#define RS232P3_TAG "rs232p3"
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// MPCC
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MCFG_MPCC68561_ADD ("mpcc", XTAL_32MHz / 4, 0, 0)
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MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_txd))
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MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_dtr))
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MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_rts))
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MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int1_w))
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/* Additional MPCC sits on slave boards like SRAM-22 */
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// MPCC2
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MCFG_MPCC68561_ADD ("mpcc2", XTAL_32MHz / 4, 0, 0)
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MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_txd))
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MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_dtr))
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MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_rts))
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MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int3_w))
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// MPCC3
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MCFG_MPCC68561_ADD ("mpcc3", XTAL_32MHz / 4, 0, 0)
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MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_txd))
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MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_dtr))
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MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_rts))
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MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int3_w))
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// MPCC - RS232
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MCFG_RS232_PORT_ADD (RS232P1_TAG, default_rs232_devices, "terminal")
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MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc", mpcc68561_device, write_rx))
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MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc", mpcc68561_device, cts_w))
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// MPCC2 - RS232
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MCFG_RS232_PORT_ADD (RS232P2_TAG, default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc2", mpcc68561_device, write_rx))
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MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc2", mpcc68561_device, cts_w))
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// MPCC3 - RS232
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MCFG_RS232_PORT_ADD (RS232P3_TAG, default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc3", mpcc68561_device, write_rx))
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MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc3", mpcc68561_device, cts_w))
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MACHINE_CONFIG_END
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/* ROM definitions */
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ROM_START (fccpu20) /* This is an original rom dump */
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ROM_REGION32_BE(0x10000, "roms", 0)
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// Boots with Board ID set to: 0x36 (FGA002 BOOT on terminal P4, "Wait until harddisk is up to speed " on terminal P1)
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ROM_LOAD32_BYTE("L.BIN", 0x000002, 0x4000, CRC (174ab801) SHA1 (0d7b8ed29d5fdd4bd2073005008120c5f20128dd))
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ROM_LOAD32_BYTE("LL.BIN", 0x000003, 0x4000, CRC (9fd9e3e4) SHA1 (e5a7c87021e6be412dd5a8166d9f62b681169eda))
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ROM_LOAD32_BYTE("U.BIN", 0x000001, 0x4000, CRC (d1afe4c0) SHA1 (b5baf9798d73632f7bb843cbc4b306c8c03f4296))
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ROM_LOAD32_BYTE("UU.BIN", 0x000000, 0x4000, CRC (b54d623b) SHA1 (49b272184a04570b09004de71fae0ed0d1bf5929))
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ROM_END
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machine_config_constructor vme_fccpu20_card_device::device_mconfig_additions() const
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{
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LOG("%s %s\n", tag(), FUNCNAME);
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return MACHINE_CONFIG_NAME( fccpu20 );
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}
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const tiny_rom_entry *vme_fccpu20_card_device::device_rom_region() const
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{
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LOG("%s\n", FUNCNAME);
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return ROM_NAME( fccpu20 );
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
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device_t(mconfig, type, name, tag, owner, clock, shortname, source)
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,device_vme_card_interface(mconfig, *this)
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, m_maincpu (*this, "maincpu")
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, m_pit (*this, "pit")
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, m_bim (*this, "bim")
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, m_mpcc (*this, "mpcc")
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, m_mpcc2 (*this, "mpcc2")
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, m_mpcc3 (*this, "mpcc3")
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{
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LOG("%s\n", FUNCNAME);
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}
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vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, VME_FCCPU20, "Force Computer SYS68K/CPU-20 CPU Board", tag, owner, clock, "fccpu20", __FILE__)
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,device_vme_card_interface(mconfig, *this)
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, m_maincpu (*this, "maincpu")
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, m_pit (*this, "pit")
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, m_bim (*this, "bim")
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, m_mpcc (*this, "mpcc")
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, m_mpcc2 (*this, "mpcc2")
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, m_mpcc3 (*this, "mpcc3")
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{
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LOG("%s %s\n", tag, FUNCNAME);
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}
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/* Start it up */
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void vme_fccpu20_card_device::device_start()
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{
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LOG("%s\n", FUNCNAME);
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set_vme_device();
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save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
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save_pointer (NAME (m_sysram), sizeof(m_sysram));
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/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
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m_sysrom = (uint32_t*)(memregion ("roms")->base());
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#if 0 // TODO: Setup VME access handlers for shared memory area
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uint32_t base = 0xFFFF5000;
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m_vme->install_device(base + 0, base + 1, // Channel B - Data
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read8_delegate(FUNC(z80sio_device::db_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::db_w), subdevice<z80sio_device>("pit")), 0x00ff);
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m_vme->install_device(base + 2, base + 3, // Channel B - Control
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read8_delegate(FUNC(z80sio_device::cb_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::cb_w), subdevice<z80sio_device>("pit")), 0x00ff);
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#endif
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}
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void vme_fccpu20_card_device::device_reset()
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{
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LOG("%s\n", FUNCNAME);
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}
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/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
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READ32_MEMBER (vme_fccpu20_card_device::bootvect_r){
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LOG("%s\n", FUNCNAME);
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return m_sysrom[offset];
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}
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WRITE32_MEMBER (vme_fccpu20_card_device::bootvect_w){
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LOG("%s\n", FUNCNAME);
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m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
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m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
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m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
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}
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WRITE_LINE_MEMBER(vme_fccpu20_card_device::bim_irq_callback)
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{
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LOGINT("%s(%02x)\n", FUNCNAME, state);
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bim_irq_state = state;
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bim_irq_level = m_bim->get_irq_level();
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LOGINT(" - BIM irq level %02x\n", bim_irq_level);
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update_irq_to_maincpu();
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}
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void vme_fccpu20_card_device::update_irq_to_maincpu()
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{
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LOGINT("%s()\n", FUNCNAME);
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LOGINT(" - bim_irq_level: %02x\n", bim_irq_level);
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LOGINT(" - bim_irq_state: %02x\n", bim_irq_state);
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switch (bim_irq_level & 0x07)
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{
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case 1: m_maincpu->set_input_line(M68K_IRQ_1, bim_irq_state); break;
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case 2: m_maincpu->set_input_line(M68K_IRQ_2, bim_irq_state); break;
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case 3: m_maincpu->set_input_line(M68K_IRQ_3, bim_irq_state); break;
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case 4: m_maincpu->set_input_line(M68K_IRQ_4, bim_irq_state); break;
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case 5: m_maincpu->set_input_line(M68K_IRQ_5, bim_irq_state); break;
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case 6: m_maincpu->set_input_line(M68K_IRQ_6, bim_irq_state); break;
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case 7: m_maincpu->set_input_line(M68K_IRQ_7, bim_irq_state); break;
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default: logerror("Programmatic error in %s, please report\n", FUNCNAME);
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}
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}
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/* 8 configuration DIP switches
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Baud B3 B2 B1 B0
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9600 0 0 0 1
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28800 0 0 1 0
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38400 1 0 1 0
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57600 0 0 1 1
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B3: 8 bit 38400 baud
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B4:
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B5:
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B6: Auto execute FF00C0000
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B7: memory size?
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*/
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#define BR7N9600 0x01
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#define BR7N28800 0x02
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#define BR7N38400 0x06
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#define BR7N57600 0x03
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#define BR8N38400 0x08
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#define FORCEBUG 0x30
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READ8_MEMBER (vme_fccpu20_card_device::pita_r){
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LOG("%s\n", FUNCNAME);
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return FORCEBUG | BR7N9600;
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}
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/* Enabling/Disabling of VME IRQ 1-7 */
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READ8_MEMBER (vme_fccpu20_card_device::pitb_r){
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LOG("%s\n", FUNCNAME);
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return 0xff;
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}
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/* VME bus release software settings (output) (ROR, RAT, RATAR, RATBCLR, RORAT, RORRAT */
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READ8_MEMBER (vme_fccpu20_card_device::pitc_r){
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LOG("%s\n", FUNCNAME);
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return 0xff;
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}
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61
src/devices/bus/vme/vme_fccpu20.h
Normal file
61
src/devices/bus/vme/vme_fccpu20.h
Normal file
@ -0,0 +1,61 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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#ifndef VME_FCCPU20_H
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#define VME_FCCPU20_H
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#pragma once
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#include "emu.h"
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#include "machine/68561mpcc.h"
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#include "machine/68230pit.h"
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#include "machine/68153bim.h"
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#include "bus/vme/vme.h"
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extern const device_type VME_FCCPU20;
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class vme_fccpu20_card_device :
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public device_t
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,public device_vme_card_interface
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{
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public:
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vme_fccpu20_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
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vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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// optional information overrides
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virtual machine_config_constructor device_mconfig_additions() const override;
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virtual const tiny_rom_entry *device_rom_region() const override;
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// Below are duplicated declarations from src/mame/drivers/fccpu20.cpp
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DECLARE_READ32_MEMBER (bootvect_r);
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DECLARE_WRITE32_MEMBER (bootvect_w);
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DECLARE_WRITE_LINE_MEMBER(bim_irq_callback);
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uint8_t bim_irq_state;
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int bim_irq_level;
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/* PIT callbacks */
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DECLARE_READ8_MEMBER (pita_r);
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DECLARE_READ8_MEMBER (pitb_r);
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DECLARE_READ8_MEMBER (pitc_r);
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private:
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required_device<cpu_device> m_maincpu;
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||||
required_device<pit68230_device> m_pit;
|
||||
required_device<bim68153_device> m_bim;
|
||||
required_device<mpcc68561_device> m_mpcc;
|
||||
required_device<mpcc68561_device> m_mpcc2;
|
||||
required_device<mpcc68561_device> m_mpcc3;
|
||||
|
||||
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
|
||||
uint32_t *m_sysrom;
|
||||
uint32_t m_sysram[2];
|
||||
void update_irq_to_maincpu();
|
||||
|
||||
// Below replaces machine_start and machine_reset from src/mame/drivers/fccpu20.cpp
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
};
|
||||
|
||||
#endif // VME_FCCPU20_H
|
||||
@ -97,6 +97,7 @@
|
||||
*/
|
||||
#include "emu.h"
|
||||
#include "bus/vme/vme.h"
|
||||
#include "bus/vme/vme_fccpu20.h"
|
||||
#include "bus/vme/vme_fcisio.h"
|
||||
#include "bus/vme/vme_fcscsi.h"
|
||||
#include "machine/clock.h"
|
||||
@ -163,6 +164,7 @@ static INPUT_PORTS_START (miniforce)
|
||||
INPUT_PORTS_END
|
||||
|
||||
static SLOT_INTERFACE_START(miniforce_vme_cards)
|
||||
SLOT_INTERFACE("fccpu20", VME_FCCPU20)
|
||||
SLOT_INTERFACE("fcisio", VME_FCISIO1)
|
||||
SLOT_INTERFACE("fcscsi", VME_FCSCSI1)
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
Loading…
Reference in New Issue
Block a user