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https://github.com/holub/mame
synced 2025-06-07 21:33:45 +03:00
Initial Hector cleanup. In the future, please ensure your code comments are in English. nw
This commit is contained in:
parent
89f5248eb5
commit
629b7fd63e
@ -113,15 +113,15 @@ public:
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uint8_t m_hector_disc2_data_w_ready;
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uint8_t m_hector_disc2_data_w_ready;
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uint8_t m_hector_disc2_data_read;
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uint8_t m_hector_disc2_data_read;
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uint8_t m_hector_disc2_data_write;
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uint8_t m_hector_disc2_data_write;
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uint8_t m_hector_disc2_RNMI;
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uint8_t m_hector_disc2_rnmi;
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uint8_t m_state3000;
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uint8_t m_state3000;
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uint8_t m_write_cassette;
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uint8_t m_write_cassette;
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emu_timer *m_Cassette_timer;
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emu_timer *m_cassette_timer;
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uint8_t m_CK_signal ;
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uint8_t m_ck_signal;
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uint8_t m_flag_clk;
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uint8_t m_flag_clk;
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double m_Pin_Value[29][2];
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double m_pin_value[29][2];
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int m_AU[17];
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int m_au[17];
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int m_ValMixer;
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int m_val_mixer;
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int m_oldstate3000;
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int m_oldstate3000;
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int m_oldstate1000;
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int m_oldstate1000;
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uint8_t m_pot0;
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uint8_t m_pot0;
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@ -134,10 +134,10 @@ public:
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uint8_t m_hector_port_cmd;
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uint8_t m_hector_port_cmd;
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uint8_t m_cassette_bit;
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uint8_t m_cassette_bit;
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uint8_t m_cassette_bit_mem;
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uint8_t m_cassette_bit_mem;
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uint8_t m_Data_K7;
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uint8_t m_data_k7;
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int m_counter_write;
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int m_counter_write;
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int m_IRQ_current_state;
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int m_irq_current_state;
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int m_NMI_current_state;
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int m_nmi_current_state;
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int m_hector_cmd[10];
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int m_hector_cmd[10];
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int m_hector_nb_cde;
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int m_hector_nb_cde;
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int m_hector_flag_result;
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int m_hector_flag_result;
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@ -167,22 +167,22 @@ public:
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DECLARE_MACHINE_START(hec2mdhrx);
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DECLARE_MACHINE_START(hec2mdhrx);
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DECLARE_MACHINE_RESET(hec2mdhrx);
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DECLARE_MACHINE_RESET(hec2mdhrx);
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uint32_t screen_update_hec2hrp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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uint32_t screen_update_hec2hrp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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TIMER_CALLBACK_MEMBER(Callback_CK);
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TIMER_CALLBACK_MEMBER(cassette_clock);
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DECLARE_WRITE_LINE_MEMBER( disc2_fdc_interrupt );
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DECLARE_WRITE_LINE_MEMBER( disc2_fdc_interrupt );
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DECLARE_WRITE_LINE_MEMBER( disc2_fdc_dma_irq );
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DECLARE_WRITE_LINE_MEMBER( disc2_fdc_dma_irq );
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int isHectorWithDisc2();
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int has_disc2();
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int isHectorWithMiniDisc();
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int has_minidisc();
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int isHectorHR();
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int is_hr();
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int isHectoreXtend();
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int is_extended();
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void Mise_A_Jour_Etat(int Adresse, int Value );
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void update_state(int Adresse, int Value );
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void Init_Value_SN76477_Hector();
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void init_sn76477();
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void Update_Sound(address_space &space, uint8_t data);
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void update_sound(address_space &space, uint8_t data);
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void hector_reset(int hr, int with_D2 );
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void hector_reset(int hr, int with_d2);
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void hector_init();
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void hector_init();
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void Init_Hector_Palette();
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void init_palette();
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void hector_80c(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram) ;
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void hector_80c(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram);
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void hector_hr(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram) ;
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void hector_hr(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram);
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/*----------- defined in machine/hecdisk2.c -----------*/
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/*----------- defined in machine/hecdisk2.c -----------*/
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// disc2 handling
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// disc2 handling
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@ -14,7 +14,7 @@
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31/06/2009 Video - Robbbert
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31/06/2009 Video - Robbbert
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29/10/2009 Update skeleton to functional machine
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29/10/2009 Update skeleton to functional machine
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by yo_fr (jj.stac @ aliceadsl.fr)
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by yo_fr (jj.stac@aliceadsl.fr)
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=> add Keyboard,
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=> add Keyboard,
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=> add color,
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=> add color,
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@ -27,15 +27,16 @@
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03/01/2010 Update and clean prog by yo_fr (jj.stac @ aliceadsl.fr)
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03/01/2010 Update and clean prog by yo_fr (jj.stac @ aliceadsl.fr)
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=> add the port mapping for keyboard
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=> add the port mapping for keyboard
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28/09/2010 add the DISK II support by yo_fr (jj.stac @ aliceadsl.fr)
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28/09/2010 add the DISK II support by yo_fr (jj.stac @ aliceadsl.fr)
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=> Note that actually the DISK II boot (loading CPM : OK) but do not run (don't run the CPM...).
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=> Note that the DISK II boots and loads CP/M, but CP/M doesn't yet work.
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20/11/2010 : synchronization between uPD765 and Z80 are now OK, CP/M running! JJStacino
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20/11/2010 : synchronization between uPD765 and Z80 is now OK, CP/M works. JJStacino
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11/11/2011 : add the minidisque support -3 pouces 1/2 driver- JJStacino (jj.stac @ aliceadsl.fr)
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11/11/2011 : add the minidisk support (3.5" drive) JJStacino
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19/02/2012 : few adjustment for the hrp and hr machine - JJStacino
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19/02/2012 : few adjustment for the hrp and hr machine - JJStacino
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don't forget to keep some information about these machines, see DChector project : http://dchector.free.fr/ made by DanielCoulom
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More information:
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(and thank's to Daniel!) and Yves site : http://hectorvictor.free.fr/ (thank's too Yves!)
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- http://dchector.free.fr/
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- http://hectorvictor.free.fr/
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TODO : Add the cartridge function,
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TODO : Add cartridge functionality,
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Adjust the one shot and A/D timing (sn76477)
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Adjust the one shot and A/D timing (sn76477)
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*/
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*/
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@ -46,7 +47,7 @@
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#include "imagedev/cassette.h"
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#include "imagedev/cassette.h"
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#include "imagedev/printer.h"
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#include "imagedev/printer.h"
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#include "machine/upd765.h" /* for floppy disc controller */
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#include "machine/upd765.h" /* for floppy disc controller */
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#include "sound/wave.h" /* for K7 sound*/
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#include "sound/wave.h" /* for K7 sound */
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#include "sound/discrete.h" /* for 1 Bit sound*/
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#include "sound/discrete.h" /* for 1 Bit sound*/
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#include "speaker.h"
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#include "speaker.h"
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@ -71,40 +72,39 @@ hec2mx40
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*/
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*/
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/* Helper function*/
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/* Helper function*/
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int hec2hrp_state::isHectorWithDisc2()
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int hec2hrp_state::has_disc2()
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{
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{
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return ((strncmp(machine().system().name , "hec2hrx" , 7)==0) ||
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return ((strncmp(machine().system().name , "hec2hrx" , 7)==0) ||
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(strncmp(machine().system().name , "hec2mx40" , 8)==0) ||
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(strncmp(machine().system().name , "hec2mx40" , 8)==0) ||
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(strncmp(machine().system().name , "hec2mx80" , 8)==0));
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(strncmp(machine().system().name , "hec2mx80" , 8)==0));
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}
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}
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int hec2hrp_state::isHectorWithMiniDisc()
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int hec2hrp_state::has_minidisc()
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{
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{
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return ((strncmp(machine().system().name , "hec2mdhrx", 9)==0));
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return ((strncmp(machine().system().name , "hec2mdhrx", 9)==0));
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}
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}
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int hec2hrp_state::isHectorHR()
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int hec2hrp_state::is_hr()
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{
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{
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return ((strncmp(machine().system().name , "hec2hr" , 6)==0) || //Aviable for hr & hrp
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return ((strncmp(machine().system().name , "hec2hr" , 6)==0) || //Aviable for hr & hrp
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(strncmp(machine().system().name , "hec2mdhrx", 9)==0) ||
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(strncmp(machine().system().name , "hec2mdhrx", 9)==0) ||
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(strncmp(machine().system().name , "victor" , 6)==0) ||
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(strncmp(machine().system().name , "victor" , 6)==0) ||
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(strncmp(machine().system().name , "hec2mx40" , 8)==0) ||
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(strncmp(machine().system().name , "hec2mx40" , 8)==0) ||
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(strncmp(machine().system().name , "hec2mx80" , 8)==0));
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(strncmp(machine().system().name , "hec2mx80" , 8)==0));
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}
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}
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int hec2hrp_state::isHectoreXtend()
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int hec2hrp_state::is_extended()
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{
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{
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return ((strncmp(machine().system().name , "hec2mdhrx", 9)==0) ||
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return ((strncmp(machine().system().name , "hec2mdhrx", 9)==0) ||
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(strncmp(machine().system().name , "hec2hrx" , 7)==0) ||
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(strncmp(machine().system().name , "hec2hrx" , 7)==0) ||
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(strncmp(machine().system().name , "hec2mx40" , 8)==0) ||
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(strncmp(machine().system().name , "hec2mx40" , 8)==0) ||
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(strncmp(machine().system().name , "hec2mx80" , 8)==0));
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(strncmp(machine().system().name , "hec2mx80" , 8)==0));
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}
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}
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/* Cassette timer*/
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/* Cassette timer*/
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TIMER_CALLBACK_MEMBER(hec2hrp_state::Callback_CK)
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TIMER_CALLBACK_MEMBER(hec2hrp_state::cassette_clock)
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{
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{
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/* To generate the CK signal (K7)*/
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m_ck_signal++;
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m_CK_signal++;
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}
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}
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WRITE8_MEMBER( hec2hrp_state::minidisc_control_w )
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WRITE8_MEMBER( hec2hrp_state::minidisc_control_w )
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@ -128,83 +128,98 @@ WRITE8_MEMBER( hec2hrp_state::minidisc_control_w )
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WRITE8_MEMBER(hec2hrp_state::hector_switch_bank_w)
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WRITE8_MEMBER(hec2hrp_state::hector_switch_bank_w)
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{
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{
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if (offset==0x00) { /* 0x800 et 0x000=> video page, HR*/
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if (offset==0x00)
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if (isHectoreXtend())
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{
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if (is_extended())
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{
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membank("bank1")->set_entry(HECTOR_BANK_VIDEO);
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membank("bank1")->set_entry(HECTOR_BANK_VIDEO);
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if (m_flag_clk ==1)
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}
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if (m_flag_clk == 1)
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{
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{
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m_flag_clk=0;
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m_flag_clk = 0;
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m_maincpu->set_unscaled_clock(XTAL(5'000'000)); /* increase CPU*/
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m_maincpu->set_unscaled_clock(XTAL(5'000'000));
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}
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}
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}
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}
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if (offset==0x04) { /* 0x804 => video page, BR*/
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m_hector_flag_hr=0;
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if (isHectoreXtend())
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membank("bank1")->set_entry(HECTOR_BANK_VIDEO);
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if (m_flag_clk ==0)
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{
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m_flag_clk=1;
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m_maincpu->set_unscaled_clock(XTAL(1'750'000)); /* slowdown CPU*/
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}
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}
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if (offset==0x08) { /* 0x808 => base page, HR*/
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if (isHectoreXtend())
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membank("bank1")->set_entry(HECTOR_BANK_PROG);
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if (m_flag_clk ==1)
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{
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m_flag_clk=0;
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m_maincpu->set_unscaled_clock(XTAL(5'000'000)); /* increase CPU*/
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}
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}
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if (offset==0x04)
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if (offset==0x0c) { /* 0x80c => base page, BR*/
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m_hector_flag_hr=0;
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if (isHectoreXtend())
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membank("bank1")->set_entry(HECTOR_BANK_PROG);
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if (m_flag_clk ==0)
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{
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{
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m_flag_clk=1;
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m_hector_flag_hr = 0;
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m_maincpu->set_unscaled_clock(XTAL(1'750'000)); /* slowdown CPU*/
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if (is_extended())
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{
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membank("bank1")->set_entry(HECTOR_BANK_VIDEO);
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}
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if (m_flag_clk == 0)
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{
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m_flag_clk = 1;
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m_maincpu->set_unscaled_clock(XTAL(1'750'000));
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}
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}
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if (offset==0x08)
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{
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if (is_extended())
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{
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membank("bank1")->set_entry(HECTOR_BANK_PROG);
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}
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if (m_flag_clk == 1)
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{
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m_flag_clk = 0;
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m_maincpu->set_unscaled_clock(XTAL(5'000'000));
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}
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}
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if (offset == 0x0c)
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{
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m_hector_flag_hr = 0;
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if (is_extended())
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{
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membank("bank1")->set_entry(HECTOR_BANK_PROG);
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}
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if (m_flag_clk == 0)
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{
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m_flag_clk = 1;
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m_maincpu->set_unscaled_clock(XTAL(1'750'000));
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}
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}
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}
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}
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}
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}
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WRITE8_MEMBER(hec2hrp_state::hector_keyboard_w)
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WRITE8_MEMBER(hec2hrp_state::hector_keyboard_w)
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{
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{
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/*nothing to do => read function manage the value*/
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/* nothing to do (read function manages the value) */
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}
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}
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READ8_MEMBER(hec2hrp_state::hector_keyboard_r)
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READ8_MEMBER(hec2hrp_state::hector_keyboard_r)
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{
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{
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uint8_t data = 0xff;
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uint8_t data = 0xff;
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if (offset ==7) /* Only when joy reading*/
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if (offset == 7) /* Only when reading joystick */
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{
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{
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/* Read special key for analog joystick emulation only (button and pot are analog signal!) and the reset */
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/* Read special key for analog joystick emulation only (button and pot are analog signals), and reset */
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data=m_keyboard[8]->read();
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data=m_keyboard[8]->read();
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if (data & 0x01) /* Reset machine ! (on ESC key)*/
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if (data & 0x01) /* Reset machine */
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{
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{
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m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
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m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
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if (isHectorHR()) /* aviable for HR and up */
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if (is_hr())
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{
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{
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m_hector_flag_hr=1;
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m_hector_flag_hr = 1;
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if (isHectoreXtend())
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if (is_extended())
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{
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{
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membank("bank1")->set_entry(HECTOR_BANK_PROG);
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membank("bank1")->set_entry(HECTOR_BANK_PROG);
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membank("bank2")->set_entry(HECTORMX_BANK_PAGE0);
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membank("bank2")->set_entry(HECTORMX_BANK_PAGE0);
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}
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}
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//RESET DISC II unit
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//RESET DISC II unit
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if (isHectorWithDisc2() )
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if (has_disc2())
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hector_disc2_reset();
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hector_disc2_reset();
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/* floppy md master reset */
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/* floppy md master reset */
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if (isHectorWithMiniDisc())
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if (has_minidisc())
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m_minidisc_fdc->reset();
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m_minidisc_fdc->reset();
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}
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}
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else
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else /* aviable for BR machines */
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{
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m_hector_flag_hr=0;
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m_hector_flag_hr=0;
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}
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/*Common flag*/
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/*Common flag*/
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@ -238,28 +253,30 @@ READ8_MEMBER(hec2hrp_state::hector_keyboard_r)
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if (m_pot1>250) m_pot1 = 0;
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if (m_pot1>250) m_pot1 = 0;
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}
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}
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/* in all case return the request value*/
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/* in all case return the requested value */
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return m_keyboard[offset]->read();
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return m_keyboard[offset]->read();
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}
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}
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WRITE8_MEMBER(hec2hrp_state::hector_sn_2000_w)
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WRITE8_MEMBER(hec2hrp_state::hector_sn_2000_w)
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{
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{
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Mise_A_Jour_Etat(0x2000+ offset, data);
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update_state(0x2000+ offset, data);
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Update_Sound(space, data);
|
update_sound(space, data);
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE8_MEMBER(hec2hrp_state::hector_sn_2800_w)
|
WRITE8_MEMBER(hec2hrp_state::hector_sn_2800_w)
|
||||||
{
|
{
|
||||||
Mise_A_Jour_Etat(0x2800+ offset, data);
|
update_state(0x2800+ offset, data);
|
||||||
Update_Sound(space, data);
|
update_sound(space, data);
|
||||||
}
|
}
|
||||||
|
|
||||||
READ8_MEMBER(hec2hrp_state::hector_cassette_r)
|
READ8_MEMBER(hec2hrp_state::hector_cassette_r)
|
||||||
{
|
{
|
||||||
double level;
|
double level;
|
||||||
uint8_t value=0;
|
uint8_t value = 0;
|
||||||
|
|
||||||
if ((m_state3000 & 0x38) != 0x38 ) /* Selon Sb choix cassette ou timer (74153)*/
|
if ((m_state3000 & 0x38) != 0x38 )
|
||||||
{
|
{
|
||||||
m_Data_K7 = 0x00; /* No cassette => clear bit*/
|
m_data_k7 = 0x00; /* No cassette => clear bit*/
|
||||||
switch (m_state3000 & 0x38 )
|
switch (m_state3000 & 0x38 )
|
||||||
{
|
{
|
||||||
case 0x08: value = (m_actions & 1) ? 0x80 : 0; break;
|
case 0x08: value = (m_actions & 1) ? 0x80 : 0; break;
|
||||||
@ -273,25 +290,23 @@ READ8_MEMBER(hec2hrp_state::hector_cassette_r)
|
|||||||
{
|
{
|
||||||
if (m_write_cassette == 0)
|
if (m_write_cassette == 0)
|
||||||
{
|
{
|
||||||
/* Accee a la cassette*/
|
|
||||||
level = m_cassette->input();
|
level = m_cassette->input();
|
||||||
|
|
||||||
/* Travail du 741 en trigger*/
|
|
||||||
if (level < -0.08)
|
if (level < -0.08)
|
||||||
m_cassette_bit = 0x00;
|
m_cassette_bit = 0x00;
|
||||||
if (level > +0.08)
|
if (level > +0.08)
|
||||||
m_cassette_bit = 0x01;
|
m_cassette_bit = 0x01;
|
||||||
}
|
}
|
||||||
/* Programme du sn7474 (bascule) : Changement ??tat bit Data K7 ?? chaque front montant de m_cassette_bit*/
|
|
||||||
if ((m_cassette_bit != m_cassette_bit_mem) && (m_cassette_bit !=0))
|
if ((m_cassette_bit != m_cassette_bit_mem) && (m_cassette_bit !=0))
|
||||||
{
|
{
|
||||||
if (m_Data_K7 == 0x00)
|
if (m_data_k7 == 0x00)
|
||||||
m_Data_K7 = 0x80;/* En poids fort*/
|
m_data_k7 = 0x80;
|
||||||
else
|
else
|
||||||
m_Data_K7 = 0x00;
|
m_data_k7 = 0x00;
|
||||||
}
|
}
|
||||||
value = ( m_CK_signal & 0x7F ) + m_Data_K7;
|
value = ( m_ck_signal & 0x7F ) + m_data_k7;
|
||||||
m_cassette_bit_mem = m_cassette_bit; /* Memorisation etat bit cassette*/
|
m_cassette_bit_mem = m_cassette_bit;
|
||||||
}
|
}
|
||||||
return value;
|
return value;
|
||||||
}
|
}
|
||||||
@ -301,8 +316,8 @@ WRITE8_MEMBER(hec2hrp_state::hector_sn_3000_w)
|
|||||||
if ((data & 7) != m_oldstate3000 )
|
if ((data & 7) != m_oldstate3000 )
|
||||||
{
|
{
|
||||||
/* Update sn76477 only when necessary!*/
|
/* Update sn76477 only when necessary!*/
|
||||||
Mise_A_Jour_Etat(0x3000, data & 7 );
|
update_state(0x3000, data & 7 );
|
||||||
Update_Sound(space, data & 7);
|
update_sound(space, data & 7);
|
||||||
}
|
}
|
||||||
m_oldstate3000 = data & 7;
|
m_oldstate3000 = data & 7;
|
||||||
}
|
}
|
||||||
@ -452,35 +467,27 @@ WRITE8_MEMBER(hec2hrp_state::hector_io_8255_w)
|
|||||||
{
|
{
|
||||||
m_hector_port_c_l = data & 0x0f;
|
m_hector_port_c_l = data & 0x0f;
|
||||||
// Utilizing bits port C : PC0 for the printer : strobe!
|
// Utilizing bits port C : PC0 for the printer : strobe!
|
||||||
if (BIT(m_hector_port_c_l , 0)) // PC0 (bit X0)= true
|
if (BIT(m_hector_port_c_l, 0)) // PC0 (bit 0)= true
|
||||||
{
|
{
|
||||||
/* Port A => to printer*/
|
/* Port A goes to the printer */
|
||||||
//printer_output(machine().device("printer"), m_hector_port_a);
|
|
||||||
}
|
}
|
||||||
// Utilizing bits port C : PC1 // PC2 for the communication with disc2
|
// Utilizing bits port C : PC1 // PC2 for the communication with disc2
|
||||||
if (!BIT(m_hector_port_c_l , 1)) // PC1 (bit X1)= true
|
if (!BIT(m_hector_port_c_l, 1)) // PC1 (bit 1)= true
|
||||||
{
|
{
|
||||||
// Lecture effectuee => RAZ memoire donnee m_hector_disc2_data_write dispo
|
m_hector_port_b = m_hector_disc2_data_write;
|
||||||
m_hector_port_b = m_hector_disc2_data_write; // Mep sur port B si 2eme 74374 existant !
|
|
||||||
m_hector_disc2_data_w_ready = 0x00;
|
m_hector_disc2_data_w_ready = 0x00;
|
||||||
#ifdef DEBUG_TRACE_COM_HECTOR
|
|
||||||
printf("\nEcriture port B vers m_hector_disc2_data_write suite a PC1");
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
if (!BIT(m_hector_port_c_l, 2)) // PC2 (bit X2)= true
|
if (!BIT(m_hector_port_c_l, 2)) // PC2 (bit 2)= true
|
||||||
{
|
{
|
||||||
m_hector_disc2_data_read = m_hector_port_a; /* mise en place de l'info presente sur le port A */
|
m_hector_disc2_data_read = m_hector_port_a;
|
||||||
m_hector_disc2_data_r_ready = 0x08; /* memorisation de l'info */
|
m_hector_disc2_data_r_ready = 0x08; /* memorisation de l'info */
|
||||||
#ifdef DEBUG_TRACE_COM_HECTOR
|
|
||||||
printf("\nEcriture port A pour m_hector_disc2_data_read suite a PC2");
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (!BIT(m_hector_port_cmd, 3)) /* cmd -> Quartet sup en sortie ?*/
|
if (!BIT(m_hector_port_cmd, 3))
|
||||||
m_hector_port_c_h = (data & 0xf0);
|
m_hector_port_c_h = (data & 0xf0);
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((offset & 0x3) == 0x3) /* Port commande */
|
if ((offset & 0x3) == 0x3) /* command */
|
||||||
{
|
{
|
||||||
m_hector_port_cmd = data;
|
m_hector_port_cmd = data;
|
||||||
}
|
}
|
||||||
@ -488,10 +495,10 @@ WRITE8_MEMBER(hec2hrp_state::hector_io_8255_w)
|
|||||||
/* End of 8255 managing */
|
/* End of 8255 managing */
|
||||||
|
|
||||||
|
|
||||||
/******************* Ecriture PIO specifique machine MX40 *******************/
|
/******************* PIO write handler for MX40 *******************/
|
||||||
WRITE8_MEMBER(hec2hrp_state::hector_mx40_io_port_w)
|
WRITE8_MEMBER(hec2hrp_state::hector_mx40_io_port_w)
|
||||||
{
|
{
|
||||||
/* Bank switching on several address */
|
/* Bank switching on several address */
|
||||||
if ((offset &0x0ff) == 0x40) /* Port page 0*/
|
if ((offset &0x0ff) == 0x40) /* Port page 0*/
|
||||||
membank("bank2")->set_entry(HECTORMX_BANK_PAGE0);
|
membank("bank2")->set_entry(HECTORMX_BANK_PAGE0);
|
||||||
if ((offset &0x0ff) == 0x41) /* Port page 1*/
|
if ((offset &0x0ff) == 0x41) /* Port page 1*/
|
||||||
@ -505,7 +512,7 @@ WRITE8_MEMBER(hec2hrp_state::hector_mx40_io_port_w)
|
|||||||
m_hector_flag_80c=0;/* No 80c in 40c !*/
|
m_hector_flag_80c=0;/* No 80c in 40c !*/
|
||||||
}
|
}
|
||||||
|
|
||||||
/******************* Ecriture PIO specifique machine MX80 *******************/
|
/******************* PIO write handlerfor MX80 *******************/
|
||||||
WRITE8_MEMBER(hec2hrp_state::hector_mx80_io_port_w)
|
WRITE8_MEMBER(hec2hrp_state::hector_mx80_io_port_w)
|
||||||
{
|
{
|
||||||
if ((offset &0x0ff) == 0x40) /* Port page 0*/
|
if ((offset &0x0ff) == 0x40) /* Port page 0*/
|
||||||
@ -522,259 +529,249 @@ WRITE8_MEMBER(hec2hrp_state::hector_mx80_io_port_w)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/********************************************************************************
|
/********************************************************************************
|
||||||
sound managment
|
sound management
|
||||||
********************************************************************************/
|
********************************************************************************/
|
||||||
|
|
||||||
void hec2hrp_state::Mise_A_Jour_Etat(int Adresse, int Value )
|
void hec2hrp_state::update_state(int Adresse, int Value )
|
||||||
{
|
{
|
||||||
/* Adjust value depending on I/O main CPU request*/
|
/* Adjust value depending on I/O main CPU request*/
|
||||||
switch(Adresse )
|
switch(Adresse )
|
||||||
{
|
{
|
||||||
case 0x2000:
|
case 0x2000:
|
||||||
/* Modification AU0 / AU8*/
|
|
||||||
{ /* AU0*/
|
|
||||||
m_AU[ 0] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU8 : 0*/
|
|
||||||
m_AU[ 8] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2001:
|
|
||||||
/* Modification AU1 / AU9*/
|
|
||||||
{ /* AU1*/
|
|
||||||
m_AU[ 1] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU9*/
|
|
||||||
m_AU[ 9] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2002:
|
|
||||||
/* Modification AU2 / AU10*/
|
|
||||||
{ /* AU2*/
|
|
||||||
m_AU[ 2] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU10*/
|
|
||||||
m_AU[10] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2003:
|
|
||||||
/* Modification AU3 / AU11*/
|
|
||||||
{ /* AU3*/
|
|
||||||
m_AU[ 3] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU11*/
|
|
||||||
m_AU[11] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2800:
|
|
||||||
/* Modification AU4 / AU12*/
|
|
||||||
{ /* AU4*/
|
|
||||||
m_AU[ 4] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU8*/
|
|
||||||
m_AU[12] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2801:
|
|
||||||
/* Modification AU5 / AU13*/
|
|
||||||
{ /* AU5*/
|
|
||||||
m_AU[ 5] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU13*/
|
|
||||||
m_AU[13] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2802:
|
|
||||||
{ /* Modification AU6 / AU14*/
|
|
||||||
/* AU6*/
|
|
||||||
m_AU[ 6] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU14*/
|
|
||||||
m_AU[14] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x2803:
|
|
||||||
/* Modification AU7 / AU15*/
|
|
||||||
{ /* AU7*/
|
|
||||||
m_AU[ 7] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
|
||||||
/* AU15*/
|
|
||||||
m_AU[15] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x3000:
|
|
||||||
/* Mixer modification*/
|
|
||||||
{
|
{
|
||||||
m_ValMixer = (Value & 7) ;
|
m_au[ 0] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[ 8] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2001:
|
||||||
|
{
|
||||||
|
m_au[ 1] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[ 9] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2002:
|
||||||
|
{
|
||||||
|
m_au[ 2] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[10] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2003:
|
||||||
|
{
|
||||||
|
m_au[ 3] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[11] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2800:
|
||||||
|
{
|
||||||
|
m_au[ 4] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[12] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2801:
|
||||||
|
{
|
||||||
|
m_au[ 5] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[13] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2802:
|
||||||
|
{
|
||||||
|
m_au[ 6] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[14] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x2803:
|
||||||
|
{
|
||||||
|
m_au[ 7] = ((Value & 0x080 )==0) ? 0 : 1 ;
|
||||||
|
m_au[15] = ((Value & 0x040 )==0) ? 0 : 1 ;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x3000:
|
||||||
|
{
|
||||||
|
m_val_mixer = (Value & 7) ;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: break;
|
default: break;
|
||||||
} /*switch*/
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void hec2hrp_state::Init_Value_SN76477_Hector()
|
void hec2hrp_state::init_sn76477()
|
||||||
{
|
{
|
||||||
/* Remplissage des valeurs de resistance et capacite d'Hector*/
|
/* R/C value setup */
|
||||||
|
|
||||||
/* Decay R*/
|
/* decay resistors */
|
||||||
m_Pin_Value[7][1] = RES_K(680.0); /*680K */
|
m_pin_value[7][1] = RES_K(680.0); /*680K */
|
||||||
m_Pin_Value[7][0] = RES_K(252.325); /* 142.325 (680 // 180KOhm)*/
|
m_pin_value[7][0] = RES_K(252.325); /* 142.325 (680 // 180KOhm)*/
|
||||||
|
|
||||||
/* Capa A/D*/
|
/* attack/decay capacitors */
|
||||||
m_Pin_Value[8][0] = CAP_U(0.47); /* 0.47uf*/
|
m_pin_value[8][0] = CAP_U(0.47); /* 0.47uf*/
|
||||||
m_Pin_Value[8][1] = CAP_U(1.47); /* 1.47*/
|
m_pin_value[8][1] = CAP_U(1.47); /* 1.47*/
|
||||||
|
|
||||||
/* ATTACK R*/
|
/* attack resistors */
|
||||||
m_Pin_Value[10][1]= RES_K(180.0); /* 180*/
|
m_pin_value[10][1]= RES_K(180.0); /* 180*/
|
||||||
m_Pin_Value[10][0]= RES_K(32.054); /* 32.054 (180 // 39 KOhm)*/
|
m_pin_value[10][0]= RES_K(32.054); /* 32.054 (180 // 39 KOhm)*/
|
||||||
|
|
||||||
/* Version 3 : Ajuste pour les frequences mesurees :
|
/* Version 3 : Frequency measurement adjustment:
|
||||||
// 4 0 SOUND 255 Hz => ajuste a l'oreille
|
// 4 0 SOUND 255 Hz => ajuste a l'oreille
|
||||||
// 4 4 SOUND 65 Hz => ajuste a l'oreille
|
// 4 4 SOUND 65 Hz => ajuste a l'oreille
|
||||||
// 4 8 SOUND 17 Hz => ajuste a l'oreille
|
// 4 8 SOUND 17 Hz => ajuste a l'oreille
|
||||||
// 4 12 SOUND 4,3 Hz => ajuste a l'oreille*/
|
// 4 12 SOUND 4,3 Hz => ajuste a l'oreille*/
|
||||||
/* SLF C Version 3*/
|
/* SLF C Version 3*/
|
||||||
m_Pin_Value[21][0]= CAP_U(0.1); /*CAPU(0.1) */
|
m_pin_value[21][0]= CAP_U(0.1); /*CAPU(0.1) */
|
||||||
m_Pin_Value[21][1]= CAP_U(1.1); /*1.1*/
|
m_pin_value[21][1]= CAP_U(1.1); /*1.1*/
|
||||||
|
|
||||||
/*SLF R Version 3*/
|
/* SLF R Version 3*/
|
||||||
m_Pin_Value[20][1]= RES_K(180); //180 vu
|
m_pin_value[20][1]= RES_K(180); //180 (based on visual inspection of the resistor)
|
||||||
m_Pin_Value[20][0]= RES_K(37.268); //37.268 (47//180 KOhms)
|
m_pin_value[20][0]= RES_K(37.268); // 37.268 (47//180 KOhms)
|
||||||
|
|
||||||
/* Capa VCO*/
|
/* Capa VCO*/
|
||||||
/* Version 3 : Ajust?? pour les frequences mesur??es :
|
/* Version 3 : Frequency measurement adjustment:
|
||||||
// 0 0 SOUND 5,5KHz => 5,1KHz
|
// 0 0 SOUND 5,5KHz => 5,1KHz
|
||||||
// 0 16 SOUND 1,3KHz => 1,2KHz
|
// 0 16 SOUND 1,3KHz => 1,2KHz
|
||||||
// 0 32 SOUND 580Hz => 570Hz
|
// 0 32 SOUND 580Hz => 570Hz
|
||||||
// 0 48 SOUND 132Hz => 120Hz*/
|
// 0 48 SOUND 132Hz => 120Hz*/
|
||||||
m_Pin_Value[17][0] = CAP_N(47.0) ; /*47,0 mesure ok */
|
m_pin_value[17][0] = CAP_N(47.0) ; /* measured */
|
||||||
m_Pin_Value[17][1] = CAP_N(580.0) ; /*580 mesure ok */
|
m_pin_value[17][1] = CAP_N(580.0) ; /* measured */
|
||||||
/* R VCO Version 3*/
|
/* R VCO Version 3*/
|
||||||
m_Pin_Value[18][1] = RES_K(1400.0 );/*1300 mesure ok // au lieu de 1Mohm*/
|
m_pin_value[18][1] = RES_K(1400.0 );/* Measured 1300, instead of 1Mohm*/
|
||||||
m_Pin_Value[18][0] = RES_K( 203.548 );/*223 mesure ok // au lieu de 193.548 (1000 // 240KOhm)*/
|
m_pin_value[18][0] = RES_K( 203.548 );/* Measured 223, instead of 193.548 (1000 // 240KOhm)*/
|
||||||
|
|
||||||
/* VCO Controle*/
|
/* VCO Controle*/
|
||||||
m_Pin_Value[16][0] = 0.0; /* Volts */
|
m_pin_value[16][0] = 0.0; /* Volts */
|
||||||
m_Pin_Value[16][1] = 1.41; /* 2 = 10/15eme de 5V*/
|
m_pin_value[16][1] = 1.41; /* 2 = 10/15th of 5V*/
|
||||||
|
|
||||||
/* Pitch*/
|
/* Pitch*/
|
||||||
m_Pin_Value[19][0] = 0.0; /*Volts */
|
m_pin_value[19][0] = 0.0; /*Volts */
|
||||||
m_Pin_Value[19][1] = 1.41;
|
m_pin_value[19][1] = 1.41;
|
||||||
|
|
||||||
m_Pin_Value[22][0] = 0; /* TOR */
|
m_pin_value[22][0] = 0; /* TOR */
|
||||||
m_Pin_Value[22][1] = 1;
|
m_pin_value[22][1] = 1;
|
||||||
|
|
||||||
/* R OneShot*/
|
/* One-shot resistor */
|
||||||
m_Pin_Value[24][1] = RES_K(100);
|
m_pin_value[24][1] = RES_K(100);
|
||||||
m_Pin_Value[24][0] = RES_K(1000); /*RES_M(1) infini sur Hector car non connectee*/
|
m_pin_value[24][0] = RES_K(1000); /* infinite on Hector due to lack of connection */
|
||||||
|
|
||||||
/* Capa OneShot*/
|
/* One-shot capacitor */
|
||||||
m_Pin_Value[23][0] = 1.0;
|
m_pin_value[23][0] = 1.0;
|
||||||
m_Pin_Value[23][1] = 0.0; /* Valeur Bidon sur Hector car mise au 5Volts sans capa*/
|
m_pin_value[23][1] = 0.0; /* bogus value on Hector, as +5V lacks a capacitor */
|
||||||
|
|
||||||
/* Enabled*/
|
/* Enabled*/
|
||||||
m_Pin_Value[9][0] = 0;
|
m_pin_value[9][0] = 0;
|
||||||
m_Pin_Value[9][1] = 1;
|
m_pin_value[9][1] = 1;
|
||||||
|
|
||||||
/* Volume*/
|
/* Volume*/
|
||||||
m_Pin_Value[11][0] = 128; /* Rapport 50% et 100% 128*/
|
m_pin_value[11][0] = 128;
|
||||||
m_Pin_Value[11][1] = 255; /* 255*/
|
m_pin_value[11][1] = 255;
|
||||||
|
|
||||||
/* Noise filter*/
|
/* Noise filter*/
|
||||||
m_Pin_Value[6][0] = CAP_U(0.390); /* 0.390*/
|
m_pin_value[6][0] = CAP_U(0.390); /* 0.390*/
|
||||||
m_Pin_Value[6][1] = CAP_U(08.60); /* 0.48*/
|
m_pin_value[6][1] = CAP_U(08.60); /* 0.48*/
|
||||||
|
|
||||||
/* Valeur corrige par rapport au schema :*/
|
/* Values from schematic */
|
||||||
m_Pin_Value[5][1] = RES_K(3.30 ) ; /* 330Kohm*/
|
m_pin_value[5][1] = RES_K(3.30 ) ; /* 330Kohm*/
|
||||||
m_Pin_Value[5][0] = RES_K(1.76 ) ; /* 76 Kohm*/
|
m_pin_value[5][0] = RES_K(1.76 ) ; /* 76 Kohm*/
|
||||||
|
|
||||||
/* Noise pas commande par le bus audio !*/
|
/* Noise is not controlled by the audio bus! */
|
||||||
/* Seule la valeur [0] est documentee !*/
|
/* Only value[0] is documented! */
|
||||||
m_Pin_Value[4][0] = RES_K(47) ; /* 47 K ohm*/
|
m_pin_value[4][0] = RES_K(47) ; /* 47 K ohm*/
|
||||||
m_Pin_Value[12][0] = RES_K(100); /* 100K ohm*/
|
m_pin_value[12][0] = RES_K(100); /* 100K ohm*/
|
||||||
m_Pin_Value[3][0] = 0 ; /* NC*/
|
m_pin_value[3][0] = 0 ; /* NC*/
|
||||||
|
|
||||||
/* Gestion du type d'enveloppe*/
|
/* Envelope-related */
|
||||||
m_Pin_Value[ 1][0] = 0;
|
m_pin_value[ 1][0] = 0;
|
||||||
m_Pin_Value[ 1][1] = 1;
|
m_pin_value[ 1][1] = 1;
|
||||||
|
|
||||||
m_Pin_Value[28][0] = 0;
|
m_pin_value[28][0] = 0;
|
||||||
m_Pin_Value[28][1] = 1;
|
m_pin_value[28][1] = 1;
|
||||||
|
|
||||||
/* Initialisation a 0 des pin du SN*/
|
/* SN pins initialized to 0 */
|
||||||
m_AU[0]=0;
|
m_au[0]=0;
|
||||||
m_AU[1]=0;
|
m_au[1]=0;
|
||||||
m_AU[2]=0;
|
m_au[2]=0;
|
||||||
m_AU[3]=0;
|
m_au[3]=0;
|
||||||
m_AU[4]=0;
|
m_au[4]=0;
|
||||||
m_AU[5]=0;
|
m_au[5]=0;
|
||||||
m_AU[6]=0;
|
m_au[6]=0;
|
||||||
m_AU[7]=0;
|
m_au[7]=0;
|
||||||
m_AU[8]=0;
|
m_au[8]=0;
|
||||||
m_AU[9]=0;
|
m_au[9]=0;
|
||||||
m_AU[10]=0;
|
m_au[10]=0;
|
||||||
m_AU[11]=0;
|
m_au[11]=0;
|
||||||
m_AU[12]=0;
|
m_au[12]=0;
|
||||||
m_AU[13]=0;
|
m_au[13]=0;
|
||||||
m_AU[14]=0;
|
m_au[14]=0;
|
||||||
m_AU[15]=0;
|
m_au[15]=0;
|
||||||
m_ValMixer = 0;
|
m_val_mixer = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void hec2hrp_state::Update_Sound(address_space &space, uint8_t data)
|
void hec2hrp_state::update_sound(address_space &space, uint8_t data)
|
||||||
{
|
{
|
||||||
/* keep device*/
|
/* MIXER */
|
||||||
/* MIXER*/
|
m_sn->mixer_a_w(((m_val_mixer & 0x04)==4) ? 1 : 0);
|
||||||
m_sn->mixer_a_w(((m_ValMixer & 0x04)==4) ? 1 : 0);
|
m_sn->mixer_b_w(((m_val_mixer & 0x01)==1) ? 1 : 0);
|
||||||
m_sn->mixer_b_w(((m_ValMixer & 0x01)==1) ? 1 : 0);
|
m_sn->mixer_c_w(((m_val_mixer & 0x02)==2) ? 1 : 0); /* Measured on HRX*/
|
||||||
m_sn->mixer_c_w(((m_ValMixer & 0x02)==2) ? 1 : 0);/* Revu selon mesure electronique sur HRX*/
|
|
||||||
|
|
||||||
/* VCO oscillateur*/
|
/* VCO oscillator */
|
||||||
if (m_AU[12]==1)
|
if (m_au[12]==1)
|
||||||
m_sn->vco_res_w(m_Pin_Value[18][m_AU[10]]/12.0); /* en non AU11*/
|
m_sn->vco_res_w(m_pin_value[18][m_au[10]]/12.0); /* no AU11 */
|
||||||
else
|
else
|
||||||
m_sn->vco_res_w(m_Pin_Value[18][m_AU[10]]); /* en non AU11*/
|
m_sn->vco_res_w(m_pin_value[18][m_au[10]]); /* no AU11 */
|
||||||
|
|
||||||
m_sn->vco_cap_w(m_Pin_Value[17][m_AU[2 ]]);
|
m_sn->vco_cap_w(m_pin_value[17][m_au[2 ]]);
|
||||||
m_sn->pitch_voltage_w(m_Pin_Value[19][m_AU[15]]);
|
m_sn->pitch_voltage_w(m_pin_value[19][m_au[15]]);
|
||||||
m_sn->vco_voltage_w(m_Pin_Value[16][m_AU[15]]);
|
m_sn->vco_voltage_w(m_pin_value[16][m_au[15]]);
|
||||||
m_sn->vco_w(m_Pin_Value[22][m_AU[12]]); /* VCO Select Ext/SLF*/
|
m_sn->vco_w(m_pin_value[22][m_au[12]]); /* VCO Select Ext/SLF */
|
||||||
|
|
||||||
/* SLF*/
|
/* SLF */
|
||||||
m_sn->slf_res_w(m_Pin_Value[20][m_AU[ 9]]);/*AU10*/
|
m_sn->slf_res_w(m_pin_value[20][m_au[ 9]]); /* AU10 */
|
||||||
m_sn->slf_cap_w(m_Pin_Value[21][m_AU[1 ]]);
|
m_sn->slf_cap_w(m_pin_value[21][m_au[1 ]]);
|
||||||
|
|
||||||
/* One Shot*/
|
/* One Shot */
|
||||||
m_sn->one_shot_res_w(m_Pin_Value[24][ 0]); /* NC*/
|
m_sn->one_shot_res_w(m_pin_value[24][ 0]); /* NC */
|
||||||
m_sn->one_shot_cap_w(m_Pin_Value[23][m_AU[13]]);
|
m_sn->one_shot_cap_w(m_pin_value[23][m_au[13]]);
|
||||||
|
|
||||||
/* Ampli value*/
|
/* amplitude value*/
|
||||||
m_sn->amplitude_res_w(m_Pin_Value[11][m_AU[5]]);
|
m_sn->amplitude_res_w(m_pin_value[11][m_au[5]]);
|
||||||
|
|
||||||
/* Attack / Decay*/
|
/* attack/decay */
|
||||||
m_sn->attack_res_w(m_Pin_Value[10][m_AU[ 8]]);
|
m_sn->attack_res_w(m_pin_value[10][m_au[ 8]]);
|
||||||
m_sn->decay_res_w(m_Pin_Value[7 ][m_AU[11]]);/*AU9*/
|
m_sn->decay_res_w(m_pin_value[7 ][m_au[11]]);
|
||||||
m_sn->attack_decay_cap_w(m_Pin_Value[8][m_AU[0]]);
|
m_sn->attack_decay_cap_w(m_pin_value[8][m_au[0]]);
|
||||||
|
|
||||||
/* Filtre*/
|
/* filter */
|
||||||
m_sn->noise_filter_res_w(m_Pin_Value[5][m_AU[4]]);
|
m_sn->noise_filter_res_w(m_pin_value[5][m_au[4]]);
|
||||||
m_sn->noise_filter_cap_w(m_Pin_Value[6][m_AU[3]]);
|
m_sn->noise_filter_cap_w(m_pin_value[6][m_au[3]]);
|
||||||
|
|
||||||
/* Clock Extern Noise*/
|
/* external noise clock */
|
||||||
m_sn->noise_clock_res_w(m_Pin_Value[4][0]); /* fix*/
|
m_sn->noise_clock_res_w(m_pin_value[4][0]);
|
||||||
m_sn->feedback_res_w(m_Pin_Value[12][0]); /*fix*/
|
m_sn->feedback_res_w(m_pin_value[12][0]);
|
||||||
|
|
||||||
/* Envelope*/
|
/* envelope */
|
||||||
m_sn->envelope_1_w(m_Pin_Value[1 ][m_AU[6]]);
|
m_sn->envelope_1_w(m_pin_value[1 ][m_au[6]]);
|
||||||
m_sn->envelope_2_w(m_Pin_Value[28][m_AU[7]]);
|
m_sn->envelope_2_w(m_pin_value[28][m_au[7]]);
|
||||||
|
|
||||||
/* En dernier on lance (ou pas !)*/
|
/* finally, enable */
|
||||||
m_sn->enable_w(m_Pin_Value[9][m_AU[14]]);
|
m_sn->enable_w(m_pin_value[9][m_au[14]]);
|
||||||
}
|
}
|
||||||
|
|
||||||
void hec2hrp_state::hector_reset(int hr, int with_D2 )
|
void hec2hrp_state::hector_reset(int hr, int with_d2)
|
||||||
{
|
{
|
||||||
// Initialization Hector
|
// Hector init
|
||||||
m_hector_flag_hr = hr;
|
m_hector_flag_hr = hr;
|
||||||
m_flag_clk = 0;
|
m_flag_clk = 0;
|
||||||
m_write_cassette = 0;
|
m_write_cassette = 0;
|
||||||
m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
||||||
|
|
||||||
// Initialization Disc II
|
// Disc II init
|
||||||
if (with_D2==1)
|
if (with_d2 == 1)
|
||||||
|
|
||||||
{
|
{
|
||||||
upd765a_device *fdc = machine().device<upd765a_device>("upd765");
|
upd765a_device *fdc = machine().device<upd765a_device>("upd765");
|
||||||
@ -787,12 +784,11 @@ void hec2hrp_state::hector_init()
|
|||||||
{
|
{
|
||||||
m_pot0 = m_pot1 = 0x40;
|
m_pot0 = m_pot1 = 0x40;
|
||||||
|
|
||||||
/* For Cassette synchro*/
|
/* for cassette sync */
|
||||||
m_Cassette_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hec2hrp_state::Callback_CK),this));
|
m_cassette_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hec2hrp_state::cassette_clock),this));
|
||||||
m_Cassette_timer->adjust(attotime::from_msec(100), 0, attotime::from_usec(64));/* => real synchro scan speed for 15,624Khz*/
|
m_cassette_timer->adjust(attotime::from_msec(100), 0, attotime::from_usec(64));/* => real sync scan speed for 15,624Khz*/
|
||||||
|
|
||||||
/* Sound sn76477*/
|
init_sn76477(); /* init R/C values */
|
||||||
Init_Value_SN76477_Hector(); /*init R/C value*/
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -824,7 +820,7 @@ MACHINE_CONFIG_START(hec2hrp_state::hector_audio)
|
|||||||
|
|
||||||
MACHINE_CONFIG_END
|
MACHINE_CONFIG_END
|
||||||
|
|
||||||
/* Lecteur de disquette DISK II pour les machines :
|
/* DISK II drive for:
|
||||||
Hector HRX
|
Hector HRX
|
||||||
Hector MX40c
|
Hector MX40c
|
||||||
Hector MX80c
|
Hector MX80c
|
||||||
@ -832,9 +828,9 @@ MACHINE_CONFIG_END
|
|||||||
JJStacino jj.stacino@aliceadsl.fr
|
JJStacino jj.stacino@aliceadsl.fr
|
||||||
|
|
||||||
15/02/2010 : Start of the disc2 project! JJStacino
|
15/02/2010 : Start of the disc2 project! JJStacino
|
||||||
26/09/2010 : first sending with bug2 (the first "dir" command finih with a crash of the Z80 disc II proc) JJStacino
|
26/09/2010 : first sending with bug2 (the first "dir" command terminates in a crash of the Z80 disc II processor) -JJStacino
|
||||||
01/11/2010 : first time ending boot sequence, probleme on the CP/M lauch JJStacino
|
01/11/2010 : first time boot sequence finishes, problem with CP/M launch -JJStacino
|
||||||
20/11/2010 : synchronization between uPD765 and Z80 are now OK, CP/M running! JJStacino
|
20/11/2010 : synchronization between uPD765 and Z80 is now OK, CP/M works! -JJStacino
|
||||||
28/11/2010 : Found at Bratislava that the disk writing with TRANS X: is NOT WORKING (the exchange Hector=>Disc2 ok)
|
28/11/2010 : Found at Bratislava that the disk writing with TRANS X: is NOT WORKING (the exchange Hector=>Disc2 ok)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -852,107 +848,102 @@ MACHINE_CONFIG_END
|
|||||||
* At this point the Z80 can read the RESULT in port 61h
|
* At this point the Z80 can read the RESULT in port 61h
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*****************************************************************************/
|
// Interrupt management
|
||||||
/**** Management of the interrupts (NMI and INT)between uPD765 and Z80 ******/
|
|
||||||
/*****************************************************************************/
|
|
||||||
|
|
||||||
/* upd765 INT is connected to interrupt of Z80 within a RNMI hardware authorization */
|
/* upd765 INT is connected to Z80 interrupt, with RNMI hardware authorization */
|
||||||
WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_interrupt )
|
WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_interrupt )
|
||||||
{
|
{
|
||||||
m_IRQ_current_state = state;
|
m_irq_current_state = state;
|
||||||
m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
|
m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state && m_hector_disc2_rnmi ? ASSERT_LINE : CLEAR_LINE);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* upd765 DRQ is connected to NMI of Z80 within a RNMI hardware authorization */
|
/* upd765 DRQ is connected to Z80 NMI, with RNMI hardware authorization */
|
||||||
WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_dma_irq )
|
WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_dma_irq )
|
||||||
{
|
{
|
||||||
m_NMI_current_state = state;
|
m_nmi_current_state = state;
|
||||||
m_disc2cpu->set_input_line(INPUT_LINE_NMI, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
|
m_disc2cpu->set_input_line(INPUT_LINE_NMI, state && m_hector_disc2_rnmi ? ASSERT_LINE : CLEAR_LINE);
|
||||||
}
|
}
|
||||||
|
|
||||||
// RESET the disc2 Unit !
|
|
||||||
void hec2hrp_state::hector_disc2_reset()
|
void hec2hrp_state::hector_disc2_reset()
|
||||||
{
|
{
|
||||||
// Initialization Disc2 unit
|
|
||||||
m_disc2cpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
m_disc2cpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
||||||
machine().device<upd765a_device>("upd765")->reset();
|
machine().device<upd765a_device>("upd765")->reset();
|
||||||
// Select ROM memory to cold restart
|
// Select ROM to cold restart
|
||||||
membank("bank3")->set_entry(DISCII_BANK_ROM);
|
membank("bank3")->set_entry(DISCII_BANK_ROM);
|
||||||
|
|
||||||
// Clear the Hardware's buffers
|
// Clear the Hardware's buffers
|
||||||
m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */
|
m_hector_disc2_data_r_ready = 0x0; /* =ff when PC2 = true and data is in read buffer (state->m_hector_disc2_data_read) */
|
||||||
m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */
|
m_hector_disc2_data_w_ready = 0x0; /* =ff when Disc 2 Port 40 has data in write buffer (state->m_hector_disc2_data_write) */
|
||||||
m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */
|
m_hector_disc2_data_read = 0; /* Data sent by Hector to Disc 2 when PC2=true */
|
||||||
m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */
|
m_hector_disc2_data_write = 0; /* Data sent by Disc 2 to Hector when Write Port I/O 40 */
|
||||||
m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */
|
m_hector_disc2_rnmi = 0; /* I/O 50 D5 state = authorization for INT / NMI */
|
||||||
m_IRQ_current_state=0; /* Clear the IRQ active request */
|
m_irq_current_state = 0; /* Clear the active IRQ request */
|
||||||
m_NMI_current_state=0; /* Clear the DMA active request */
|
m_nmi_current_state = 0; /* Clear the active DMA request */
|
||||||
}
|
}
|
||||||
|
|
||||||
/*****************************************************************************/
|
// Port handling for Z80 Disc II unit
|
||||||
/******************** Port handling of the Z80 Disc II unit *****************/
|
|
||||||
/*****************************************************************************/
|
|
||||||
READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r)
|
READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r)
|
||||||
{
|
{
|
||||||
/* Switch Disc 2 to RAM to let full RAM acces */
|
/* Switch Disc 2 to RAM */
|
||||||
membank("bank3")->set_entry(DISCII_BANK_RAM);
|
membank("bank3")->set_entry(DISCII_BANK_RAM);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w)
|
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w)
|
||||||
{
|
{
|
||||||
/* Switch Disc 2 to RAM to let full RAM acces */
|
/* Switch Disc 2 to RAM */
|
||||||
membank("bank3")->set_entry(DISCII_BANK_RAM);
|
membank("bank3")->set_entry(DISCII_BANK_RAM);
|
||||||
}
|
}
|
||||||
READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r)
|
READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r)
|
||||||
{
|
{
|
||||||
// You can implemente the 8251 chip communication here !
|
// TODO: Implement 8251 chip communication
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w)
|
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w)
|
||||||
{
|
{
|
||||||
// You can implemente the 8251 chip communication here !
|
// TODO: Implement 8251 chip communication
|
||||||
}
|
}
|
||||||
|
|
||||||
READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r)
|
READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r)
|
||||||
{
|
{
|
||||||
return m_hector_disc2_data_r_ready;
|
return m_hector_disc2_data_r_ready;
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w)
|
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w)
|
||||||
{
|
{
|
||||||
// Nothing here !
|
|
||||||
}
|
}
|
||||||
|
|
||||||
READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r)
|
READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r) /* Read data sent to Hector by Disc2 */
|
||||||
{
|
{
|
||||||
/* Read data send by Hector, by Disc2*/
|
m_hector_disc2_data_r_ready = 0x00;
|
||||||
m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/
|
return m_hector_disc2_data_read;
|
||||||
return m_hector_disc2_data_read; /* send the data !*/
|
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/
|
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data sent by Disc2 to Hector */
|
||||||
{
|
{
|
||||||
m_hector_disc2_data_write = data; /* Memorization data*/
|
m_hector_disc2_data_write = data;
|
||||||
m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/
|
m_hector_disc2_data_w_ready = 0x80;
|
||||||
}
|
}
|
||||||
|
|
||||||
READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r) /*Read memory info write ready*/
|
READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r)
|
||||||
{
|
{
|
||||||
return m_hector_disc2_data_w_ready;
|
return m_hector_disc2_data_w_ready;
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/
|
WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w)
|
||||||
{
|
{
|
||||||
upd765a_device *fdc = machine().device<upd765a_device>("upd765");
|
upd765a_device *fdc = machine().device<upd765a_device>("upd765");
|
||||||
|
|
||||||
/* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */
|
/* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */
|
||||||
machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A:
|
machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // FLoppy motor A
|
||||||
machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B:
|
machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Floppy motor B
|
||||||
|
|
||||||
/* Write bit TC uPD765 on D4 of port I/O 50 */
|
/* Write bit TC uPD765 on D4 of port I/O 50 */
|
||||||
fdc->tc_w(BIT(data, 4));
|
fdc->tc_w(BIT(data, 4));
|
||||||
|
|
||||||
|
|
||||||
/* Authorization interrupt and NMI with RNMI signal*/
|
/* allow interrupts by ANDing with RNMI signal */
|
||||||
m_hector_disc2_RNMI = BIT(data, 5);
|
m_hector_disc2_rnmi = BIT(data, 5);
|
||||||
m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_IRQ_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
|
m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_irq_current_state && m_hector_disc2_rnmi ? ASSERT_LINE : CLEAR_LINE);
|
||||||
m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_NMI_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
|
m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_nmi_current_state && m_hector_disc2_rnmi ? ASSERT_LINE : CLEAR_LINE);
|
||||||
}
|
}
|
||||||
|
@ -115,9 +115,6 @@ void hp48_state::rs232_start_recv_byte(uint8_t data)
|
|||||||
/* end of send event */
|
/* end of send event */
|
||||||
TIMER_CALLBACK_MEMBER(hp48_state::rs232_byte_sent_cb)
|
TIMER_CALLBACK_MEMBER(hp48_state::rs232_byte_sent_cb)
|
||||||
{
|
{
|
||||||
//device_image_interface *xmodem = dynamic_cast<device_image_interface *>(machine().device("rs232_x"));
|
|
||||||
//device_image_interface *kermit = dynamic_cast<device_image_interface *>(machine().device("rs232_k"));
|
|
||||||
|
|
||||||
LOG_SERIAL(("%f hp48_state::rs232_byte_sent_cb: end of send, data=%02x\n", machine().time().as_double(), param));
|
LOG_SERIAL(("%f hp48_state::rs232_byte_sent_cb: end of send, data=%02x\n", machine().time().as_double(), param));
|
||||||
|
|
||||||
m_io[0x12] &= ~3; /* clear byte sending and buffer full */
|
m_io[0x12] &= ~3; /* clear byte sending and buffer full */
|
||||||
@ -127,10 +124,6 @@ TIMER_CALLBACK_MEMBER(hp48_state::rs232_byte_sent_cb)
|
|||||||
{
|
{
|
||||||
pulse_irq(SATURN_IRQ_LINE);
|
pulse_irq(SATURN_IRQ_LINE);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* protocol action */
|
|
||||||
//if ( xmodem && xmodem->exists() ) xmodem_receive_byte( &xmodem->device(), param );
|
|
||||||
//else if ( kermit && kermit->exists() ) kermit_receive_byte( &kermit->device(), param );
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* CPU initiates a send event */
|
/* CPU initiates a send event */
|
||||||
@ -445,17 +438,8 @@ READ8_MEMBER(hp48_state::io_r)
|
|||||||
/* serial */
|
/* serial */
|
||||||
case 0x15:
|
case 0x15:
|
||||||
{
|
{
|
||||||
/* second nibble of received data */
|
|
||||||
|
|
||||||
//device_image_interface *xmodem = dynamic_cast<device_image_interface *>(machine().device("rs232_x"));
|
|
||||||
//device_image_interface *kermit = dynamic_cast<device_image_interface *>(machine().device("rs232_k"));
|
|
||||||
|
|
||||||
m_io[0x11] &= ~1; /* clear byte received */
|
m_io[0x11] &= ~1; /* clear byte received */
|
||||||
data = m_io[offset];
|
data = m_io[offset];
|
||||||
|
|
||||||
/* protocol action */
|
|
||||||
//if ( xmodem && xmodem->exists() ) xmodem_byte_transmitted( &xmodem->device() );
|
|
||||||
//else if ( kermit && kermit->exists() ) kermit_byte_transmitted( &kermit->device() );
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -26,9 +26,9 @@
|
|||||||
=> add BR/HR switching
|
=> add BR/HR switching
|
||||||
=> add bank switch for HRX
|
=> add bank switch for HRX
|
||||||
=> add device MX80c and bank switching for the ROM
|
=> add device MX80c and bank switching for the ROM
|
||||||
Importante note : the keyboard function add been piked from
|
Important note : the keyboard function has been taken from the
|
||||||
DChector project : http://dchector.free.fr/ made by DanielCoulom
|
DChector project : http://dchector.free.fr/ made by DanielCoulom
|
||||||
(thank's Daniel)
|
(thanks Daniel)
|
||||||
TODO : Add the cartridge function,
|
TODO : Add the cartridge function,
|
||||||
Adjust the one shot and A/D timing (sn76477)
|
Adjust the one shot and A/D timing (sn76477)
|
||||||
*/
|
*/
|
||||||
@ -39,50 +39,49 @@
|
|||||||
#include "screen.h"
|
#include "screen.h"
|
||||||
|
|
||||||
|
|
||||||
void hec2hrp_state::Init_Hector_Palette()
|
void hec2hrp_state::init_palette()
|
||||||
{
|
{
|
||||||
uint8_t *hector_color = m_hector_color;
|
m_hector_color[0] = 0; // black
|
||||||
// basic colors !
|
m_hector_color[1] = 1; // red
|
||||||
hector_color[0] = 0; // fond (noir)
|
m_hector_color[2] = 7; // white
|
||||||
hector_color[1] = 1; // HECTOR HRX (rouge)
|
m_hector_color[3] = 3; // yellow
|
||||||
hector_color[2] = 7; // Point interrogation (Blanc)
|
|
||||||
hector_color[3] = 3; // Ecriture de choix (jaune)
|
|
||||||
|
|
||||||
// Color initialisation : full lightning
|
// Full brightness
|
||||||
m_palette->set_pen_color( 0,rgb_t(000,000,000));//Noir
|
m_palette->set_pen_color( 0,rgb_t(000,000,000)); // black
|
||||||
m_palette->set_pen_color( 1,rgb_t(255,000,000));//Rouge
|
m_palette->set_pen_color( 1,rgb_t(255,000,000)); // red
|
||||||
m_palette->set_pen_color( 2,rgb_t(000,255,000));//Vert
|
m_palette->set_pen_color( 2,rgb_t(000,255,000)); // green
|
||||||
m_palette->set_pen_color( 3,rgb_t(255,255,000));//Jaune
|
m_palette->set_pen_color( 3,rgb_t(255,255,000)); // yellow
|
||||||
m_palette->set_pen_color( 4,rgb_t(000,000,255));//Bleu
|
m_palette->set_pen_color( 4,rgb_t(000,000,255)); // blue
|
||||||
m_palette->set_pen_color( 5,rgb_t(255,000,255));//Magneta
|
m_palette->set_pen_color( 5,rgb_t(255,000,255)); // magenta
|
||||||
m_palette->set_pen_color( 6,rgb_t(000,255,255));//Cyan
|
m_palette->set_pen_color( 6,rgb_t(000,255,255)); // cyan
|
||||||
m_palette->set_pen_color( 7,rgb_t(255,255,255));//Blanc
|
m_palette->set_pen_color( 7,rgb_t(255,255,255)); // white
|
||||||
// 1/2 lightning
|
|
||||||
|
|
||||||
m_palette->set_pen_color( 8,rgb_t(000,000,000));//Noir
|
// Half brightness
|
||||||
m_palette->set_pen_color( 9,rgb_t(128,000,000));//Rouge
|
m_palette->set_pen_color( 8,rgb_t(000,000,000)); // black
|
||||||
m_palette->set_pen_color( 10,rgb_t(000,128,000));//Vert
|
m_palette->set_pen_color( 9,rgb_t(128,000,000)); // red
|
||||||
m_palette->set_pen_color( 11,rgb_t(128,128,000));//Jaune
|
m_palette->set_pen_color( 10,rgb_t(000,128,000)); // green
|
||||||
m_palette->set_pen_color( 12,rgb_t(000,000,128));//Bleu
|
m_palette->set_pen_color( 11,rgb_t(128,128,000)); // yellow
|
||||||
m_palette->set_pen_color( 13,rgb_t(128,000,128));//Magneta
|
m_palette->set_pen_color( 12,rgb_t(000,000,128)); // blue
|
||||||
m_palette->set_pen_color( 14,rgb_t(000,128,128));//Cyan
|
m_palette->set_pen_color( 13,rgb_t(128,000,128)); // magenta
|
||||||
m_palette->set_pen_color( 15,rgb_t(128,128,128));//Blanc
|
m_palette->set_pen_color( 14,rgb_t(000,128,128)); // cyan
|
||||||
|
m_palette->set_pen_color( 15,rgb_t(128,128,128)); // white
|
||||||
}
|
}
|
||||||
|
|
||||||
void hec2hrp_state::hector_hr(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram)
|
void hec2hrp_state::hector_hr(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram)
|
||||||
{
|
{
|
||||||
uint8_t *hector_color = m_hector_color;
|
uint8_t *hector_color = m_hector_color;
|
||||||
uint8_t gfx,y;
|
int sy = 0;
|
||||||
uint16_t sy=0,ma=0,x;
|
int ma = 0;
|
||||||
for (y = 0; y <= ymax; y++) { //224
|
for (int y = 0; y <= ymax; y++)
|
||||||
uint16_t *p = &bitmap.pix16(sy++);
|
{
|
||||||
for (x = ma; x < ma + yram; x++) { // 64
|
uint16_t *pix = &bitmap.pix16(sy++);
|
||||||
gfx = *(page+x);
|
for (int x = ma; x < ma + yram; x++)
|
||||||
/* Display a scanline of a character (4 pixels !) */
|
{
|
||||||
*p++ = hector_color[(gfx >> 0) & 0x03];
|
uint8_t gfx = *(page + x);
|
||||||
*p++ = hector_color[(gfx >> 2) & 0x03];
|
*pix++ = hector_color[(gfx >> 0) & 0x03];
|
||||||
*p++ = hector_color[(gfx >> 4) & 0x03];
|
*pix++ = hector_color[(gfx >> 2) & 0x03];
|
||||||
*p++ = hector_color[(gfx >> 6) & 0x03];
|
*pix++ = hector_color[(gfx >> 4) & 0x03];
|
||||||
|
*pix++ = hector_color[(gfx >> 6) & 0x03];
|
||||||
}
|
}
|
||||||
ma+=yram;
|
ma+=yram;
|
||||||
}
|
}
|
||||||
@ -90,30 +89,31 @@ void hec2hrp_state::hector_hr(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int
|
|||||||
|
|
||||||
void hec2hrp_state::hector_80c(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram)
|
void hec2hrp_state::hector_80c(bitmap_ind16 &bitmap, uint8_t *page, int ymax, int yram)
|
||||||
{
|
{
|
||||||
uint8_t gfx,y;
|
int sy = 0;
|
||||||
uint16_t sy=0,ma=0,x;
|
int ma = 0;
|
||||||
for (y = 0; y <= ymax; y++) { //224
|
for (int y = 0; y <= ymax; y++)
|
||||||
uint16_t *p = &bitmap.pix16(sy++);
|
{
|
||||||
for (x = ma; x < ma + yram; x++) { // 64
|
uint16_t *pix = &bitmap.pix16(sy++);
|
||||||
gfx = *(page+x);
|
for (int x = ma; x < ma + yram; x++)
|
||||||
/* Display a scanline of a character (8 pixels !) */
|
{
|
||||||
*p++ = (gfx & 0x01) ? 7 : 0;
|
uint8_t gfx = *(page + x);
|
||||||
*p++ = (gfx & 0x02) ? 7 : 0;
|
*pix++ = (gfx & 0x01) ? 7 : 0;
|
||||||
*p++ = (gfx & 0x04) ? 7 : 0;
|
*pix++ = (gfx & 0x02) ? 7 : 0;
|
||||||
*p++ = (gfx & 0x08) ? 7 : 0;
|
*pix++ = (gfx & 0x04) ? 7 : 0;
|
||||||
*p++ = (gfx & 0x10) ? 7 : 0;
|
*pix++ = (gfx & 0x08) ? 7 : 0;
|
||||||
*p++ = (gfx & 0x20) ? 7 : 0;
|
*pix++ = (gfx & 0x10) ? 7 : 0;
|
||||||
*p++ = (gfx & 0x40) ? 7 : 0;
|
*pix++ = (gfx & 0x20) ? 7 : 0;
|
||||||
*p++ = (gfx & 0x80) ? 7 : 0;
|
*pix++ = (gfx & 0x40) ? 7 : 0;
|
||||||
|
*pix++ = (gfx & 0x80) ? 7 : 0;
|
||||||
}
|
}
|
||||||
ma+=yram;
|
ma += yram;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
VIDEO_START_MEMBER(hec2hrp_state,hec2hrp)
|
VIDEO_START_MEMBER(hec2hrp_state,hec2hrp)
|
||||||
{
|
{
|
||||||
Init_Hector_Palette();
|
init_palette();
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t hec2hrp_state::screen_update_hec2hrp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
uint32_t hec2hrp_state::screen_update_hec2hrp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||||
|
Loading…
Reference in New Issue
Block a user