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https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
mediagx: implement missing opcodes
but no disassembly because I don't understand it. swe1pb (at least) boots to CMOS checksum failure prompt now. I didn't trace further.
This commit is contained in:
Peter Ferrie
parent
019e37e938
commit
633ab90d90
@ -962,6 +962,7 @@ struct I386_CALL_GATE
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void pentium_cmovg_r32_rm32();
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void pentium_movnti_m16_r16();
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void pentium_movnti_m32_r32();
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void i386_cyrix_special();
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void i386_cyrix_unknown();
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void pentium_cmpxchg8b_m64();
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void pentium_movntq_m64_r64();
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@ -1004,6 +1005,12 @@ struct I386_CALL_GATE
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void mmx_paddw_r64_rm64();
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void mmx_paddd_r64_rm64();
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void mmx_emms();
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void i386_cyrix_svdc();
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void i386_cyrix_rsdc();
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void i386_cyrix_svldt();
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void i386_cyrix_rsldt();
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void i386_cyrix_svts();
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void i386_cyrix_rsts();
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void mmx_movd_r64_rm32();
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void mmx_movq_r64_rm64();
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void mmx_movd_rm32_r64();
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@ -329,6 +329,10 @@ const i386_device::X86_OPCODE i386_device::s_x86_opcode_table[] =
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{ 0x32, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_rdmsr, &i386_device::pentium_rdmsr, false},
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{ 0x38, OP_2BYTE|OP_PENTIUM, &i386_device::i386_decode_three_byte38, &i386_device::i386_decode_three_byte38,false},
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{ 0x3A, OP_2BYTE|OP_PENTIUM, &i386_device::i386_decode_three_byte3a, &i386_device::i386_decode_three_byte3a,false},
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{ 0x3A, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
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{ 0x3B, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
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{ 0x3C, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
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{ 0x3D, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
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{ 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false},
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{ 0x41, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, false},
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{ 0x42, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, false},
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@ -384,6 +388,12 @@ const i386_device::X86_OPCODE i386_device::s_x86_opcode_table[] =
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{ 0x75, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpeqw_r64_rm64, &i386_device::mmx_pcmpeqw_r64_rm64, false},
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{ 0x76, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpeqd_r64_rm64, &i386_device::mmx_pcmpeqd_r64_rm64, false},
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{ 0x77, OP_2BYTE|OP_MMX, &i386_device::mmx_emms, &i386_device::mmx_emms, false},
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{ 0x78, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_svdc, &i386_device::i386_cyrix_svdc, false},
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{ 0x79, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_rsdc, &i386_device::i386_cyrix_rsdc, false},
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{ 0x7a, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_svldt, &i386_device::i386_cyrix_svldt, false},
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{ 0x7b, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_rsldt, &i386_device::i386_cyrix_rsldt, false},
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{ 0x7c, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_svts, &i386_device::i386_cyrix_svts, false},
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{ 0x7d, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_rsts, &i386_device::i386_cyrix_rsts, false},
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{ 0x7e, OP_2BYTE|OP_MMX, &i386_device::mmx_movd_rm32_r64, &i386_device::mmx_movd_rm32_r64, false},
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{ 0x7f, OP_2BYTE|OP_MMX, &i386_device::mmx_movq_rm64_r64, &i386_device::mmx_movq_rm64_r64, false},
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{ 0x80, OP_2BYTE|OP_I386, &i386_device::i386_jo_rel16, &i386_device::i386_jo_rel32, false},
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@ -1062,6 +1062,18 @@ void i386_device::pentium_movnti_m32_r32() // Opcode 0f c3
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}
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}
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void i386_device::i386_cyrix_special() // Opcode 0x0f 3a-3d
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{
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/*
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0f 3a BB0_RESET (set BB0 pointer = base)
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0f 3b BB1_RESET (set BB1 pointer = base)
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0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax)
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0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx])
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*/
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CYCLES(1);
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}
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void i386_device::i386_cyrix_unknown() // Opcode 0x0f 74
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{
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logerror("Unemulated 0x0f 0x74 opcode called\n");
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@ -1970,6 +1982,262 @@ void i386_device::mmx_emms() // Opcode 0f 77
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CYCLES(1); // TODO: correct cycle count
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}
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void i386_device::i386_cyrix_svdc() // Opcode 0f 78
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{
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UINT8 modrm = FETCH();
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if( modrm < 0xc0 ) {
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UINT32 ea = GetEA(modrm,0);
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int index = (modrm >> 3) & 7;
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int limit;
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switch (index)
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{
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case 0:
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{
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index = ES;
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break;
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}
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case 2:
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{
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index = SS;
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break;
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}
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case 3:
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{
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index = DS;
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break;
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}
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case 4:
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{
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index = FS;
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break;
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}
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case 5:
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{
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index = GS;
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break;
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}
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default:
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{
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i386_trap(6, 0, 0);
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}
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}
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limit = m_sreg[index].limit;
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if (m_sreg[index].flags & 0x8000) //G bit
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{
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limit >>= 12;
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}
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WRITE16(ea + 0, limit);
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WRITE32(ea + 2, m_sreg[index].base);
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WRITE16(ea + 5, m_sreg[index].flags); //replace top 8 bits of base
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WRITE8(ea + 7, m_sreg[index].base >> 24);
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WRITE16(ea + 8, m_sreg[index].selector);
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} else {
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i386_trap(6, 0, 0);
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}
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CYCLES(1); // TODO: correct cycle count
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}
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void i386_device::i386_cyrix_rsdc() // Opcode 0f 79
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{
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UINT8 modrm = FETCH();
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if( modrm < 0xc0 ) {
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UINT32 ea = GetEA(modrm,0);
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int index = (modrm >> 3) & 7;
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UINT16 flags;
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UINT32 base;
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UINT32 limit;
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switch (index)
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{
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case 0:
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{
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index = ES;
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break;
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}
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case 2:
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{
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index = SS;
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break;
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}
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case 3:
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{
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index = DS;
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break;
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}
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case 4:
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{
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index = FS;
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break;
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}
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case 5:
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{
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index = GS;
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break;
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}
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default:
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{
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i386_trap(6, 0, 0);
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}
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}
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base = (READ32(ea + 2) & 0x00ffffff) | (READ8(ea + 7) << 24);
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flags = READ16(ea + 5);
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limit = READ16(ea + 0) | ((flags & 3) << 16);
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if (flags & 0x8000) //G bit
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{
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limit = (limit << 12) | 0xfff;
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}
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m_sreg[index].selector = READ16(ea + 8);
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m_sreg[index].flags = flags;
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m_sreg[index].base = base;
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m_sreg[index].limit = limit;
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} else {
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i386_trap(6, 0, 0);
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}
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CYCLES(1); // TODO: correct cycle count
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}
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void i386_device::i386_cyrix_svldt() // Opcode 0f 7a
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{
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if ( PROTECTED_MODE && !V8086_MODE )
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{
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UINT8 modrm = FETCH();
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if( !(modrm & 0xf8) ) {
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UINT32 ea = GetEA(modrm,0);
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UINT32 limit = m_ldtr.limit;
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if (m_ldtr.flags & 0x8000) //G bit
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{
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limit >>= 12;
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}
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WRITE16(ea + 0, limit);
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WRITE32(ea + 2, m_ldtr.base);
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WRITE16(ea + 5, m_ldtr.flags); //replace top 8 bits of base
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WRITE8(ea + 7, m_ldtr.base >> 24);
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WRITE16(ea + 8, m_ldtr.segment);
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} else {
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i386_trap(6, 0, 0);
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}
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} else {
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i386_trap(6, 0, 0);
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}
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CYCLES(1); // TODO: correct cycle count
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}
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void i386_device::i386_cyrix_rsldt() // Opcode 0f 7b
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{
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if ( PROTECTED_MODE && !V8086_MODE )
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{
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if(m_CPL)
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FAULT(FAULT_GP,0)
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UINT8 modrm = FETCH();
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if( !(modrm & 0xf8) ) {
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UINT32 ea = GetEA(modrm,0);
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UINT16 flags = READ16(ea + 5);
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UINT32 base = (READ32(ea + 2) | 0x00ffffff) | (READ8(ea + 7) << 24);
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UINT32 limit = READ16(ea + 0) | ((flags & 3) << 16);
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I386_SREG seg;
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if (flags & 0x8000) //G bit
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{
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limit = (limit << 12) | 0xfff;
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}
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memset(&seg, 0, sizeof(seg));
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seg.selector = READ16(ea + 8);
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i386_load_protected_mode_segment(&seg,NULL);
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m_ldtr.limit = limit;
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m_ldtr.base = base;
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m_ldtr.flags = flags;
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} else {
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i386_trap(6, 0, 0);
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}
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} else {
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i386_trap(6, 0, 0);
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}
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CYCLES(1); // TODO: correct cycle count
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}
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void i386_device::i386_cyrix_svts() // Opcode 0f 7c
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{
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if ( PROTECTED_MODE )
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{
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UINT8 modrm = FETCH();
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if( !(modrm & 0xf8) ) {
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UINT32 ea = GetEA(modrm,0);
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UINT32 limit = m_task.limit;
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if (m_task.flags & 0x8000) //G bit
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{
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limit >>= 12;
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}
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WRITE16(ea + 0, limit);
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WRITE32(ea + 2, m_task.base);
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WRITE16(ea + 5, m_task.flags); //replace top 8 bits of base
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WRITE8(ea + 7, m_task.base >> 24);
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WRITE16(ea + 8, m_task.segment);
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} else {
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i386_trap(6, 0, 0);
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}
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} else {
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i386_trap(6, 0, 0);
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}
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}
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void i386_device::i386_cyrix_rsts() // Opcode 0f 7d
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{
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if ( PROTECTED_MODE )
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{
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if(m_CPL)
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FAULT(FAULT_GP,0)
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UINT8 modrm = FETCH();
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if( !(modrm & 0xf8) ) {
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UINT32 ea = GetEA(modrm,0);
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UINT16 flags = READ16(ea + 5);
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UINT32 base = (READ32(ea + 2) | 0x00ffffff) | (READ8(ea + 7) << 24);
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UINT32 limit = READ16(ea + 0) | ((flags & 3) << 16);
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if (flags & 0x8000) //G bit
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{
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limit = (limit << 12) | 0xfff;
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}
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m_task.segment = READ16(ea + 8);
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m_task.limit = limit;
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m_task.base = base;
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m_task.flags = flags;
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} else {
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i386_trap(6, 0, 0);
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}
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} else {
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i386_trap(6, 0, 0);
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}
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CYCLES(1); // TODO: correct cycle count
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}
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void i386_device::mmx_movd_r64_rm32() // Opcode 0f 6e
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{
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MMXPROLOG();
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