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wd33c93: Style cleanup, nw

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This commit is contained in:
mooglyguy 2018-11-04 20:59:37 +01:00
parent 1a67854ebf
commit 6371127423
2 changed files with 302 additions and 310 deletions
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584
src/devices/machine/wd33c93.cpp
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@ -141,55 +141,55 @@
uint8_t wd33c93_device::getunit() uint8_t wd33c93_device::getunit()
{ {
/* return the destination unit id */ /* return the destination unit id */
return regs[WD_DESTINATION_ID] & SRCID_MASK; return m_regs[WD_DESTINATION_ID] & SRCID_MASK;
} }
void wd33c93_device::set_xfer_count( int count ) void wd33c93_device::set_xfer_count( int count )
{ {
/* set the count */ /* set the count */
regs[ WD_TRANSFER_COUNT_LSB ] = count & 0xff; m_regs[WD_TRANSFER_COUNT_LSB] = count & 0xff;
regs[ WD_TRANSFER_COUNT ] = ( count >> 8 ) & 0xff; m_regs[WD_TRANSFER_COUNT] = (count >> 8) & 0xff;
regs[ WD_TRANSFER_COUNT_MSB ] = ( count >> 16 ) & 0xff; m_regs[WD_TRANSFER_COUNT_MSB] = (count >> 16) & 0xff;
} }
int wd33c93_device::get_xfer_count() int wd33c93_device::get_xfer_count()
{ {
/* get the count */ /* get the count */
int count = regs[ WD_TRANSFER_COUNT_MSB ]; int count = m_regs[WD_TRANSFER_COUNT_MSB];
count <<= 8; count <<= 8;
count |= regs[ WD_TRANSFER_COUNT ]; count |= m_regs[WD_TRANSFER_COUNT];
count <<= 8; count <<= 8;
count |= regs[ WD_TRANSFER_COUNT_LSB ]; count |= m_regs[WD_TRANSFER_COUNT_LSB];
return count; return count;
} }
void wd33c93_device::complete_immediate( int status ) void wd33c93_device::complete_immediate(int status)
{ {
/* reset our timer */ /* reset our timer */
cmd_timer->reset(); m_cmd_timer->reset();
/* set the new status */ /* set the new status */
regs[WD_SCSI_STATUS] = status & 0xff; m_regs[WD_SCSI_STATUS] = status & 0xff;
/* set interrupt pending */ /* set interrupt pending */
regs[WD_AUXILIARY_STATUS] |= ASR_INT; m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
/* check for error conditions */ /* check for error conditions */
if ( get_xfer_count() > 0 ) if (get_xfer_count() > 0)
{ {
/* set data buffer ready */ /* set data buffer ready */
regs[WD_AUXILIARY_STATUS] |= ASR_DBR; m_regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
} }
else else
{ {
/* clear data buffer ready */ /* clear data buffer ready */
regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR; m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
} }
/* clear command in progress and bus busy */ /* clear command in progress and bus busy */
regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY); m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
/* if we have a callback, call it */ /* if we have a callback, call it */
if (!m_irq_cb.isnull()) if (!m_irq_cb.isnull())
@ -200,43 +200,43 @@ void wd33c93_device::complete_immediate( int status )
void wd33c93_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr) void wd33c93_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
{ {
switch( tid ) switch (tid)
{ {
case 0: case 0:
complete_immediate( param ); complete_immediate(param);
break; break;
case 1: case 1:
complete_immediate(CSR_SRV_REQ | busphase); complete_immediate(CSR_SRV_REQ | m_busphase);
break; break;
case 2: case 2:
regs[WD_AUXILIARY_STATUS] &= ~ASR_CIP; m_regs[WD_AUXILIARY_STATUS] &= ~ASR_CIP;
break; break;
} }
} }
void wd33c93_device::complete_cmd( uint8_t status ) void wd33c93_device::complete_cmd(uint8_t status)
{ {
/* fire off a timer to complete the command */ /* fire off a timer to complete the command */
cmd_timer->adjust( attotime::from_usec(1), status ); m_cmd_timer->adjust(attotime::from_usec(1), status);
} }
/* command handlers */ /* command handlers */
void wd33c93_device::unimplemented_cmd() void wd33c93_device::unimplemented_cmd()
{ {
logerror( "%s:Unimplemented SCSI controller command: %02x\n", machine().describe_context(), regs[WD_COMMAND] ); logerror("%s:Unimplemented SCSI controller command: %02x\n", machine().describe_context(), m_regs[WD_COMMAND]);
/* complete the command */ /* complete the command */
complete_cmd( CSR_INVALID ); complete_cmd(CSR_INVALID);
} }
void wd33c93_device::invalid_cmd() void wd33c93_device::invalid_cmd()
{ {
logerror( "%s:Invalid SCSI controller command: %02x\n", machine().describe_context(), regs[WD_COMMAND] ); logerror("%s:Invalid SCSI controller command: %02x\n", machine().describe_context(), m_regs[WD_COMMAND]);
/* complete the command */ /* complete the command */
complete_cmd( CSR_INVALID ); complete_cmd(CSR_INVALID);
} }
void wd33c93_device::reset_cmd() void wd33c93_device::reset_cmd()
@ -244,13 +244,13 @@ void wd33c93_device::reset_cmd()
int advanced = 0; int advanced = 0;
/* see if it wants us to reset with advanced features */ /* see if it wants us to reset with advanced features */
if ( regs[WD_OWN_ID] & OWNID_EAF ) if (m_regs[WD_OWN_ID] & OWNID_EAF)
{ {
advanced = 1; advanced = 1;
} }
/* clear out all registers */ /* clear out all registers */
memset( regs, 0, sizeof( regs ) ); memset(m_regs, 0, sizeof(m_regs));
/* complete the command */ /* complete the command */
complete_cmd(advanced ? CSR_RESET_AF : CSR_RESET); complete_cmd(advanced ? CSR_RESET_AF : CSR_RESET);
@ -265,7 +265,7 @@ void wd33c93_device::abort_cmd()
void wd33c93_device::disconnect_cmd() void wd33c93_device::disconnect_cmd()
{ {
/* complete the command */ /* complete the command */
regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY); m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
} }
void wd33c93_device::select_cmd() void wd33c93_device::select_cmd()
@ -280,19 +280,19 @@ void wd33c93_device::select_cmd()
newstatus = CSR_SELECT; newstatus = CSR_SELECT;
/* determine the next bus phase depending on the command */ /* determine the next bus phase depending on the command */
if ( (regs[WD_COMMAND] & 0x7f) == WD_CMD_SEL_ATN ) if ((m_regs[WD_COMMAND] & 0x7f) == WD_CMD_SEL_ATN)
{ {
/* /ATN asserted during select: Move to Message Out Phase to read identify */ /* /ATN asserted during select: Move to Message Out Phase to read identify */
busphase = PHS_MESS_OUT; m_busphase = PHS_MESS_OUT;
} }
else else
{ {
/* No /ATN asserted: Move to Command Phase */ /* No /ATN asserted: Move to Command Phase */
busphase = PHS_COMMAND; m_busphase = PHS_COMMAND;
} }
/* queue up a service request out in the future */ /* queue up a service request out in the future */
service_req_timer->adjust( attotime::from_usec(50) ); m_service_req_timer->adjust( attotime::from_usec(50) );
} }
else else
{ {
@ -312,57 +312,57 @@ void wd33c93_device::selectxfer_cmd()
/* see if we can select that device */ /* see if we can select that device */
if (select(unit)) if (select(unit))
{ {
if ( regs[WD_COMMAND_PHASE] < 0x45 ) if (m_regs[WD_COMMAND_PHASE] < 0x45)
{ {
/* device is available */ /* device is available */
int phase;
/* do the request */ /* do the request */
send_command(&regs[WD_CDB_1], 12); send_command(&m_regs[WD_CDB_1], 12);
phase = get_phase(); int phase = get_phase();
/* set transfer count */ /* set transfer count */
if ( get_xfer_count() > TEMP_INPUT_LEN ) if (get_xfer_count() > TEMP_INPUT_LEN)
{ {
logerror( "WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", get_xfer_count() ); logerror("WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", get_xfer_count());
set_xfer_count( TEMP_INPUT_LEN ); set_xfer_count(TEMP_INPUT_LEN);
} }
switch( phase ) switch (phase)
{ {
case SCSI_PHASE_DATAIN: case SCSI_PHASE_DATAIN:
read_pending = 1; m_read_pending = true;
break; break;
} }
} }
if ( read_pending ) if (m_read_pending)
{ {
int len = TEMP_INPUT_LEN; int len = TEMP_INPUT_LEN;
if ( get_xfer_count() < len ) len = get_xfer_count(); if (get_xfer_count() < len)
len = get_xfer_count();
memset( &temp_input[0], 0, TEMP_INPUT_LEN ); memset(&m_temp_input[0], 0, TEMP_INPUT_LEN);
read_data(&temp_input[0], len); read_data(&m_temp_input[0], len);
temp_input_pos = 0; m_temp_input_pos = 0;
read_pending = 0; m_read_pending = false;
} }
regs[WD_TARGET_LUN] = 0; m_regs[WD_TARGET_LUN] = 0;
regs[WD_CONTROL] |= CTRL_EDI; m_regs[WD_CONTROL] |= CTRL_EDI;
regs[WD_COMMAND_PHASE] = 0x60; m_regs[WD_COMMAND_PHASE] = 0x60;
/* signal transfer ready */ /* signal transfer ready */
newstatus = CSR_SEL_XFER_DONE; newstatus = CSR_SEL_XFER_DONE;
/* if allowed disconnect, queue a service request */ /* if allowed disconnect, queue a service request */
if ( identify & 0x40 ) if (m_identify & 0x40)
{ {
/* queue disconnect message in */ /* queue disconnect message in */
busphase = PHS_MESS_IN; m_busphase = PHS_MESS_IN;
/* queue up a service request out in the future */ /* queue up a service request out in the future */
service_req_timer->adjust( attotime::from_usec(50) ); m_service_req_timer->adjust(attotime::from_usec(50));
} }
} }
else else
@ -370,7 +370,7 @@ void wd33c93_device::selectxfer_cmd()
/* device is not available */ /* device is not available */
newstatus = CSR_TIMEOUT; newstatus = CSR_TIMEOUT;
set_xfer_count( 0 ); set_xfer_count(0);
} }
/* complete the command */ /* complete the command */
@ -379,29 +379,29 @@ void wd33c93_device::selectxfer_cmd()
void wd33c93_device::negate_ack() void wd33c93_device::negate_ack()
{ {
logerror( "WD33C93: ACK Negated\n" ); logerror("WD33C93: ACK Negated\n");
/* complete the command */ /* complete the command */
regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY); m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
} }
void wd33c93_device::xferinfo_cmd() void wd33c93_device::xferinfo_cmd()
{ {
/* make the buffer available right away */ /* make the buffer available right away */
regs[WD_AUXILIARY_STATUS] |= ASR_DBR; m_regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
regs[WD_AUXILIARY_STATUS] |= ASR_CIP; m_regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
/* the command will be completed once the data is transferred */ /* the command will be completed once the data is transferred */
deassert_cip_timer->adjust( attotime::from_msec(1) ); m_deassert_cip_timer->adjust(attotime::from_msec(1));
} }
/* Handle pending commands */ /* Handle pending commands */
void wd33c93_device::dispatch_command() void wd33c93_device::dispatch_command()
{ {
/* get the command */ /* get the command */
uint8_t cmd = regs[WD_COMMAND] & 0x7f; uint8_t cmd = m_regs[WD_COMMAND] & 0x7f;
switch(cmd) switch (cmd)
{ {
case WD_CMD_RESET: case WD_CMD_RESET:
reset_cmd(); reset_cmd();
@ -463,261 +463,253 @@ void wd33c93_device::dispatch_command()
WRITE8_MEMBER(wd33c93_device::write) WRITE8_MEMBER(wd33c93_device::write)
{ {
switch( offset ) switch (offset)
{ {
case 0: case 0:
{
/* update register select */
m_sasr = data & 0x1f;
}
break;
case 1:
{
LOG("WD33C93: %s - Write REG=%02x, data = %02x\n", machine().describe_context(), m_sasr, data);
/* update the register */
m_regs[m_sasr] = data;
/* if we receive a command, schedule to process it */
if (m_sasr == WD_COMMAND)
{ {
/* update register select */ LOG( "WDC33C93: %s - Executing command %08x - unit %d\n", machine().describe_context(), data, getunit() );
sasr = data & 0x1f;
/* signal we're processing it */
m_regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
/* process the command */
dispatch_command();
} }
break; else if (m_sasr == WD_CDB_1)
case 1:
{ {
LOG( "WD33C93: %s - Write REG=%02x, data = %02x\n", machine().describe_context(), sasr, data ); m_regs[WD_COMMAND_PHASE] = 0;
}
else if (m_sasr == WD_DATA)
{
/* if data was written, and we have a count, send to device */
int count = get_xfer_count();
/* update the register */ if (m_regs[WD_COMMAND] & 0x80)
regs[sasr] = data; count = 1;
/* if we receive a command, schedule to process it */ if (count-- > 0)
if ( sasr == WD_COMMAND )
{ {
LOG( "WDC33C93: %s - Executing command %08x - unit %d\n", machine().describe_context(), data, getunit() ); /* write to FIFO */
if (m_fifo_pos < FIFO_SIZE)
/* signal we're processing it */
regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
/* process the command */
dispatch_command();
}
else if ( sasr == WD_CDB_1 )
{
regs[WD_COMMAND_PHASE] = 0;
}
else if ( sasr == WD_DATA )
{
/* if data was written, and we have a count, send to device */
int count = get_xfer_count();
if ( regs[WD_COMMAND] & 0x80 )
count = 1;
if ( count-- > 0 )
{ {
/* write to FIFO */ m_fifo[m_fifo_pos++] = data;
if ( fifo_pos < FIFO_SIZE ) }
/* update count */
set_xfer_count(count);
/* if we're done with the write, see where we're at */
if (count == 0)
{
m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
switch (m_busphase)
{ {
fifo[fifo_pos++] = data; case PHS_MESS_OUT:
}
/* update count */
set_xfer_count( count );
/* if we're done with the write, see where we're at */
if ( count == 0 )
{
regs[WD_AUXILIARY_STATUS] |= ASR_INT;
regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
switch( busphase )
{ {
case PHS_MESS_OUT: /* reset fifo */
{ m_fifo_pos = 0;
/* reset fifo */
fifo_pos = 0;
/* Message out phase. Data is probably SCSI Identify. Move to command phase. */ /* Message out phase. Data is probably SCSI Identify. Move to command phase. */
busphase = PHS_COMMAND; m_busphase = PHS_COMMAND;
identify = fifo[0]; m_identify = m_fifo[0];
}
break;
case PHS_COMMAND:
{
int xfercount;
int phase;
/* Execute the command. Depending on the command, we'll move to data in or out */
send_command(&fifo[0], 12);
xfercount = get_length();
phase = get_phase();
/* reset fifo */
fifo_pos = 0;
/* set the new count */
set_xfer_count( xfercount );
switch( phase )
{
case SCSI_PHASE_STATUS:
busphase = PHS_STATUS;
break;
case SCSI_PHASE_DATAIN:
busphase = PHS_DATA_IN;
read_pending = 1;
break;
case SCSI_PHASE_DATAOUT:
busphase = PHS_DATA_OUT;
break;
}
}
break;
case PHS_DATA_OUT:
{
/* write data out to device */
write_data(fifo, fifo_pos);
/* reset fifo */
fifo_pos = 0;
/* move to status phase */
busphase = PHS_STATUS;
}
break;
} }
break;
/* complete the command */ case PHS_COMMAND:
complete_immediate(CSR_XFER_DONE | busphase); {
/* Execute the command. Depending on the command, we'll move to data in or out */
send_command(&m_fifo[0], 12);
int xfercount = get_length();
int phase = get_phase();
/* reset fifo */
m_fifo_pos = 0;
/* set the new count */
set_xfer_count(xfercount);
switch (phase)
{
case SCSI_PHASE_STATUS:
m_busphase = PHS_STATUS;
break;
case SCSI_PHASE_DATAIN:
m_busphase = PHS_DATA_IN;
m_read_pending = true;
break;
case SCSI_PHASE_DATAOUT:
m_busphase = PHS_DATA_OUT;
break;
}
}
break;
case PHS_DATA_OUT:
{
/* write data out to device */
write_data(m_fifo, m_fifo_pos);
/* reset fifo */
m_fifo_pos = 0;
/* move to status phase */
m_busphase = PHS_STATUS;
}
break;
} }
}
else /* complete the command */
{ complete_immediate(CSR_XFER_DONE | m_busphase);
logerror( "WD33C93: Sending data to device with transfer count = 0!. Ignoring...\n" );
} }
} }
else
/* auto-increment register select if not on special registers */
if ( sasr != WD_COMMAND && sasr != WD_DATA && sasr != WD_AUXILIARY_STATUS )
{ {
sasr = ( sasr + 1 ) & 0x1f; logerror("WD33C93: Sending data to device with transfer count = 0!. Ignoring...\n");
} }
} }
break;
default: /* auto-increment register select if not on special registers */
if (m_sasr != WD_COMMAND && m_sasr != WD_DATA && m_sasr != WD_AUXILIARY_STATUS)
{ {
logerror( "WD33C93: Write to invalid offset %d (data=%02x)\n", offset, data ); m_sasr = (m_sasr + 1) & 0x1f;
} }
break; }
break;
default:
{
logerror( "WD33C93: Write to invalid offset %d (data=%02x)\n", offset, data );
}
break;
} }
} }
READ8_MEMBER(wd33c93_device::read) READ8_MEMBER(wd33c93_device::read)
{ {
switch( offset ) switch (offset)
{ {
case 0: case 0:
{ /* read aux status */
/* read aux status */ return m_regs[WD_AUXILIARY_STATUS];
return regs[WD_AUXILIARY_STATUS];
}
case 1: case 1:
{
/* if reading status, clear irq flag */
if (m_sasr == WD_SCSI_STATUS)
{ {
uint8_t ret; m_regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
/* if reading status, clear irq flag */ if (!m_irq_cb.isnull())
if ( sasr == WD_SCSI_STATUS )
{ {
regs[WD_AUXILIARY_STATUS] &= ~ASR_INT; m_irq_cb(0);
if (!m_irq_cb.isnull())
{
m_irq_cb(0);
}
LOG( "WD33C93: %s - Status read (%02x)\n", machine().describe_context(), regs[WD_SCSI_STATUS] );
} }
else if ( sasr == WD_DATA )
LOG("WD33C93: %s - Status read (%02x)\n", machine().describe_context(), m_regs[WD_SCSI_STATUS]);
}
else if (m_sasr == WD_DATA)
{
/* we're going to be doing synchronous reads */
/* get the transfer count */
int count = get_xfer_count();
/* initialize the return value */
m_regs[WD_DATA] = 0;
if (count <= 0 && m_busphase == PHS_MESS_IN)
{ {
/* we're going to be doing synchronous reads */ /* move to disconnect */
complete_cmd(CSR_DISC);
}
else if (count == 1 && m_busphase == PHS_STATUS)
{
/* update the count */
set_xfer_count(0);
/* get the transfer count */ /* move to message in phase */
int count = get_xfer_count(); m_busphase = PHS_MESS_IN;
/* initialize the return value */ /* complete the command */
regs[WD_DATA] = 0; complete_cmd(CSR_XFER_DONE | m_busphase);
}
if ( count <= 0 && busphase == PHS_MESS_IN ) else if (count-- > 0) /* make sure we still have data to send */
{
if (m_read_pending)
{ {
/* move to disconnect */ int len = TEMP_INPUT_LEN;
complete_cmd(CSR_DISC);
if ((count + 1) < len )
len = count + 1;
read_data(&m_temp_input[0], len);
m_temp_input_pos = 0;
m_read_pending = false;
} }
else if ( count == 1 && busphase == PHS_STATUS )
{
/* update the count */
set_xfer_count( 0 );
/* move to message in phase */ m_regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
busphase = PHS_MESS_IN;
/* complete the command */ /* read in one byte */
complete_cmd(CSR_XFER_DONE | busphase); if (m_temp_input_pos < TEMP_INPUT_LEN)
} m_regs[WD_DATA] = m_temp_input[m_temp_input_pos++];
else if ( count-- > 0 ) /* make sure we still have data to send */
/* update the count */
set_xfer_count(count);
/* transfer finished, see where we're at */
if (count == 0)
{ {
if ( read_pending ) if (m_regs[WD_COMMAND_PHASE] != 0x60)
{ {
int len = TEMP_INPUT_LEN; /* move to status phase */
m_busphase = PHS_STATUS;
if ( (count+1) < len ) len = count+1; /* complete the command */
read_data(&temp_input[0], len); complete_cmd(CSR_XFER_DONE | m_busphase);
temp_input_pos = 0;
read_pending = 0;
} }
else
regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
/* read in one byte */
if ( temp_input_pos < TEMP_INPUT_LEN )
regs[WD_DATA] = temp_input[temp_input_pos++];
/* update the count */
set_xfer_count( count );
/* transfer finished, see where we're at */
if ( count == 0 )
{ {
if ( regs[WD_COMMAND_PHASE] != 0x60 ) m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
{ m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
/* move to status phase */
busphase = PHS_STATUS;
/* complete the command */
complete_cmd(CSR_XFER_DONE | busphase);
}
else
{
regs[WD_AUXILIARY_STATUS] |= ASR_INT;
regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
}
} }
} }
} }
LOG( "WD33C93: %s - Data read (%02x)\n", machine().describe_context(), regs[WD_DATA] );
/* get the register value */
ret = regs[sasr];
/* auto-increment register select if not on special registers */
if ( sasr != WD_COMMAND && sasr != WD_DATA && sasr != WD_AUXILIARY_STATUS )
{
sasr = ( sasr + 1 ) & 0x1f;
}
return ret;
} }
default: LOG("WD33C93: %s - Data read (%02x)\n", machine().describe_context(), m_regs[WD_DATA]);
/* get the register value */
uint8_t ret = m_regs[m_sasr];
/* auto-increment register select if not on special registers */
if (m_sasr != WD_COMMAND && m_sasr != WD_DATA && m_sasr != WD_AUXILIARY_STATUS)
{ {
logerror( "WD33C93: Read from invalid offset %d\n", offset ); m_sasr = (m_sasr + 1) & 0x1f;
} }
return ret;
}
default:
logerror("WD33C93: Read from invalid offset %d\n", offset);
break; break;
} }
@ -734,70 +726,70 @@ void wd33c93_device::device_start()
{ {
legacy_scsi_host_adapter::device_start(); legacy_scsi_host_adapter::device_start();
memset(regs, 0, sizeof(regs)); memset(m_regs, 0, sizeof(m_regs));
memset(fifo, 0, sizeof(fifo)); memset(m_fifo, 0, sizeof(m_fifo));
memset(temp_input, 0, sizeof(temp_input)); memset(m_temp_input, 0, sizeof(m_temp_input));
sasr = 0; m_sasr = 0;
fifo_pos = 0; m_fifo_pos = 0;
temp_input_pos = 0; m_temp_input_pos = 0;
busphase = 0; m_busphase = 0;
identify = 0; m_identify = 0;
read_pending = 0; m_read_pending = 0;
m_irq_cb.resolve(); m_irq_cb.resolve();
/* allocate a timer for commands */ /* allocate a timer for commands */
cmd_timer = timer_alloc(0); m_cmd_timer = timer_alloc(0);
service_req_timer = timer_alloc(1); m_service_req_timer = timer_alloc(1);
deassert_cip_timer = timer_alloc(2); m_deassert_cip_timer = timer_alloc(2);
save_item( NAME( sasr ) ); save_item(NAME(m_sasr));
save_item( NAME( regs ) ); save_item(NAME(m_regs));
save_item( NAME( fifo ) ); save_item(NAME(m_fifo));
save_item( NAME( fifo_pos ) ); save_item(NAME(m_fifo_pos));
save_item( NAME( temp_input ) ); save_item(NAME(m_temp_input));
save_item( NAME( temp_input_pos ) ); save_item(NAME(m_temp_input_pos));
save_item( NAME( busphase ) ); save_item(NAME(m_busphase));
save_item( NAME( identify ) ); save_item(NAME(m_identify));
save_item( NAME( read_pending ) ); save_item(NAME(m_read_pending));
} }
void wd33c93_device::dma_read_data( int bytes, uint8_t *pData ) void wd33c93_device::dma_read_data(int bytes, uint8_t *data)
{ {
int len = bytes; int len = bytes;
if ( len >= get_xfer_count() ) if (len >= get_xfer_count())
len = get_xfer_count(); len = get_xfer_count();
if ( len == 0 ) if (len == 0)
return; return;
if ( (temp_input_pos+len) >= TEMP_INPUT_LEN ) if ((m_temp_input_pos + len) >= TEMP_INPUT_LEN)
{ {
logerror( "Reading past end of buffer, increase TEMP_INPUT_LEN size\n" ); logerror("Reading past end of buffer, increase TEMP_INPUT_LEN size\n");
len = TEMP_INPUT_LEN - len; len = TEMP_INPUT_LEN - len;
} }
assert(len); assert(len);
memcpy( pData, &temp_input[temp_input_pos], len ); memcpy(data, &m_temp_input[m_temp_input_pos], len);
temp_input_pos += len; m_temp_input_pos += len;
len = get_xfer_count() - len; len = get_xfer_count() - len;
set_xfer_count(len); set_xfer_count(len);
} }
void wd33c93_device::dma_write_data(int bytes, uint8_t *pData) void wd33c93_device::dma_write_data(int bytes, uint8_t *data)
{ {
write_data(pData, bytes); write_data(data, bytes);
} }
void wd33c93_device::clear_dma() void wd33c93_device::clear_dma()
{ {
/* indicate DMA completed by clearing the transfer count */ /* indicate DMA completed by clearing the transfer count */
set_xfer_count(0); set_xfer_count(0);
regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR; m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
} }
int wd33c93_device::get_dma_count() int wd33c93_device::get_dma_count()

28
src/devices/machine/wd33c93.h
View File

@ -28,8 +28,8 @@ public:
DECLARE_READ8_MEMBER(read); DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write); DECLARE_WRITE8_MEMBER(write);
void dma_read_data( int bytes, uint8_t *pData ); void dma_read_data(int bytes, uint8_t *data);
void dma_write_data(int bytes, uint8_t *pData); void dma_write_data(int bytes, uint8_t *data);
void clear_dma(); void clear_dma();
int get_dma_count(); int get_dma_count();
@ -91,18 +91,18 @@ private:
void xferinfo_cmd(); void xferinfo_cmd();
void dispatch_command(); void dispatch_command();
uint8_t sasr; uint8_t m_sasr;
uint8_t regs[WD_AUXILIARY_STATUS+1]; uint8_t m_regs[WD_AUXILIARY_STATUS+1];
uint8_t fifo[FIFO_SIZE]; uint8_t m_fifo[FIFO_SIZE];
int fifo_pos; int m_fifo_pos;
uint8_t temp_input[TEMP_INPUT_LEN]; uint8_t m_temp_input[TEMP_INPUT_LEN];
int temp_input_pos; int m_temp_input_pos;
uint8_t busphase; uint8_t m_busphase;
uint8_t identify; uint8_t m_identify;
int read_pending; bool m_read_pending;
emu_timer *cmd_timer; emu_timer *m_cmd_timer;
emu_timer *service_req_timer; emu_timer *m_service_req_timer;
emu_timer *deassert_cip_timer; emu_timer *m_deassert_cip_timer;
devcb_write_line m_irq_cb; /* irq callback */ devcb_write_line m_irq_cb; /* irq callback */
}; };