mirror of
https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
wd33c93: Style cleanup, nw
This commit is contained in:
mooglyguy
parent
1a67854ebf
commit
6371127423
@ -141,55 +141,55 @@
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uint8_t wd33c93_device::getunit()
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{
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/* return the destination unit id */
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return regs[WD_DESTINATION_ID] & SRCID_MASK;
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return m_regs[WD_DESTINATION_ID] & SRCID_MASK;
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}
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void wd33c93_device::set_xfer_count( int count )
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{
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/* set the count */
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regs[ WD_TRANSFER_COUNT_LSB ] = count & 0xff;
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regs[ WD_TRANSFER_COUNT ] = ( count >> 8 ) & 0xff;
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regs[ WD_TRANSFER_COUNT_MSB ] = ( count >> 16 ) & 0xff;
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m_regs[WD_TRANSFER_COUNT_LSB] = count & 0xff;
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m_regs[WD_TRANSFER_COUNT] = (count >> 8) & 0xff;
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m_regs[WD_TRANSFER_COUNT_MSB] = (count >> 16) & 0xff;
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}
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int wd33c93_device::get_xfer_count()
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{
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/* get the count */
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int count = regs[ WD_TRANSFER_COUNT_MSB ];
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int count = m_regs[WD_TRANSFER_COUNT_MSB];
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count <<= 8;
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count |= regs[ WD_TRANSFER_COUNT ];
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count |= m_regs[WD_TRANSFER_COUNT];
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count <<= 8;
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count |= regs[ WD_TRANSFER_COUNT_LSB ];
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count |= m_regs[WD_TRANSFER_COUNT_LSB];
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return count;
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}
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void wd33c93_device::complete_immediate( int status )
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void wd33c93_device::complete_immediate(int status)
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{
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/* reset our timer */
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cmd_timer->reset();
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m_cmd_timer->reset();
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/* set the new status */
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regs[WD_SCSI_STATUS] = status & 0xff;
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m_regs[WD_SCSI_STATUS] = status & 0xff;
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/* set interrupt pending */
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regs[WD_AUXILIARY_STATUS] |= ASR_INT;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
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/* check for error conditions */
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if ( get_xfer_count() > 0 )
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if (get_xfer_count() > 0)
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{
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/* set data buffer ready */
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regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
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}
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else
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{
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/* clear data buffer ready */
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regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
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m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
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}
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/* clear command in progress and bus busy */
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regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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/* if we have a callback, call it */
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if (!m_irq_cb.isnull())
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@ -200,43 +200,43 @@ void wd33c93_device::complete_immediate( int status )
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void wd33c93_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
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{
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switch( tid )
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switch (tid)
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{
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case 0:
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complete_immediate( param );
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complete_immediate(param);
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break;
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case 1:
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complete_immediate(CSR_SRV_REQ | busphase);
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complete_immediate(CSR_SRV_REQ | m_busphase);
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break;
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case 2:
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regs[WD_AUXILIARY_STATUS] &= ~ASR_CIP;
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m_regs[WD_AUXILIARY_STATUS] &= ~ASR_CIP;
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break;
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}
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}
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void wd33c93_device::complete_cmd( uint8_t status )
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void wd33c93_device::complete_cmd(uint8_t status)
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{
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/* fire off a timer to complete the command */
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cmd_timer->adjust( attotime::from_usec(1), status );
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m_cmd_timer->adjust(attotime::from_usec(1), status);
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}
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/* command handlers */
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void wd33c93_device::unimplemented_cmd()
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{
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logerror( "%s:Unimplemented SCSI controller command: %02x\n", machine().describe_context(), regs[WD_COMMAND] );
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logerror("%s:Unimplemented SCSI controller command: %02x\n", machine().describe_context(), m_regs[WD_COMMAND]);
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/* complete the command */
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complete_cmd( CSR_INVALID );
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complete_cmd(CSR_INVALID);
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}
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void wd33c93_device::invalid_cmd()
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{
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logerror( "%s:Invalid SCSI controller command: %02x\n", machine().describe_context(), regs[WD_COMMAND] );
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logerror("%s:Invalid SCSI controller command: %02x\n", machine().describe_context(), m_regs[WD_COMMAND]);
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/* complete the command */
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complete_cmd( CSR_INVALID );
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complete_cmd(CSR_INVALID);
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}
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void wd33c93_device::reset_cmd()
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@ -244,13 +244,13 @@ void wd33c93_device::reset_cmd()
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int advanced = 0;
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/* see if it wants us to reset with advanced features */
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if ( regs[WD_OWN_ID] & OWNID_EAF )
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if (m_regs[WD_OWN_ID] & OWNID_EAF)
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{
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advanced = 1;
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}
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/* clear out all registers */
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memset( regs, 0, sizeof( regs ) );
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memset(m_regs, 0, sizeof(m_regs));
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/* complete the command */
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complete_cmd(advanced ? CSR_RESET_AF : CSR_RESET);
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@ -265,7 +265,7 @@ void wd33c93_device::abort_cmd()
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void wd33c93_device::disconnect_cmd()
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{
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/* complete the command */
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regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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}
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void wd33c93_device::select_cmd()
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@ -280,19 +280,19 @@ void wd33c93_device::select_cmd()
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newstatus = CSR_SELECT;
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/* determine the next bus phase depending on the command */
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if ( (regs[WD_COMMAND] & 0x7f) == WD_CMD_SEL_ATN )
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if ((m_regs[WD_COMMAND] & 0x7f) == WD_CMD_SEL_ATN)
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{
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/* /ATN asserted during select: Move to Message Out Phase to read identify */
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busphase = PHS_MESS_OUT;
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m_busphase = PHS_MESS_OUT;
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}
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else
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{
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/* No /ATN asserted: Move to Command Phase */
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busphase = PHS_COMMAND;
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m_busphase = PHS_COMMAND;
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}
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/* queue up a service request out in the future */
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service_req_timer->adjust( attotime::from_usec(50) );
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m_service_req_timer->adjust( attotime::from_usec(50) );
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}
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else
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{
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@ -312,57 +312,57 @@ void wd33c93_device::selectxfer_cmd()
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/* see if we can select that device */
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if (select(unit))
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{
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if ( regs[WD_COMMAND_PHASE] < 0x45 )
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if (m_regs[WD_COMMAND_PHASE] < 0x45)
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{
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/* device is available */
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int phase;
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/* do the request */
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send_command(®s[WD_CDB_1], 12);
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phase = get_phase();
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send_command(&m_regs[WD_CDB_1], 12);
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int phase = get_phase();
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/* set transfer count */
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if ( get_xfer_count() > TEMP_INPUT_LEN )
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if (get_xfer_count() > TEMP_INPUT_LEN)
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{
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logerror( "WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", get_xfer_count() );
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set_xfer_count( TEMP_INPUT_LEN );
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logerror("WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", get_xfer_count());
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set_xfer_count(TEMP_INPUT_LEN);
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}
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switch( phase )
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switch (phase)
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{
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case SCSI_PHASE_DATAIN:
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read_pending = 1;
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m_read_pending = true;
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break;
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}
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}
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if ( read_pending )
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if (m_read_pending)
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{
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int len = TEMP_INPUT_LEN;
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if ( get_xfer_count() < len ) len = get_xfer_count();
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if (get_xfer_count() < len)
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len = get_xfer_count();
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memset( &temp_input[0], 0, TEMP_INPUT_LEN );
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read_data(&temp_input[0], len);
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temp_input_pos = 0;
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read_pending = 0;
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memset(&m_temp_input[0], 0, TEMP_INPUT_LEN);
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read_data(&m_temp_input[0], len);
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m_temp_input_pos = 0;
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m_read_pending = false;
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}
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regs[WD_TARGET_LUN] = 0;
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regs[WD_CONTROL] |= CTRL_EDI;
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regs[WD_COMMAND_PHASE] = 0x60;
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m_regs[WD_TARGET_LUN] = 0;
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m_regs[WD_CONTROL] |= CTRL_EDI;
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m_regs[WD_COMMAND_PHASE] = 0x60;
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/* signal transfer ready */
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newstatus = CSR_SEL_XFER_DONE;
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/* if allowed disconnect, queue a service request */
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if ( identify & 0x40 )
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if (m_identify & 0x40)
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{
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/* queue disconnect message in */
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busphase = PHS_MESS_IN;
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m_busphase = PHS_MESS_IN;
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/* queue up a service request out in the future */
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service_req_timer->adjust( attotime::from_usec(50) );
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m_service_req_timer->adjust(attotime::from_usec(50));
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}
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}
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else
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@ -370,7 +370,7 @@ void wd33c93_device::selectxfer_cmd()
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/* device is not available */
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newstatus = CSR_TIMEOUT;
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set_xfer_count( 0 );
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set_xfer_count(0);
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}
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/* complete the command */
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@ -379,29 +379,29 @@ void wd33c93_device::selectxfer_cmd()
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void wd33c93_device::negate_ack()
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{
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logerror( "WD33C93: ACK Negated\n" );
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logerror("WD33C93: ACK Negated\n");
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/* complete the command */
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regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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}
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void wd33c93_device::xferinfo_cmd()
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{
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/* make the buffer available right away */
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regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
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regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
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/* the command will be completed once the data is transferred */
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deassert_cip_timer->adjust( attotime::from_msec(1) );
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m_deassert_cip_timer->adjust(attotime::from_msec(1));
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}
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/* Handle pending commands */
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void wd33c93_device::dispatch_command()
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{
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/* get the command */
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uint8_t cmd = regs[WD_COMMAND] & 0x7f;
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uint8_t cmd = m_regs[WD_COMMAND] & 0x7f;
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switch(cmd)
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switch (cmd)
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{
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case WD_CMD_RESET:
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reset_cmd();
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@ -463,105 +463,102 @@ void wd33c93_device::dispatch_command()
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WRITE8_MEMBER(wd33c93_device::write)
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{
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switch( offset )
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switch (offset)
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{
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case 0:
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{
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/* update register select */
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sasr = data & 0x1f;
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m_sasr = data & 0x1f;
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}
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break;
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case 1:
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{
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LOG( "WD33C93: %s - Write REG=%02x, data = %02x\n", machine().describe_context(), sasr, data );
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LOG("WD33C93: %s - Write REG=%02x, data = %02x\n", machine().describe_context(), m_sasr, data);
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/* update the register */
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regs[sasr] = data;
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m_regs[m_sasr] = data;
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/* if we receive a command, schedule to process it */
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if ( sasr == WD_COMMAND )
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if (m_sasr == WD_COMMAND)
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{
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LOG( "WDC33C93: %s - Executing command %08x - unit %d\n", machine().describe_context(), data, getunit() );
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/* signal we're processing it */
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regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
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/* process the command */
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dispatch_command();
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}
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else if ( sasr == WD_CDB_1 )
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else if (m_sasr == WD_CDB_1)
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{
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regs[WD_COMMAND_PHASE] = 0;
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m_regs[WD_COMMAND_PHASE] = 0;
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}
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else if ( sasr == WD_DATA )
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else if (m_sasr == WD_DATA)
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{
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/* if data was written, and we have a count, send to device */
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int count = get_xfer_count();
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if ( regs[WD_COMMAND] & 0x80 )
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if (m_regs[WD_COMMAND] & 0x80)
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count = 1;
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if ( count-- > 0 )
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if (count-- > 0)
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{
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/* write to FIFO */
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if ( fifo_pos < FIFO_SIZE )
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if (m_fifo_pos < FIFO_SIZE)
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{
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fifo[fifo_pos++] = data;
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m_fifo[m_fifo_pos++] = data;
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}
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/* update count */
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set_xfer_count( count );
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set_xfer_count(count);
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/* if we're done with the write, see where we're at */
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if ( count == 0 )
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if (count == 0)
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{
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regs[WD_AUXILIARY_STATUS] |= ASR_INT;
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regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
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m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
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switch( busphase )
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switch (m_busphase)
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{
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case PHS_MESS_OUT:
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{
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/* reset fifo */
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fifo_pos = 0;
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m_fifo_pos = 0;
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/* Message out phase. Data is probably SCSI Identify. Move to command phase. */
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busphase = PHS_COMMAND;
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m_busphase = PHS_COMMAND;
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identify = fifo[0];
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m_identify = m_fifo[0];
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}
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break;
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case PHS_COMMAND:
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{
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int xfercount;
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int phase;
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/* Execute the command. Depending on the command, we'll move to data in or out */
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send_command(&fifo[0], 12);
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xfercount = get_length();
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phase = get_phase();
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send_command(&m_fifo[0], 12);
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int xfercount = get_length();
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int phase = get_phase();
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/* reset fifo */
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fifo_pos = 0;
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m_fifo_pos = 0;
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/* set the new count */
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set_xfer_count( xfercount );
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set_xfer_count(xfercount);
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switch( phase )
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switch (phase)
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{
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case SCSI_PHASE_STATUS:
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busphase = PHS_STATUS;
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m_busphase = PHS_STATUS;
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break;
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case SCSI_PHASE_DATAIN:
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busphase = PHS_DATA_IN;
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read_pending = 1;
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m_busphase = PHS_DATA_IN;
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m_read_pending = true;
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break;
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case SCSI_PHASE_DATAOUT:
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busphase = PHS_DATA_OUT;
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m_busphase = PHS_DATA_OUT;
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break;
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}
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}
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@ -570,31 +567,31 @@ WRITE8_MEMBER(wd33c93_device::write)
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case PHS_DATA_OUT:
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{
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/* write data out to device */
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write_data(fifo, fifo_pos);
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write_data(m_fifo, m_fifo_pos);
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/* reset fifo */
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fifo_pos = 0;
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m_fifo_pos = 0;
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/* move to status phase */
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busphase = PHS_STATUS;
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m_busphase = PHS_STATUS;
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}
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break;
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}
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/* complete the command */
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complete_immediate(CSR_XFER_DONE | busphase);
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complete_immediate(CSR_XFER_DONE | m_busphase);
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}
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}
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else
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{
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logerror( "WD33C93: Sending data to device with transfer count = 0!. Ignoring...\n" );
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logerror("WD33C93: Sending data to device with transfer count = 0!. Ignoring...\n");
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}
|
||||
}
|
||||
|
||||
/* auto-increment register select if not on special registers */
|
||||
if ( sasr != WD_COMMAND && sasr != WD_DATA && sasr != WD_AUXILIARY_STATUS )
|
||||
if (m_sasr != WD_COMMAND && m_sasr != WD_DATA && m_sasr != WD_AUXILIARY_STATUS)
|
||||
{
|
||||
sasr = ( sasr + 1 ) & 0x1f;
|
||||
m_sasr = (m_sasr + 1) & 0x1f;
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -609,31 +606,27 @@ WRITE8_MEMBER(wd33c93_device::write)
|
||||
|
||||
READ8_MEMBER(wd33c93_device::read)
|
||||
{
|
||||
switch( offset )
|
||||
switch (offset)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
/* read aux status */
|
||||
return regs[WD_AUXILIARY_STATUS];
|
||||
}
|
||||
return m_regs[WD_AUXILIARY_STATUS];
|
||||
|
||||
case 1:
|
||||
{
|
||||
uint8_t ret;
|
||||
|
||||
/* if reading status, clear irq flag */
|
||||
if ( sasr == WD_SCSI_STATUS )
|
||||
if (m_sasr == WD_SCSI_STATUS)
|
||||
{
|
||||
regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
|
||||
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
|
||||
|
||||
if (!m_irq_cb.isnull())
|
||||
{
|
||||
m_irq_cb(0);
|
||||
}
|
||||
|
||||
LOG( "WD33C93: %s - Status read (%02x)\n", machine().describe_context(), regs[WD_SCSI_STATUS] );
|
||||
LOG("WD33C93: %s - Status read (%02x)\n", machine().describe_context(), m_regs[WD_SCSI_STATUS]);
|
||||
}
|
||||
else if ( sasr == WD_DATA )
|
||||
else if (m_sasr == WD_DATA)
|
||||
{
|
||||
/* we're going to be doing synchronous reads */
|
||||
|
||||
@ -641,83 +634,82 @@ READ8_MEMBER(wd33c93_device::read)
|
||||
int count = get_xfer_count();
|
||||
|
||||
/* initialize the return value */
|
||||
regs[WD_DATA] = 0;
|
||||
m_regs[WD_DATA] = 0;
|
||||
|
||||
if ( count <= 0 && busphase == PHS_MESS_IN )
|
||||
if (count <= 0 && m_busphase == PHS_MESS_IN)
|
||||
{
|
||||
/* move to disconnect */
|
||||
complete_cmd(CSR_DISC);
|
||||
}
|
||||
else if ( count == 1 && busphase == PHS_STATUS )
|
||||
else if (count == 1 && m_busphase == PHS_STATUS)
|
||||
{
|
||||
/* update the count */
|
||||
set_xfer_count( 0 );
|
||||
set_xfer_count(0);
|
||||
|
||||
/* move to message in phase */
|
||||
busphase = PHS_MESS_IN;
|
||||
m_busphase = PHS_MESS_IN;
|
||||
|
||||
/* complete the command */
|
||||
complete_cmd(CSR_XFER_DONE | busphase);
|
||||
complete_cmd(CSR_XFER_DONE | m_busphase);
|
||||
}
|
||||
else if ( count-- > 0 ) /* make sure we still have data to send */
|
||||
else if (count-- > 0) /* make sure we still have data to send */
|
||||
{
|
||||
if ( read_pending )
|
||||
if (m_read_pending)
|
||||
{
|
||||
int len = TEMP_INPUT_LEN;
|
||||
|
||||
if ( (count+1) < len ) len = count+1;
|
||||
read_data(&temp_input[0], len);
|
||||
temp_input_pos = 0;
|
||||
read_pending = 0;
|
||||
if ((count + 1) < len )
|
||||
len = count + 1;
|
||||
read_data(&m_temp_input[0], len);
|
||||
m_temp_input_pos = 0;
|
||||
m_read_pending = false;
|
||||
}
|
||||
|
||||
regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
|
||||
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
|
||||
|
||||
/* read in one byte */
|
||||
if ( temp_input_pos < TEMP_INPUT_LEN )
|
||||
regs[WD_DATA] = temp_input[temp_input_pos++];
|
||||
if (m_temp_input_pos < TEMP_INPUT_LEN)
|
||||
m_regs[WD_DATA] = m_temp_input[m_temp_input_pos++];
|
||||
|
||||
/* update the count */
|
||||
set_xfer_count( count );
|
||||
set_xfer_count(count);
|
||||
|
||||
/* transfer finished, see where we're at */
|
||||
if ( count == 0 )
|
||||
if (count == 0)
|
||||
{
|
||||
if ( regs[WD_COMMAND_PHASE] != 0x60 )
|
||||
if (m_regs[WD_COMMAND_PHASE] != 0x60)
|
||||
{
|
||||
/* move to status phase */
|
||||
busphase = PHS_STATUS;
|
||||
m_busphase = PHS_STATUS;
|
||||
|
||||
/* complete the command */
|
||||
complete_cmd(CSR_XFER_DONE | busphase);
|
||||
complete_cmd(CSR_XFER_DONE | m_busphase);
|
||||
}
|
||||
else
|
||||
{
|
||||
regs[WD_AUXILIARY_STATUS] |= ASR_INT;
|
||||
regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
|
||||
m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
|
||||
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
LOG( "WD33C93: %s - Data read (%02x)\n", machine().describe_context(), regs[WD_DATA] );
|
||||
LOG("WD33C93: %s - Data read (%02x)\n", machine().describe_context(), m_regs[WD_DATA]);
|
||||
|
||||
/* get the register value */
|
||||
ret = regs[sasr];
|
||||
uint8_t ret = m_regs[m_sasr];
|
||||
|
||||
/* auto-increment register select if not on special registers */
|
||||
if ( sasr != WD_COMMAND && sasr != WD_DATA && sasr != WD_AUXILIARY_STATUS )
|
||||
if (m_sasr != WD_COMMAND && m_sasr != WD_DATA && m_sasr != WD_AUXILIARY_STATUS)
|
||||
{
|
||||
sasr = ( sasr + 1 ) & 0x1f;
|
||||
m_sasr = (m_sasr + 1) & 0x1f;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
logerror( "WD33C93: Read from invalid offset %d\n", offset );
|
||||
}
|
||||
logerror("WD33C93: Read from invalid offset %d\n", offset);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -734,70 +726,70 @@ void wd33c93_device::device_start()
|
||||
{
|
||||
legacy_scsi_host_adapter::device_start();
|
||||
|
||||
memset(regs, 0, sizeof(regs));
|
||||
memset(fifo, 0, sizeof(fifo));
|
||||
memset(temp_input, 0, sizeof(temp_input));
|
||||
memset(m_regs, 0, sizeof(m_regs));
|
||||
memset(m_fifo, 0, sizeof(m_fifo));
|
||||
memset(m_temp_input, 0, sizeof(m_temp_input));
|
||||
|
||||
sasr = 0;
|
||||
fifo_pos = 0;
|
||||
temp_input_pos = 0;
|
||||
busphase = 0;
|
||||
identify = 0;
|
||||
read_pending = 0;
|
||||
m_sasr = 0;
|
||||
m_fifo_pos = 0;
|
||||
m_temp_input_pos = 0;
|
||||
m_busphase = 0;
|
||||
m_identify = 0;
|
||||
m_read_pending = 0;
|
||||
|
||||
m_irq_cb.resolve();
|
||||
|
||||
/* allocate a timer for commands */
|
||||
cmd_timer = timer_alloc(0);
|
||||
service_req_timer = timer_alloc(1);
|
||||
deassert_cip_timer = timer_alloc(2);
|
||||
m_cmd_timer = timer_alloc(0);
|
||||
m_service_req_timer = timer_alloc(1);
|
||||
m_deassert_cip_timer = timer_alloc(2);
|
||||
|
||||
save_item( NAME( sasr ) );
|
||||
save_item( NAME( regs ) );
|
||||
save_item( NAME( fifo ) );
|
||||
save_item( NAME( fifo_pos ) );
|
||||
save_item( NAME( temp_input ) );
|
||||
save_item( NAME( temp_input_pos ) );
|
||||
save_item( NAME( busphase ) );
|
||||
save_item( NAME( identify ) );
|
||||
save_item( NAME( read_pending ) );
|
||||
save_item(NAME(m_sasr));
|
||||
save_item(NAME(m_regs));
|
||||
save_item(NAME(m_fifo));
|
||||
save_item(NAME(m_fifo_pos));
|
||||
save_item(NAME(m_temp_input));
|
||||
save_item(NAME(m_temp_input_pos));
|
||||
save_item(NAME(m_busphase));
|
||||
save_item(NAME(m_identify));
|
||||
save_item(NAME(m_read_pending));
|
||||
}
|
||||
|
||||
void wd33c93_device::dma_read_data( int bytes, uint8_t *pData )
|
||||
void wd33c93_device::dma_read_data(int bytes, uint8_t *data)
|
||||
{
|
||||
int len = bytes;
|
||||
|
||||
if ( len >= get_xfer_count() )
|
||||
if (len >= get_xfer_count())
|
||||
len = get_xfer_count();
|
||||
|
||||
if ( len == 0 )
|
||||
if (len == 0)
|
||||
return;
|
||||
|
||||
if ( (temp_input_pos+len) >= TEMP_INPUT_LEN )
|
||||
if ((m_temp_input_pos + len) >= TEMP_INPUT_LEN)
|
||||
{
|
||||
logerror( "Reading past end of buffer, increase TEMP_INPUT_LEN size\n" );
|
||||
logerror("Reading past end of buffer, increase TEMP_INPUT_LEN size\n");
|
||||
len = TEMP_INPUT_LEN - len;
|
||||
}
|
||||
|
||||
assert(len);
|
||||
|
||||
memcpy( pData, &temp_input[temp_input_pos], len );
|
||||
memcpy(data, &m_temp_input[m_temp_input_pos], len);
|
||||
|
||||
temp_input_pos += len;
|
||||
m_temp_input_pos += len;
|
||||
len = get_xfer_count() - len;
|
||||
set_xfer_count(len);
|
||||
}
|
||||
|
||||
void wd33c93_device::dma_write_data(int bytes, uint8_t *pData)
|
||||
void wd33c93_device::dma_write_data(int bytes, uint8_t *data)
|
||||
{
|
||||
write_data(pData, bytes);
|
||||
write_data(data, bytes);
|
||||
}
|
||||
|
||||
void wd33c93_device::clear_dma()
|
||||
{
|
||||
/* indicate DMA completed by clearing the transfer count */
|
||||
set_xfer_count(0);
|
||||
regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
|
||||
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
|
||||
}
|
||||
|
||||
int wd33c93_device::get_dma_count()
|
||||
|
||||
@ -28,8 +28,8 @@ public:
|
||||
DECLARE_READ8_MEMBER(read);
|
||||
DECLARE_WRITE8_MEMBER(write);
|
||||
|
||||
void dma_read_data( int bytes, uint8_t *pData );
|
||||
void dma_write_data(int bytes, uint8_t *pData);
|
||||
void dma_read_data(int bytes, uint8_t *data);
|
||||
void dma_write_data(int bytes, uint8_t *data);
|
||||
void clear_dma();
|
||||
int get_dma_count();
|
||||
|
||||
@ -91,18 +91,18 @@ private:
|
||||
void xferinfo_cmd();
|
||||
void dispatch_command();
|
||||
|
||||
uint8_t sasr;
|
||||
uint8_t regs[WD_AUXILIARY_STATUS+1];
|
||||
uint8_t fifo[FIFO_SIZE];
|
||||
int fifo_pos;
|
||||
uint8_t temp_input[TEMP_INPUT_LEN];
|
||||
int temp_input_pos;
|
||||
uint8_t busphase;
|
||||
uint8_t identify;
|
||||
int read_pending;
|
||||
emu_timer *cmd_timer;
|
||||
emu_timer *service_req_timer;
|
||||
emu_timer *deassert_cip_timer;
|
||||
uint8_t m_sasr;
|
||||
uint8_t m_regs[WD_AUXILIARY_STATUS+1];
|
||||
uint8_t m_fifo[FIFO_SIZE];
|
||||
int m_fifo_pos;
|
||||
uint8_t m_temp_input[TEMP_INPUT_LEN];
|
||||
int m_temp_input_pos;
|
||||
uint8_t m_busphase;
|
||||
uint8_t m_identify;
|
||||
bool m_read_pending;
|
||||
emu_timer *m_cmd_timer;
|
||||
emu_timer *m_service_req_timer;
|
||||
emu_timer *m_deassert_cip_timer;
|
||||
devcb_write_line m_irq_cb; /* irq callback */
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user