mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
sbrain: Driver overhaul
- Support cursor and scrolling through CRTC registers - Correct number of interrupts per frame - Actually show the "insert diskette" message with -bios 0 - Add RAM size option - Add option for two more floppy drives - Add RS232 ports and DIP switch for selecting baud clocks - Redo memory banking without configured banks or bankdev to be hardware-accurate (nw) - Rename all "portXX" handlers (nw) - Acknowledge interrupt on reads as well as writes (nw) - Remove palette device (nw) - Update manufacturer and system names (nw) - Update notes (nw) - Many small code refinements (nw)
This commit is contained in:
AJR
parent
4a7fdb0d9b
commit
6392ecb0fa
@ -44,6 +44,9 @@
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#include "video/dp8350.h"
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#include "screen.h"
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//#define VERBOSE 1
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#include "logmacro.h"
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//**************************************************************************
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// GLOBAL VARIABLES
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@ -344,7 +347,7 @@ void dp835x_device::register_load(u8 rs, u16 addr)
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case 1:
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// A = 0, B = 1: Top-of-Page
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logerror("Top-of-Page Register = %03X\n", addr);
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LOG("Top-of-Page Register = %03X\n", addr);
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m_topr = addr;
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break;
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@ -352,19 +355,19 @@ void dp835x_device::register_load(u8 rs, u16 addr)
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// A = 1, B = 0: Row Start (also Top-of-Page during vertical blanking)
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if (m_line >= m_video_scan_lines)
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{
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logerror("Row Start Register = %03X (redirected to Top-of-Page)\n", addr);
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LOG("Row Start Register = %03X (redirected to Top-of-Page)\n", addr);
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m_topr = addr;
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}
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else
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{
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logerror("Row Start Register = %03X\n", addr);
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LOG("Row Start Register = %03X\n", addr);
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m_rsr = addr;
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}
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break;
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case 3:
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// A = 1, B = 1: Cursor
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logerror("Cursor Register = %03X\n", addr);
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LOG("Cursor Register = %03X\n", addr);
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m_cr = addr;
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break;
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}
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@ -66,6 +66,11 @@ public:
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DECLARE_READ_LINE_MEMBER(vsync_r);
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DECLARE_READ_LINE_MEMBER(vblank_r);
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// address getters (TODO: accurate character-by-character emulation)
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u16 top_of_page() const { return m_topr; }
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u16 row_start() const { return m_row_start; }
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u16 cursor_address() const { return m_cr; }
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protected:
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// base type constructor
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dp835x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock,
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@ -8,10 +8,12 @@ Intertec SuperBrain
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Intertec Compustar terminal appears to have identical hardware. Need roms for it.
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Chips: 2x Z80; FD1791; 2x 8251; 8255; BR1941; CRT8002; KR3600; DP8350
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Chips: 2x Z80; FD1791; 2x 8251; 8255; BR1941; CRT8002-003; KR3600-056; DP8350; MM5035
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Xtals: 16.0, 10.92, 5.0688
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RAM: 32K or 64K dynamic (TMS4116-20NL); 1K static disk buffer (MM2114)
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Disk parameters: 512 bytes x 10 sectors x 35 tracks. 1 and 2-sided disks supported.
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Sound: Beeper
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Expansion bus: 40 pins, nearly identical to TRS-80
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The boot prom is shared between both cpus. This feat is accomplished by holding the sub cpu
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in reset, until the main cpu has prepared a few memory locations. The first thing in the rom
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@ -26,30 +28,31 @@ When booted, the time (corrupted) is displayed at top right. You need to run TIM
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The schematic in parts is difficult to read. Some assumptions have been made.
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To Do:
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- Without a disk in, it should display a message to insert a disk. Doesn't happen. May
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attempt to execute empty memory instead. (-bios 1, -bios 2)
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- Without a disk in, it should display a message to insert a disk. This happens, but only with
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-bios 0. May attempt to execute empty memory instead. (-bios 1, -bios 2)
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- Improve keyboard.
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- Video chips need to be emulated (CRT8002 and DP8350), attributes etc.
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- Row buffering DMA (DP8350, MM5035) and line-by-line rendering.
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- Proper character generator emulation (CRT8002).
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- Add expansion bus slot.
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- Probably lots of other stuff.
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- PC0 when high will swap out lower 16k of RAM for the DP8350 device. The value of HL (the
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"memory" address) is the data (cursor location, top of screen, etc). The byte "written"
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to this address (d0,d1) is the command for the CRTC.
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*************************************************************************************************************/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "bus/rs232/rs232.h"
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#include "machine/com8116.h"
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#include "machine/i8251.h"
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#include "machine/i8255.h"
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#include "machine/wd_fdc.h"
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#include "machine/ram.h"
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#include "machine/timer.h"
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#include "sound/beep.h"
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#include "video/dp8350.h"
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#include "emupal.h"
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#include "screen.h"
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#include "speaker.h"
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#include <algorithm>
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class sbrain_state : public driver_device
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@ -59,43 +62,56 @@ public:
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_subcpu(*this, "subcpu")
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, m_p_videoram(*this, "videoram")
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, m_p_chargen(*this, "chargen")
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, m_beep(*this, "beeper")
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, m_crtc(*this, "crtc")
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, m_u0(*this, "uart0")
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, m_u1(*this, "uart1")
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, m_usart(*this, "usart%u", 0U)
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, m_mainport(*this, "mainport")
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, m_ppi(*this, "ppi")
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, m_fdc (*this, "fdc")
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, m_floppy0(*this, "fdc:0")
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, m_floppy1(*this, "fdc:1")
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, m_vs(*this, "VS")
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, m_bankr0(*this, "bankr0")
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, m_bankw0(*this, "bankw0")
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, m_bank2(*this, "bank2")
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, m_fdc(*this, "fdc")
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, m_floppy(*this, "fdc:%u", 0U)
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, m_ram(*this, RAM_TAG)
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, m_boot_prom(*this, "subcpu")
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, m_disk_buffer(*this, "buffer")
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, m_keyboard(*this, "X%u", 0)
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, m_modifiers(*this, "MODIFIERS")
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, m_serial_sw(*this, "BAUDCLOCK")
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{
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}
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void sbrain(machine_config &config);
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void init_sbrain();
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protected:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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private:
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DECLARE_MACHINE_RESET(sbrain);
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DECLARE_READ8_MEMBER(ppi_pa_r);
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DECLARE_WRITE8_MEMBER(ppi_pa_w);
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DECLARE_READ8_MEMBER(ppi_pb_r);
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DECLARE_WRITE8_MEMBER(ppi_pb_w);
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DECLARE_READ8_MEMBER(ppi_pc_r);
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DECLARE_WRITE8_MEMBER(ppi_pc_w);
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DECLARE_READ8_MEMBER(port48_r);
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DECLARE_READ8_MEMBER(port50_r);
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DECLARE_READ8_MEMBER(port10_r);
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DECLARE_WRITE8_MEMBER(port10_w);
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u32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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u8 mem_r(offs_t offset);
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void mem_w(offs_t offset, u8 data);
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u8 ppi_pa_r();
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void ppi_pa_w(u8 data);
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u8 ppi_pb_r();
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void ppi_pb_w(u8 data);
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u8 ppi_pc_r();
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void ppi_pc_w(u8 data);
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u8 char_int_ack_r();
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void char_int_ack_w(u8 data);
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u8 keyboard_r();
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void disk_select_w(u8 data);
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u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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TIMER_DEVICE_CALLBACK_MEMBER(kbd_scan);
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DECLARE_WRITE_LINE_MEMBER(crtc_lrc_w);
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DECLARE_WRITE_LINE_MEMBER(crtc_vblank_w);
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DECLARE_WRITE_LINE_MEMBER(crtc_vsync_w);
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DECLARE_WRITE_LINE_MEMBER(external_txc_w);
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DECLARE_WRITE_LINE_MEMBER(external_rxc_w);
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DECLARE_WRITE_LINE_MEMBER(internal_txc_rxc_w);
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void sbrain_io(address_map &map);
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void sbrain_mem(address_map &map);
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void sbrain_subio(address_map &map);
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@ -107,79 +123,135 @@ private:
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u8 m_portb;
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u8 m_portc;
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u8 m_port10;
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u8 m_term_data;
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u8 m_key_data;
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u8 m_framecnt;
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_subcpu;
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required_shared_ptr<u8> m_p_videoram;
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required_region_ptr<u8> m_p_chargen;
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required_device<beep_device> m_beep;
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required_device<dp8350_device> m_crtc;
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required_device<i8251_device> m_u0;
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required_device<i8251_device> m_u1;
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required_device_array<i8251_device, 2> m_usart;
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required_device<rs232_port_device> m_mainport;
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required_device<i8255_device> m_ppi;
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required_device<fd1791_device> m_fdc;
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required_device<floppy_connector> m_floppy0;
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required_device<floppy_connector> m_floppy1;
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required_ioport m_vs;
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required_memory_bank m_bankr0;
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required_memory_bank m_bankw0;
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required_memory_bank m_bank2;
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required_device_array<floppy_connector, 4> m_floppy;
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required_device<ram_device> m_ram;
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required_region_ptr<u8> m_boot_prom;
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required_shared_ptr<u8> m_disk_buffer;
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required_ioport_array<10> m_keyboard;
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required_ioport m_modifiers;
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required_ioport m_serial_sw;
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};
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void sbrain_state::sbrain_mem(address_map &map)
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{
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map(0x0000, 0x3fff).bankr("bankr0").bankw("bankw0");
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map(0x4000, 0x7fff).ram();
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map(0x8000, 0xbfff).bankrw("bank2");
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map(0xc000, 0xf7ff).ram();
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map(0xf800, 0xffff).ram().share("videoram");
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map(0x0000, 0xffff).rw(FUNC(sbrain_state::mem_r), FUNC(sbrain_state::mem_w));
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}
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void sbrain_state::sbrain_io(address_map &map)
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{
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map.global_mask(0xff);
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map(0x40, 0x41).mirror(6).rw(m_u0, FUNC(i8251_device::read), FUNC(i8251_device::write));
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map(0x48, 0x4f).r(FUNC(sbrain_state::port48_r)); //chr_int_latch
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map(0x50, 0x57).r(FUNC(sbrain_state::port50_r));
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map(0x58, 0x59).mirror(6).rw(m_u1, FUNC(i8251_device::read), FUNC(i8251_device::write));
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map(0x40, 0x41).mirror(6).rw(m_usart[0], FUNC(i8251_device::read), FUNC(i8251_device::write));
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map(0x48, 0x48).mirror(7).rw(FUNC(sbrain_state::char_int_ack_r), FUNC(sbrain_state::char_int_ack_w)); //chr_int_latch
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map(0x50, 0x50).mirror(7).r(FUNC(sbrain_state::keyboard_r));
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map(0x58, 0x59).mirror(6).rw(m_usart[1], FUNC(i8251_device::read), FUNC(i8251_device::write));
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map(0x60, 0x60).mirror(7).w("brg", FUNC(com8116_device::stt_str_w));
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map(0x68, 0x6b).mirror(4).rw(m_ppi, FUNC(i8255_device::read), FUNC(i8255_device::write));
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}
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void sbrain_state::sbrain_submem(address_map &map)
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{
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map(0x0000, 0x07ff).rom();
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map(0x8800, 0x8bff).ram().region("subcpu", 0x8800);
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map(0x0000, 0x07ff).mirror(0xf000).rom().region("subcpu", 0);
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map(0x8800, 0x8bff).mirror(0x7400).ram().share("buffer");
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}
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void sbrain_state::sbrain_subio(address_map &map)
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{
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map.global_mask(0xff);
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map(0x08, 0x0b).rw(m_fdc, FUNC(fd1791_device::read), FUNC(fd1791_device::write));
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map(0x10, 0x10).rw(FUNC(sbrain_state::port10_r), FUNC(sbrain_state::port10_w));
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map.global_mask(0x1f);
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map(0x08, 0x0b).mirror(4).rw(m_fdc, FUNC(fd1791_device::read), FUNC(fd1791_device::write));
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map(0x10, 0x10).mirror(7).w(FUNC(sbrain_state::disk_select_w));
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}
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READ8_MEMBER( sbrain_state::port48_r )
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u8 sbrain_state::mem_r(offs_t offset)
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{
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
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switch (offset & 0xc000)
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{
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case 0x0000:
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// PPIC-2 set selects boot PROM
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if (BIT(m_portc, 2))
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return m_boot_prom[offset & 0x7ff];
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// lowest 16K of RAM is disabled when PPIC-0 is set
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if (BIT(m_portc, 0))
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return 0xff;
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break;
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case 0x8000:
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// resetting PPIC-4 selects disk buffer RAM
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if (!BIT(m_portc, 4))
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return m_disk_buffer[offset & 0x3ff];
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break;
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}
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return m_ram->read(offset);
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}
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void sbrain_state::mem_w(offs_t offset, u8 data)
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{
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// any memory write affects CRTC when PPIC-0 is set
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if (BIT(m_portc, 0))
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m_crtc->register_load(bitswap<2>(data, 0, 1), offset & 0xfff);
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switch (offset & 0xc000)
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{
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case 0x0000:
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// can't write to boot PROM
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if (BIT(m_portc, 2))
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return;
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// RAS is disabled for bank 0 when PPIC-0 is set
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if (BIT(m_portc, 0))
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return;
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break;
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case 0x8000:
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// resetting PPIC-4 selects disk buffer RAM
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if (!BIT(m_portc, 4))
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{
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m_disk_buffer[offset & 0x3ff] = data;
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break;
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}
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break;
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}
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m_ram->write(offset, data);
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}
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u8 sbrain_state::char_int_ack_r()
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{
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if (!machine().side_effects_disabled())
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
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return 0xff;
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}
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READ8_MEMBER( sbrain_state::port50_r )
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void sbrain_state::char_int_ack_w(u8 data)
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{
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return m_term_data;
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
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}
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READ8_MEMBER( sbrain_state::port10_r )
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u8 sbrain_state::keyboard_r()
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{
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return m_port10;
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return m_key_data;
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}
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/* Misc disk functions
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d0 : ?
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d0 : busy signal to master CPU
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d1 : SEL A (drive 0?)
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d2 : SEL B (drive 1?)
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d3 : SEL C
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@ -187,24 +259,27 @@ d4 : SEL D
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d5 : side select
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d6,7 : not used
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*/
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WRITE8_MEMBER( sbrain_state::port10_w )
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void sbrain_state::disk_select_w(u8 data)
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{
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m_port10 = data | 0xc0;
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floppy_image_device *floppy = nullptr;
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if (BIT(m_port10, 1)) floppy = m_floppy0->get_device();
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if (BIT(m_port10, 2)) floppy = m_floppy1->get_device();
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m_fdc->set_floppy(floppy);
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if (floppy)
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floppy->ss_w(BIT(m_port10, 5));
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m_floppy0->get_device()->mon_w(0); // motors run all the time
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m_floppy1->get_device()->mon_w(0);
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m_fdc->set_floppy(nullptr);
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for (int d = 0; d < 4; d++)
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{
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if (BIT(m_port10, d + 1))
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{
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floppy_image_device *floppy = m_floppy[d]->get_device();
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if (floppy && floppy->exists())
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{
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m_fdc->set_floppy(floppy);
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floppy->ss_w(BIT(m_port10, 5));
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break;
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}
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}
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}
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}
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READ8_MEMBER( sbrain_state::ppi_pa_r )
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u8 sbrain_state::ppi_pa_r()
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{
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return m_porta;
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}
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@ -217,7 +292,7 @@ d5 : strike through
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d6 : 1=60hz 0=50hz
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d7 : reverse video
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*/
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WRITE8_MEMBER( sbrain_state::ppi_pa_w )
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void sbrain_state::ppi_pa_w(u8 data)
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{
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m_crtc->refresh_control(BIT(data, 6));
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@ -230,25 +305,26 @@ d1 : key held down
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d2 : Vert Blank
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d3 : not used
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d4 : /capslock
|
||||
d5 : ?
|
||||
d5 : disk status: 1 = busy, 0 = ready
|
||||
d6 : Ring Indicator line from main rs232 port, 1=normal, 0=set
|
||||
d7 : cpu2 /busak line
|
||||
*/
|
||||
READ8_MEMBER( sbrain_state::ppi_pb_r )
|
||||
u8 sbrain_state::ppi_pb_r()
|
||||
{
|
||||
u8 vertsync = m_vs->read(); // bit 2
|
||||
u8 capslock = BIT(ioport("MODIFIERS")->read(), 0) << 4; // bit 4, capslock
|
||||
u8 vertsync = m_crtc->vblank_r() << 2;
|
||||
u8 capslock = BIT(m_modifiers->read(), 0) << 4; // bit 4, capslock
|
||||
u8 p10d0 = BIT(m_port10, 0) << 5; // bit 5
|
||||
u8 ri = m_mainport->ri_r() << 6;
|
||||
u8 busak = m_busak ? 128 : 0; // bit 7
|
||||
return busak | p10d0 | capslock | vertsync | m_keydown;
|
||||
return busak | ri | p10d0 | capslock | vertsync | m_keydown;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( sbrain_state::ppi_pb_w )
|
||||
void sbrain_state::ppi_pb_w(u8 data)
|
||||
{
|
||||
m_portb = data & 8;
|
||||
}
|
||||
|
||||
READ8_MEMBER( sbrain_state::ppi_pc_r )
|
||||
u8 sbrain_state::ppi_pc_r()
|
||||
{
|
||||
return m_portc;
|
||||
}
|
||||
@ -263,20 +339,45 @@ d5 : cpu2 /busreq line
|
||||
d6 : beeper
|
||||
d7 : keyboard, 1=enable comms, 0=reset
|
||||
*/
|
||||
WRITE8_MEMBER( sbrain_state::ppi_pc_w )
|
||||
void sbrain_state::ppi_pc_w(u8 data)
|
||||
{
|
||||
m_portc = data;
|
||||
m_beep->set_state(BIT(data, 6));
|
||||
m_bankr0->set_entry(BIT(data, 2));
|
||||
m_bank2->set_entry(BIT(data, 4));
|
||||
if (!BIT(data, 7))
|
||||
m_keydown &= 2; // ack DR
|
||||
|
||||
m_subcpu->set_input_line(INPUT_LINE_RESET, BIT(data, 3) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(data, 3))
|
||||
{
|
||||
m_fdc->reset();
|
||||
disk_select_w(0);
|
||||
}
|
||||
m_subcpu->set_input_line(Z80_INPUT_LINE_BUSRQ, BIT(data, 5) ? ASSERT_LINE : CLEAR_LINE); // ignored in z80.cpp
|
||||
m_busak = BIT(data, 5);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(sbrain_state::external_txc_w)
|
||||
{
|
||||
if (!BIT(m_serial_sw->read(), 0))
|
||||
m_usart[1]->write_txc(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(sbrain_state::external_rxc_w)
|
||||
{
|
||||
if (!BIT(m_serial_sw->read(), 2))
|
||||
m_usart[1]->write_rxc(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(sbrain_state::internal_txc_rxc_w)
|
||||
{
|
||||
if (!BIT(m_serial_sw->read(), 1))
|
||||
m_usart[1]->write_txc(state);
|
||||
if (!BIT(m_serial_sw->read(), 3))
|
||||
m_usart[1]->write_rxc(state);
|
||||
if (!BIT(m_serial_sw->read(), 4))
|
||||
m_mainport->write_etc(state);
|
||||
}
|
||||
|
||||
u8 translate_table[3][10][8] = {
|
||||
// unshifted
|
||||
{
|
||||
@ -419,16 +520,23 @@ static INPUT_PORTS_START( sbrain )
|
||||
PORT_BIT(0x02,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
|
||||
PORT_BIT(0x04,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
|
||||
|
||||
/* vblank */
|
||||
PORT_START("VS")
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_CUSTOM) PORT_VBLANK("screen")
|
||||
PORT_START("BAUDCLOCK")
|
||||
PORT_DIPNAME(0x03, 0x01, "Main TX Clock") PORT_DIPLOCATION("SW:1,3")
|
||||
PORT_DIPSETTING(0x01, "Internal")
|
||||
PORT_DIPSETTING(0x02, "External")
|
||||
PORT_DIPNAME(0x0c, 0x04, "Main RX Clock") PORT_DIPLOCATION("SW:2,4")
|
||||
PORT_DIPSETTING(0x04, "Internal")
|
||||
PORT_DIPSETTING(0x08, "External")
|
||||
PORT_DIPNAME(0x10, 0x10, "Internal Baud Clock to Main Port") PORT_DIPLOCATION("SW:5")
|
||||
PORT_DIPSETTING(0x10, DEF_STR(Off))
|
||||
PORT_DIPSETTING(0x00, DEF_STR(On))
|
||||
INPUT_PORTS_END
|
||||
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(sbrain_state::kbd_scan)
|
||||
{
|
||||
// m_keydown: d0 = 1 after key pressed, and is reset by pc7; d1 = 1 while a key is down.
|
||||
m_keydown &= 1;
|
||||
u8 i, j, keyin, mods = ioport("MODIFIERS")->read() & 6;
|
||||
u8 i, j, keyin, mods = m_modifiers->read() & 6;
|
||||
u8 translate_set = 0;
|
||||
if (BIT(mods, 1))
|
||||
translate_set = 1;
|
||||
@ -446,26 +554,41 @@ TIMER_DEVICE_CALLBACK_MEMBER(sbrain_state::kbd_scan)
|
||||
if (BIT(keyin, j))
|
||||
{
|
||||
u8 pressed = translate_table[translate_set][i][j];
|
||||
m_keydown = (m_term_data == pressed) ? (m_keydown | 2) : 3;
|
||||
m_term_data = pressed;
|
||||
m_keydown = (m_key_data == pressed) ? (m_keydown | 2) : 3;
|
||||
m_key_data = pressed;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
m_term_data = 0xff;
|
||||
m_key_data = 0xff;
|
||||
}
|
||||
|
||||
void sbrain_state::init_sbrain()
|
||||
WRITE_LINE_MEMBER(sbrain_state::crtc_lrc_w)
|
||||
{
|
||||
u8 *main = memregion("maincpu")->base();
|
||||
u8 *sub = memregion("subcpu")->base();
|
||||
// TODO: actually triggered by BUSACK and taken after DMA burst finishes
|
||||
if (state && !m_crtc->lbre_r() && !m_crtc->vblank_r())
|
||||
m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
|
||||
}
|
||||
|
||||
m_bankr0->configure_entry(0, &main[0x0000]);
|
||||
m_bankr0->configure_entry(1, &sub[0x0000]);
|
||||
m_bankw0->configure_entry(0, &main[0x0000]);
|
||||
m_bank2->configure_entry(0, &sub[0x8000]);
|
||||
m_bank2->configure_entry(1, &main[0x8000]);
|
||||
WRITE_LINE_MEMBER(sbrain_state::crtc_vblank_w)
|
||||
{
|
||||
if (state)
|
||||
m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(sbrain_state::crtc_vsync_w)
|
||||
{
|
||||
// TODO: internal to the CRT8002
|
||||
if (!state)
|
||||
m_framecnt++;
|
||||
}
|
||||
|
||||
void sbrain_state::machine_start()
|
||||
{
|
||||
std::fill_n(m_ram->pointer(), m_ram->size(), 0x00);
|
||||
|
||||
m_usart[0]->write_cts(0);
|
||||
}
|
||||
|
||||
static void sbrain_floppies(device_slot_interface &device)
|
||||
@ -473,20 +596,31 @@ static void sbrain_floppies(device_slot_interface &device)
|
||||
device.option_add("525dd", FLOPPY_525_DD);
|
||||
}
|
||||
|
||||
MACHINE_RESET_MEMBER( sbrain_state, sbrain )
|
||||
void sbrain_state::machine_reset()
|
||||
{
|
||||
m_keydown = 0;
|
||||
m_bankr0->set_entry(1); // point at rom
|
||||
m_bankw0->set_entry(0); // always write to ram
|
||||
m_bank2->set_entry(1); // point at maincpu bank
|
||||
m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); // hold subcpu in reset
|
||||
|
||||
for (auto &floppy : m_floppy)
|
||||
{
|
||||
floppy_image_device *device = floppy->get_device();
|
||||
if (device != nullptr)
|
||||
device->mon_w(0); // motors run all the time
|
||||
}
|
||||
|
||||
// PPI resets to input mode, which causes PPIC-3 to be pulled up to +5V, resetting disk CPU
|
||||
}
|
||||
|
||||
u32 sbrain_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
u32 sbrain_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
// PPIC-3 blanks entire display
|
||||
if (BIT(m_portc, 3))
|
||||
{
|
||||
bitmap.fill(rgb_t::black(), cliprect);
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 y,ra,chr,gfx;
|
||||
uint16_t sy=0,ma=0,x;
|
||||
m_framecnt++;
|
||||
uint16_t sy=0,x;
|
||||
|
||||
// Where attributes come from:
|
||||
// - Most systems use ram for character-based attributes, but this one uses strictly hardware which would seem cumbersome
|
||||
@ -497,39 +631,45 @@ u32 sbrain_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, con
|
||||
// - d5 blank from PC1 (scan-line based)
|
||||
// - d6 flash from bit 7 of each character
|
||||
|
||||
uint16_t ma = m_crtc->top_of_page();
|
||||
uint16_t cr = m_crtc->cursor_address();
|
||||
uint8_t *videoram = &m_ram->pointer()[m_ram->size() - 0x800];
|
||||
for (y = 0; y < 24; y++)
|
||||
{
|
||||
for (ra = 0; ra < 10; ra++)
|
||||
{
|
||||
uint16_t *p = &bitmap.pix16(sy++);
|
||||
uint32_t *p = &bitmap.pix32(sy++);
|
||||
|
||||
for (x = 0; x < 80; x++)
|
||||
{
|
||||
gfx = 0;
|
||||
if (ra < 9)
|
||||
if (ra > 0)
|
||||
{
|
||||
chr = m_p_videoram[x+ma];
|
||||
chr = videoram[(x + ma) & 0x7ff];
|
||||
|
||||
if (!BIT(chr, 7) || BIT(m_framecnt, 5))
|
||||
{
|
||||
chr &= 0x7f;
|
||||
|
||||
if (chr)
|
||||
gfx = m_p_chargen[(chr<<4) | ra ];
|
||||
gfx = m_p_chargen[(chr<<4) | (ra - 1)]; // ra hacked for incorrect character generator
|
||||
}
|
||||
}
|
||||
|
||||
if (((x + ma) & 0xfff) == cr)
|
||||
gfx ^= 0x7f;
|
||||
|
||||
/* Display a scanline of a character */
|
||||
*p++ = BIT(gfx, 6);
|
||||
*p++ = BIT(gfx, 5);
|
||||
*p++ = BIT(gfx, 4);
|
||||
*p++ = BIT(gfx, 3);
|
||||
*p++ = BIT(gfx, 2);
|
||||
*p++ = BIT(gfx, 1);
|
||||
*p++ = BIT(gfx, 0);
|
||||
*p++ = BIT(gfx, 6) ? rgb_t::white() : rgb_t::black();
|
||||
*p++ = BIT(gfx, 5) ? rgb_t::white() : rgb_t::black();
|
||||
*p++ = BIT(gfx, 4) ? rgb_t::white() : rgb_t::black();
|
||||
*p++ = BIT(gfx, 3) ? rgb_t::white() : rgb_t::black();
|
||||
*p++ = BIT(gfx, 2) ? rgb_t::white() : rgb_t::black();
|
||||
*p++ = BIT(gfx, 1) ? rgb_t::white() : rgb_t::black();
|
||||
*p++ = BIT(gfx, 0) ? rgb_t::white() : rgb_t::black();
|
||||
}
|
||||
}
|
||||
ma+=80;
|
||||
ma = (ma + 80) & 0xfff;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -539,27 +679,26 @@ MACHINE_CONFIG_START(sbrain_state::sbrain)
|
||||
MCFG_DEVICE_ADD("maincpu", Z80, 16_MHz_XTAL / 4)
|
||||
MCFG_DEVICE_PROGRAM_MAP(sbrain_mem)
|
||||
MCFG_DEVICE_IO_MAP(sbrain_io)
|
||||
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", sbrain_state, irq0_line_hold)
|
||||
|
||||
MCFG_DEVICE_ADD("subcpu", Z80, 16_MHz_XTAL / 4)
|
||||
MCFG_DEVICE_PROGRAM_MAP(sbrain_submem)
|
||||
MCFG_DEVICE_IO_MAP(sbrain_subio)
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE(sbrain_state, sbrain)
|
||||
RAM(config, m_ram).set_default_size("64K").set_extra_options("32K");
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::amber())
|
||||
MCFG_SCREEN_UPDATE_DRIVER(sbrain_state, screen_update)
|
||||
MCFG_SCREEN_PALETTE("palette")
|
||||
|
||||
MCFG_PALETTE_ADD_MONOCHROME("palette")
|
||||
|
||||
DP8350(config, m_crtc, 10.92_MHz_XTAL).set_screen("screen");
|
||||
DP8350(config, m_crtc, 10.92_MHz_XTAL).set_screen("screen"); // XTAL not directly connected
|
||||
m_crtc->character_generator_program(1);
|
||||
m_crtc->lrc_callback().set(FUNC(sbrain_state::crtc_lrc_w));
|
||||
m_crtc->vblank_callback().set(FUNC(sbrain_state::crtc_vblank_w));
|
||||
m_crtc->vsync_callback().set(FUNC(sbrain_state::crtc_vsync_w));
|
||||
|
||||
/* sound hardware */
|
||||
SPEAKER(config, "mono").front_center();
|
||||
MCFG_DEVICE_ADD("beeper", BEEP, 800)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
|
||||
BEEP(config, m_beep, 800).add_route(ALL_OUTPUTS, "mono", 1.00);
|
||||
|
||||
/* Devices */
|
||||
I8255(config, m_ppi);
|
||||
@ -570,29 +709,45 @@ MACHINE_CONFIG_START(sbrain_state::sbrain)
|
||||
m_ppi->in_pc_callback().set(FUNC(sbrain_state::ppi_pc_r));
|
||||
m_ppi->out_pc_callback().set(FUNC(sbrain_state::ppi_pc_w));
|
||||
|
||||
I8251(config, m_u0, 0);
|
||||
I8251(config, m_usart[0], 16_MHz_XTAL / 8);
|
||||
m_usart[0]->txd_handler().set("auxport", FUNC(rs232_port_device::write_txd));
|
||||
|
||||
I8251(config, m_u1, 0);
|
||||
I8251(config, m_usart[1], 16_MHz_XTAL / 8);
|
||||
m_usart[1]->txd_handler().set(m_mainport, FUNC(rs232_port_device::write_txd));
|
||||
m_usart[1]->rts_handler().set(m_mainport, FUNC(rs232_port_device::write_rts));
|
||||
m_usart[1]->dtr_handler().set(m_mainport, FUNC(rs232_port_device::write_dtr));
|
||||
|
||||
RS232_PORT(config, m_mainport, default_rs232_devices, nullptr);
|
||||
m_mainport->rxd_handler().set(m_usart[1], FUNC(i8251_device::write_rxd));
|
||||
m_mainport->cts_handler().set(m_usart[1], FUNC(i8251_device::write_cts));
|
||||
m_mainport->dsr_handler().set(m_usart[1], FUNC(i8251_device::write_dsr));
|
||||
m_mainport->txc_handler().set(FUNC(sbrain_state::external_txc_w));
|
||||
m_mainport->rxc_handler().set(FUNC(sbrain_state::external_rxc_w));
|
||||
|
||||
rs232_port_device &auxport(RS232_PORT(config, "auxport", default_rs232_devices, nullptr));
|
||||
auxport.rxd_handler().set(m_usart[0], FUNC(i8251_device::write_rxd));
|
||||
auxport.dsr_handler().set(m_usart[0], FUNC(i8251_device::write_dsr));
|
||||
|
||||
com8116_device &brg(COM8116(config, "brg", 5.0688_MHz_XTAL)); // BR1941L
|
||||
brg.fr_handler().set(m_u0, FUNC(i8251_device::write_txc));
|
||||
brg.fr_handler().append(m_u0, FUNC(i8251_device::write_rxc));
|
||||
brg.ft_handler().set(m_u1, FUNC(i8251_device::write_txc));
|
||||
brg.ft_handler().append(m_u1, FUNC(i8251_device::write_rxc));
|
||||
brg.fr_handler().set(m_usart[0], FUNC(i8251_device::write_txc));
|
||||
brg.fr_handler().append(m_usart[0], FUNC(i8251_device::write_rxc));
|
||||
brg.ft_handler().set(FUNC(sbrain_state::internal_txc_rxc_w));
|
||||
|
||||
FD1791(config, m_fdc, 16_MHz_XTAL / 16);
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:0", sbrain_floppies, "525dd", floppy_image_device::default_floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_SOUND(true)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:1", sbrain_floppies, "525dd", floppy_image_device::default_floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_SOUND(true)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:2", sbrain_floppies, nullptr, floppy_image_device::default_floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_SOUND(true)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:3", sbrain_floppies, nullptr, floppy_image_device::default_floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_SOUND(true)
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer_a", sbrain_state, kbd_scan, attotime::from_hz(15))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START( sbrain )
|
||||
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
|
||||
|
||||
ROM_REGION( 0x10000, "subcpu", ROMREGION_ERASEFF )
|
||||
ROM_REGION( 0x0800, "subcpu", ROMREGION_ERASEFF ) // only the second CPU has its own ROM
|
||||
ROM_SYSTEM_BIOS( 0, "4_003", "4.003" )
|
||||
ROMX_LOAD("4_003_vc8001.z69", 0x0000, 0x0800, CRC(3ce3cd53) SHA1(fb6ade6bd67de3d9f911a1a48481ca619bda65ae), ROM_BIOS(0))
|
||||
ROM_SYSTEM_BIOS( 1, "3_1", "3.1" )
|
||||
@ -604,4 +759,4 @@ ROM_START( sbrain )
|
||||
ROM_LOAD("c10_char.bin", 0x0000, 0x2000, BAD_DUMP CRC(cb530b6f) SHA1(95590bbb433db9c4317f535723b29516b9b9fcbf))
|
||||
ROM_END
|
||||
|
||||
COMP( 1981, sbrain, 0, 0, sbrain, sbrain, sbrain_state, init_sbrain, "Intertec", "Superbrain", MACHINE_NOT_WORKING )
|
||||
COMP( 1981, sbrain, 0, 0, sbrain, sbrain, sbrain_state, empty_init, "Intertec Data Systems", "SuperBrain Video Computer System", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user