mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
don't use my ill-conceived generator for arcompact, easier to work with as regular files (nw)
This commit is contained in:
DavidHaywood
parent
d35c39bb16
commit
639a5c1fe6
@ -113,14 +113,6 @@ if (CPUS["ARCOMPACT"]~=null) then
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MAME_DIR .. "src/devices/cpu/arcompact/arcompact.h",
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MAME_DIR .. "src/devices/cpu/arcompact/arcompact_execute.cpp",
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}
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dependency {
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{ MAME_DIR .. "src/devices/cpu/arcompact/arcompact.cpp", GEN_DIR .. "emu/cpu/arcompact/arcompact.hxx" },
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{ MAME_DIR .. "src/devices/cpu/arcompact/arcompact_execute.cpp", GEN_DIR .. "emu/cpu/arcompact/arcompact.hxx" },
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}
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custombuildtask {
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{ MAME_DIR .. "src/devices/cpu/arcompact/arcompact_make.py" , GEN_DIR .. "emu/cpu/arcompact/arcompact.hxx", { MAME_DIR .. "src/devices/cpu/arcompact/arcompact_make.py" }, {"@echo Generating ARCOMPACT source files...", PYTHON .. " $(1) $(@)" }},
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}
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end
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if (CPUS["ARCOMPACT"]~=null or _OPTIONS["with-tools"]) then
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File diff suppressed because it is too large
Load Diff
@ -1,435 +0,0 @@
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#!/usr/bin/python
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# license:BSD-3-Clause
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# copyright-holders:David Haywood
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from __future__ import print_function
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import sys
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def EmitGroup04_Handle_NZ_Flags(f, funcname, opname):
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print(" if (result & 0x80000000) { STATUS32_SET_N; }", file=f)
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print(" else { STATUS32_CLEAR_N; }", file=f)
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print(" if (result == 0x00000000) { STATUS32_SET_Z; }", file=f)
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print(" else { STATUS32_CLEAR_Z; }", file=f)
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def EmitGroup04_Handle_NZC_LSR1_Flags(f, funcname, opname):
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print(" if (result & 0x80000000) { STATUS32_SET_N; }", file=f)
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print(" else { STATUS32_CLEAR_N; }", file=f)
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print(" if (result == 0x00000000) { STATUS32_SET_Z; }", file=f)
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print(" else { STATUS32_CLEAR_Z; }", file=f)
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print(" if (c == 0x00000001) { STATUS32_SET_C; }", file=f)
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print(" else { STATUS32_CLEAR_C; }", file=f)
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def EmitGroup04_Handle_NZCV_ADD_Flags(f, funcname, opname):
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print(" if (result & 0x80000000) { STATUS32_SET_N; }", file=f)
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print(" else { STATUS32_CLEAR_N; }", file=f)
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print(" if (result == 0x00000000) { STATUS32_SET_Z; }", file=f)
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print(" else { STATUS32_CLEAR_Z; }", file=f)
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print(" if ((b & 0x80000000) == (c & 0x80000000))", file=f)
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print(" {", file=f)
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print(" if ((result & 0x80000000) != (b & 0x80000000))", file=f)
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print(" {", file=f)
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print(" STATUS32_SET_V;", file=f)
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print(" }", file=f)
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print(" else", file=f)
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print(" {", file=f)
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print(" STATUS32_CLEAR_V;", file=f)
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print(" }", file=f)
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print(" }", file=f)
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print(" if (b < c)", file=f)
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print(" {", file=f)
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print(" STATUS32_SET_C;", file=f)
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print(" }", file=f)
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print(" else", file=f)
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print(" {", file=f)
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print(" STATUS32_CLEAR_C;", file=f)
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print(" }", file=f)
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def EmitGroup04_no_Flags(f, funcname, opname):
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print(" // no flag changes", file=f)
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def EmitGroup04_unsupported_Flags(f, funcname, opname):
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print(" arcompact_fatal(\"arcompact_handle%s (%s) (F set)\\n\"); // not yet supported" % (funcname, opname), file=f)
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def EmitGroup04_Flaghandler(f,funcname, opname, flagcondition, flaghandler):
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if flagcondition == -1:
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print(" if (F)", file=f)
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print(" {", file=f)
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flaghandler(f, funcname, opname)
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print(" }", file=f)
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elif flagcondition == 0:
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print(" if (0)", file=f)
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print(" {", file=f)
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flaghandler(f, funcname, opname)
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print(" }", file=f)
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elif flagcondition == 1:
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print(" if (1)", file=f)
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print(" {", file=f)
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flaghandler(f, funcname, opname)
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print(" }", file=f)
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def EmitGroup04_u5fragment(f,funcname, opname, opexecute, opwrite, opwrite_alt, ignore_a, breg_is_dst_only, flagcondition, flaghandler):
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print(" int size = 4;", file=f)
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if breg_is_dst_only == 0:
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print(" uint32_t limm = 0;", file=f)
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print("/* int got_limm = 0; */", file=f)
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print(" ", file=f)
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print(" COMMON32_GET_breg;", file=f)
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if flagcondition == -1:
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print(" COMMON32_GET_F;", file=f)
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print(" COMMON32_GET_u6;", file=f)
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if ignore_a == 0:
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print(" COMMON32_GET_areg;", file=f)
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elif ignore_a == 1:
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print(" //COMMON32_GET_areg; // areg is reserved / not used", file=f)
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elif ignore_a == 2:
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print(" //COMMON32_GET_areg; // areg bits already used as opcode select", file=f)
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elif ignore_a == 3:
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print(" //COMMON32_GET_areg; // areg bits already used as condition code select", file=f)
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print(" ", file=f)
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print(" uint32_t c;", file=f)
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if breg_is_dst_only == 0:
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print(" uint32_t b;", file=f)
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print(" ", file=f)
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print(" /* is having b as LIMM valid here? LIMM vs. fixed u6 value makes no sense */", file=f)
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print(" if (breg == LIMM_REG)", file=f)
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print(" {", file=f)
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print(" GET_LIMM_32;", file=f)
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print(" size = 8;", file=f)
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print("/* got_limm = 1; */", file=f)
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print(" b = limm;", file=f)
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print(" }", file=f)
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print(" else", file=f)
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print(" {", file=f)
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print(" b = m_regs[breg];", file=f)
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print(" }", file=f)
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print(" ", file=f)
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print(" c = u;", file=f)
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print(" ", file=f)
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print(" /* todo: if areg = LIMM then there is no result (but since that register can never be read, I guess it doesn't matter if we store it there anyway?) */", file=f)
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def EmitGroup04(f,funcname, opname, opexecute, opwrite, opwrite_alt, ignore_a, breg_is_dst_only, flagcondition, flaghandler):
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# the mode 0x00 handler
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s_p00(OPS_32)" % funcname, file=f)
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print("{", file=f)
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print(" int size = 4;", file=f)
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print(" uint32_t limm = 0;", file=f)
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print(" int got_limm = 0;", file=f)
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print(" ", file=f)
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print(" COMMON32_GET_breg;", file=f)
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if flagcondition == -1:
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print(" COMMON32_GET_F;", file=f)
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print(" COMMON32_GET_creg;", file=f)
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if ignore_a == 0:
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print(" COMMON32_GET_areg;", file=f)
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elif ignore_a == 1:
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print(" //COMMON32_GET_areg; // areg is reserved / not used", file=f)
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elif ignore_a == 2:
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print(" //COMMON32_GET_areg; // areg bits already used as opcode select", file=f)
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print(" ", file=f)
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print(" uint32_t c;", file=f)
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if breg_is_dst_only == 0:
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print(" uint32_t b;", file=f)
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print(" ", file=f)
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print(" if (breg == LIMM_REG)", file=f)
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print(" {", file=f)
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print(" GET_LIMM_32;", file=f)
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print(" size = 8;", file=f)
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print(" got_limm = 1;", file=f)
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print(" b = limm;", file=f)
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print(" }", file=f)
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print(" else", file=f)
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print(" {", file=f)
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print(" b = m_regs[breg];", file=f)
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print(" }", file=f)
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print(" ", file=f)
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print(" if (creg == LIMM_REG)", file=f)
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print(" {", file=f)
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print(" if (!got_limm)", file=f)
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print(" {", file=f)
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print(" GET_LIMM_32;", file=f)
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print(" size = 8;", file=f)
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print(" }", file=f)
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print(" c = limm;", file=f)
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print(" }", file=f)
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print(" else", file=f)
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print(" {", file=f)
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print(" c = m_regs[creg];", file=f)
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print(" }", file=f)
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print(" /* todo: is the limm, limm syntax valid? (it's pointless.) */", file=f)
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print(" /* todo: if areg = LIMM then there is no result (but since that register can never be read, I guess it doesn't matter if we store it there anyway?) */", file=f)
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print(" %s" % opexecute, file=f)
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print(" %s" % opwrite, file=f)
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print(" ", file=f)
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EmitGroup04_Flaghandler(f,funcname,opname,flagcondition,flaghandler)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# the mode 0x01 handler
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s_p01(OPS_32)" % funcname, file=f)
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print("{", file=f)
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EmitGroup04_u5fragment(f,funcname, opname, opexecute, opwrite, opwrite_alt, ignore_a, breg_is_dst_only, flagcondition, flaghandler)
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print(" %s" % opexecute, file=f)
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print(" %s" % opwrite, file=f)
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print(" ", file=f)
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EmitGroup04_Flaghandler(f,funcname,opname,flagcondition,flaghandler)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# the mode 0x10 handler
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s_p10(OPS_32)" % funcname, file=f)
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if ignore_a == 2:
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print("{", file=f)
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print(" int size = 4;", file=f)
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print(" arcompact_fatal(\"illegal arcompact_handle%s_p10 (ares bits already used as opcode select, can't be used as s12) (%s)\\n\");" % (funcname, opname), file=f)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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else:
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print("{", file=f)
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print(" int size = 4;", file=f)
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if breg_is_dst_only == 0:
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print(" uint32_t limm = 0;", file=f)
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print("/* int got_limm = 0; */", file=f)
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print(" ", file=f)
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print(" COMMON32_GET_breg;", file=f)
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if flagcondition == -1:
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print(" COMMON32_GET_F;", file=f)
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print(" COMMON32_GET_s12;", file=f)
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# areg can't be used here, it's used for s12 bits
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print(" ", file=f)
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print(" uint32_t c;", file=f)
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if breg_is_dst_only == 0:
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print(" uint32_t b;", file=f)
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print(" ", file=f)
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print(" /* is having b as LIMM valid here? LIMM vs. fixed u6 value makes no sense */", file=f)
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print(" if (breg == LIMM_REG)", file=f)
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print(" {", file=f)
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print(" GET_LIMM_32;", file=f)
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print(" size = 8;", file=f)
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print("/* got_limm = 1; */", file=f)
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print(" b = limm;", file=f)
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print(" }", file=f)
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print(" else", file=f)
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print(" {", file=f)
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print(" b = m_regs[breg];", file=f)
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print(" }", file=f)
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print(" ", file=f)
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print(" c = (uint32_t)S;", file=f)
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print(" ", file=f)
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print(" /* todo: if areg = LIMM then there is no result (but since that register can never be read, I guess it doesn't matter if we store it there anyway?) */", file=f)
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print(" %s" % opexecute, file=f)
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print(" %s" % opwrite_alt, file=f)
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print(" ", file=f)
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EmitGroup04_Flaghandler(f,funcname,opname,flagcondition,flaghandler)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# the mode 0x11 m0 handler
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s_p11_m0(OPS_32)" % funcname, file=f)
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if ignore_a == 2:
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print("{", file=f)
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print(" int size = 4;", file=f)
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print(" arcompact_fatal(\"illegal arcompact_handle%s_p11_m0 (ares bits already used as opcode select, can't be used as Q condition) (%s)\\n\");" % (funcname, opname), file=f)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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else:
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print("{", file=f)
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print(" int size = 4;", file=f)
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print(" arcompact_fatal(\"arcompact_handle%s_p11_m0 (%s)\\n\");" % (funcname, opname), file=f)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# the mode 0x11 m1 handler
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s_p11_m1(OPS_32)" % funcname, file=f)
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if ignore_a == 2:
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print("{", file=f)
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print(" int size = 4;", file=f)
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print(" arcompact_fatal(\"illegal arcompact_handle%s_p11_m1 (ares bits already used as opcode select, can't be used as Q condition) (%s)\\n\");" % (funcname, opname), file=f)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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else:
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print("{", file=f)
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EmitGroup04_u5fragment(f,funcname, opname, opexecute, opwrite, opwrite_alt, 3, breg_is_dst_only, flagcondition, flaghandler)
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print(" COMMON32_GET_CONDITION;", file=f)
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print(" if (!check_condition(condition))", file=f)
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print(" return m_pc + (size>>0);", file=f)
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print("", file=f)
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print(" %s" % opexecute, file=f)
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print(" %s" % opwrite_alt, file=f)
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print(" ", file=f)
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EmitGroup04_Flaghandler(f,funcname,opname,flagcondition,flaghandler)
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print(" return m_pc + (size >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# xxx_S c, b, u3 format opcodes (note c is destination)
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def EmitGroup0d(f,funcname, opname, opexecute, opwrite):
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s(OPS_16)" % funcname, file=f)
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print("{", file=f)
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print(" int u, breg, creg;", file=f)
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print("", file=f)
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print(" COMMON16_GET_u3;", file=f)
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print(" COMMON16_GET_breg;", file=f)
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print(" COMMON16_GET_creg;", file=f)
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print("", file=f)
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print(" REG_16BIT_RANGE(breg);", file=f)
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print(" REG_16BIT_RANGE(creg);", file=f)
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print("", file=f)
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print(" %s" % opexecute, file=f)
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print(" %s" % opwrite, file=f)
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print("", file=f)
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print(" return m_pc + (2 >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# xxx_S b <- b,c format opcodes
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def EmitGroup0f(f,funcname, opname, opexecute, opwrite):
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s(OPS_16)"% funcname, file=f)
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print("{", file=f)
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print(" int breg, creg;", file=f)
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print("", file=f)
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print(" COMMON16_GET_breg;", file=f)
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print(" COMMON16_GET_creg;", file=f)
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print("", file=f)
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print(" REG_16BIT_RANGE(breg);", file=f)
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print(" REG_16BIT_RANGE(creg);", file=f)
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print("", file=f)
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print(" %s" % opexecute, file=f)
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print(" %s" % opwrite, file=f)
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print("", file=f)
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print(" return m_pc + (2 >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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# xxx_S b, b, u5 format opcodes
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def EmitGroup17(f,funcname, opname, opexecute):
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print("ARCOMPACT_RETTYPE arcompact_device::arcompact_handle%s(OPS_16)" % funcname, file=f)
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print("{", file=f)
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print(" int breg, u;", file=f)
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print(" ", file=f)
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print(" COMMON16_GET_breg;", file=f)
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print(" COMMON16_GET_u5;", file=f)
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print(" ", file=f)
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print(" REG_16BIT_RANGE(breg);", file=f)
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print(" ", file=f)
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print(" %s" % opexecute, file=f)
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print(" ", file=f)
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print(" return m_pc + (2 >> 0);", file=f)
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print("}", file=f)
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print("", file=f)
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print("", file=f)
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try:
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f = open(sys.argv[1], "w")
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except Exception:
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err = sys.exc_info()[1]
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||||
sys.stderr.write("cannot write file %s [%s]\n" % (sys.argv[1], err))
|
||||
sys.exit(1)
|
||||
|
||||
|
||||
EmitGroup04(f, "04_00", "ADD", "uint32_t result = b + c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_Handle_NZCV_ADD_Flags )
|
||||
|
||||
EmitGroup04(f, "04_02", "SUB", "uint32_t result = b - c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
|
||||
EmitGroup04(f, "04_04", "AND", "uint32_t result = b & c;", "if (areg != LIMM_REG) { m_regs[areg] = result; }", "if (breg != LIMM_REG) { m_regs[breg] = result; }", 0,0, -1, EmitGroup04_Handle_NZ_Flags )
|
||||
EmitGroup04(f, "04_05", "OR", "uint32_t result = b | c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_06", "BIC", "uint32_t result = b & (~c);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_07", "XOR", "uint32_t result = b ^ c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
|
||||
EmitGroup04(f, "04_0a", "MOV", "uint32_t result = c;", "m_regs[breg] = result;", "m_regs[breg] = result;", 1,1, -1, EmitGroup04_Handle_NZ_Flags ) # special case, result always goes to breg
|
||||
|
||||
EmitGroup04(f, "04_0e", "RSUB", "uint32_t result = c - b;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_0f", "BSET", "uint32_t result = b | (1 << (c & 0x1f));", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
|
||||
EmitGroup04(f, "04_13", "BMSK", "uint32_t result = b & ((1<<(c+1))-1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
|
||||
|
||||
EmitGroup04(f, "04_14", "ADD1", "uint32_t result = b + (c << 1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_15", "ADD2", "uint32_t result = b + (c << 2);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_16", "ADD3", "uint32_t result = b + (c << 3);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_17", "SUB1", "uint32_t result = b - (c << 1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_18", "SUB2", "uint32_t result = b - (c << 2);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "04_19", "SUB3", "uint32_t result = b - (c << 3);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
|
||||
EmitGroup04(f, "04_2a", "LR", "m_regs[breg] = READAUX(c);", "", "", 1,1, -1, EmitGroup04_no_Flags ) # this can't be conditional (todo)
|
||||
EmitGroup04(f, "04_2b", "SR", "WRITEAUX(c,b);", "", "", 1,0, -1, EmitGroup04_no_Flags ) # this can't be conditional (todo)
|
||||
|
||||
|
||||
|
||||
EmitGroup04(f, "05_00", "ASL", "uint32_t result = b << (c&0x1f);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
EmitGroup04(f, "05_01", "LSR", "uint32_t result = b >> (c&0x1f);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
|
||||
|
||||
# the 04_2f subgroup uses the same encoding, but the areg is already used as sub-opcode select, so any modes relying on areg bits for other reasons (sign, condition) (modes 10, 11m0, 11m1) are illegal. the destination is also breg not areg
|
||||
EmitGroup04(f, "04_2f_02", "LSR1", "uint32_t result = c >> 1;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_Handle_NZC_LSR1_Flags ) # no alt handler (invalid path)
|
||||
EmitGroup04(f, "04_2f_03", "ROR", "int shift = 1; uint32_t mask = (1 << (shift)) - 1; mask <<= (32-shift); uint32_t result = ((c >> shift) & ~mask) | ((c << (32-shift)) & mask);", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_Handle_NZC_LSR1_Flags )
|
||||
|
||||
|
||||
EmitGroup04(f, "04_2f_07", "EXTB", "uint32_t result = c & 0x000000ff;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_unsupported_Flags ) # ^
|
||||
EmitGroup04(f, "04_2f_08", "EXTW", "uint32_t result = c & 0x0000ffff;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_unsupported_Flags ) # ^
|
||||
|
||||
# xxx_S c, b, u3 format opcodes (note c is destination)
|
||||
EmitGroup0d(f, "0d_00", "ADD_S", "uint32_t result = m_regs[breg] + u;", "m_regs[creg] = result;" )
|
||||
EmitGroup0d(f, "0d_01", "SUB_S", "uint32_t result = m_regs[breg] - u;", "m_regs[creg] = result;" )
|
||||
EmitGroup0d(f, "0d_02", "ASL_S", "uint32_t result = m_regs[breg] << u;", "m_regs[creg] = result;" )
|
||||
|
||||
# xxx_S b <- b,c format opcodes (or in some cases xxx_S b,c)
|
||||
EmitGroup0f(f, "0f_02", "SUB_S", "uint32_t result = m_regs[breg] - m_regs[creg];", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_04", "AND_S", "uint32_t result = m_regs[breg] & m_regs[creg];", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_05", "OR_S", "uint32_t result = m_regs[breg] | m_regs[creg];", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_07", "XOR_S", "uint32_t result = m_regs[breg] ^ m_regs[creg];", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_0f", "EXTB_S","uint32_t result = m_regs[creg] & 0x000000ff;", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_10", "EXTW_S","uint32_t result = m_regs[creg] & 0x0000ffff;", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_13", "NEG_S"," uint32_t result = 0 - m_regs[creg];", "m_regs[breg] = result;" )
|
||||
|
||||
EmitGroup0f(f, "0f_14", "ADD1_S"," uint32_t result = m_regs[breg] + (m_regs[creg] <<1);", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_15", "ADD2_S"," uint32_t result = m_regs[breg] + (m_regs[creg] <<2);", "m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_16", "ADD3_S"," uint32_t result = m_regs[breg] + (m_regs[creg] <<3);", "m_regs[breg] = result;" )
|
||||
|
||||
EmitGroup0f(f, "0f_19", "LSR_S", "uint32_t result = m_regs[breg] >> (m_regs[creg]&0x1f);","m_regs[breg] = result;" )
|
||||
EmitGroup0f(f, "0f_1b", "ASL1_S","uint32_t result = m_regs[creg] << 1;", "m_regs[breg] = result;" )
|
||||
|
||||
|
||||
# xxx_S b, b, u5 format opcodes
|
||||
EmitGroup17(f, "17_00", "ASL_S", "m_regs[breg] = m_regs[breg] << (u&0x1f);" )
|
||||
EmitGroup17(f, "17_01", "LSR_S", "m_regs[breg] = m_regs[breg] >> (u&0x1f);" )
|
||||
EmitGroup17(f, "17_02", "ASR_S", "int32_t temp = (int32_t)m_regs[breg]; m_regs[breg] = temp >> (u&0x1f); // treat it as a signed value, so sign extension occurs during shift" )
|
||||
EmitGroup17(f, "17_03", "SUB_S", "m_regs[breg] = m_regs[breg] - u;" )
|
||||
EmitGroup17(f, "17_04", "BSET_S", "m_regs[breg] = m_regs[breg] | (1 << (u & 0x1f));" )
|
||||
|
||||
EmitGroup17(f, "17_06", "BMSK_S", "m_regs[breg] = m_regs[breg] | ((1 << (u + 1)) - 1);" )
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user