mirror of
https://github.com/holub/mame
synced 2025-04-20 15:32:45 +03:00
-cpu/uml.cpp: Rewrote the UML simplification code.
* Fixed many cases that could cause the upper bits of a register not to cleared following a 32-bit operation. * Added more simplifications. * Allow many simplifications when flag updates are requested. * Fixed various bits of unreachable code. * cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed code for special-casing some situations the simplifier can now take care of consistently. -cpu/drcbex64.cpp: Fixed a bug causing some shifts to be treated as a no-op when the destination and source are not the same. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Added a special case for comparing something to itself. -cpu/e132xs: Use the CARRY instruction rather than a right shift to set up carry in.
This commit is contained in:
Vas Crabb
parent
113d351625
commit
63be095e58
@ -3718,23 +3718,32 @@ void drcbe_arm64::op_cmp(a64::Assembler &a, const uml::instruction &inst)
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be_parameter src1p(*this, inst.param(0), PTYPE_MRI);
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be_parameter src2p(*this, inst.param(1), PTYPE_MRI);
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const a64::Gp src1 = src1p.select_register(TEMP_REG1, inst.size());
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mov_reg_param(a, inst.size(), src1, src1p);
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if (src2p.is_immediate() && is_valid_immediate_addsub(src2p.immediate()))
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if (src1p == src2p)
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{
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if (src2p.is_immediate_value(0))
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a.cmp(src1, select_register(a64::xzr, inst.size()));
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else
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a.cmp(src1, src2p.immediate());
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const a64::Gp zero = select_register(a64::xzr, inst.size());
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a.cmp(zero, zero);
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}
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else
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{
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const a64::Gp src2 = src2p.select_register(TEMP_REG2, inst.size());
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const a64::Gp src1 = src1p.select_register(TEMP_REG1, inst.size());
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mov_reg_param(a, inst.size(), src2, src2p);
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a.cmp(src1, src2);
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mov_reg_param(a, inst.size(), src1, src1p);
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if (src2p.is_immediate() && is_valid_immediate_addsub(src2p.immediate()))
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{
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if (src2p.is_immediate_value(0))
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a.cmp(src1, select_register(a64::xzr, inst.size()));
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else
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a.cmp(src1, src2p.immediate());
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}
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else
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{
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const a64::Gp src2 = src2p.select_register(TEMP_REG2, inst.size());
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mov_reg_param(a, inst.size(), src2, src2p);
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a.cmp(src1, src2);
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}
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}
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if (inst.flags() & FLAG_C)
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@ -4087,12 +4096,6 @@ void drcbe_arm64::op_and(a64::Assembler &a, const uml::instruction &inst)
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be_parameter src1p(*this, inst.param(1), PTYPE_MRI);
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be_parameter src2p(*this, inst.param(2), PTYPE_MRI);
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if (src1p.is_immediate() || (dstp.is_int_register() && (dstp == src2p)))
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{
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using std::swap;
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swap(src1p, src2p);
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}
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const a64::Gp dst = dstp.select_register(TEMP_REG3, inst.size());
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const a64::Gp src1 = src1p.select_register(dst, inst.size());
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@ -4210,12 +4213,6 @@ void drcbe_arm64::op_or(a64::Assembler &a, const uml::instruction &inst)
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be_parameter src1p(*this, inst.param(1), PTYPE_MRI);
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be_parameter src2p(*this, inst.param(2), PTYPE_MRI);
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if (src1p.is_immediate() || (dstp.is_int_register() && (dstp == src2p)))
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{
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using std::swap;
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swap(src1p, src2p);
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}
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const a64::Gp dst = dstp.select_register(TEMP_REG3, inst.size());
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const a64::Gp src1 = src1p.select_register(dst, inst.size());
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@ -4274,12 +4271,6 @@ void drcbe_arm64::op_xor(a64::Assembler &a, const uml::instruction &inst)
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be_parameter src1p(*this, inst.param(1), PTYPE_MRI);
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be_parameter src2p(*this, inst.param(2), PTYPE_MRI);
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if (src1p.is_immediate() || (dstp.is_int_register() && (dstp == src2p)))
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{
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using std::swap;
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swap(src1p, src2p);
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}
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const a64::Gp dst = dstp.select_register(TEMP_REG3, inst.size());
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const a64::Gp src1 = src1p.select_register(dst, inst.size());
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@ -1395,11 +1395,13 @@ void drcbe_x64::alu_op_param(Assembler &a, Inst::Id const opcode, Operand const
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if (is64 && !short_immediate(param.immediate()))
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{
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// use scratch register for 64-bit immediate
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a.mov(r11, param.immediate()); // mov r11,param
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a.emit(opcode, dst, r11); // op dst,r11
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a.mov(r11, param.immediate());
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a.emit(opcode, dst, r11);
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}
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else
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a.emit(opcode, dst, param.immediate()); // op dst,param
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{
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a.emit(opcode, dst, param.immediate());
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}
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}
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}
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else if (param.is_memory())
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@ -1407,7 +1409,7 @@ void drcbe_x64::alu_op_param(Assembler &a, Inst::Id const opcode, Operand const
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if (dst.isMem())
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{
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// use temporary register for memory,memory
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Gp const tmp = is64 ? param.select_register(rax) : param.select_register(eax);
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Gp const tmp = param.select_register(is64 ? Gp(rax) : Gp(eax));
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a.mov(tmp, MABS(param.memory()));
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a.emit(opcode, dst, tmp);
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@ -1555,7 +1557,7 @@ void drcbe_x64::shift_op_param(Assembler &a, Inst::Id const opcode, size_t opsiz
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if (bitshift)
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a.emit(opcode, dst, imm(param.immediate()));
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else if (update_flags & FLAG_C)
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else if (!carryin && (update_flags & FLAG_C))
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a.clc(); // throw away carry since it'll never be used
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if (update_flags & (FLAG_S | FLAG_Z))
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@ -1594,8 +1596,7 @@ void drcbe_x64::shift_op_param(Assembler &a, Inst::Id const opcode, size_t opsiz
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if (carryin)
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a.mov(rax, r10);
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if (update_flags & FLAG_C)
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else if (update_flags & FLAG_C)
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a.clc(); // throw away carry since it'll never be used
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a.short_().jmp(end);
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@ -3832,11 +3833,7 @@ void drcbe_x64::op_roland(Assembler &a, const instruction &inst)
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// pick a target register
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Gp dstreg = dstp.select_register((inst.size() == 4) ? Gp(eax) : Gp(rax), maskp);
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if (maskp.is_immediate_value(0))
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{
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a.xor_(dstreg, dstreg);
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}
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else if (shiftp.is_immediate() && (srcp.is_immediate() || maskp.is_immediate()))
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if (shiftp.is_immediate() && (srcp.is_immediate() || maskp.is_immediate()))
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{
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const unsigned shift = shiftp.immediate() & (bits - 1);
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const uint64_t sizemask = util::make_bitmask<uint64_t>(bits);
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@ -3875,55 +3872,33 @@ void drcbe_x64::op_roland(Assembler &a, const instruction &inst)
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{
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const uint64_t mask = maskp.immediate() & sizemask;
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mov_reg_param(a, dstreg, srcp);
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if (mask == sizemask)
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a.rol(dstreg, shift);
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if (!inst.flags() && (mask == 0x000000ff))
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{
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if (shift)
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a.rol(dstreg, shift);
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if (inst.flags())
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a.test(dstreg, dstreg);
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a.movzx(dstreg, dstreg.r8());
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}
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else if (mask == (util::make_bitmask<uint64_t>(shift) & sizemask))
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else if (!inst.flags() && (mask == 0x0000ffff))
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{
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a.shr(dstreg, bits - shift);
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if (inst.flags())
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a.test(dstreg, dstreg);
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a.movzx(dstreg, dstreg.r16());
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}
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else if (mask == (~util::make_bitmask<uint64_t>(shift) & sizemask))
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else if (!inst.flags() && (mask == 0xffffffff))
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{
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a.shl(dstreg, shift);
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a.mov(dstreg.r32(), dstreg.r32());
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}
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else if ((bits == 32) || (util::sext(mask, 32) == mask))
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{
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a.and_(dstreg, mask);
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}
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else if (uint32_t(mask) == mask)
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{
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a.and_(dstreg, mask); // asmjit converts this to a DWORD-size operation
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if (inst.flags())
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a.test(dstreg, dstreg);
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}
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else
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{
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a.rol(dstreg, shift);
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if (!inst.flags() && (mask == 0x000000ff))
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{
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a.movzx(dstreg, dstreg.r8());
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}
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else if (!inst.flags() && (mask == 0x0000ffff))
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{
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a.movzx(dstreg, dstreg.r16());
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}
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else if (!inst.flags() && (mask == 0xffffffff))
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{
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a.mov(dstreg.r32(), dstreg.r32());
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}
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else if ((bits == 32) || (util::sext(mask, 32) == mask))
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{
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a.and_(dstreg, mask);
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}
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else if (uint32_t(mask) == mask)
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{
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a.and_(dstreg, mask);
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if (inst.flags())
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a.test(dstreg, dstreg);
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}
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else
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{
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a.mov(rdx, mask);
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a.and_(dstreg, rdx);
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}
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a.mov(rdx, mask);
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a.and_(dstreg, rdx);
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}
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}
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}
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@ -3940,19 +3915,7 @@ void drcbe_x64::op_roland(Assembler &a, const instruction &inst)
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mov_reg_param(a, dstreg, srcp);
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a.rol(dstreg, cl);
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}
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alu_op_param(a, Inst::kIdAnd, dstreg, maskp,
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[inst] (Assembler &a, Operand const &dst, be_parameter const &src)
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{
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// all-one cases
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if (ones(src.immediate(), inst.size()))
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{
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if (inst.flags())
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a.test(dst.as<Gp>(), dst.as<Gp>());
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return true;
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}
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return false;
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});
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alu_op_param(a, Inst::kIdAnd, dstreg, maskp);
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}
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mov_param_reg(a, dstp, dstreg);
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@ -3984,15 +3947,7 @@ void drcbe_x64::op_rolins(Assembler &a, const instruction &inst)
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const unsigned bits = inst.size() * 8;
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const uint64_t sizemask = util::make_bitmask<uint64_t>(bits);
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if (maskp.is_immediate_value(0))
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{
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if (inst.flags())
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{
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mov_reg_param(a, dstreg, dstp);
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a.test(dstreg, dstreg);
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}
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}
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else if (shiftp.is_immediate() && (srcp.is_immediate() || maskp.is_immediate()))
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if (shiftp.is_immediate() && (srcp.is_immediate() || maskp.is_immediate()))
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{
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const unsigned shift = shiftp.immediate() & (bits - 1);
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if (srcp.is_immediate())
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@ -4006,68 +3961,53 @@ void drcbe_x64::op_rolins(Assembler &a, const instruction &inst)
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{
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const uint64_t mask = maskp.immediate() & sizemask;
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src &= mask;
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if (mask == sizemask)
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bool flags = false;
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mov_reg_param(a, dstreg, dstp);
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if (mask == 0xffffffff'00000000)
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{
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if (src)
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{
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a.mov(dstreg, src);
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if (inst.flags())
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a.test(dstreg, dstreg);
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}
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else
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{
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a.xor_(dstreg, dstreg);
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}
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a.mov(dstreg.r32(), dstreg.r32());
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}
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else if (mask == (0xffffffff'ffff0000 & sizemask))
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{
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a.movzx(dstreg, dstreg.r16());
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}
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else if (mask == (0xffffffff'ffffff00 & sizemask))
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{
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a.movzx(dstreg, dstreg.r8());
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}
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else if ((bits == 32) || (util::sext(~mask, 32) == ~mask))
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{
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a.and_(dstreg, ~mask);
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flags = true;
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}
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else if (uint32_t(~mask) == ~mask)
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{
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a.and_(dstreg, ~mask);
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}
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else
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{
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bool flags = false;
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mov_reg_param(a, dstreg, dstp);
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if (mask == 0xffffffff'00000000)
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a.mov(maskreg, ~mask);
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a.and_(dstreg, maskreg);
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flags = true;
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}
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if (src)
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{
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if ((bits == 32) || (util::sext(src, 32) == src))
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{
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a.mov(dstreg.r32(), dstreg.r32());
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}
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else if (mask == (0xffffffff'ffff0000 & sizemask))
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{
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a.movzx(dstreg, dstreg.r16());
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}
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else if (mask == (0xffffffff'ffffff00 & sizemask))
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{
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a.movzx(dstreg, dstreg.r8());
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}
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else if ((bits == 32) || (util::sext(~mask, 32) == ~mask))
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{
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a.and_(dstreg, ~mask);
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flags = true;
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}
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else if (uint32_t(~mask) == ~mask)
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{
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a.and_(dstreg, ~mask);
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a.or_(dstreg, src);
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}
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else
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{
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a.mov(maskreg, ~mask);
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a.and_(dstreg, maskreg);
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flags = true;
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}
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if (src)
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{
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if ((bits == 32) || (util::sext(src, 32) == src))
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{
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a.or_(dstreg, src);
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}
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else
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{
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a.mov(srcreg, src);
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a.or_(dstreg, srcreg);
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}
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}
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else if (!flags && inst.flags())
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{
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a.test(dstreg, dstreg);
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a.mov(srcreg, src);
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a.or_(dstreg, srcreg);
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}
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}
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else if (!flags && inst.flags())
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{
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a.test(dstreg, dstreg);
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}
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}
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else
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{
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@ -4101,110 +4041,100 @@ void drcbe_x64::op_rolins(Assembler &a, const instruction &inst)
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{
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// variables source, immediate mask
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const uint64_t mask = maskp.immediate() & sizemask;
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if (mask == sizemask)
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mov_reg_param(a, dstreg, dstp);
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bool maskloaded = false;
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if (!shift)
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{
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mov_reg_param(a, dstreg, srcp);
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if (shift)
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a.rol(dstreg, shift);
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if (inst.flags())
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a.test(dstreg, dstreg);
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if (mask == 0x00000000'000000ff)
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{
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if (srcp.is_int_register())
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a.movzx(srcreg, GpbLo(srcp.ireg()));
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else if (srcp.is_memory())
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a.movzx(srcreg, MABS(srcp.memory(), 1));
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}
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else if (mask == 0x00000000'0000ffff)
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{
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if (srcp.is_int_register())
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a.movzx(srcreg, Gpw(srcp.ireg()));
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else if (srcp.is_memory())
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a.movzx(srcreg, MABS(srcp.memory(), 2));
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}
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else if (mask == 0x00000000'ffffffff)
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{
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mov_reg_param(a, srcreg.r32(), srcp);
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}
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else
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{
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mov_reg_param(a, srcreg, srcp);
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a.and_(srcreg, mask);
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}
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}
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else if (mask == (util::make_bitmask<uint64_t>(shift) & sizemask))
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{
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mov_reg_param(a, srcreg, srcp);
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a.shr(srcreg, bits - shift);
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}
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else if (mask == (~util::make_bitmask<uint64_t>(shift) & sizemask))
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{
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mov_reg_param(a, srcreg, srcp);
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a.shl(srcreg, shift);
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}
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else
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{
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mov_reg_param(a, dstreg, dstp);
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bool maskloaded = false;
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if (!shift)
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mov_reg_param(a, srcreg, srcp);
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a.rol(srcreg, shift);
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if (mask == 0x00000000'000000ff)
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{
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if (mask == 0x00000000'000000ff)
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{
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if (srcp.is_int_register())
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a.movzx(srcreg, GpbLo(srcp.ireg()));
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else if (srcp.is_memory())
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a.movzx(srcreg, MABS(srcp.memory(), 1));
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}
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else if (mask == 0x00000000'0000ffff)
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{
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if (srcp.is_int_register())
|
||||
a.movzx(srcreg, Gpw(srcp.ireg()));
|
||||
else if (srcp.is_memory())
|
||||
a.movzx(srcreg, MABS(srcp.memory(), 2));
|
||||
}
|
||||
else if (mask == 0x00000000'ffffffff)
|
||||
{
|
||||
mov_reg_param(a, srcreg.r32(), srcp);
|
||||
}
|
||||
else
|
||||
{
|
||||
mov_reg_param(a, srcreg, srcp);
|
||||
a.and_(srcreg, mask);
|
||||
}
|
||||
a.movzx(srcreg, srcreg.r8());
|
||||
}
|
||||
else if (mask == (util::make_bitmask<uint64_t>(shift) & sizemask))
|
||||
else if (mask == 0x00000000'0000ffff)
|
||||
{
|
||||
mov_reg_param(a, srcreg, srcp);
|
||||
a.shr(srcreg, bits - shift);
|
||||
a.movzx(srcreg, srcreg.r16());
|
||||
}
|
||||
else if (mask == (~util::make_bitmask<uint64_t>(shift) & sizemask))
|
||||
else if (mask == 0x00000000'ffffffff)
|
||||
{
|
||||
mov_reg_param(a, srcreg, srcp);
|
||||
a.shl(srcreg, shift);
|
||||
a.mov(srcreg.r32(), srcreg.r32());
|
||||
}
|
||||
else if ((bits == 32) || (util::sext(mask, 32) == mask) || (uint32_t(mask) == mask))
|
||||
{
|
||||
a.and_(srcreg, mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
mov_reg_param(a, srcreg, srcp);
|
||||
a.rol(srcreg, shift);
|
||||
if (mask == 0x00000000'000000ff)
|
||||
{
|
||||
a.movzx(srcreg, srcreg.r8());
|
||||
}
|
||||
else if (mask == 0x00000000'0000ffff)
|
||||
{
|
||||
a.movzx(srcreg, srcreg.r16());
|
||||
}
|
||||
else if (mask == 0x00000000'ffffffff)
|
||||
{
|
||||
a.mov(srcreg.r32(), srcreg.r32());
|
||||
}
|
||||
else if ((bits == 32) || (util::sext(mask, 32) == mask) || (uint32_t(mask) == mask))
|
||||
{
|
||||
a.and_(srcreg, mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
a.mov(maskreg, mask);
|
||||
a.and_(srcreg, maskreg);
|
||||
maskloaded = true;
|
||||
}
|
||||
a.mov(maskreg, mask);
|
||||
a.and_(srcreg, maskreg);
|
||||
maskloaded = true;
|
||||
}
|
||||
|
||||
if (mask == 0xffffffff'00000000)
|
||||
{
|
||||
a.mov(dstreg.r32(), dstreg.r32());
|
||||
}
|
||||
else if (mask == (0xffffffff'ffff0000 & sizemask))
|
||||
{
|
||||
a.movzx(dstreg, dstreg.r16());
|
||||
}
|
||||
else if (mask == (0xffffffff'ffffff00 & sizemask))
|
||||
{
|
||||
a.movzx(dstreg, dstreg.r8());
|
||||
}
|
||||
else if ((bits == 32) || (util::sext(~mask, 32) == ~mask) || (uint32_t(~mask) == ~mask))
|
||||
{
|
||||
a.and_(dstreg, ~mask & sizemask);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (maskloaded)
|
||||
a.not_(maskreg);
|
||||
else
|
||||
a.mov(maskreg, ~mask);
|
||||
a.and_(dstreg, maskreg);
|
||||
}
|
||||
|
||||
a.or_(dstreg, srcreg);
|
||||
}
|
||||
|
||||
if (mask == 0xffffffff'00000000)
|
||||
{
|
||||
a.mov(dstreg.r32(), dstreg.r32());
|
||||
}
|
||||
else if (mask == (0xffffffff'ffff0000 & sizemask))
|
||||
{
|
||||
a.movzx(dstreg, dstreg.r16());
|
||||
}
|
||||
else if (mask == (0xffffffff'ffffff00 & sizemask))
|
||||
{
|
||||
a.movzx(dstreg, dstreg.r8());
|
||||
}
|
||||
else if ((bits == 32) || (util::sext(~mask, 32) == ~mask) || (uint32_t(~mask) == ~mask))
|
||||
{
|
||||
a.and_(dstreg, ~mask & sizemask);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (maskloaded)
|
||||
a.not_(maskreg);
|
||||
else
|
||||
a.mov(maskreg, ~mask);
|
||||
a.and_(dstreg, maskreg);
|
||||
}
|
||||
|
||||
a.or_(dstreg, srcreg);
|
||||
}
|
||||
|
||||
mov_param_reg(a, dstp, dstreg);
|
||||
@ -4469,24 +4399,33 @@ void drcbe_x64::op_cmp(Assembler &a, const instruction &inst)
|
||||
be_parameter src1p(*this, inst.param(0), PTYPE_MRI);
|
||||
be_parameter src2p(*this, inst.param(1), PTYPE_MRI);
|
||||
|
||||
// memory versus anything
|
||||
if (src1p.is_memory())
|
||||
alu_op_param(a, Inst::kIdCmp, MABS(src1p.memory(), inst.size()), src2p); // cmp [dstp],src2p
|
||||
if (src1p == src2p)
|
||||
{
|
||||
// doesn't matter what we compare if it's always equal
|
||||
const Gp srcreg = (inst.size() == 4) ? Gp(eax) : Gp(rax); // TODO: consider false dependencies
|
||||
|
||||
// general case
|
||||
a.cmp(srcreg, srcreg);
|
||||
}
|
||||
else if (src1p.is_memory())
|
||||
{
|
||||
// memory versus anything
|
||||
alu_op_param(a, Inst::kIdCmp, MABS(src1p.memory(), inst.size()), src2p);
|
||||
}
|
||||
else
|
||||
{
|
||||
// general case
|
||||
|
||||
// pick a target register for the general case
|
||||
Gp src1reg = (inst.size() == 4) ? src1p.select_register(eax) : src1p.select_register(rax);
|
||||
const Gp src1reg = src1p.select_register((inst.size() == 4) ? Gp(eax) : Gp(rax));
|
||||
|
||||
if (src1p.is_immediate())
|
||||
{
|
||||
if (inst.size() == 4)
|
||||
a.mov(src1reg, src1p.immediate()); // mov src1reg,imm
|
||||
a.mov(src1reg, src1p.immediate());
|
||||
else
|
||||
mov_r64_imm(a, src1reg, src1p.immediate()); // mov src1reg,imm
|
||||
mov_r64_imm(a, src1reg, src1p.immediate());
|
||||
}
|
||||
alu_op_param(a, Inst::kIdCmp, src1reg, src2p); // cmp src1reg,src2p
|
||||
alu_op_param(a, Inst::kIdCmp, src1reg, src2p);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5361,10 +5300,6 @@ void drcbe_x64::op_shift(Assembler &a, const uml::instruction &inst)
|
||||
|
||||
const bool carry = (Opcode == Inst::kIdRcl) || (Opcode == Inst::kIdRcr);
|
||||
|
||||
// optimize immediate zero case
|
||||
if (!carry && !inst.flags() && src2p.is_immediate() && !(src2p.immediate() & (inst.size() * 8 - 1)))
|
||||
return; // FIXME: needs to clear upper bits for 32-bit form
|
||||
|
||||
if (dstp.is_memory() && ((inst.size() == 8) || !dstp.is_cold_register()) && (dstp == src1p))
|
||||
{
|
||||
// dstp == src1p in memory
|
||||
@ -5375,7 +5310,7 @@ void drcbe_x64::op_shift(Assembler &a, const uml::instruction &inst)
|
||||
// general case
|
||||
|
||||
// pick a target register
|
||||
Gp dstreg = (inst.size() == 4) ? dstp.select_register(eax, src2p) : dstp.select_register(rax, src2p);
|
||||
const Gp dstreg = dstp.select_register((inst.size() == 4) ? Gp(eax) : Gp(rax), src2p);
|
||||
|
||||
if (carry)
|
||||
mov_reg_param(a, dstreg, src1p, true);
|
||||
|
||||
@ -1582,7 +1582,7 @@ void hyperstone_device::generate_subc(drcuml_block &block, compiler_state &compi
|
||||
|
||||
if (!SrcGlobal || (src_code != SR_REGISTER))
|
||||
{
|
||||
UML_SHR(block, I4, I2, C_SHIFT + 1); // set up carry in, result unused
|
||||
UML_CARRY(block, I2, C_SHIFT);
|
||||
UML_SUBB(block, I0, I0, I1);
|
||||
}
|
||||
else
|
||||
@ -1680,7 +1680,7 @@ void hyperstone_device::generate_addc(drcuml_block &block, compiler_state &compi
|
||||
|
||||
if (!SrcGlobal || (src_code != SR_REGISTER))
|
||||
{
|
||||
UML_SHR(block, I4, I2, C_SHIFT + 1); // set up carry in, result unused
|
||||
UML_CARRY(block, I2, C_SHIFT);
|
||||
UML_ADDC(block, I0, I0, I1);
|
||||
}
|
||||
else
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -222,7 +222,7 @@ namespace uml
|
||||
};
|
||||
|
||||
// C function callback definition
|
||||
typedef void (*c_function)(void *ptr);
|
||||
using c_function = void (*)(void *ptr);
|
||||
|
||||
// class describing a global code handle
|
||||
class code_handle
|
||||
@ -585,8 +585,6 @@ namespace uml
|
||||
|
||||
// opcode validation and simplification
|
||||
void validate();
|
||||
void convert_to_mov_immediate(u64 immediate) { m_opcode = OP_MOV; m_numparams = 2; m_param[1] = immediate; }
|
||||
void convert_to_mov_param(int pnum) { m_opcode = OP_MOV; m_numparams = 2; m_param[1] = m_param[pnum]; }
|
||||
|
||||
// internal state
|
||||
opcode_t m_opcode = OP_INVALID; // opcode
|
||||
@ -597,6 +595,7 @@ namespace uml
|
||||
parameter m_param[MAX_PARAMS]; // up to 4 parameters
|
||||
|
||||
static opcode_info const s_opcode_info_table[OP_MAX];
|
||||
struct simplify_op;
|
||||
};
|
||||
|
||||
// structure describing rules for parameter encoding
|
||||
|
||||
Loading…
Reference in New Issue
Block a user