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Cleanup and version bump

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This commit is contained in:
Miodrag Milanovic 2016-06-29 08:34:30 +02:00
parent 1f6f1bfd6c
commit 63f9a01f8c
283 changed files with 5972 additions and 6062 deletions
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4
android-project/app/src/main/AndroidManifest.xml
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@ -4,8 +4,8 @@
--> -->
<manifest xmlns:android="http://schemas.android.com/apk/res/android" <manifest xmlns:android="http://schemas.android.com/apk/res/android"
package="org.mamedev.mame" package="org.mamedev.mame"
android:versionCode="174" android:versionCode="175"
android:versionName="0.174" android:versionName="0.175"
android:installLocation="auto"> android:installLocation="auto">
<!-- Android 4.0 --> <!-- Android 4.0 -->

8
hash/cdi.xml
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@ -3,8 +3,8 @@
<softwarelist name="cdi" description="CD-i CD-ROMs"> <softwarelist name="cdi" description="CD-i CD-ROMs">
<!-- <!--
These are converted from old TOSEC set (I think v2009-04-05), but a double check is being performed, at These are converted from old TOSEC set (I think v2009-04-05), but a double check is being performed, at
least for discs that can still be found for this set least for discs that can still be found for this set
--> -->
<software name="3degree"> <software name="3degree">
@ -10591,7 +10591,7 @@
<!-- <!--
These are converted from rips released on the web These are converted from rips released on the web
--> -->
<software name="frogfeas"> <software name="frogfeas">
@ -10670,7 +10670,7 @@
<!-- <!--
These are non-tosec sourced, and could be bad These are non-tosec sourced, and could be bad
--> -->

344
hash/fmtowns_cd.xml
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@ -100,186 +100,186 @@
High School War Sep-94 I.S.C. (CDx1) High School War Sep-94 I.S.C. (CDx1)
Hiouden 2 Mar-94 Telenet Japan (CDx1) Hiouden 2 Mar-94 Telenet Japan (CDx1)
If Jun-93 Active (CDx1) If Jun-93 Active (CDx1)
If 2 Nov-93 Active (CDx1) If 2 Nov-93 Active (CDx1)
If 3 Apr-95 Active (CDx1) If 3 Apr-95 Active (CDx1)
Igo Doujou Shodan Kaigan! Kyuu Karadane no Chousen May-91 Fujitsu (CDx1) Igo Doujou Shodan Kaigan! Kyuu Karadane no Chousen May-91 Fujitsu (CDx1)
Igo Doujou Yaburi Menkyokaiden!! Mezase 7-Kyuu Oct-90 Fujitsu (CDx1) Igo Doujou Yaburi Menkyokaiden!! Mezase 7-Kyuu Oct-90 Fujitsu (CDx1)
Inindou: Datou Nobunaga Feb-92 Koei (CDx1) Inindou: Datou Nobunaga Feb-92 Koei (CDx1)
Introduction to Go Dojo Jun-91 GAM (CDx1) Introduction to Go Dojo Jun-91 GAM (CDx1)
Intruder: Sakura Yashiki no Tansaku XXX-89 Alice Soft (CDx1) Intruder: Sakura Yashiki no Tansaku XXX-89 Alice Soft (CDx1)
Irisu-tei Sayokyoku Nov-92 Agumix (CDx1) Irisu-tei Sayokyoku Nov-92 Agumix (CDx1)
Ishin no Arashi Mar-90 Koei (CDx1) Ishin no Arashi Mar-90 Koei (CDx1)
J-League Professional Soccer 1994 Sep-94 Victor (CDx1) J-League Professional Soccer 1994 Sep-94 Victor (CDx1)
Jinmon Yuugi Aug-95 Fairytale - Red Zone (CDx1) Jinmon Yuugi Aug-95 Fairytale - Red Zone (CDx1)
Joker Towns Jul-92 Birdy Soft (CDx1) Joker Towns Jul-92 Birdy Soft (CDx1)
Joshikou Seifuku Monogatari Apr-95 KSS (CDx1) Joshikou Seifuku Monogatari Apr-95 KSS (CDx1)
JYB Apr-93 Cocktail Soft (CDx1) JYB Apr-93 Cocktail Soft (CDx1)
Kamigami No Daichi: Kojiki Gaiden Oct-93 Koei (CDx1) Kamigami No Daichi: Kojiki Gaiden Oct-93 Koei (CDx1)
Kero Kero Keroppi to Origami no Tabibito Jul-95 Fujitsu (CDx1) Kero Kero Keroppi to Origami no Tabibito Jul-95 Fujitsu (CDx1)
Kikou Shidan 2 Mar-93 Artdink (CDx1) Kikou Shidan 2 Mar-93 Artdink (CDx1)
Kouryuuki Oct-93 Koei (CDx1) Kouryuuki Oct-93 Koei (CDx1)
Kousoku Choujin Aug-96 Foster Japan (CDx1) Kousoku Choujin Aug-96 Foster Japan (CDx1)
KU2++ Nov-93 Panther Software (CDx1) KU2++ Nov-93 Panther Software (CDx1)
Kusuriyubi no Kyoukasho Apr-96 Active (CDx1) Kusuriyubi no Kyoukasho Apr-96 Active (CDx1)
Kyouko no Ijiwaru! Oct-94 Ponytail Soft (CDx1) Kyouko no Ijiwaru! Oct-94 Ponytail Soft (CDx1)
L'Empereur Jan-91 Koei (CDx1) L'Empereur Jan-91 Koei (CDx1)
Leading Company Apr-92 Koei (CDx1) Leading Company Apr-92 Koei (CDx1)
Lemon Cocktail Collection Mar-93 Cocktail Soft (CDx1) Lemon Cocktail Collection Mar-93 Cocktail Soft (CDx1)
Lipstick Adventure 3 May-93 Fairytale (CDx1) Lipstick Adventure 3 May-93 Fairytale (CDx1)
Little Big Adventure Dec-95 Electronic Arts (CDx1) Little Big Adventure Dec-95 Electronic Arts (CDx1)
Lord of the Rings 2: The Two Towers Apr-93 Star Craft (CDx1) Lord of the Rings 2: The Two Towers Apr-93 Star Craft (CDx1)
Lord of the Rings: The Fellowship of the Ring Mar-92 Star Craft (CDx1) Lord of the Rings: The Fellowship of the Ring Mar-92 Star Craft (CDx1)
Lua Jun-93 Inter Heart (CDx1) Lua Jun-93 Inter Heart (CDx1)
Mahjong Bishoujo Den Rippuru Feb-95 Foresight (CDx1) Mahjong Bishoujo Den Rippuru Feb-95 Foresight (CDx1)
Mahjong Fantasia 2 Sep-93 Active (CDx1) Mahjong Fantasia 2 Sep-93 Active (CDx1)
Mahjong Fantasia 3 Nov-95 Active (CDx1) Mahjong Fantasia 3 Nov-95 Active (CDx1)
Mahjong Goku Apr-89 ASCII (CDx1) Mahjong Goku Apr-89 ASCII (CDx1)
Mahjong Musashi XXX-89 Computer Cosmos (CDx1) Mahjong Musashi XXX-89 Computer Cosmos (CDx1)
Manami no Doko made Iku no May-95 Wendy Magazine (CDx1) Manami no Doko made Iku no May-95 Wendy Magazine (CDx1)
Manami no Doko made Iku no 2: Return of the Kuro Pack May-95 Wendy Magazine (CDx1) Manami no Doko made Iku no 2: Return of the Kuro Pack May-95 Wendy Magazine (CDx1)
Manami: Ai to Koukan no Hibi XXX-95 Fairytale - Red Zone (CDx1) Manami: Ai to Koukan no Hibi XXX-95 Fairytale - Red Zone (CDx1)
Marionette Mind Mar-94 Studio Milk (CDx1) Marionette Mind Mar-94 Studio Milk (CDx1)
Mega Lo Mania Mar-93 Imagineer (CDx1) Mega Lo Mania Mar-93 Imagineer (CDx1)
Meisou Toshi Dec-95 Tiare (CDx1) Meisou Toshi Dec-95 Tiare (CDx1)
Might & Magic: World of Xeen Oct-92 Star Craft (CDx1) Might & Magic: World of Xeen Oct-92 Star Craft (CDx1)
Mirage 2 Dec-94 Discovery (CDx1) Mirage 2 Dec-94 Discovery (CDx1)
Misato-chan no Yume Nikki Apr-97 Active (CDx1) Misato-chan no Yume Nikki Apr-97 Active (CDx1)
Moeru Asoko no Pai Pai Yuugi Dec-93 Illusion (CDx1) Moeru Asoko no Pai Pai Yuugi Dec-93 Illusion (CDx1)
Mokkori Man RPG Jun-94 Illusion (CDx1) Mokkori Man RPG Jun-94 Illusion (CDx1)
Monoshiri ji Yuugaku Hyakunin Ichishuhen Oct-94 Shinko Human Request (CDx1) Monoshiri ji Yuugaku Hyakunin Ichishuhen Oct-94 Shinko Human Request (CDx1)
Moonlight Energy Dec-92 Inter Heart (CDx1) Moonlight Energy Dec-92 Inter Heart (CDx1)
Murder Club DX May-92 Riverhill Soft (CDx1) Murder Club DX May-92 Riverhill Soft (CDx1)
Naru Mahjong Apr-95 Libido (CDx1) Naru Mahjong Apr-95 Libido (CDx1)
Nemurenu Yoru no Chisana Ohanashi Dec-93 Amuse (CDx1) Nemurenu Yoru no Chisana Ohanashi Dec-93 Amuse (CDx1)
Never Land Mar-96 Tips (CDx1) Never Land Mar-96 Tips (CDx1)
NHK Hitori de Dekiru Mon! Mar-95 Rei (CDx1) NHK Hitori de Dekiru Mon! Mar-95 Rei (CDx1)
Niko 2 Nov-91 Telenet Japan (CDx1) Niko 2 Nov-91 Telenet Japan (CDx1)
Nippon Mukashibanashi Nov-90 Gyosei (CDx1) Nippon Mukashibanashi Nov-90 Gyosei (CDx1)
Nippon Mukashibanashi 2 Jul-91 Gyosei (CDx1) Nippon Mukashibanashi 2 Jul-91 Gyosei (CDx1)
Nippon Mukashibanashi 3 Dec-93 Gyosei (CDx1) Nippon Mukashibanashi 3 Dec-93 Gyosei (CDx1)
Nippon Mukashibanashi 4 Dec-93 Gyosei (CDx1) Nippon Mukashibanashi 4 Dec-93 Gyosei (CDx1)
Nippon Mukashibanashi 5 Mar-94 Gyosei (CDx1) Nippon Mukashibanashi 5 Mar-94 Gyosei (CDx1)
Nobunaga no Yabou: Bushou Fuunroku Jul-91 Koei (CDx1) Nobunaga no Yabou: Bushou Fuunroku Jul-91 Koei (CDx1)
Nobunaga no Yabou: Sengoku Gunyuu Den Dec-89 Koei (CDx1) Nobunaga no Yabou: Sengoku Gunyuu Den Dec-89 Koei (CDx1)
Nostalgia 1907 May-92 Sur de Wave (CDx1) Nostalgia 1907 May-92 Sur de Wave (CDx1)
Obachan no Chiebukuro Nov-91 Gyosei (CDx1) Obachan no Chiebukuro Nov-91 Gyosei (CDx1)
Oku man Choja 2 Jul-91 Computer Cosmos (CDx1) Oku man Choja 2 Jul-91 Computer Cosmos (CDx1)
Only You: Juliet of the Century Jan-96 Alice Soft (CDx1) Only You: Juliet of the Century Jan-96 Alice Soft (CDx1)
Orient Express Dec-94 Gyosei (CDx1) Orient Express Dec-94 Gyosei (CDx1)
Palamedes XXX-91 Ving (CDx1) Palamedes XXX-91 Ving (CDx1)
Para Para Paradise Dec-95 Family Soft (CDx2) Para Para Paradise Dec-95 Family Soft (CDx2)
Phobos Aug-95 Himeya Soft, Inc (CDx1) Phobos Aug-95 Himeya Soft, Inc (CDx1)
Pocky & Ponyon Jun-94 Ponytail Soft (CDx1) Pocky & Ponyon Jun-94 Ponytail Soft (CDx1)
Populous 2 Feb-93 Imagineer (CDx1) Populous 2 Feb-93 Imagineer (CDx1)
Presence Dec-92 Sur de Wave (CDx1) Presence Dec-92 Sur de Wave (CDx1)
Private Slave Aug-93 Raccoon (CDx1) Private Slave Aug-93 Raccoon (CDx1)
ProYakyuu Family Stadium '90 Sep-90 Game Arts (CDx1) ProYakyuu Family Stadium '90 Sep-90 Game Arts (CDx1)
Reijou Monogatari Apr-95 Inter Heart (CDx1) Reijou Monogatari Apr-95 Inter Heart (CDx1)
Rinkan Gakkou Feb-96 Foster Japan (CDx1) Rinkan Gakkou Feb-96 Foster Japan (CDx1)
Royal Blood May-92 Koei (CDx1) Royal Blood May-92 Koei (CDx1)
Ryuutatakaden Jun-94 Fujitsu (CDx1) Ryuutatakaden Jun-94 Fujitsu (CDx1)
Sakura no Mori XXX-95 Active (CDx1) Sakura no Mori XXX-95 Active (CDx1)
Sangokushi 2 Jun-90 Koei (CDx1) Sangokushi 2 Jun-90 Koei (CDx1)
Sangokushi 3 Jun-92 Koei (CDx1) Sangokushi 3 Jun-92 Koei (CDx1)
Sargon 5 Nov-92 GAM (CDx1) Sargon 5 Nov-92 GAM (CDx1)
Sayonara no Mukougawa Aug-97 Foster Japan (CDx1) Sayonara no Mukougawa Aug-97 Foster Japan (CDx1)
Seikatsu Simulation Watashi no Machi May-95 Cocktail Soft (CDx1) Seikatsu Simulation Watashi no Machi May-95 Cocktail Soft (CDx1)
Sekai no o Hanashi May-92 Gyosei (CDx1) Sekai no o Hanashi May-92 Gyosei (CDx1)
Sekigahara Apr-92 Artdink (CDx1) Sekigahara Apr-92 Artdink (CDx1)
Sensual Angels Jan-94 JHV (CDx1) Sensual Angels Jan-94 JHV (CDx1)
Sexy P/K Part 2: World Cup Hen May-95 Birdy Soft (CDx1) Sexy P/K Part 2: World Cup Hen May-95 Birdy Soft (CDx1)
Sexy P/K Part Nihon Apr-95 Birdy Soft (CDx1) Sexy P/K Part Nihon Apr-95 Birdy Soft (CDx1)
Shanghai Dec-90 ASCII (CDx1) Shanghai Dec-90 ASCII (CDx1)
Shanghai: Great Wall Sep-95 Electronic Arts (CDx1) Shanghai: Great Wall Sep-95 Electronic Arts (CDx1)
Shooting Towns Mar-90 Amorphous (CDx1) Shooting Towns Mar-90 Amorphous (CDx1)
SL o mitai! Uruwashi no Joki Kikan-sha Jul-95 Gyosei (CDx1) SL o mitai! Uruwashi no Joki Kikan-sha Jul-95 Gyosei (CDx1)
Soft de Hard na Monogatari Apr-89 System Sacom (CDx1) Soft de Hard na Monogatari Apr-89 System Sacom (CDx1)
Soft de Hard na Monogatari 2 Jul-89 System Sacom (CDx1) Soft de Hard na Monogatari 2 Jul-89 System Sacom (CDx1)
Sokoban Perfect Jul-90 Thinking Rabbit (CDx1) Sokoban Perfect Jul-90 Thinking Rabbit (CDx1)
Space Odyssey Galaxy Mar-91 Fujitsu (CDx1) Space Odyssey Galaxy Mar-91 Fujitsu (CDx1)
Space Odyssey Galaxy 2 Apr-92 Fujitsu (CDx1) Space Odyssey Galaxy 2 Apr-92 Fujitsu (CDx1)
Steepia Jun-93 Fujitsu (CDx1) Steepia Jun-93 Fujitsu (CDx1)
Steepia Lite Mar-93 Fujitsu (CDx1) Steepia Lite Mar-93 Fujitsu (CDx1)
Suikoden: Tenmei no Chikai Feb-90 Koei (CDx1) Suikoden: Tenmei no Chikai Feb-90 Koei (CDx1)
Super Real Mahjong P2 & P3 + Mar-93 Ving (CDx1) Super Real Mahjong P2 & P3 + Mar-93 Ving (CDx1)
Suzaku Oct-92 Wolf Team (CDx1) Suzaku Oct-92 Wolf Team (CDx1)
Tactical Tank Corps DX Feb-95 GAM (CDx1) Tactical Tank Corps DX Feb-95 GAM (CDx1)
Tamashi no Mon: Dante Shinkyoku Yori Jun-93 Koei (CDx1) Tamashi no Mon: Dante Shinkyoku Yori Jun-93 Koei (CDx1)
Tania Nov-96 Tips (CDx1) Tania Nov-96 Tips (CDx1)
Teito Taisen Dec-89 Supersonic (CDx1) Teito Taisen Dec-89 Supersonic (CDx1)
Teitoku no Ketsudan Apr-90 Koei (CDx1) Teitoku no Ketsudan Apr-90 Koei (CDx1)
Tenshi-Tachi no Gogo Collection 2 Nov-95 Jast (CDx1) Tenshi-Tachi no Gogo Collection 2 Nov-95 Jast (CDx1)
Tenshin Ranma May-92 Elf (CDx1) Tenshin Ranma May-92 Elf (CDx1)
Teo: Another Earth Sep-95 Fujitsu (CDx1) Teo: Another Earth Sep-95 Fujitsu (CDx1)
Teo: Another Earth 2 Jul-96 Fujitsu (CDx1) Teo: Another Earth 2 Jul-96 Fujitsu (CDx1)
The Playroom Feb-95 Fujitsu (CDx1) The Playroom Feb-95 Fujitsu (CDx1)
The Queen of Duellist Alpha Mar-94 Agumix (CDx1) The Queen of Duellist Alpha Mar-94 Agumix (CDx1)
The Queen of Duellist Alpha Light Apr-94 Agumix (CDx1) The Queen of Duellist Alpha Light Apr-94 Agumix (CDx1)
Theme Park Sep-95 Electronic Arts (CDx1) Theme Park Sep-95 Electronic Arts (CDx1)
Time Stripper Mako-chan Jan-96 Foster Japan (CDx1) Time Stripper Mako-chan Jan-96 Foster Japan (CDx1)
Tokyo Sexy Ave. Jul-94 HOP (CDx1) Tokyo Sexy Ave. Jul-94 HOP (CDx1)
Tokyo-to Dai 24-Ku Dec-92 Artdink (CDx1) Tokyo-to Dai 24-Ku Dec-92 Artdink (CDx1)
Tom Snyder's Puppy Love Jul-89 Fujitsu (CDx1) Tom Snyder's Puppy Love Jul-89 Fujitsu (CDx1)
Tom Snyder's Puppy Love 2 Mar-93 Fujitsu (CDx1) Tom Snyder's Puppy Love 2 Mar-93 Fujitsu (CDx1)
Toushin Toshi Apr-95 Alice Soft (CDx1) Toushin Toshi Apr-95 Alice Soft (CDx1)
Trigger Jun-94 ZyX (CDx1) Trigger Jun-94 ZyX (CDx1)
Trigger 2 Sep-95 ZyX (CDx1) Trigger 2 Sep-95 ZyX (CDx1)
Vampire High School Jun-93 Inter Heart (CDx1) Vampire High School Jun-93 Inter Heart (CDx1)
Vanishing Point XXX-95 Tiare (CDx1) Vanishing Point XXX-95 Tiare (CDx1)
Viper GTS Nov-95 Sogna (CDx1) Viper GTS Nov-95 Sogna (CDx1)
Viper V12 Dec-95 Sogna (CDx1) Viper V12 Dec-95 Sogna (CDx1)
Viper V8 Turbo RS Jun-95 Sogna (CDx1) Viper V8 Turbo RS Jun-95 Sogna (CDx1)
Winning Post May-93 Koei (CDx1) Winning Post May-93 Koei (CDx1)
Yayo 1-2-3 Jul-93 Hado (CDx1) Yayo 1-2-3 Jul-93 Hado (CDx1)
Yayo 4 Feb-93 Hado (CDx1) Yayo 4 Feb-93 Hado (CDx1)
Yes! HG Dec-95 Himeya Soft, Inc (CDx1) Yes! HG Dec-95 Himeya Soft, Inc (CDx1)
Youjuu Senki 2 Reimei no Senshi Feb-94 D.O. (CDx1) Youjuu Senki 2 Reimei no Senshi Feb-94 D.O. (CDx1)
Youjuu Senki: Sajin no Mokushiroku Feb-94 D.O. (CDx1) Youjuu Senki: Sajin no Mokushiroku Feb-94 D.O. (CDx1)
Yume Utsutsu: Dreamy May-92 Megami (CDx1) Yume Utsutsu: Dreamy May-92 Megami (CDx1)
Zan 3 Apr-94 Telenet Japan (CDx1) Zan 3 Apr-94 Telenet Japan (CDx1)
Zenith Feb-95 Himeya Soft, Inc 1 Zenith Feb-95 Himeya Soft, Inc 1
FM-Towns Marty CDs FM-Towns Marty CDs
================== ==================
4D Boxing Jul-93 Electronic Arts (CDx1) 4D Boxing Jul-93 Electronic Arts (CDx1)
4D Driving Jul-93 Electronic Arts (CDx1) 4D Driving Jul-93 Electronic Arts (CDx1)
Psychic Detective Vol.1: Invitation Nov-93 Data West (CDx1) Psychic Detective Vol.1: Invitation Nov-93 Data West (CDx1)
Psychic Detective Vol.2: Memories Apr-94 Data West (CDx1) Psychic Detective Vol.2: Memories Apr-94 Data West (CDx1)
Psychic Detective Vol.3: Aya Jul-94 Data West (CDx1) Psychic Detective Vol.3: Aya Jul-94 Data West (CDx1)
Psychic Detective Vol.4: Orgel Dec-94 Data West (CDx1) Psychic Detective Vol.4: Orgel Dec-94 Data West (CDx1)
Psychic Detective Vol.5: Nightmare Apr-95 Data West (CDx1) Psychic Detective Vol.5: Nightmare Apr-95 Data West (CDx1)
Bible Master 2 Jan-95 Glodia (CDx1) Bible Master 2 Jan-95 Glodia (CDx1)
Custom Mate Dec-94 Cocktail Soft (CDx1) Custom Mate Dec-94 Cocktail Soft (CDx1)
Demon City Mar-94 Cocktail Soft (CDx1) Demon City Mar-94 Cocktail Soft (CDx1)
Dengeki Nurse 2: More Sexy Dec-94 Cocktail Soft (CDx1) Dengeki Nurse 2: More Sexy Dec-94 Cocktail Soft (CDx1)
Doki Doki Vacation Mar-95 Cocktail Soft (CDx1) Doki Doki Vacation Mar-95 Cocktail Soft (CDx1)
DOR Best Collection Chapter 1 Apr-93 D.O. (CDx2) DOR Best Collection Chapter 1 Apr-93 D.O. (CDx2)
DOR Best Collection Chapter 2 May-93 D.O. (CDx2) DOR Best Collection Chapter 2 May-93 D.O. (CDx2)
Dracula Hakushaku Mar-93 Fairytale (CDx1) Dracula Hakushaku Mar-93 Fairytale (CDx1)
Emit Vol.1 Mar-94 Koei (CDx1) Emit Vol.1 Mar-94 Koei (CDx1)
Emit Vol.2 Jul-94 Koei (CDx1) Emit Vol.2 Jul-94 Koei (CDx1)
Emit Vol.3 Sep-94 Koei (CDx1) Emit Vol.3 Sep-94 Koei (CDx1)
Fujitsu Habitat 2 May-94 Fujitsu (CDx1) Fujitsu Habitat 2 May-94 Fujitsu (CDx1)
Gokko Vol.1: Doctor Nov-94 Mink (CDx1) Gokko Vol.1: Doctor Nov-94 Mink (CDx1)
Gokko Vol.2: School Gals Dec-94 Mink (CDx1) Gokko Vol.2: School Gals Dec-94 Mink (CDx1)
Gokko Vol.3: Etcetera Dec-94 Mink (CDx1) Gokko Vol.3: Etcetera Dec-94 Mink (CDx1)
Gokuraku Mandala Feb-94 Fairytale (CDx1) Gokuraku Mandala Feb-94 Fairytale (CDx1)
Joshikousei Shoujo Densetsu Apr-94 Byakuya Shobou (CDx1) Joshikousei Shoujo Densetsu Apr-94 Byakuya Shobou (CDx1)
Ms. Detective XXX-93 Data West (CDx1) Ms. Detective XXX-93 Data West (CDx1)
Nijiiro Denshoku Musume Aug-94 I.S.C. (CDx1) Nijiiro Denshoku Musume Aug-94 I.S.C. (CDx1)
Noushuku Angel 120% Apr-95 Cocktail Soft (CDx1) Noushuku Angel 120% Apr-95 Cocktail Soft (CDx1)
Record of Lodoss War 2 Jun-94 MAC (CDx1) Record of Lodoss War 2 Jun-94 MAC (CDx1)
Sangokushi 4 Jun-94 Koei (CDx1) Sangokushi 4 Jun-94 Koei (CDx1)
Shamhat: The Holy Circlet Apr-93 Data West (CDx1) Shamhat: The Holy Circlet Apr-93 Data West (CDx1)
Shinjuku Labyrinth ==== Tokuma Shoten (CDx1) Shinjuku Labyrinth ==== Tokuma Shoten (CDx1)
Teitoku no Ketsudan 2 Jun-94 Koei (CDx1) Teitoku no Ketsudan 2 Jun-94 Koei (CDx1)
Tokyo Labyrinth Dec-94 Tokuma Shoten (CDx1) Tokyo Labyrinth Dec-94 Tokuma Shoten (CDx1)
True Heart Feb-95 Cocktail Soft (CDx1) True Heart Feb-95 Cocktail Soft (CDx1)
Two Shot Diary Oct-94 Mink 1 Two Shot Diary Oct-94 Mink 1
URM Dec-94 JHV (CDx1) URM Dec-94 JHV (CDx1)
Virtuacall 2 Dec-95 Fairytale (CDx1) Virtuacall 2 Dec-95 Fairytale (CDx1)
Wonpara Wars Feb-95 Mink (CDx1) Wonpara Wars Feb-95 Mink (CDx1)
Wonpara Wars 2 Apr-95 Mink (CDx1) Wonpara Wars 2 Apr-95 Mink (CDx1)
--> -->

4
hash/gba.xml
View File

@ -30364,7 +30364,7 @@
<publisher>Infogrames</publisher> <publisher>Infogrames</publisher>
<info name="serial" value="AGB-ASOP-(EUR,UKV)"/> <info name="serial" value="AGB-ASOP-(EUR,UKV)"/>
<part name="cart" interface="gba_cart"> <part name="cart" interface="gba_cart">
<feature name="pcb" value="AGB-E02-30" /> <!-- Also found on AGB-E02-20 --> <feature name="pcb" value="AGB-E02-30" /> <!-- Also found on AGB-E02-20 -->
<feature name="u1" value="U1 GPIO MASKROM" /> <feature name="u1" value="U1 GPIO MASKROM" />
<feature name="u2" value="U2 512K/1M FLASH [39VF512]" /> <feature name="u2" value="U2 512K/1M FLASH [39VF512]" />
<feature name="slot" value="gba_flash" /> <feature name="slot" value="gba_flash" />
@ -32407,7 +32407,7 @@ The cart also contained a non-empty SRAM save which we currently include in the
<publisher>Nintendo</publisher> <publisher>Nintendo</publisher>
<info name="serial" value="AGB-AMAE-USA, AGB-AMAP"/> <info name="serial" value="AGB-AMAE-USA, AGB-AMAP"/>
<part name="cart" interface="gba_cart"> <part name="cart" interface="gba_cart">
<feature name="pcb" value="AGB-E03-01" /> <!-- Also found on AGB-E03-10 --> <feature name="pcb" value="AGB-E03-01" /> <!-- Also found on AGB-E03-10 -->
<feature name="u1" value="U1 MASK ROM" /> <feature name="u1" value="U1 MASK ROM" />
<feature name="u2" value="U2 4K/64K EEPROM [9853]" /> <feature name="u2" value="U2 4K/64K EEPROM [9853]" />
<feature name="slot" value="gba_eeprom_4k" /> <feature name="slot" value="gba_eeprom_4k" />

2
hash/n64.xml
View File

@ -9874,7 +9874,7 @@ patched out (+ a fix for internal checksum)
<part name="cart" interface="n64_cart"> <part name="cart" interface="n64_cart">
<feature name="pcb" value="NUS-01A-01" /> <feature name="pcb" value="NUS-01A-01" />
<feature name="u1" value="NUS-NSMP-0" /> <feature name="u1" value="NUS-NSMP-0" />
<feature name="u2" value="BU9850" /> <!-- also found with BK4D-NUS --> <feature name="u2" value="BU9850" /> <!-- also found with BK4D-NUS -->
<feature name="u3" value="CIC-NUS-7101" /> <feature name="u3" value="CIC-NUS-7101" />
<feature name="cart_model" value="NUS-006(EUR)" /> <feature name="cart_model" value="NUS-006(EUR)" />
<feature name="cart_back_label" value="NUS-EUR" /> <feature name="cart_back_label" value="NUS-EUR" />

48
hash/pippin.xml
View File

@ -106,7 +106,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="hanshind"> <software name="hanshind">
<description>1995.1.17 Hanshin Daishinsai (Jpn)</description> <description>1995.1.17 Hanshin Daishinsai (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Keikakudo</publisher> <!-- 計画堂 --> <publisher>Keikakudo</publisher> <!-- 計画堂 -->
<info name="serial" value="BDS-20005" /> <info name="serial" value="BDS-20005" />
<info name="alt_title" value="1995.1.17 阪神大震災" /> <info name="alt_title" value="1995.1.17 阪神大震災" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -236,7 +236,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="chisatom"> <software name="chisatom">
<description>Chisato Moritaka CD-Rom Watarase Bashi (Jpn)</description> <description>Chisato Moritaka CD-Rom Watarase Bashi (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Oracion</publisher> <!-- オラシオン --> <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDE-10007" /> <info name="serial" value="BDE-10007" />
<info name="alt_title" value="森高千里CD-ROM　渡良瀬橋" /> <info name="alt_title" value="森高千里CD-ROM　渡良瀬橋" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -249,7 +249,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="circus"> <software name="circus">
<description>Circus! (Jpn)</description> <description>Circus! (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Voyager</publisher> <!-- ボイジャー --> <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20031" /> <info name="serial" value="BDS-20031" />
<info name="alt_title" value="サーカス！" /> <info name="alt_title" value="サーカス！" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -274,7 +274,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="dazzloid"> <software name="dazzloid">
<description>Dazzeloids (Jpn)</description> <description>Dazzeloids (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Voyager</publisher> <!-- ボイジャー --> <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20030" /> <info name="serial" value="BDS-20030" />
<info name="alt_title" value="ダズロイド" /> <info name="alt_title" value="ダズロイド" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -336,7 +336,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="ffaliens"> <software name="ffaliens">
<description>Funky Funny Aliens (Jpn)</description> <description>Funky Funny Aliens (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Amuse</publisher> <!-- アミューズ --> <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20014" /> <info name="serial" value="BDS-20014" />
<info name="alt_title" value="ファンキー ファニー エイリアンズ" /> <info name="alt_title" value="ファンキー ファニー エイリアンズ" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -349,7 +349,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="gadget"> <software name="gadget">
<description>Gadget (Jpn)</description> <description>Gadget (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 --> <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20033" /> <info name="serial" value="BDS-20033" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom"> <diskarea name="cdrom">
@ -361,7 +361,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="gakkoku"> <software name="gakkoku">
<description>Gakko no Kowai Uwasa - Hanako-san ga Kita!! (Jpn)</description> <description>Gakko no Kowai Uwasa - Hanako-san ga Kita!! (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Amuse</publisher> <!-- アミューズ --> <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20012" /> <info name="serial" value="BDS-20012" />
<info name="alt_title" value="学校のコワイうわさ　花子さんがきた!!" /> <info name="alt_title" value="学校のコワイうわさ　花子さんがきた!!" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -425,7 +425,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="kidsbox"> <software name="kidsbox">
<description>Kids Box (Jpn)</description> <description>Kids Box (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Ask Kodansha</publisher> <!-- アスク講談社 --> <publisher>Ask Kodansha</publisher> <!-- アスク講談社 -->
<info name="serial" value="BDS-20003" /> <info name="serial" value="BDS-20003" />
<info name="alt_title" value="キッズ・ボックス" /> <info name="alt_title" value="キッズ・ボックス" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -475,7 +475,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="lzone"> <software name="lzone">
<description>L-Zone (Jpn)</description> <description>L-Zone (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 --> <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20017" /> <info name="serial" value="BDS-20017" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom"> <diskarea name="cdrom">
@ -561,7 +561,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music1"> <software name="music1">
<description>Music Island Vol. 1 (Prokofiev Peter &amp; the Wolf) (Jpn)</description> <description>Music Island Vol. 1 (Prokofiev Peter &amp; the Wolf) (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Oracion</publisher> <!-- オラシオン --> <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20007" /> <info name="serial" value="BDS-20007" />
<info name="alt_title" value="MUSIC ISLAND プロコフィエフ　ピーターと狼 PETER AND THE WOLF" /> <info name="alt_title" value="MUSIC ISLAND プロコフィエフ　ピーターと狼 PETER AND THE WOLF" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -574,7 +574,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music2"> <software name="music2">
<description>Music Island Vol. 2 (Tchaikovsky The Nutcracker) (Jpn)</description> <description>Music Island Vol. 2 (Tchaikovsky The Nutcracker) (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Oracion</publisher> <!-- オラシオン --> <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20027" /> <info name="serial" value="BDS-20027" />
<info name="alt_title" value="MUSIC ISLAND チャイコフスキー　くるみわり人形 The Nutcracker" /> <info name="alt_title" value="MUSIC ISLAND チャイコフスキー　くるみわり人形 The Nutcracker" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -587,7 +587,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music3"> <software name="music3">
<description>Music Island Vol. 3 (Vivaldi The Four Seasons) (Jpn)</description> <description>Music Island Vol. 3 (Vivaldi The Four Seasons) (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Oracion</publisher> <!-- オラシオン --> <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20028" /> <info name="serial" value="BDS-20028" />
<info name="alt_title" value="MUSIC ISLAND ヴィヴァルディ　四季 The Four Seasons" /> <info name="alt_title" value="MUSIC ISLAND ヴィヴァルディ　四季 The Four Seasons" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -600,7 +600,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="music4"> <software name="music4">
<description>Music Island Vol. 4 (Saint-Saens Carnival of the Animals) (Jpn)</description> <description>Music Island Vol. 4 (Saint-Saens Carnival of the Animals) (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Oracion</publisher> <!-- オラシオン --> <publisher>Oracion</publisher> <!-- オラシオン -->
<info name="serial" value="BDS-20029" /> <info name="serial" value="BDS-20029" />
<info name="alt_title" value="MUSIC ISLAND サン=サーンス 動物の謝肉祭 Carnival of the Animals" /> <info name="alt_title" value="MUSIC ISLAND サン=サーンス 動物の謝肉祭 Carnival of the Animals" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -613,7 +613,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="nemuyoru"> <software name="nemuyoru">
<description>Nemurenu Yoru no Chiisana Ohanashi (Jpn)</description> <description>Nemurenu Yoru no Chiisana Ohanashi (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Amuse</publisher> <!-- アミューズ --> <publisher>Amuse</publisher> <!-- アミューズ -->
<info name="serial" value="BDS-20015" /> <info name="serial" value="BDS-20015" />
<info name="alt_title" value="眠れぬ夜の小さなお話" /> <info name="alt_title" value="眠れぬ夜の小さなお話" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -809,7 +809,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="seesawc1"> <software name="seesawc1">
<description>SeesawC 1 - My favorite things - Sukinamonodake Eitango 120 (Jpn)</description> <description>SeesawC 1 - My favorite things - Sukinamonodake Eitango 120 (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 --> <publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 -->
<info name="serial" value="BDE-10006" /> <info name="serial" value="BDE-10006" />
<info name="alt_title" value="シーソーシー1" /> <info name="alt_title" value="シーソーシー1" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -822,7 +822,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="seesawc2"> <software name="seesawc2">
<description>SeesawC 2 - My favorite places - Sukinatokorode Eitango 400 (Jpn)</description> <description>SeesawC 2 - My favorite places - Sukinatokorode Eitango 400 (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 --> <publisher>Aigaareba Daijoubu</publisher> <!-- 愛があれば大丈夫 -->
<info name="serial" value="BDE-10023" /> <info name="serial" value="BDE-10023" />
<info name="alt_title" value="シーソーシー2" /> <info name="alt_title" value="シーソーシー2" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -835,7 +835,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="shichiso"> <software name="shichiso">
<description>Shichisokusen (Jpn)</description> <description>Shichisokusen (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Media Five</publisher> <!-- メディアファイブ --> <publisher>Media Five</publisher> <!-- メディアファイブ -->
<info name="serial" value="BDS-20019" /> <info name="serial" value="BDS-20019" />
<info name="alt_title" value="死地則戦 ビジネスエデュテイメントソフト" /> <info name="alt_title" value="死地則戦 ビジネスエデュテイメントソフト" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -885,7 +885,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="tbreak"> <software name="tbreak">
<description>T-Break (Jpn)</description> <description>T-Break (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Infocity</publisher> <!-- インフォシティ --> <publisher>Infocity</publisher> <!-- インフォシティ -->
<info name="serial" value="BDS-20026" /> <info name="serial" value="BDS-20026" />
<info name="alt_title" value="ティ・ブレイク" /> <info name="alt_title" value="ティ・ブレイク" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -912,7 +912,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="tropicis"> <software name="tropicis">
<description>Tropic Island (Jpn)</description> <description>Tropic Island (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Momoderazu Brand</publisher> <!-- モモデラーズブランド --> <publisher>Momoderazu Brand</publisher> <!-- モモデラーズブランド -->
<info name="serial" value="BDS-20011" /> <info name="serial" value="BDS-20011" />
<info name="alt_title" value="トロピック　アイランド" /> <info name="alt_title" value="トロピック　アイランド" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -1069,7 +1069,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellow1"> <software name="yellow1">
<description>Yellow Brick Road I (Jpn)</description> <description>Yellow Brick Road I (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 --> <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20022" /> <info name="serial" value="BDS-20022" />
<info name="alt_title" value="イエロー・ブリック・ロード I" /> <info name="alt_title" value="イエロー・ブリック・ロード I" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -1082,7 +1082,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellow2"> <software name="yellow2">
<description>Yellow Brick Road II - Glinda to Nishi no Majo (Jpn)</description> <description>Yellow Brick Road II - Glinda to Nishi no Majo (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 --> <publisher>Synergy Ikunangaku</publisher> <!-- シナジー幾何学 -->
<info name="serial" value="BDS-20023" /> <info name="serial" value="BDS-20023" />
<info name="alt_title" value="イエロー・ブリック・ロード II　グリンダと西の魔女" /> <info name="alt_title" value="イエロー・ブリック・ロード II　グリンダと西の魔女" />
<part name="cdrom1" interface="scd_cdrom"> <part name="cdrom1" interface="scd_cdrom">
@ -1102,7 +1102,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellows"> <software name="yellows">
<description>Yellows - Akira Gomi Photographs (Jpn)</description> <description>Yellows - Akira Gomi Photographs (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Digitalogue</publisher> <!-- デジタローグ --> <publisher>Digitalogue</publisher> <!-- デジタローグ -->
<info name="serial" value="BDS-20001" /> <info name="serial" value="BDS-20001" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
<diskarea name="cdrom"> <diskarea name="cdrom">
@ -1114,7 +1114,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yellws2"> <software name="yellws2">
<description>Yellows 2.0 - Tokyo 1993 Akira Gomi Photographs (Jpn)</description> <description>Yellows 2.0 - Tokyo 1993 Akira Gomi Photographs (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Digitalogue</publisher> <!-- デジタローグ --> <publisher>Digitalogue</publisher> <!-- デジタローグ -->
<info name="serial" value="BDS-20002" /> <info name="serial" value="BDS-20002" />
<info name="alt_title" value="イエローズ 2.0" /> <info name="alt_title" value="イエローズ 2.0" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">
@ -1127,7 +1127,7 @@ NOTE: This list is here only to document available dumps and it's not used (yet)
<software name="yokumite"> <software name="yokumite">
<description>Yoku Mite Goran! (Jpn)</description> <description>Yoku Mite Goran! (Jpn)</description>
<year>1996</year> <year>1996</year>
<publisher>Voyager</publisher> <!-- ボイジャー --> <publisher>Voyager</publisher> <!-- ボイジャー -->
<info name="serial" value="BDS-20018" /> <info name="serial" value="BDS-20018" />
<info name="alt_title" value="よく見てごらん！美術館へ行こう" /> <info name="alt_title" value="よく見てごらん！美術館へ行こう" />
<part name="cdrom" interface="pippin_cdrom"> <part name="cdrom" interface="pippin_cdrom">

4
hash/pofo.xml
View File

@ -21,8 +21,8 @@
Undumped 3rd party cartridges: Undumped 3rd party cartridges:
Adcalc AAC-1000 Adcalc AAC-1000
Alpha Paging Interface SAMpage Alpha Paging Interface SAMpage
Business Contacts and Information Manager BCIM Business Contacts and Information Manager BCIM
Checkwriter Checkwriter
Colossal Cave Adventure Colossal Cave Adventure

2
hash/snes.xml
View File

@ -1357,7 +1357,7 @@ Beyond that last category are the roms waiting to be classified.
<feature name="u1" value="U1 EPROM" /> <feature name="u1" value="U1 EPROM" />
<feature name="u2" value="U2 EPROM" /> <feature name="u2" value="U2 EPROM" />
<feature name="u3" value="U3 EPROM" /> <feature name="u3" value="U3 EPROM" />
<feature name="u4" value="U4 EPROM" /> <!-- empty socket --> <feature name="u4" value="U4 EPROM" /> <!-- empty socket -->
<feature name="u5" value="U5 SRAM" /> <feature name="u5" value="U5 SRAM" />
<feature name="u6" value="U6 PLD" /> <feature name="u6" value="U6 PLD" />
<feature name="u7" value="U7 74LS157" /> <feature name="u7" value="U7 74LS157" />

4
makefile
View File

@ -1486,14 +1486,14 @@ endif
ifeq (posix,$(SHELLTYPE)) ifeq (posix,$(SHELLTYPE))
$(GENDIR)/version.cpp: $(GENDIR)/git_desc | $(GEN_FOLDERS) $(GENDIR)/version.cpp: $(GENDIR)/git_desc | $(GEN_FOLDERS)
@echo '#define BARE_BUILD_VERSION "0.174"' > $@ @echo '#define BARE_BUILD_VERSION "0.175"' > $@
@echo 'extern const char bare_build_version[];' >> $@ @echo 'extern const char bare_build_version[];' >> $@
@echo 'extern const char build_version[];' >> $@ @echo 'extern const char build_version[];' >> $@
@echo 'const char bare_build_version[] = BARE_BUILD_VERSION;' >> $@ @echo 'const char bare_build_version[] = BARE_BUILD_VERSION;' >> $@
@echo 'const char build_version[] = BARE_BUILD_VERSION " ($(NEW_GIT_VERSION))";' >> $@ @echo 'const char build_version[] = BARE_BUILD_VERSION " ($(NEW_GIT_VERSION))";' >> $@
else else
$(GENDIR)/version.cpp: $(GENDIR)/git_desc $(GENDIR)/version.cpp: $(GENDIR)/git_desc
@echo #define BARE_BUILD_VERSION "0.174" > $@ @echo #define BARE_BUILD_VERSION "0.175" > $@
@echo extern const char bare_build_version[]; >> $@ @echo extern const char bare_build_version[]; >> $@
@echo extern const char build_version[]; >> $@ @echo extern const char build_version[]; >> $@
@echo const char bare_build_version[] = BARE_BUILD_VERSION; >> $@ @echo const char bare_build_version[] = BARE_BUILD_VERSION; >> $@

2
src/devices/bus/electron/exp.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Nigel Barnes // copyright-holders:Nigel Barnes
/********************************************************************** /**********************************************************************
Electron Expansion Port emulation Electron Expansion Port emulation
**********************************************************************/ **********************************************************************/

140
src/devices/bus/electron/exp.h
View File

@ -2,84 +2,84 @@
// copyright-holders:Nigel Barnes // copyright-holders:Nigel Barnes
/********************************************************************** /**********************************************************************
Electron Expansion Port emulation Electron Expansion Port emulation
********************************************************************** **********************************************************************
Pinout: Pinout:
18V AC 2 1 18V AC 18V AC 2 1 18V AC
AC RETURN 4 3 AC RETURN AC RETURN 4 3 AC RETURN
-5V 6 5 -5V -5V 6 5 -5V
0V 8 7 0V 0V 8 7 0V
+5V 10 9 +5V +5V 10 9 +5V
16MHz 12 11 SOUND O/P 16MHz 12 11 SOUND O/P
PHI OUT 14 13 ÷13 IN PHI OUT 14 13 13 IN
NMI 16 15 RST NMI 16 15 RST
R/W 18 17 IRQ R/W 18 17 IRQ
D6 20 19 D7 D6 20 19 D7
D4 22 21 D5 D4 22 21 D5
D2 24 23 D3 D2 24 23 D3
D0 26 25 D1 D0 26 25 D1
NC 28 27 RDY NC 28 27 RDY
SLOT 30 29 SLOT SLOT 30 29 SLOT
A14 32 31 A15 A14 32 31 A15
A12 34 33 A13 A12 34 33 A13
A10 36 35 A11 A10 36 35 A11
A0 38 37 A9 A0 38 37 A9
A2 40 39 A1 A2 40 39 A1
A4 42 41 A3 A4 42 41 A3
A6 44 43 A5 A6 44 43 A5
A8 46 45 A7 A8 46 45 A7
0V 48 47 0V 0V 48 47 0V
+5V 50 49 +5V +5V 50 49 +5V
Signal Definitions: Signal Definitions:
18V AC (pins 1,2) - These lines are connected directly to the output from the Electron mains power 18V AC (pins 1,2) - These lines are connected directly to the output from the Electron mains power
AC RETURNS (pins 3,4) - adaptor. A total of 6W may be drawn from these lines as long as no power is AC RETURNS (pins 3,4) - adaptor. A total of 6W may be drawn from these lines as long as no power is
taken from +5V (pins 9,10,49,50). For safety reasons these lines must never taken from +5V (pins 9,10,49,50). For safety reasons these lines must never
be used as an AC input to the Electron. be used as an AC input to the Electron.
-5V (pins 5,6) - A -5V supply from the Electron. Up to 20mA (total) may safely be drawn -5V (pins 5,6) - A -5V supply from the Electron. Up to 20mA (total) may safely be drawn
from this line by expansion modules. from this line by expansion modules.
0V (pins 7,8,47,48) - Ground. Expansion modules with their own power supply must have the 0V 0V (pins 7,8,47,48) - Ground. Expansion modules with their own power supply must have the 0V
lines commoned with the Electron. lines commoned with the Electron.
+5V (pins 9,10,49,50) - A +5V supply from the Electron. Up to 500mA (total) may safely be drawn +5V (pins 9,10,49,50) - A +5V supply from the Electron. Up to 500mA (total) may safely be drawn
from this line by expansion modules as long as no power is taken from 18V from this line by expansion modules as long as no power is taken from 18V
AC (pins 1,2,3,4). AC (pins 1,2,3,4).
SOUND O/P (pin 11) - Sound output. A 3V peak to peak source via a 1K series resistor from the SOUND O/P (pin 11) - Sound output. A 3V peak to peak source via a 1K series resistor from the
Electron ULA. Electron ULA.
16 MHz (pin 12) - 16 Megahertz from the Electron main oscillator. This output may be used 16 MHz (pin 12) - 16 Megahertz from the Electron main oscillator. This output may be used
for clock generation within an expansion module. for clock generation within an expansion module.
/13 IN (pin 13) - 16 Megahertz divided by 13. This output may be used for baud rate /13 IN (pin 13) - 16 Megahertz divided by 13. This output may be used for baud rate
generation. If divided by 1024 it will give approximately 1200Hz. generation. If divided by 1024 it will give approximately 1200Hz.
PHI OUT (pin 14) - The 6502 input clock. The low time is nominally 250ns. The high time may PHI OUT (pin 14) - The 6502 input clock. The low time is nominally 250ns. The high time may
be 250ns (2MHz operation when reading ROMs) or 750ns or 1250ns be 250ns (2MHz operation when reading ROMs) or 750ns or 1250ns
(stretched clock for a 1MHz access, the length depending on the phase of the (stretched clock for a 1MHz access, the length depending on the phase of the
2MHz clock) or up to 40us (if in modes 0-3) 2MHz clock) or up to 40us (if in modes 0-3)
RST (pin 15) - Reset (active low). This is an OUTPUT ONLY for the system reset line. It RST (pin 15) - Reset (active low). This is an OUTPUT ONLY for the system reset line. It
may be used to initialise expansion modules on power up and when the may be used to initialise expansion modules on power up and when the
BREAK key is pressed. BREAK key is pressed.
NMI (pin 16) - Non-Maskable Interrupt (negative edge triggered). This is the system NMI NMI (pin 16) - Non-Maskable Interrupt (negative edge triggered). This is the system NMI
line which is open collector (wire-OR) and may be asserted by an expansion line which is open collector (wire-OR) and may be asserted by an expansion
module. The pull-up resistor on this line inside the ULA is 3k3. Care must module. The pull-up resistor on this line inside the ULA is 3k3. Care must
be taken to avoid masking other interrupts by holding the line low. Using be taken to avoid masking other interrupts by holding the line low. Using
NMI on the Electron requires knowledge of operating system protocols. NMI on the Electron requires knowledge of operating system protocols.
IRQ (pin 17) - Interrupt Request (active low). This is the system IRQ line which is open IRQ (pin 17) - Interrupt Request (active low). This is the system IRQ line which is open
collector (wire-OR) and may be asserted by an expansion module. The pull- collector (wire-OR) and may be asserted by an expansion module. The pull-
up resistor on this line inside the ULA is 3k3. It is essential for the correct up resistor on this line inside the ULA is 3k3. It is essential for the correct
operation of the machine that interrupts to not occur until the software is operation of the machine that interrupts to not occur until the software is
capable of dealing with them. Interrupts on the Electron expansion bus should capable of dealing with them. Interrupts on the Electron expansion bus should
therefore be disabled on power-up and reset. Significant use of interrupt therefore be disabled on power-up and reset. Significant use of interrupt
service time may affect other machine functions, eg the real time clock. service time may affect other machine functions, eg the real time clock.
R/W (pin 18) - The system read/write line from the 6502. R/W (pin 18) - The system read/write line from the 6502.
D7-D0 (pins 19-26) - Bi-directional data bus. The direction of data is determined by R/W. D7-D0 (pins 19-26) - Bi-directional data bus. The direction of data is determined by R/W.
RDY (pin 27) - 6502 ready line (active low). May be asserted by an expansion module to RDY (pin 27) - 6502 ready line (active low). May be asserted by an expansion module to
stop the processor when reading slow memory. This line works on read only stop the processor when reading slow memory. This line works on read only
(R/W=1). (R/W=1).
(pin 28) - No connection (pin 28) - No connection
(pins 29,30) - Polarising key connector. (pins 29,30) - Polarising key connector.
A0-A15 (pins 31-46) - 6502 address bus. A0-A15 (pins 31-46) - 6502 address bus.
**********************************************************************/ **********************************************************************/

1
src/devices/bus/gameboy/mbc.cpp
View File

@ -719,7 +719,6 @@ WRITE8_MEMBER(gb_rom_m161_device::write_bank)
READ8_MEMBER(gb_rom_mmm01_device::read_rom) READ8_MEMBER(gb_rom_mmm01_device::read_rom)
{ {
UINT16 romb = m_romb & ~m_romb_nwe; UINT16 romb = m_romb & ~m_romb_nwe;
UINT16 romb_base = m_romb & (0x1e0 | m_romb_nwe); UINT16 romb_base = m_romb & (0x1e0 | m_romb_nwe);
UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03); UINT8 ramb_masked = ((offset & 0x4000) | m_mode ? m_ramb : m_ramb & ~0x03);

2
src/devices/bus/gba/gba_slot.h
View File

@ -607,7 +607,7 @@ static const gba_chip_fix_item gba_chip_fix_rumble_list[] =
{ "KYGP" }, // Yoshi's Universal Gravitation (EUR) { "KYGP" }, // Yoshi's Universal Gravitation (EUR)
{ "KYGE" }, // Yoshi - Topsy-Turvy (USA) { "KYGE" }, // Yoshi - Topsy-Turvy (USA)
{ "KYGJ" }, // Yoshi no Banyuuinryoku (JPN) { "KYGJ" }, // Yoshi no Banyuuinryoku (JPN)
{ "KHPJ" } // Koro Koro Puzzle - Happy Panechu! (JPN) { "KHPJ" } // Koro Koro Puzzle - Happy Panechu! (JPN)
}; };

11
src/devices/bus/gba/rom.cpp
View File

@ -840,7 +840,7 @@ int gba_s3511_device::read_line()
if (m_bits == 8 * m_data_len) if (m_bits == 8 * m_data_len)
{ {
//for (int i = 0; i < m_data_len; i++) //for (int i = 0; i < m_data_len; i++)
// printf("RTC DATA OUT COMPLETE %X (reg %d) \n", m_data[i], i); // printf("RTC DATA OUT COMPLETE %X (reg %d) \n", m_data[i], i);
m_bits = 0; m_bits = 0;
m_phase = S3511_RTC_IDLE; m_phase = S3511_RTC_IDLE;
} }
@ -852,7 +852,7 @@ int gba_s3511_device::read_line()
void gba_s3511_device::write(UINT16 data, int gpio_dirs) void gba_s3511_device::write(UINT16 data, int gpio_dirs)
{ {
// printf("gpio_dev_write data %X\n", data); // printf("gpio_dev_write data %X\n", data);
if (m_phase == S3511_RTC_IDLE && (m_last_val & 5) == 1 && (data & 5) == 5) if (m_phase == S3511_RTC_IDLE && (m_last_val & 5) == 1 && (data & 5) == 5)
{ {
m_phase = S3511_RTC_COMMAND; m_phase = S3511_RTC_COMMAND;
@ -861,8 +861,8 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
} }
else else
{ {
// if (m_phase == 3) // if (m_phase == 3)
// printf("RTC command OK\n"); // printf("RTC command OK\n");
if (!(m_last_val & 1) && (data & 1)) if (!(m_last_val & 1) && (data & 1))
{ {
// bit transfer // bit transfer
@ -877,7 +877,7 @@ void gba_s3511_device::write(UINT16 data, int gpio_dirs)
if (m_bits == 8 * m_data_len) if (m_bits == 8 * m_data_len)
{ {
//for (int i = 0; i < m_data_len; i++) //for (int i = 0; i < m_data_len; i++)
// printf("RTC DATA IN COMPLETE %X (reg %d) \n", m_data[i], i); // printf("RTC DATA IN COMPLETE %X (reg %d) \n", m_data[i], i);
m_bits = 0; m_bits = 0;
m_phase = S3511_RTC_IDLE; m_phase = S3511_RTC_IDLE;
} }
@ -1092,4 +1092,3 @@ void gba_eeprom_device::write(UINT32 data)
break; break;
} }
} }

8
src/devices/bus/isa/cga.cpp
View File

@ -1814,12 +1814,12 @@ WRITE8_MEMBER( isa8_ec1841_0002_device::io_write )
m_p3df = data; m_p3df = data;
if (data & 1) { if (data & 1) {
m_isa->install_memory(0xb8000, 0xb9fff, m_isa->install_memory(0xb8000, 0xb9fff,
read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this), read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) ); write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
if(m_vram_size == 0x4000) if(m_vram_size == 0x4000)
m_isa->install_memory(0xbc000, 0xbdfff, m_isa->install_memory(0xbc000, 0xbdfff,
read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this), read8_delegate( FUNC(isa8_ec1841_0002_device::char_ram_read), this),
write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) ); write8_delegate(FUNC(isa8_ec1841_0002_device::char_ram_write), this) );
} else { } else {
m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, "bank_cga", &m_vram[0]); m_isa->install_bank(0xb8000, 0xb8000 + MIN(0x8000,m_vram_size) - 1, "bank_cga", &m_vram[0]);
if(m_vram_size == 0x4000) if(m_vram_size == 0x4000)

2
src/devices/bus/macpds/macpds.h
View File

@ -83,7 +83,7 @@ public:
void add_macpds_card(device_macpds_card_interface *card); void add_macpds_card(device_macpds_card_interface *card);
void install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, UINT32 mask=0xffffffff); void install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, UINT32 mask=0xffffffff);
void install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, UINT32 mask=0xffffffff); void install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, UINT32 mask=0xffffffff);
void install_bank(offs_t start, offs_t end, const char *tag, UINT8 *data); void install_bank(offs_t start, offs_t end, const char *tag, UINT8 *data);
void set_irq_line(int line, int state); void set_irq_line(int line, int state);
protected: protected:

11
src/devices/bus/nes/bootleg.cpp
View File

@ -1238,7 +1238,7 @@ READ8_MEMBER(nes_lh32_device::read_m)
READ8_MEMBER(nes_lh32_device::read_h) READ8_MEMBER(nes_lh32_device::read_h)
{ {
// LOG_MMC(("lh32 read_h, offset: %04x\n", offset)); // LOG_MMC(("lh32 read_h, offset: %04x\n", offset));
if (offset >= 0x4000 && offset < 0x6000) if (offset >= 0x4000 && offset < 0x6000)
return m_prgram[offset & 0x1fff]; return m_prgram[offset & 0x1fff];
@ -1294,7 +1294,7 @@ READ8_MEMBER(nes_lh10_device::read_m)
READ8_MEMBER(nes_lh10_device::read_h) READ8_MEMBER(nes_lh10_device::read_h)
{ {
// LOG_MMC(("lh10 read_h, offset: %04x\n", offset)); // LOG_MMC(("lh10 read_h, offset: %04x\n", offset));
if (offset >= 0x4000 && offset < 0x6000) if (offset >= 0x4000 && offset < 0x6000)
return m_prgram[offset & 0x1fff]; return m_prgram[offset & 0x1fff];
@ -1363,7 +1363,7 @@ READ8_MEMBER(nes_lh53_device::read_m)
READ8_MEMBER(nes_lh53_device::read_h) READ8_MEMBER(nes_lh53_device::read_h)
{ {
// LOG_MMC(("lh53 read_h, offset: %04x\n", offset)); // LOG_MMC(("lh53 read_h, offset: %04x\n", offset));
if (offset >= 0x3800 && offset < 0x5800) if (offset >= 0x3800 && offset < 0x5800)
return m_battery[offset & 0x1fff]; return m_battery[offset & 0x1fff];
@ -1431,7 +1431,7 @@ WRITE8_MEMBER(nes_2708_device::write_m)
READ8_MEMBER(nes_2708_device::read_h) READ8_MEMBER(nes_2708_device::read_h)
{ {
// LOG_MMC(("btl-2708 read_h, offset: %04x\n", offset)); // LOG_MMC(("btl-2708 read_h, offset: %04x\n", offset));
if (offset >= 0x3800 && offset < 0x5800 && !m_reg[1]) if (offset >= 0x3800 && offset < 0x5800 && !m_reg[1])
return m_prgram[0x2000 + ((offset - 0x3800) & 0x1fff)]; // higher 8K of WRAM return m_prgram[0x2000 + ((offset - 0x3800) & 0x1fff)]; // higher 8K of WRAM
@ -1673,7 +1673,7 @@ READ8_MEMBER(nes_shuiguan_device::read_m)
READ8_MEMBER(nes_rt01_device::read_h) READ8_MEMBER(nes_rt01_device::read_h)
{ {
// LOG_MMC(("rt01 read_h, offset: %04x\n", offset)); // LOG_MMC(("rt01 read_h, offset: %04x\n", offset));
if ((offset >= 0x4e80) && (offset < 0x4f00)) if ((offset >= 0x4e80) && (offset < 0x4f00))
return 0xf2 | (machine().rand() & 0x0d); return 0xf2 | (machine().rand() & 0x0d);
@ -1682,4 +1682,3 @@ READ8_MEMBER(nes_rt01_device::read_h)
return hi_access_rom(offset); return hi_access_rom(offset);
} }

5
src/devices/bus/nes/kaiser.cpp
View File

@ -696,7 +696,7 @@ void nes_ks7037_device::update_prg()
READ8_MEMBER(nes_ks7037_device::read_m) READ8_MEMBER(nes_ks7037_device::read_m)
{ {
// LOG_MMC(("ks7037 read_m, offset: %04x\n", offset)); // LOG_MMC(("ks7037 read_m, offset: %04x\n", offset));
if (offset < 0x1000) if (offset < 0x1000)
return m_prgram[offset & 0x0fff]; return m_prgram[offset & 0x0fff];
else else
@ -712,7 +712,7 @@ WRITE8_MEMBER(nes_ks7037_device::write_m)
READ8_MEMBER(nes_ks7037_device::read_h) READ8_MEMBER(nes_ks7037_device::read_h)
{ {
// LOG_MMC(("ks7037 read_h, offset: %04x\n", offset)); // LOG_MMC(("ks7037 read_h, offset: %04x\n", offset));
if (offset >= 0x3000 && offset < 0x4000) if (offset >= 0x3000 && offset < 0x4000)
return m_prgram[0x1000 + (offset & 0x0fff)]; return m_prgram[0x1000 + (offset & 0x0fff)];
@ -740,4 +740,3 @@ WRITE8_MEMBER(nes_ks7037_device::write_h)
} }
} }
} }

2
src/devices/bus/nubus/nubus_image.h
View File

@ -18,7 +18,7 @@ struct nbfilectx {
UINT32 curcmd; UINT32 curcmd;
UINT8 filename[128]; UINT8 filename[128];
UINT8 curdir[1024]; UINT8 curdir[1024];
osd::directory::ptr dirp; osd::directory::ptr dirp;
osd_file::ptr fd; osd_file::ptr fd;
UINT64 filelen; UINT64 filelen;
UINT32 bytecount; UINT32 bytecount;

76
src/devices/bus/pofo/exp.h
View File

@ -65,16 +65,16 @@
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
#define MCFG_PORTFOLIO_EXPANSION_SLOT_IINT_CALLBACK(_write) \ #define MCFG_PORTFOLIO_EXPANSION_SLOT_IINT_CALLBACK(_write) \
devcb = &portfolio_expansion_slot_t::set_iint_wr_callback(*device, DEVCB_##_write); devcb = &portfolio_expansion_slot_t::set_iint_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_EINT_CALLBACK(_write) \ #define MCFG_PORTFOLIO_EXPANSION_SLOT_EINT_CALLBACK(_write) \
devcb = &portfolio_expansion_slot_t::set_eint_wr_callback(*device, DEVCB_##_write); devcb = &portfolio_expansion_slot_t::set_eint_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_NMIO_CALLBACK(_write) \ #define MCFG_PORTFOLIO_EXPANSION_SLOT_NMIO_CALLBACK(_write) \
devcb = &portfolio_expansion_slot_t::set_nmio_wr_callback(*device, DEVCB_##_write); devcb = &portfolio_expansion_slot_t::set_nmio_wr_callback(*device, DEVCB_##_write);
#define MCFG_PORTFOLIO_EXPANSION_SLOT_WAKE_CALLBACK(_write) \ #define MCFG_PORTFOLIO_EXPANSION_SLOT_WAKE_CALLBACK(_write) \
devcb = &portfolio_expansion_slot_t::set_wake_wr_callback(*device, DEVCB_##_write); devcb = &portfolio_expansion_slot_t::set_wake_wr_callback(*device, DEVCB_##_write);
@ -89,71 +89,71 @@ class portfolio_expansion_slot_t;
class device_portfolio_expansion_slot_interface : public device_slot_card_interface class device_portfolio_expansion_slot_interface : public device_slot_card_interface
{ {
public: public:
// construction/destruction // construction/destruction
device_portfolio_expansion_slot_interface(const machine_config &mconfig, device_t &device); device_portfolio_expansion_slot_interface(const machine_config &mconfig, device_t &device);
virtual ~device_portfolio_expansion_slot_interface() { } virtual ~device_portfolio_expansion_slot_interface() { }
virtual bool nmd1() { return 1; } virtual bool nmd1() { return 1; }
virtual bool pdet() { return 0; } virtual bool pdet() { return 0; }
virtual bool cdet() { return 1; } virtual bool cdet() { return 1; }
virtual UINT8 iack_r() { return 0xff; } virtual UINT8 iack_r() { return 0xff; }
virtual UINT8 eack_r() { return 0xff; } virtual UINT8 eack_r() { return 0xff; }
virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return data; }; virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return data; };
virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { }; virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { };
DECLARE_WRITE_LINE_MEMBER( iint_w ); DECLARE_WRITE_LINE_MEMBER( iint_w );
DECLARE_WRITE_LINE_MEMBER( eint_w ); DECLARE_WRITE_LINE_MEMBER( eint_w );
DECLARE_WRITE_LINE_MEMBER( nmio_w ); DECLARE_WRITE_LINE_MEMBER( nmio_w );
DECLARE_WRITE_LINE_MEMBER( wake_w ); DECLARE_WRITE_LINE_MEMBER( wake_w );
protected: protected:
portfolio_expansion_slot_t *m_slot; portfolio_expansion_slot_t *m_slot;
}; };
// ======================> portfolio_expansion_slot_t // ======================> portfolio_expansion_slot_t
class portfolio_expansion_slot_t : public device_t, class portfolio_expansion_slot_t : public device_t,
public device_slot_interface public device_slot_interface
{ {
public: public:
// construction/destruction // construction/destruction
portfolio_expansion_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); portfolio_expansion_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
virtual ~portfolio_expansion_slot_t() { } virtual ~portfolio_expansion_slot_t() { }
template<class _Object> static devcb_base &set_iint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_iint.set_callback(object); } template<class _Object> static devcb_base &set_iint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_iint.set_callback(object); }
template<class _Object> static devcb_base &set_eint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_eint.set_callback(object); } template<class _Object> static devcb_base &set_eint_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_eint.set_callback(object); }
template<class _Object> static devcb_base &set_nmio_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_nmio.set_callback(object); } template<class _Object> static devcb_base &set_nmio_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_nmio.set_callback(object); }
template<class _Object> static devcb_base &set_wake_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_wake.set_callback(object); } template<class _Object> static devcb_base &set_wake_wr_callback(device_t &device, _Object object) { return downcast<portfolio_expansion_slot_t &>(device).m_write_wake.set_callback(object); }
// computer interface // computer interface
bool nmd1_r() { return (m_card != nullptr) ? m_card->nmd1() : 1; } bool nmd1_r() { return (m_card != nullptr) ? m_card->nmd1() : 1; }
bool pdet_r() { return (m_card != nullptr) ? m_card->pdet() : 0; } bool pdet_r() { return (m_card != nullptr) ? m_card->pdet() : 0; }
bool cdet_r() { return (m_card != nullptr) ? m_card->cdet() : 1; } bool cdet_r() { return (m_card != nullptr) ? m_card->cdet() : 1; }
UINT8 iack_r() { return (m_card != nullptr) ? m_card->iack_r() : 0xff; }; UINT8 iack_r() { return (m_card != nullptr) ? m_card->iack_r() : 0xff; };
UINT8 eack_r() { return (m_card != nullptr) ? m_card->eack_r() : 0xff; }; UINT8 eack_r() { return (m_card != nullptr) ? m_card->eack_r() : 0xff; };
UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return (m_card != nullptr) ? m_card->nrdi_r(space, offset, data, iom, bcom, ncc1) : data; } UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { return (m_card != nullptr) ? m_card->nrdi_r(space, offset, data, iom, bcom, ncc1) : data; }
void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { if (m_card != nullptr) m_card->nwri_w(space, offset, data, iom, bcom, ncc1); } void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) { if (m_card != nullptr) m_card->nwri_w(space, offset, data, iom, bcom, ncc1); }
// peripheral interface // peripheral interface
WRITE_LINE_MEMBER( iint_w ) { m_write_iint(state); } WRITE_LINE_MEMBER( iint_w ) { m_write_iint(state); }
WRITE_LINE_MEMBER( eint_w ) { m_write_eint(state); } WRITE_LINE_MEMBER( eint_w ) { m_write_eint(state); }
WRITE_LINE_MEMBER( nmio_w ) { m_write_nmio(state); } WRITE_LINE_MEMBER( nmio_w ) { m_write_nmio(state); }
WRITE_LINE_MEMBER( wake_w ) { m_write_wake(state); } WRITE_LINE_MEMBER( wake_w ) { m_write_wake(state); }
protected: protected:
// device-level overrides // device-level overrides
virtual void device_start() override; virtual void device_start() override;
virtual void device_reset() override; virtual void device_reset() override;
devcb_write_line m_write_iint; devcb_write_line m_write_iint;
devcb_write_line m_write_eint; devcb_write_line m_write_eint;
devcb_write_line m_write_nmio; devcb_write_line m_write_nmio;
devcb_write_line m_write_wake; devcb_write_line m_write_wake;
device_portfolio_expansion_slot_interface *m_card; device_portfolio_expansion_slot_interface *m_card;
}; };

6
src/devices/bus/pofo/hpc101.h
View File

@ -25,7 +25,7 @@
// ======================> hpc101_t // ======================> hpc101_t
class hpc101_t : public device_t, class hpc101_t : public device_t,
public device_portfolio_expansion_slot_interface public device_portfolio_expansion_slot_interface
{ {
public: public:
// construction/destruction // construction/destruction
@ -42,8 +42,8 @@ protected:
// device_portfolio_expansion_slot_interface overrides // device_portfolio_expansion_slot_interface overrides
bool pdet() override { return 1; } bool pdet() override { return 1; }
virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override; virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override; virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
private: private:
required_device<i8255_device> m_ppi; required_device<i8255_device> m_ppi;

8
src/devices/bus/pofo/hpc102.h
View File

@ -25,7 +25,7 @@
// ======================> hpc102_t // ======================> hpc102_t
class hpc102_t : public device_t, class hpc102_t : public device_t,
public device_portfolio_expansion_slot_interface public device_portfolio_expansion_slot_interface
{ {
public: public:
// construction/destruction // construction/destruction
@ -42,10 +42,10 @@ protected:
// device_portfolio_expansion_slot_interface overrides // device_portfolio_expansion_slot_interface overrides
bool pdet() override { return 1; } bool pdet() override { return 1; }
virtual UINT8 eack_r() override; virtual UINT8 eack_r() override;
virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override; virtual UINT8 nrdi_r(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override; virtual void nwri_w(address_space &space, offs_t offset, UINT8 data, bool iom, bool bcom, bool ncc1) override;
private: private:
required_device<ins8250_device> m_uart; required_device<ins8250_device> m_uart;

1
src/devices/bus/sg1000_exp/fm_unit.cpp
View File

@ -116,4 +116,3 @@ bool sega_fm_unit_device::is_writeable(UINT8 offset)
{ {
return (offset <= 2) ? true : false; return (offset <= 2) ? true : false;
} }

1
src/devices/bus/sg1000_exp/sk1100.cpp
View File

@ -334,4 +334,3 @@ WRITE8_MEMBER( sega_sk1100_device::ppi_pc_w )
/* TODO printer */ /* TODO printer */
} }

2
src/devices/cpu/asap/asapdasm.cpp
View File

@ -91,7 +91,7 @@ CPU_DISASSEMBLE( asap )
sprintf(buffer, "mov%s %s,%s", setcond[cond], reg[rsrc1], reg[rdst]); sprintf(buffer, "mov%s %s,%s", setcond[cond], reg[rsrc1], reg[rdst]);
else else
sprintf(buffer, "add%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); sprintf(buffer, "add%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]);
break; break;
case 0x09: sprintf(buffer, "sub%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break; case 0x09: sprintf(buffer, "sub%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
case 0x0a: sprintf(buffer, "addc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break; case 0x0a: sprintf(buffer, "addc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;
case 0x0b: sprintf(buffer, "subc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break; case 0x0b: sprintf(buffer, "subc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break;

2
src/devices/cpu/avr8/avr8.cpp
View File

@ -2915,7 +2915,7 @@ READ8_MEMBER( avr8_device::regs_r )
default: default:
printf("[%08X] AVR8: Unknown Register Read: 0x%03X\n", m_shifted_pc, offset); printf("[%08X] AVR8: Unknown Register Read: 0x%03X\n", m_shifted_pc, offset);
// machine().debug_break(); // machine().debug_break();
return 0; return 0;
} }
} }

1
src/devices/cpu/drcbex64.cpp
View File

@ -175,7 +175,6 @@
// This is a trick to make it build on Android where the ARM SDK declares ::REG_Rn // This is a trick to make it build on Android where the ARM SDK declares ::REG_Rn
namespace drc { namespace drc {
using namespace uml; using namespace uml;
using namespace x64emit; using namespace x64emit;

1
src/devices/cpu/drcbex64.h
View File

@ -22,7 +22,6 @@
namespace drc { namespace drc {
//************************************************************************** //**************************************************************************
// TYPE DEFINITIONS // TYPE DEFINITIONS
//************************************************************************** //**************************************************************************

2
src/devices/cpu/m6502/odeco16.lst
View File

@ -92,7 +92,7 @@ vbl_zpg
TMP2 = read_pc(); TMP2 = read_pc();
A = io->read_byte(0); A = io->read_byte(0);
//if(DECO16_VERBOSE) //if(DECO16_VERBOSE)
// logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2); // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2);
prefetch(); prefetch();
# exceptions # exceptions

50
src/devices/cpu/mb86235/mb86235d.cpp
View File

@ -6,14 +6,14 @@
static const char *regname[128] = static const char *regname[128] =
{ {
"MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7",
"AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7",
"EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC", "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC",
"AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7", "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7",
"MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
"AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
"PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP", "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP",
"???", "???", "???", "???", "???", "???", "???", "???" "???", "???", "???", "???", "???", "???", "???", "???"
}; };
static const char *db_mnemonic[64] = static const char *db_mnemonic[64] =
@ -69,22 +69,22 @@ static const char *mi1_field[16] =
static const char *mi2_field[32] = static const char *mi2_field[32] =
{ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", { "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
"PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" }; "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
static const char *mo_field[32] = static const char *mo_field[32] =
{ "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", { "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7",
"AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" }; "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
static const char *ai1_field[16] = static const char *ai1_field[16] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" }; { "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" };
static const char *ai2_field[32] = static const char *ai2_field[32] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", { "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
"PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" }; "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" };
static const char *ai2f_field[32] = static const char *ai2f_field[32] =
{ "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", { "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7",
"PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" }; "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" };
static char* get_ea(int md, int arx, int ary, int disp) static char* get_ea(int md, int arx, int ary, int disp)
{ {
@ -296,12 +296,12 @@ static char* dasm_control(UINT32 pc, UINT64 opcode)
p += sprintf(p, "DRET"); p += sprintf(p, "DRET");
break; break;
case 0x10: // DBcc case 0x10: // DBcc
case 0x11: // DBNcc case 0x11: // DBNcc
case 0x18: // DCcc case 0x18: // DCcc
case 0x19: // DCNcc case 0x19: // DCNcc
case 0x1a: // DCALL case 0x1a: // DCALL
case 0x12: // DJMP case 0x12: // DJMP
{ {
if (cop == 0x10) if (cop == 0x10)
p += sprintf(p, "%s ", db_mnemonic[ef1]); p += sprintf(p, "%s ", db_mnemonic[ef1]);
@ -798,25 +798,25 @@ static unsigned dasm_mb86235(char *buffer, UINT32 pc, UINT64 opcode)
switch ((opcode >> 61) & 7) switch ((opcode >> 61) & 7)
{ {
case 0: // ALU / MUL / double transfer (type 1) case 0: // ALU / MUL / double transfer (type 1)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_double_xfer1(opcode)); p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_double_xfer1(opcode));
break; break;
case 1: // ALU / MYL / transfer (type 1) case 1: // ALU / MYL / transfer (type 1)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_xfer1(opcode)); p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_xfer1(opcode));
break; break;
case 2: // ALU / MUL / control case 2: // ALU / MUL / control
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_control(pc, opcode)); p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_control(pc, opcode));
break; break;
case 4: // ALU or MUL / double transfer (type 2) case 4: // ALU or MUL / double transfer (type 2)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_double_xfer2(opcode)); p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_double_xfer2(opcode));
break; break;
case 5: // ALU or MUL / transfer (type 2) case 5: // ALU or MUL / transfer (type 2)
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_xfer2(opcode)); p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_xfer2(opcode));
break; break;
case 6: // ALU or MUL / control case 6: // ALU or MUL / control
p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_control(pc, opcode)); p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_control(pc, opcode));
break; break;
case 7: // transfer (type 3) case 7: // transfer (type 3)
p += sprintf(p, "%s", dasm_xfer3(opcode)); p += sprintf(p, "%s", dasm_xfer3(opcode));
break; break;

36
src/devices/cpu/patinhofeio/patinho_feio.cpp
View File

@ -1,7 +1,7 @@
// license:GPL-2.0+ // license:GPL-2.0+
// copyright-holders:Felipe Sanches // copyright-holders:Felipe Sanches
/* /*
CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil
*/ */
#include "emu.h" #include "emu.h"
@ -91,11 +91,11 @@ void patinho_feio_cpu_device::device_start()
//TODO: implement handling of these special purpose registers //TODO: implement handling of these special purpose registers
// which are also mapped to the first few main memory positions: // which are also mapped to the first few main memory positions:
// //
// ERI: "Endereço de Retorno de Interrupção" // ERI: "Endereco de Retorno de Interrupcao"
// "Interrupt Return Address" // "Interrupt Return Address"
// stored at addresses 002 and 003 // stored at addresses 002 and 003
// //
// ETI: "início de uma rotina de tratamento de interrupção (se houver)" // ETI: "inicio de uma rotina de tratamento de interrupcao (se houver)"
// "start of an interrupt service routine (if any)" // "start of an interrupt service routine (if any)"
// stored at address 004 (and 005 as well?) // stored at address 004 (and 005 as well?)
// //
@ -333,7 +333,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x90: case 0x90:
//ST 0 = "Se T=0, Pula" //ST 0 = "Se T=0, Pula"
// If T is zero, skip the next instruction // If T is zero, skip the next instruction
if ((FLAGS & T) == 0) if ((FLAGS & T) == 0)
INCREMENT_PC_4K; //skip INCREMENT_PC_4K; //skip
return; return;
case 0x91: case 0x91:
@ -348,7 +348,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x92: case 0x92:
//ST 1 = "Se T=1, Pula" //ST 1 = "Se T=1, Pula"
// If T is one, skip the next instruction // If T is one, skip the next instruction
if ((FLAGS & T) == 1) if ((FLAGS & T) == 1)
INCREMENT_PC_4K; //skip INCREMENT_PC_4K; //skip
return; return;
case 0x93: case 0x93:
@ -363,7 +363,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x94: case 0x94:
//SV 0 = "Se V=0, Pula" //SV 0 = "Se V=0, Pula"
// If V is zero, skip the next instruction // If V is zero, skip the next instruction
if ((FLAGS & V) == 0) if ((FLAGS & V) == 0)
INCREMENT_PC_4K; //skip INCREMENT_PC_4K; //skip
return; return;
case 0x95: case 0x95:
@ -378,7 +378,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x96: case 0x96:
//SV 1 = "Se V=1, Pula" //SV 1 = "Se V=1, Pula"
// If V is one, skip the next instruction // If V is one, skip the next instruction
if ((FLAGS & V) == 1) if ((FLAGS & V) == 1)
INCREMENT_PC_4K; //skip INCREMENT_PC_4K; //skip
return; return;
case 0x97: case 0x97:
@ -391,17 +391,17 @@ void patinho_feio_cpu_device::execute_instruction()
} }
return; return;
case 0x98: case 0x98:
//PUL="Pula para /002 a limpa estado de interrupção" //PUL="Pula para /002 a limpa estado de interrupcao"
// Jump to address /002 and disables interrupts // Jump to address /002 and disables interrupts
PC = 0x002; PC = 0x002;
m_interrupts_enabled = false; m_interrupts_enabled = false;
return; return;
case 0x99: case 0x99:
//TRE="Troca conteúdos de ACC e EXT" //TRE="Troca conteudos de ACC e EXT"
// Exchange the value of the accumulator with the ACC extension register // Exchange the value of the accumulator with the ACC extension register
value = ACC; value = ACC;
ACC = READ_ACC_EXTENSION_REG(); ACC = READ_ACC_EXTENSION_REG();
WRITE_ACC_EXTENSION_REG(value); WRITE_ACC_EXTENSION_REG(value);
return; return;
case 0x9A: case 0x9A:
//INIB="Inibe" //INIB="Inibe"
@ -621,7 +621,7 @@ void patinho_feio_cpu_device::execute_instruction()
{ {
case 0: case 0:
// FNC /n0: Desliga flip-flop PERMITE/IMPEDE para // FNC /n0: Desliga flip-flop PERMITE/IMPEDE para
// o dispositivo n (isto é, impede inter- // o dispositivo n (isto e, impede inter-
// -rupcao do dispositivo n). // -rupcao do dispositivo n).
// //
// Turns off the interrupt ENABLE/DISABLE // Turns off the interrupt ENABLE/DISABLE
@ -654,7 +654,7 @@ void patinho_feio_cpu_device::execute_instruction()
break; break;
case 5: case 5:
// FNC /n5: Liga flip-flop PERMITE/IMPEDE para o // FNC /n5: Liga flip-flop PERMITE/IMPEDE para o
// dispositivo n (isto é, permite inter- // dispositivo n (isto e, permite inter-
// -rupcao do dispositivo n). // -rupcao do dispositivo n).
// //
// Turns on the interrupt ENABLE/DISABLE // Turns on the interrupt ENABLE/DISABLE
@ -681,7 +681,7 @@ void patinho_feio_cpu_device::execute_instruction()
m_iodev_control[channel] = NO_REQUEST; m_iodev_control[channel] = NO_REQUEST;
break; break;
case 8: case 8:
// FNC /n8: Só funciona na leitora de fita, ca- // FNC /n8: So funciona na leitora de fita, ca-
// nal /E. Ignora todos os "feed-fra- // nal /E. Ignora todos os "feed-fra-
// -mes" ("bytes" nulos) da fita, ate' a // -mes" ("bytes" nulos) da fita, ate' a
// proxima perfuracao (1o "byte" nao // proxima perfuracao (1o "byte" nao
@ -695,7 +695,7 @@ void patinho_feio_cpu_device::execute_instruction()
//TODO: Implement-me! //TODO: Implement-me!
} else { } else {
printf("Function 8 of the /FNC instruction can only be used with"\ printf("Function 8 of the /FNC instruction can only be used with"\
"the papertape reader device at channel /E.\n"); "the papertape reader device at channel /E.\n");
} }
break; break;
default: default:
@ -705,7 +705,7 @@ void patinho_feio_cpu_device::execute_instruction()
case 0x20: case 0x20:
//SAL="Salta" //SAL="Salta"
// Skips a couple bytes if a condition is met // Skips a couple bytes if a condition is met
skip = false; skip = false;
switch(function) switch(function)
{ {
case 1: case 1:

38
src/devices/cpu/patinhofeio/patinhofeio_cpu.h
View File

@ -35,18 +35,18 @@ enum
#define REQUEST true #define REQUEST true
#define NO_REQUEST false #define NO_REQUEST false
#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */ #define BUTTON_NORMAL (1 << 0) /* normal CPU execution */
#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */ #define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */
#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */ #define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */
#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */ #define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */
#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */ #define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */
#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */ #define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */
#define BUTTON_ESPERA (1 << 6) /* wait */ #define BUTTON_ESPERA (1 << 6) /* wait */
#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */ #define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */
#define BUTTON_PARTIDA (1 << 8) /* startup */ #define BUTTON_PARTIDA (1 << 8) /* startup */
#define BUTTON_PREPARACAO (1 << 9) /* reset */ #define BUTTON_PREPARACAO (1 << 9) /* reset */
#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */ #define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */
#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */ #define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */
class patinho_feio_cpu_device : public cpu_device { class patinho_feio_cpu_device : public cpu_device {
public: public:
@ -76,14 +76,14 @@ protected:
/* processor registers */ /* processor registers */
unsigned char m_acc; /* accumulator (8 bits) */ unsigned char m_acc; /* accumulator (8 bits) */
unsigned int m_pc; /* program counter (12 bits) unsigned int m_pc; /* program counter (12 bits)
* Actual register name is CI, which * Actual register name is CI, which
* stands for "Contador de Instrucao" * stands for "Contador de Instrucao"
* or "instructions counter". * or "instructions counter".
*/ */
unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register) unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register)
* It represents the 12 bits of input data * It represents the 12 bits of input data
* from toggle switches in the computer panel * from toggle switches in the computer panel
*/ */
unsigned char m_idx; /* IDX = Index Register */ unsigned char m_idx; /* IDX = Index Register */
unsigned char m_ext; /* EXT = Accumulator Extension Register */ unsigned char m_ext; /* EXT = Accumulator Extension Register */

2
src/devices/cpu/sharc/sharc.cpp
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@ -11,7 +11,7 @@
#include "sharcfe.h" #include "sharcfe.h"
#define DISABLE_FAST_REGISTERS 1 #define DISABLE_FAST_REGISTERS 1

38
src/devices/cpu/sharc/sharc.h
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@ -111,25 +111,25 @@ struct SHARC_DMA_OP
#define MODE2_CAFRZ 0x80000 /* Cache freeze */ #define MODE2_CAFRZ 0x80000 /* Cache freeze */
#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x)) #define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x))
#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x)) #define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x))
#define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length)))) #define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length))))
#define OP_USERFLAG_COUNTER_LOOP 0x00000001 #define OP_USERFLAG_COUNTER_LOOP 0x00000001
#define OP_USERFLAG_COND_LOOP 0x00000002 #define OP_USERFLAG_COND_LOOP 0x00000002
#define OP_USERFLAG_COND_FIELD 0x000003fc #define OP_USERFLAG_COND_FIELD 0x000003fc
#define OP_USERFLAG_COND_FIELD_SHIFT 2 #define OP_USERFLAG_COND_FIELD_SHIFT 2
#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000 #define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000
#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000 #define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000
#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000 #define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000
#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000 #define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000
#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000 #define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000
#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000 #define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000
#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000 #define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000
#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000 #define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000
#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000 #define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000
#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000 #define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000
#define OP_USERFLAG_CALL 0x10000000 #define OP_USERFLAG_CALL 0x10000000
#define MCFG_SHARC_BOOT_MODE(boot_mode) \ #define MCFG_SHARC_BOOT_MODE(boot_mode) \
@ -439,7 +439,7 @@ private:
uml::code_handle *m_pop_loop; uml::code_handle *m_pop_loop;
uml::code_handle *m_push_status; uml::code_handle *m_push_status;
uml::code_handle *m_pop_status; uml::code_handle *m_pop_status;
uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers
uml::code_handle *m_swap_dag1_0_3; uml::code_handle *m_swap_dag1_0_3;
uml::code_handle *m_swap_dag1_4_7; uml::code_handle *m_swap_dag1_4_7;
uml::code_handle *m_swap_dag2_0_3; uml::code_handle *m_swap_dag2_0_3;
@ -596,7 +596,7 @@ private:
{ {
UINT32 cycles; /* accumulated cycles */ UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */ UINT8 checkints; /* need to check interrupts before next instruction */
uml::code_label labelnum; /* index for local labels */ uml::code_label labelnum; /* index for local labels */
struct struct
{ {
int counter; int counter;

1982
src/devices/cpu/sharc/sharcdrc.cpp
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File diff suppressed because it is too large Load Diff

766
src/devices/cpu/sharc/sharcfe.cpp
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File diff suppressed because it is too large Load Diff

1163
src/devices/cpu/sparc/mb86901.cpp
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File diff suppressed because it is too large Load Diff

100
src/devices/cpu/sparc/sparc.h
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@ -11,36 +11,36 @@
#include "sparcdasm.h" #include "sparcdasm.h"
#define SPARCV8 (0) #define SPARCV8 (0)
#define SPARC_NO_TRAP 256 #define SPARC_NO_TRAP 256
#define SPARC_RESET 0 #define SPARC_RESET 0
#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1 #define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
#define SPARC_ILLEGAL_INSTRUCTION 2 #define SPARC_ILLEGAL_INSTRUCTION 2
#define SPARC_PRIVILEGED_INSTRUCTION 3 #define SPARC_PRIVILEGED_INSTRUCTION 3
#define SPARC_FP_DISABLED 4 #define SPARC_FP_DISABLED 4
#define SPARC_WINDOW_OVERFLOW 5 #define SPARC_WINDOW_OVERFLOW 5
#define SPARC_WINDOW_UNDERFLOW 6 #define SPARC_WINDOW_UNDERFLOW 6
#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7 #define SPARC_MEM_ADDRESS_NOT_ALIGNED 7
#define SPARC_FLOATING_POINT_EXCEPTION 8 #define SPARC_FLOATING_POINT_EXCEPTION 8
#define SPARC_DATA_ACCESS_EXCEPTION 9 #define SPARC_DATA_ACCESS_EXCEPTION 9
#define SPARC_TAG_OVERFLOW 10 #define SPARC_TAG_OVERFLOW 10
#define SPARC_INT1 17 #define SPARC_INT1 17
#define SPARC_INT2 18 #define SPARC_INT2 18
#define SPARC_INT3 19 #define SPARC_INT3 19
#define SPARC_INT4 20 #define SPARC_INT4 20
#define SPARC_INT5 21 #define SPARC_INT5 21
#define SPARC_INT6 22 #define SPARC_INT6 22
#define SPARC_INT7 23 #define SPARC_INT7 23
#define SPARC_INT8 24 #define SPARC_INT8 24
#define SPARC_INT9 25 #define SPARC_INT9 25
#define SPARC_INT10 26 #define SPARC_INT10 26
#define SPARC_INT11 27 #define SPARC_INT11 27
#define SPARC_INT12 28 #define SPARC_INT12 28
#define SPARC_INT13 29 #define SPARC_INT13 29
#define SPARC_INT14 30 #define SPARC_INT14 30
#define SPARC_INT15 31 #define SPARC_INT15 31
#define SPARC_TRAP_INSTRUCTION 128 #define SPARC_TRAP_INSTRUCTION 128
#define SPARC_FPU_SEQUENCE_ERROR #define SPARC_FPU_SEQUENCE_ERROR
// TODO: when there are more SPARC CPUs, move setter to a base class // TODO: when there are more SPARC CPUs, move setter to a base class
@ -200,16 +200,16 @@ protected:
UINT8 m_cp_sequence_err; UINT8 m_cp_sequence_err;
// fields separated out from PSR (Processor State Register) // fields separated out from PSR (Processor State Register)
UINT8 m_impl; // implementation (always 0 in MB86901) UINT8 m_impl; // implementation (always 0 in MB86901)
UINT8 m_ver; // version (always 0 in MB86901) UINT8 m_ver; // version (always 0 in MB86901)
UINT8 m_icc; // integer condition codes UINT8 m_icc; // integer condition codes
bool m_ec; // enable coprocessor bool m_ec; // enable coprocessor
bool m_ef; // enable FPU bool m_ef; // enable FPU
UINT8 m_pil; // processor interrupt level UINT8 m_pil; // processor interrupt level
bool m_s; // supervisor mode bool m_s; // supervisor mode
bool m_ps; // prior S state bool m_ps; // prior S state
bool m_et; // enable traps bool m_et; // enable traps
UINT8 m_cwp; // current window pointer UINT8 m_cwp; // current window pointer
bool m_alu_op3_assigned[64]; bool m_alu_op3_assigned[64];
bool m_ldst_op3_assigned[64]; bool m_ldst_op3_assigned[64];
@ -259,10 +259,10 @@ enum
SPARC_ICC, SPARC_ICC,
SPARC_CWP, SPARC_CWP,
SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7, SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7,
SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7, SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7,
SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7, SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7,
SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7, SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7,
SPARC_EC, SPARC_EC,
SPARC_EF, SPARC_EF,
@ -271,13 +271,13 @@ enum
SPARC_S, SPARC_S,
SPARC_PS, SPARC_PS,
SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15, SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15,
SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31, SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31,
SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47, SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47,
SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63, SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63,
SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79, SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79,
SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95, SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95,
SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111 SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111
}; };
#endif /* __SPARC_H__ */ #endif /* __SPARC_H__ */

644
src/devices/cpu/sparc/sparcdefs.h
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@ -12,375 +12,375 @@
#ifndef __MB86901_DEFS_H__ #ifndef __MB86901_DEFS_H__
#define __MB86901_DEFS_H__ #define __MB86901_DEFS_H__
#define PSR_CWP_MASK 0x0000001f #define PSR_CWP_MASK 0x0000001f
#define PSR_ET_SHIFT 5 #define PSR_ET_SHIFT 5
#define PSR_ET_MASK 0x00000020 #define PSR_ET_MASK 0x00000020
#define PSR_PS_SHIFT 6 #define PSR_PS_SHIFT 6
#define PSR_PS_MASK 0x00000040 #define PSR_PS_MASK 0x00000040
#define PSR_S_SHIFT 7 #define PSR_S_SHIFT 7
#define PSR_S_MASK 0x00000080 #define PSR_S_MASK 0x00000080
#define PSR_PIL_SHIFT 8 #define PSR_PIL_SHIFT 8
#define PSR_PIL_MASK 0x00000f00 #define PSR_PIL_MASK 0x00000f00
#define PSR_EF_SHIFT 12 #define PSR_EF_SHIFT 12
#define PSR_EF_MASK 0x00001000 #define PSR_EF_MASK 0x00001000
#define PSR_EC_SHIFT 13 #define PSR_EC_SHIFT 13
#define PSR_EC_MASK 0x00002000 #define PSR_EC_MASK 0x00002000
#define PSR_ICC_SHIFT 20 #define PSR_ICC_SHIFT 20
#define PSR_RES_MASK 0x000fc000 #define PSR_RES_MASK 0x000fc000
#define PSR_ICC_MASK 0x00f00000 #define PSR_ICC_MASK 0x00f00000
#define PSR_N_MASK 0x00800000 #define PSR_N_MASK 0x00800000
#define PSR_Z_MASK 0x00400000 #define PSR_Z_MASK 0x00400000
#define PSR_V_MASK 0x00200000 #define PSR_V_MASK 0x00200000
#define PSR_C_MASK 0x00100000 #define PSR_C_MASK 0x00100000
#define PSR_VER_SHIFT 24 #define PSR_VER_SHIFT 24
#define PSR_VER_MASK 0x0f000000 #define PSR_VER_MASK 0x0f000000
#define PSR_VER 0 #define PSR_VER 0
#define PSR_IMPL_SHIFT 28 #define PSR_IMPL_SHIFT 28
#define PSR_IMPL_MASK 0xf0000000 #define PSR_IMPL_MASK 0xf0000000
#define PSR_IMPL 0 #define PSR_IMPL 0
#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK) #define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
#define ICC_N_SET (m_psr & PSR_N_MASK) #define ICC_N_SET (m_psr & PSR_N_MASK)
#define ICC_N (ICC_N_SET ? 1 : 0) #define ICC_N (ICC_N_SET ? 1 : 0)
#define ICC_N_CLEAR (!ICC_N_SET) #define ICC_N_CLEAR (!ICC_N_SET)
#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0) #define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0)
#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0) #define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0)
#define ICC_Z_SET (m_psr & PSR_Z_MASK) #define ICC_Z_SET (m_psr & PSR_Z_MASK)
#define ICC_Z (ICC_Z_SET ? 1 : 0) #define ICC_Z (ICC_Z_SET ? 1 : 0)
#define ICC_Z_CLEAR (!ICC_Z_SET) #define ICC_Z_CLEAR (!ICC_Z_SET)
#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0) #define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0)
#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0) #define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0)
#define ICC_V_SET (m_psr & PSR_V_MASK) #define ICC_V_SET (m_psr & PSR_V_MASK)
#define ICC_V (ICC_V_SET ? 1 : 0) #define ICC_V (ICC_V_SET ? 1 : 0)
#define ICC_V_CLEAR (!ICC_V_SET) #define ICC_V_CLEAR (!ICC_V_SET)
#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0) #define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0)
#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0) #define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0)
#define ICC_C_SET (m_psr & PSR_C_MASK) #define ICC_C_SET (m_psr & PSR_C_MASK)
#define ICC_C (ICC_C_SET ? 1 : 0) #define ICC_C (ICC_C_SET ? 1 : 0)
#define ICC_C_CLEAR (!ICC_C_SET) #define ICC_C_CLEAR (!ICC_C_SET)
#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0) #define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0)
#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0) #define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0)
#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0) #define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0)
#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0) #define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0)
#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0) #define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0)
#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0) #define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0)
#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0) #define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0)
#define CWP m_cwp #define CWP m_cwp
#define S m_s #define S m_s
#define PS m_ps #define PS m_ps
#define IS_SUPERVISOR (m_psr & PSR_S_MASK) #define IS_SUPERVISOR (m_psr & PSR_S_MASK)
#define IS_USER (!IS_SUPERVISOR) #define IS_USER (!IS_SUPERVISOR)
#define TRAPS_ENABLED (m_psr & PSR_ET_MASK) #define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
#define TRAPS_DISABLED (!TRAPS_ENABLED) #define TRAPS_DISABLED (!TRAPS_ENABLED)
#define PSR m_psr #define PSR m_psr
#define WIM m_wim #define WIM m_wim
#define TBR m_tbr #define TBR m_tbr
#define OP (op >> 30) // gangnam style #define OP (op >> 30) // gangnam style
#define OP2 ((op >> 22) & 7) #define OP2 ((op >> 22) & 7)
#define OP3 ((op >> 19) & 63) #define OP3 ((op >> 19) & 63)
#define OPF ((op >> 5) & 0x1ff) #define OPF ((op >> 5) & 0x1ff)
#define OPC ((op >> 5) & 0x1ff) #define OPC ((op >> 5) & 0x1ff)
#define OPFLOW ((op >> 5) & 0x3f) #define OPFLOW ((op >> 5) & 0x3f)
#define DISP30 (INT32(op << 2)) #define DISP30 (INT32(op << 2))
#define DISP22 (INT32(op << 10) >> 8) #define DISP22 (INT32(op << 10) >> 8)
#define DISP19 (INT32(op << 13) >> 11) #define DISP19 (INT32(op << 13) >> 11)
#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14) #define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
#define IMM22 (op << 10) #define IMM22 (op << 10)
#define CONST22 (op & 0x3fffff) #define CONST22 (op & 0x3fffff)
#define SIMM13 (INT32(op << 19) >> 19) #define SIMM13 (INT32(op << 19) >> 19)
#define SIMM11 (INT32(op << 21) >> 21) #define SIMM11 (INT32(op << 21) >> 21)
#define SIMM10 (INT32(op << 22) >> 22) #define SIMM10 (INT32(op << 22) >> 22)
#define SIMM8 (INT32(op << 24) >> 24) #define SIMM8 (INT32(op << 24) >> 24)
#define IMM7 (op & 0x7f) #define IMM7 (op & 0x7f)
#define SIMM7 (INT32(op << 25) >> 25) #define SIMM7 (INT32(op << 25) >> 25)
#define SHCNT32 (op & 31) #define SHCNT32 (op & 31)
#define SHCNT64 (op & 63) #define SHCNT64 (op & 63)
#define IAMODE (op & 0x7) #define IAMODE (op & 0x7)
#define USEIMM ((op >> 13) & 1) #define USEIMM ((op >> 13) & 1)
#define USEEXT ((op >> 12) & 1) #define USEEXT ((op >> 12) & 1)
#define COND ((op >> 25) & 15) #define COND ((op >> 25) & 15)
#define RCOND ((op >> 10) & 7) #define RCOND ((op >> 10) & 7)
#define MOVCOND ((op >> 14) & 15) #define MOVCOND ((op >> 14) & 15)
#define PRED ((op >> 19) & 1) #define PRED ((op >> 19) & 1)
#define ANNUL ((op >> 29) & 1) #define ANNUL ((op >> 29) & 1)
#define BRCC ((op >> 20) & 3) #define BRCC ((op >> 20) & 3)
#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4)) #define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
#define OPFCC ((op >> 11) & 7) #define OPFCC ((op >> 11) & 7)
#define TCCCC ((op >> 11) & 3) #define TCCCC ((op >> 11) & 3)
#define ASI ((op >> 5) & 255) #define ASI ((op >> 5) & 255)
#define MMASK (op & 15) #define MMASK (op & 15)
#define CMASK ((op >> 4) & 7) #define CMASK ((op >> 4) & 7)
#define RD ((op >> 25) & 31) #define RD ((op >> 25) & 31)
#define RS1 ((op >> 14) & 31) #define RS1 ((op >> 14) & 31)
#define RS2 (op & 31) #define RS2 (op & 31)
#define FREG(x) m_fpr[(x)] #define FREG(x) m_fpr[(x)]
#define FDREG m_fpr[RD] #define FDREG m_fpr[RD]
#define FSR m_fsr #define FSR m_fsr
#define REG(x) *m_regs[(x)] #define REG(x) *m_regs[(x)]
#define RDREG *m_regs[RD] #define RDREG *m_regs[RD]
#define RS1REG *m_regs[RS1] #define RS1REG *m_regs[RS1]
#define RS2REG *m_regs[RS2] #define RS2REG *m_regs[RS2]
#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0) #define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG)) #define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
#define PC m_pc #define PC m_pc
#define nPC m_npc #define nPC m_npc
#define Y m_y #define Y m_y
#define ET m_et #define ET m_et
#define EF m_ef #define EF m_ef
#define EC m_ec #define EC m_ec
#define PIL m_pil #define PIL m_pil
#define MAE m_mae #define MAE m_mae
#define HOLD_BUS m_hold_bus #define HOLD_BUS m_hold_bus
#define BIT31(x) ((x) & 0x80000000) #define BIT31(x) ((x) & 0x80000000)
#define UPDATE_PC true #define UPDATE_PC true
#define PC_UPDATED false #define PC_UPDATED false
#define OP_TYPE0 0 #define OP_TYPE0 0
#define OP_CALL 1 #define OP_CALL 1
#define OP_ALU 2 #define OP_ALU 2
#define OP_LDST 3 #define OP_LDST 3
#define OP2_UNIMP 0 #define OP2_UNIMP 0
#define OP2_BICC 2 #define OP2_BICC 2
#define OP2_SETHI 4 #define OP2_SETHI 4
#define OP2_FBFCC 6 #define OP2_FBFCC 6
#define OP2_CBCCC 7 #define OP2_CBCCC 7
#define OP3_ADD 0 #define OP3_ADD 0
#define OP3_AND 1 #define OP3_AND 1
#define OP3_OR 2 #define OP3_OR 2
#define OP3_XOR 3 #define OP3_XOR 3
#define OP3_SUB 4 #define OP3_SUB 4
#define OP3_ANDN 5 #define OP3_ANDN 5
#define OP3_ORN 6 #define OP3_ORN 6
#define OP3_XNOR 7 #define OP3_XNOR 7
#define OP3_ADDX 8 #define OP3_ADDX 8
#define OP3_UMUL 10 #define OP3_UMUL 10
#define OP3_SMUL 11 #define OP3_SMUL 11
#define OP3_SUBX 12 #define OP3_SUBX 12
#define OP3_UDIV 14 #define OP3_UDIV 14
#define OP3_SDIV 15 #define OP3_SDIV 15
#define OP3_ADDCC 16 #define OP3_ADDCC 16
#define OP3_ANDCC 17 #define OP3_ANDCC 17
#define OP3_ORCC 18 #define OP3_ORCC 18
#define OP3_XORCC 19 #define OP3_XORCC 19
#define OP3_SUBCC 20 #define OP3_SUBCC 20
#define OP3_ANDNCC 21 #define OP3_ANDNCC 21
#define OP3_ORNCC 22 #define OP3_ORNCC 22
#define OP3_XNORCC 23 #define OP3_XNORCC 23
#define OP3_ADDXCC 24 #define OP3_ADDXCC 24
#define OP3_UMULCC 26 #define OP3_UMULCC 26
#define OP3_SMULCC 27 #define OP3_SMULCC 27
#define OP3_SUBXCC 28 #define OP3_SUBXCC 28
#define OP3_UDIVCC 30 #define OP3_UDIVCC 30
#define OP3_SDIVCC 31 #define OP3_SDIVCC 31
#define OP3_TADDCC 32 #define OP3_TADDCC 32
#define OP3_TSUBCC 33 #define OP3_TSUBCC 33
#define OP3_TADDCCTV 34 #define OP3_TADDCCTV 34
#define OP3_TSUBCCTV 35 #define OP3_TSUBCCTV 35
#define OP3_MULSCC 36 #define OP3_MULSCC 36
#define OP3_SLL 37 #define OP3_SLL 37
#define OP3_SRL 38 #define OP3_SRL 38
#define OP3_SRA 39 #define OP3_SRA 39
#define OP3_RDASR 40 #define OP3_RDASR 40
#define OP3_RDPSR 41 #define OP3_RDPSR 41
#define OP3_RDWIM 42 #define OP3_RDWIM 42
#define OP3_RDTBR 43 #define OP3_RDTBR 43
#define OP3_WRASR 48 #define OP3_WRASR 48
#define OP3_WRPSR 49 #define OP3_WRPSR 49
#define OP3_WRWIM 50 #define OP3_WRWIM 50
#define OP3_WRTBR 51 #define OP3_WRTBR 51
#define OP3_FPOP1 52 #define OP3_FPOP1 52
#define OP3_FPOP2 53 #define OP3_FPOP2 53
#define OP3_JMPL 56 #define OP3_JMPL 56
#define OP3_RETT 57 #define OP3_RETT 57
#define OP3_TICC 58 #define OP3_TICC 58
#define OP3_SAVE 60 #define OP3_SAVE 60
#define OP3_RESTORE 61 #define OP3_RESTORE 61
#define OP3_LD 0 #define OP3_LD 0
#define OP3_LDUB 1 #define OP3_LDUB 1
#define OP3_LDUH 2 #define OP3_LDUH 2
#define OP3_LDD 3 #define OP3_LDD 3
#define OP3_ST 4 #define OP3_ST 4
#define OP3_STB 5 #define OP3_STB 5
#define OP3_STH 6 #define OP3_STH 6
#define OP3_STD 7 #define OP3_STD 7
#define OP3_LDSB 9 #define OP3_LDSB 9
#define OP3_LDSH 10 #define OP3_LDSH 10
#define OP3_LDSTUB 13 #define OP3_LDSTUB 13
#define OP3_SWAP 15 #define OP3_SWAP 15
#define OP3_LDA 16 #define OP3_LDA 16
#define OP3_LDUBA 17 #define OP3_LDUBA 17
#define OP3_LDUHA 18 #define OP3_LDUHA 18
#define OP3_LDDA 19 #define OP3_LDDA 19
#define OP3_STA 20 #define OP3_STA 20
#define OP3_STBA 21 #define OP3_STBA 21
#define OP3_STHA 22 #define OP3_STHA 22
#define OP3_STDA 23 #define OP3_STDA 23
#define OP3_LDSBA 25 #define OP3_LDSBA 25
#define OP3_LDSHA 26 #define OP3_LDSHA 26
#define OP3_LDSTUBA 29 #define OP3_LDSTUBA 29
#define OP3_SWAPA 31 #define OP3_SWAPA 31
#define OP3_LDFPR 32 #define OP3_LDFPR 32
#define OP3_LDFSR 33 #define OP3_LDFSR 33
#define OP3_LDDFPR 35 #define OP3_LDDFPR 35
#define OP3_STFPR 36 #define OP3_STFPR 36
#define OP3_STFSR 37 #define OP3_STFSR 37
#define OP3_STDFQ 38 #define OP3_STDFQ 38
#define OP3_STDFPR 39 #define OP3_STDFPR 39
#define OP3_LDCPR 40 #define OP3_LDCPR 40
#define OP3_LDCSR 41 #define OP3_LDCSR 41
#define OP3_LDDCPR 43 #define OP3_LDDCPR 43
#define OP3_STCPR 44 #define OP3_STCPR 44
#define OP3_STCSR 45 #define OP3_STCSR 45
#define OP3_STDCQ 46 #define OP3_STDCQ 46
#define OP3_STDCPR 47 #define OP3_STDCPR 47
#define OP3_CPOP1 54 #define OP3_CPOP1 54
#define OP3_CPOP2 55 #define OP3_CPOP2 55
#define COND_BN 0 #define COND_BN 0
#define COND_BE 1 #define COND_BE 1
#define COND_BLE 2 #define COND_BLE 2
#define COND_BL 3 #define COND_BL 3
#define COND_BLEU 4 #define COND_BLEU 4
#define COND_BCS 5 #define COND_BCS 5
#define COND_BNEG 6 #define COND_BNEG 6
#define COND_BVS 7 #define COND_BVS 7
#define COND_BA 8 #define COND_BA 8
#define COND_BNE 9 #define COND_BNE 9
#define COND_BG 10 #define COND_BG 10
#define COND_BGE 11 #define COND_BGE 11
#define COND_BGU 12 #define COND_BGU 12
#define COND_BCC 13 #define COND_BCC 13
#define COND_BPOS 14 #define COND_BPOS 14
#define COND_BVC 15 #define COND_BVC 15
#define LDD (OP3 == OP3_LDD) #define LDD (OP3 == OP3_LDD)
#define LD (OP3 == OP3_LD) #define LD (OP3 == OP3_LD)
#define LDSH (OP3 == OP3_LDSH) #define LDSH (OP3 == OP3_LDSH)
#define LDUH (OP3 == OP3_LDUH) #define LDUH (OP3 == OP3_LDUH)
#define LDSB (OP3 == OP3_LDSB) #define LDSB (OP3 == OP3_LDSB)
#define LDUB (OP3 == OP3_LDUB) #define LDUB (OP3 == OP3_LDUB)
#define LDDF (OP3 == OP3_LDDFPR) #define LDDF (OP3 == OP3_LDDFPR)
#define LDF (OP3 == OP3_LDFPR) #define LDF (OP3 == OP3_LDFPR)
#define LDFSR (OP3 == OP3_LDFSR) #define LDFSR (OP3 == OP3_LDFSR)
#define LDDC (OP3 == OP3_LDDCPR) #define LDDC (OP3 == OP3_LDDCPR)
#define LDC (OP3 == OP3_LDCPR) #define LDC (OP3 == OP3_LDCPR)
#define LDCSR (OP3 == OP3_LDCSR) #define LDCSR (OP3 == OP3_LDCSR)
#define LDDA (OP3 == OP3_LDDA) #define LDDA (OP3 == OP3_LDDA)
#define LDA (OP3 == OP3_LDA) #define LDA (OP3 == OP3_LDA)
#define LDSHA (OP3 == OP3_LDSHA) #define LDSHA (OP3 == OP3_LDSHA)
#define LDUHA (OP3 == OP3_LDUHA) #define LDUHA (OP3 == OP3_LDUHA)
#define LDSBA (OP3 == OP3_LDSBA) #define LDSBA (OP3 == OP3_LDSBA)
#define LDUBA (OP3 == OP3_LDUBA) #define LDUBA (OP3 == OP3_LDUBA)
#define STD (OP3 == OP3_STD) #define STD (OP3 == OP3_STD)
#define ST (OP3 == OP3_ST) #define ST (OP3 == OP3_ST)
#define STH (OP3 == OP3_STH) #define STH (OP3 == OP3_STH)
#define STB (OP3 == OP3_STB) #define STB (OP3 == OP3_STB)
#define STDA (OP3 == OP3_STDA) #define STDA (OP3 == OP3_STDA)
#define STA (OP3 == OP3_STA) #define STA (OP3 == OP3_STA)
#define STHA (OP3 == OP3_STHA) #define STHA (OP3 == OP3_STHA)
#define STBA (OP3 == OP3_STBA) #define STBA (OP3 == OP3_STBA)
#define STF (OP3 == OP3_STFPR) #define STF (OP3 == OP3_STFPR)
#define STFSR (OP3 == OP3_STFSR) #define STFSR (OP3 == OP3_STFSR)
#define STDFQ (OP3 == OP3_STDFQ) #define STDFQ (OP3 == OP3_STDFQ)
#define STDF (OP3 == OP3_STDFPR) #define STDF (OP3 == OP3_STDFPR)
#define STC (OP3 == OP3_STCPR) #define STC (OP3 == OP3_STCPR)
#define STCSR (OP3 == OP3_STCSR) #define STCSR (OP3 == OP3_STCSR)
#define STDCQ (OP3 == OP3_STDCQ) #define STDCQ (OP3 == OP3_STDCQ)
#define STDC (OP3 == OP3_STDCPR) #define STDC (OP3 == OP3_STDCPR)
#define JMPL (OP3 == OP3_JMPL) #define JMPL (OP3 == OP3_JMPL)
#define TICC (OP3 == OP3_TICC) #define TICC (OP3 == OP3_TICC)
#define RETT (OP3 == OP3_RETT) #define RETT (OP3 == OP3_RETT)
#define SWAP (OP3 == OP3_SWAP) #define SWAP (OP3 == OP3_SWAP)
#define SWAPA (OP3 == OP3_SWAPA) #define SWAPA (OP3 == OP3_SWAPA)
#define FPOP1 (OP3 == OP3_FPOP1) #define FPOP1 (OP3 == OP3_FPOP1)
#define FPOP2 (OP3 == OP3_FPOP2) #define FPOP2 (OP3 == OP3_FPOP2)
#define CPOP1 (OP3 == OP3_CPOP1) #define CPOP1 (OP3 == OP3_CPOP1)
#define CPOP2 (OP3 == OP3_CPOP2) #define CPOP2 (OP3 == OP3_CPOP2)
#define LDSTUB (OP3 == OP3_LDSTUB) #define LDSTUB (OP3 == OP3_LDSTUB)
#define LDSTUBA (OP3 == OP3_LDSTUBA) #define LDSTUBA (OP3 == OP3_LDSTUBA)
#define ADD (OP3 == OP3_ADD) #define ADD (OP3 == OP3_ADD)
#define ADDX (OP3 == OP3_ADDX) #define ADDX (OP3 == OP3_ADDX)
#define ADDCC (OP3 == OP3_ADDCC) #define ADDCC (OP3 == OP3_ADDCC)
#define ADDXCC (OP3 == OP3_ADDXCC) #define ADDXCC (OP3 == OP3_ADDXCC)
#define SUB (OP3 == OP3_SUB) #define SUB (OP3 == OP3_SUB)
#define SUBX (OP3 == OP3_SUBX) #define SUBX (OP3 == OP3_SUBX)
#define SUBCC (OP3 == OP3_SUBCC) #define SUBCC (OP3 == OP3_SUBCC)
#define SUBXCC (OP3 == OP3_SUBXCC) #define SUBXCC (OP3 == OP3_SUBXCC)
#define TADDCCTV (OP3 == OP3_TADDCCTV) #define TADDCCTV (OP3 == OP3_TADDCCTV)
#define TSUBCCTV (OP3 == OP3_TSUBCCTV) #define TSUBCCTV (OP3 == OP3_TSUBCCTV)
#define AND (OP3 == OP3_AND) #define AND (OP3 == OP3_AND)
#define OR (OP3 == OP3_OR) #define OR (OP3 == OP3_OR)
#define XOR (OP3 == OP3_XOR) #define XOR (OP3 == OP3_XOR)
#define ANDN (OP3 == OP3_ANDN) #define ANDN (OP3 == OP3_ANDN)
#define ORN (OP3 == OP3_ORN) #define ORN (OP3 == OP3_ORN)
#define XNOR (OP3 == OP3_XNOR) #define XNOR (OP3 == OP3_XNOR)
#define ANDCC (OP3 == OP3_ANDCC) #define ANDCC (OP3 == OP3_ANDCC)
#define ORCC (OP3 == OP3_ORCC) #define ORCC (OP3 == OP3_ORCC)
#define XORCC (OP3 == OP3_XORCC) #define XORCC (OP3 == OP3_XORCC)
#define ANDNCC (OP3 == OP3_ANDNCC) #define ANDNCC (OP3 == OP3_ANDNCC)
#define ORNCC (OP3 == OP3_ORNCC) #define ORNCC (OP3 == OP3_ORNCC)
#define XNORCC (OP3 == OP3_XNORCC) #define XNORCC (OP3 == OP3_XNORCC)
#define SLL (OP3 == OP3_SLL) #define SLL (OP3 == OP3_SLL)
#define SRL (OP3 == OP3_SRL) #define SRL (OP3 == OP3_SRL)
#define SRA (OP3 == OP3_SRA) #define SRA (OP3 == OP3_SRA)
#define RDASR (OP3 == OP3_RDASR) #define RDASR (OP3 == OP3_RDASR)
#define RDPSR (OP3 == OP3_RDPSR) #define RDPSR (OP3 == OP3_RDPSR)
#define RDWIM (OP3 == OP3_RDWIM) #define RDWIM (OP3 == OP3_RDWIM)
#define RDTBR (OP3 == OP3_RDTBR) #define RDTBR (OP3 == OP3_RDTBR)
#define WRASR (OP3 == OP3_WRASR) #define WRASR (OP3 == OP3_WRASR)
#define WRPSR (OP3 == OP3_WRPSR) #define WRPSR (OP3 == OP3_WRPSR)
#define WRWIM (OP3 == OP3_WRWIM) #define WRWIM (OP3 == OP3_WRWIM)
#define WRTBR (OP3 == OP3_WRTBR) #define WRTBR (OP3 == OP3_WRTBR)
#define SAVE (OP3 == OP3_SAVE) #define SAVE (OP3 == OP3_SAVE)
#define RESTORE (OP3 == OP3_RESTORE) #define RESTORE (OP3 == OP3_RESTORE)
#define UMUL (OP3 == OP3_UMUL) #define UMUL (OP3 == OP3_UMUL)
#define UMULCC (OP3 == OP3_UMULCC) #define UMULCC (OP3 == OP3_UMULCC)
#define SMUL (OP3 == OP3_SMUL) #define SMUL (OP3 == OP3_SMUL)
#define SMULCC (OP3 == OP3_SMULCC) #define SMULCC (OP3 == OP3_SMULCC)
#define UDIV (OP3 == OP3_UDIV) #define UDIV (OP3 == OP3_UDIV)
#define UDIVCC (OP3 == OP3_UDIVCC) #define UDIVCC (OP3 == OP3_UDIVCC)
#define SDIV (OP3 == OP3_SDIV) #define SDIV (OP3 == OP3_SDIV)
#define SDIVCC (OP3 == OP3_SDIVCC) #define SDIVCC (OP3 == OP3_SDIVCC)
#endif // __MB86901_DEFS_H__ #endif // __MB86901_DEFS_H__

6
src/devices/imagedev/cassette.cpp
View File

@ -359,7 +359,7 @@ void cassette_image_device::call_unload()
//------------------------------------------------- //-------------------------------------------------
// display a small tape animation, with the // display a small tape animation, with the
// current position in the tape image // current position in the tape image
//------------------------------------------------- //-------------------------------------------------
std::string cassette_image_device::call_display() std::string cassette_image_device::call_display()
@ -391,8 +391,8 @@ std::string cassette_image_device::call_display()
// Since you can have anything in a BDF file, we will use crude ascii characters instead // Since you can have anything in a BDF file, we will use crude ascii characters instead
result = string_format("%s %s %02d:%02d (%04d) [%02d:%02d (%04d)]", result = string_format("%s %s %02d:%02d (%04d) [%02d:%02d (%04d)]",
shapes[n], // animation shapes[n], // animation
status_icon, // play or record status_icon, // play or record
((int)position / 60), ((int)position / 60),
((int)position % 60), ((int)position % 60),
(int)position, (int)position,

168
src/devices/machine/68230pit.cpp
View File

@ -46,7 +46,7 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
//------------------------------------------------- //-------------------------------------------------
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source) pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source), : device_t (mconfig, type, name, tag, owner, clock, shortname, source),
device_execute_interface (mconfig, *this) device_execute_interface (mconfig, *this)
, m_icount (0) , m_icount (0)
, m_pa_out_cb(*this) , m_pa_out_cb(*this)
, m_pa_in_cb(*this) , m_pa_in_cb(*this)
@ -70,9 +70,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_psr(0) , m_psr(0)
, m_tcr(0) , m_tcr(0)
, m_cpr(0) , m_cpr(0)
// , m_cprh(0) // , m_cprh(0)
// , m_cprm(0) // , m_cprm(0)
// , m_cprl(0) // , m_cprl(0)
, m_cntr(0) , m_cntr(0)
{ {
} }
@ -80,7 +80,7 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__), : device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
device_execute_interface (mconfig, *this) device_execute_interface (mconfig, *this)
, m_icount (0) , m_icount (0)
, m_pa_out_cb (*this) , m_pa_out_cb (*this)
, m_pa_in_cb(*this) , m_pa_in_cb(*this)
@ -104,9 +104,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_psr(0) , m_psr(0)
, m_tcr(0) , m_tcr(0)
, m_cpr(0) , m_cpr(0)
// , m_cprh(0) // , m_cprh(0)
// , m_cprm(0) // , m_cprm(0)
// , m_cprl(0) // , m_cprl(0)
, m_cntr(0) , m_cntr(0)
{ {
} }
@ -271,62 +271,62 @@ at all times. All bits are cleared to zero when the RESET pin is asserted.
TCR bits TCR bits
7 6 5 TOUT/TIACK Control 7 6 5 TOUT/TIACK Control
---------------------------- ----------------------------
0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function. 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
pin PC7/TIACK carries the PC7 function. pin PC7/TIACK carries the PC7 function.
1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated. a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
5.1.3. Timer Interrupt Acknowledge Cycles for details. 5.1.3. Timer Interrupt Acknowledge Cycles for details.
1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
supports vectored timer interrupts. supports vectored timer interrupts.
1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
pin PC7/TIACK carries the PC7 function. pin PC7/TIACK carries the PC7 function.
1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported. The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
TCR bit 4 - Zero Detect Control TCR bit 4 - Zero Detect Control
0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
zero detect, then resumes counting. zero detect, then resumes counting.
1 The counter rolls over on zero detect, then continues counting. 1 The counter rolls over on zero detect, then continues counting.
TCR bit 3 - Unused and is always read as zero. TCR bit 3 - Unused and is always read as zero.
TCR bits TCR bits
2 1 Clock Control 2 1 Clock Control
0 0 The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The 0 0 The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The
prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented, prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
to $1F. The timer enable bit determines whether the timer is in the run or halt state. to $1F. The timer enable bit determines whether the timer is in the run or halt state.
0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F. over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise, The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
the timer is in the halt state. the timer is in the halt state.
1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
following the rising transition of the TIN pin after being synchronized with the internal clock. The following the rising transition of the TIN pin after being synchronized with the internal clock. The
24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
run or halt state. run or halt state.
1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented, 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
rolls over, or is loaded from the counter preload registers following the rising edge of rolls over, or is loaded from the counter preload registers following the rising edge of
the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
the timer is in the run or halt state. the timer is in the run or halt state.
TCR bit 0 - Timer Enable TCR bit 0 - Timer Enable
0 Disabled 0 Disabled
1 Enabled 1 Enabled
*/ */
void pit68230_device::wr_pitreg_tcr(UINT8 data) void pit68230_device::wr_pitreg_tcr(UINT8 data)
{ {
LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n", LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled")); FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
m_tcr = data; m_tcr = data;
} }
@ -335,7 +335,7 @@ void pit68230_device::wr_pitreg_cprh(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data)); LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0xff0000; m_cpr &= ~0xff0000;
m_cpr |= ((data << 16) & 0xff0000); m_cpr |= ((data << 16) & 0xff0000);
// m_cprh = data; // m_cprh = data;
} }
void pit68230_device::wr_pitreg_cprm(UINT8 data) void pit68230_device::wr_pitreg_cprm(UINT8 data)
@ -343,7 +343,7 @@ void pit68230_device::wr_pitreg_cprm(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data)); LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x00ff00; m_cpr &= ~0x00ff00;
m_cpr |= ((data << 8) & 0x00ff00); m_cpr |= ((data << 8) & 0x00ff00);
// m_cprm = data; // m_cprm = data;
} }
void pit68230_device::wr_pitreg_cprl(UINT8 data) void pit68230_device::wr_pitreg_cprl(UINT8 data)
@ -351,28 +351,28 @@ void pit68230_device::wr_pitreg_cprl(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data)); LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x0000ff; m_cpr &= ~0x0000ff;
m_cpr |= ((data << 0) & 0x0000ff); m_cpr |= ((data << 0) & 0x0000ff);
// m_cprl = data; // m_cprl = data;
} }
WRITE8_MEMBER (pit68230_device::write) WRITE8_MEMBER (pit68230_device::write)
{ {
LOG(("%s %s \n",tag(), FUNCNAME)); LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) { switch (offset) {
case PIT_68230_PGCR: wr_pitreg_pgcr(data); break; case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
case PIT_68230_PSRR: wr_pitreg_psrr(data); break; case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
case PIT_68230_PADDR: wr_pitreg_paddr(data); break; case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break; case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break; case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
case PIT_68230_PACR: wr_pitreg_pacr(data); break; case PIT_68230_PACR: wr_pitreg_pacr(data); break;
case PIT_68230_PBCR: wr_pitreg_pbcr(data); break; case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
case PIT_68230_PADR: wr_pitreg_padr(data); break; case PIT_68230_PADR: wr_pitreg_padr(data); break;
case PIT_68230_PAAR: break; // RO register so ignored case PIT_68230_PAAR: break; // RO register so ignored
case PIT_68230_PBAR: break; // RO register so ignored case PIT_68230_PBAR: break; // RO register so ignored
case PIT_68230_PSR: wr_pitreg_psr(data); break; case PIT_68230_PSR: wr_pitreg_psr(data); break;
case PIT_68230_TCR: wr_pitreg_tcr(data); break; case PIT_68230_TCR: wr_pitreg_tcr(data); break;
case PIT_68230_CPRH: wr_pitreg_cprh(data); break; case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
case PIT_68230_CPRM: wr_pitreg_cprm(data); break; case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
case PIT_68230_CPRL: wr_pitreg_cprl(data); break; case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
default: default:
LOG (("Unhandled Write of %02x to register %02x", data, offset)); LOG (("Unhandled Write of %02x to register %02x", data, offset));
} }
@ -518,21 +518,21 @@ READ8_MEMBER (pit68230_device::read){
UINT8 data; UINT8 data;
switch (offset) { switch (offset) {
case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break; case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
case PIT_68230_PSRR: data = rr_pitreg_psrr(); break; case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
case PIT_68230_PADDR: data = rr_pitreg_paddr(); break; case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break; case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break; case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
case PIT_68230_PACR: data = rr_pitreg_pacr(); break; case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break; case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
case PIT_68230_PADR: data = rr_pitreg_padr(); break; case PIT_68230_PADR: data = rr_pitreg_padr(); break;
case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break; case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
case PIT_68230_PAAR: data = rr_pitreg_paar(); break; case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
case PIT_68230_PBAR: data = rr_pitreg_pbar(); break; case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
case PIT_68230_PSR: data = rr_pitreg_psr(); break; case PIT_68230_PSR: data = rr_pitreg_psr(); break;
case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break; case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break; case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break; case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
default: default:
LOG (("Unhandled read register %02x\n", offset)); LOG (("Unhandled read register %02x\n", offset));
data = 0; data = 0;

36
src/devices/machine/68230pit.h
View File

@ -105,7 +105,7 @@
//************************************************************************** //**************************************************************************
class pit68230_device : public device_t, public device_execute_interface class pit68230_device : public device_t, public device_execute_interface
{ {
public: public:
// construction/destruction // construction/destruction
pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source); pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
@ -161,7 +161,7 @@ class pit68230_device : public device_t, public device_execute_interface
protected: protected:
enum { enum {
REG_TCR_ENABLE = 0x01 REG_TCR_ENABLE = 0x01
}; };
// device-level overrides // device-level overrides
@ -171,16 +171,16 @@ protected:
virtual void execute_run () override; virtual void execute_run () override;
int m_icount; int m_icount;
devcb_write8 m_pa_out_cb; devcb_write8 m_pa_out_cb;
devcb_read8 m_pa_in_cb; devcb_read8 m_pa_in_cb;
devcb_write8 m_pb_out_cb; devcb_write8 m_pb_out_cb;
devcb_read8 m_pb_in_cb; devcb_read8 m_pb_in_cb;
devcb_write8 m_pc_out_cb; devcb_write8 m_pc_out_cb;
devcb_read8 m_pc_in_cb; devcb_read8 m_pc_in_cb;
devcb_write_line m_h1_out_cb; devcb_write_line m_h1_out_cb;
devcb_write_line m_h2_out_cb; devcb_write_line m_h2_out_cb;
devcb_write_line m_h3_out_cb; devcb_write_line m_h3_out_cb;
devcb_write_line m_h4_out_cb; devcb_write_line m_h4_out_cb;
// peripheral ports // peripheral ports
UINT8 m_pgcr; // Port General Control register UINT8 m_pgcr; // Port General Control register
@ -193,12 +193,12 @@ protected:
UINT8 m_padr; // Port A Data register UINT8 m_padr; // Port A Data register
UINT8 m_pbdr; // Port B Data register UINT8 m_pbdr; // Port B Data register
UINT8 m_psr; // Port Status Register UINT8 m_psr; // Port Status Register
UINT8 m_tcr; // Timer Control Register UINT8 m_tcr; // Timer Control Register
int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits) int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
// UINT8 m_cprh; // Counter Preload Register High // UINT8 m_cprh; // Counter Preload Register High
// UINT8 m_cprm; // Counter Preload Register Mid // UINT8 m_cprm; // Counter Preload Register Mid
// UINT8 m_cprl; // Counter Preload Register Low // UINT8 m_cprl; // Counter Preload Register Low
int m_cntr; // - The 24 bit Counter int m_cntr; // - The 24 bit Counter
}; };
// device type definition // device type definition

16
src/devices/machine/8530scc.cpp
View File

@ -480,8 +480,8 @@ UINT8 scc8530_t::read_reg(int offset)
switch(offset) switch(offset)
{ {
case 0: /* Channel B (Printer Port) Control */ case 0: /* Channel B (Printer Port) Control */
case 1: /* Channel A (Modem Port) Control */ case 1: /* Channel A (Modem Port) Control */
if (mode == 1) if (mode == 1)
mode = 0; mode = 0;
@ -491,7 +491,7 @@ UINT8 scc8530_t::read_reg(int offset)
result = (offset == 0) ? getbreg() : getareg(); result = (offset == 0) ? getbreg() : getareg();
break; break;
case 2: /* Channel B (Printer Port) Data */ case 2: /* Channel B (Printer Port) Data */
case 3:/* Channel A (Modem Port) Data */ case 3:/* Channel A (Modem Port) Data */
result = channel[offset == 2 ? 1 : 0].rxData; result = channel[offset == 2 ? 1 : 0].rxData;
break; break;
@ -527,8 +527,8 @@ void scc8530_t::write_reg(int offset, UINT8 data)
//Chan *pChan; //Chan *pChan;
switch(offset) switch(offset)
{ {
case 0: /* Channel B (Printer Port) Control */ case 0: /* Channel B (Printer Port) Control */
case 1: /* Channel A (Modem Port) Control */ case 1: /* Channel A (Modem Port) Control */
{ {
int chan = ((offset == 2) ? 1 : 0); int chan = ((offset == 2) ? 1 : 0);
if (mode == 0) if (mode == 0)
@ -537,7 +537,7 @@ void scc8530_t::write_reg(int offset, UINT8 data)
{ {
mode = 1; mode = 1;
reg = data & 0x0f; reg = data & 0x0f;
// putbreg(data & 0xf0); // putbreg(data & 0xf0);
} }
else if (data == 0x10) else if (data == 0x10)
{ {
@ -555,8 +555,8 @@ void scc8530_t::write_reg(int offset, UINT8 data)
break; break;
} }
case 2: /* Channel B (Printer Port) Data */ case 2: /* Channel B (Printer Port) Data */
case 3: /* Channel A (Modem Port) Data */ case 3: /* Channel A (Modem Port) Data */
{ {
int chan = ((offset == 2) ? 1 : 0); int chan = ((offset == 2) ? 1 : 0);
if (channel[chan].txEnable) if (channel[chan].txEnable)

2
src/devices/machine/eeprom.h
View File

@ -44,7 +44,7 @@
// ======================> eeprom_base_device // ======================> eeprom_base_device
class eeprom_base_device : public device_t, class eeprom_base_device : public device_t,
public device_nvram_interface public device_nvram_interface
{ {
protected: protected:
// construction/destruction // construction/destruction

16
src/devices/machine/ldp1000.cpp
View File

@ -2,12 +2,12 @@
// copyright-holders:Angelo Salese // copyright-holders:Angelo Salese
/*************************************************************************** /***************************************************************************
Sony LDP-1000 laserdisc emulation. Sony LDP-1000 laserdisc emulation.
TODO: TODO:
- Dump BIOSes (seven of them according to docs); - Dump BIOSes (seven of them according to docs);
- Serial interface, needs BIOS dump; - Serial interface, needs BIOS dump;
- Hookup with Sony SMC-70 / SMC-777; - Hookup with Sony SMC-70 / SMC-777;
***************************************************************************/ ***************************************************************************/
@ -194,9 +194,9 @@ WRITE8_MEMBER( sony_ldp1000_device::command_w )
break; break;
/* /*
audio channels absolute enable / disable audio channels absolute enable / disable
---- --x- select channel ---- --x- select channel
---- ---x enable channel (active low) ---- ---x enable channel (active low)
*/ */
case 0x46: case 0x46:
case 0x47: case 0x47:

18
src/devices/machine/ldp1000.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Angelo Salese // copyright-holders:Angelo Salese
/*************************************************************************** /***************************************************************************
Sony LDP-1000 laserdisc emulation. Sony LDP-1000 laserdisc emulation.
***************************************************************************/ ***************************************************************************/
@ -52,14 +52,14 @@ protected:
virtual void player_overlay(bitmap_yuy16 &bitmap) override { } virtual void player_overlay(bitmap_yuy16 &bitmap) override { }
enum ldp1000_status { enum ldp1000_status {
stat_undef = 0x00, stat_undef = 0x00,
stat_completion = 0x01, stat_completion = 0x01,
stat_error = 0x02, stat_error = 0x02,
stat_pgm_end = 0x04, stat_pgm_end = 0x04,
stat_not_target = 0x05, stat_not_target = 0x05,
stat_no_frame = 0x06, stat_no_frame = 0x06,
stat_ack = 0x0a, stat_ack = 0x0a,
stat_nak = 0x0b stat_nak = 0x0b
}; };
enum ldp1000_player_state { enum ldp1000_player_state {

1
src/devices/machine/pci-ide.cpp
View File

@ -132,7 +132,6 @@ WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
// PCI646U2 Offset 0x50 is interrupt status // PCI646U2 Offset 0x50 is interrupt status
if (main_id == 0x10950646) { if (main_id == 0x10950646) {
if (state) if (state)
m_config_data[0x10 / 4] |= 0x4; m_config_data[0x10 / 4] |= 0x4;
else else

889
src/devices/machine/scnxx562.cpp
View File

File diff suppressed because it is too large Load Diff

342
src/devices/machine/scnxx562.h
View File

@ -186,10 +186,10 @@ public:
void do_dusccreg_ictsr_w(UINT8 data); void do_dusccreg_ictsr_w(UINT8 data);
void do_dusccreg_gsr_w(UINT8 data); void do_dusccreg_gsr_w(UINT8 data);
void do_dusccreg_ier_w(UINT8 data); void do_dusccreg_ier_w(UINT8 data);
// void do_dusccreg_rea_w(UINT8 data); // Short cutted non complex feature // void do_dusccreg_rea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_ivr_w(UINT8 data); void do_dusccreg_ivr_w(UINT8 data);
void do_dusccreg_icr_w(UINT8 data); void do_dusccreg_icr_w(UINT8 data);
// void do_dusccreg_sea_w(UINT8 data); // Short cutted non complex feature // void do_dusccreg_sea_w(UINT8 data); // Short cutted non complex feature
void do_dusccreg_mrr_w(UINT8 data); void do_dusccreg_mrr_w(UINT8 data);
void do_dusccreg_ier1_w(UINT8 data); void do_dusccreg_ier1_w(UINT8 data);
void do_dusccreg_ier2_w(UINT8 data); void do_dusccreg_ier2_w(UINT8 data);
@ -201,8 +201,8 @@ public:
UINT8 read(offs_t &offset); UINT8 read(offs_t &offset);
void write(UINT8 data, offs_t &offset); void write(UINT8 data, offs_t &offset);
// UINT8 data_read(); // UINT8 data_read();
// void data_write(UINT8 data); // void data_write(UINT8 data);
void receive_data(UINT8 data); void receive_data(UINT8 data);
void m_tx_fifo_rp_step(); void m_tx_fifo_rp_step();
@ -246,11 +246,11 @@ public:
UINT8 m_ictsr; UINT8 m_ictsr;
UINT8 m_gsr; UINT8 m_gsr;
UINT8 m_ier; UINT8 m_ier;
// UINT8 m_rea; // UINT8 m_rea;
UINT8 m_cid; UINT8 m_cid;
UINT8 m_ivr; UINT8 m_ivr;
UINT8 m_icr; UINT8 m_icr;
// UINT8 m_sea; // UINT8 m_sea;
UINT8 m_ivrm; UINT8 m_ivrm;
UINT8 m_mrr; UINT8 m_mrr;
UINT8 m_ier1; UINT8 m_ier1;
@ -273,24 +273,24 @@ protected:
enum enum
{ {
REG_CCR_RESET_TX = 0x00, REG_CCR_RESET_TX = 0x00,
REG_CCR_ENABLE_TX = 0x02, REG_CCR_ENABLE_TX = 0x02,
REG_CCR_DISABLE_TX = 0x03, REG_CCR_DISABLE_TX = 0x03,
REG_CCR_RESET_RX = 0x40, REG_CCR_RESET_RX = 0x40,
REG_CCR_ENABLE_RX = 0x42, REG_CCR_ENABLE_RX = 0x42,
REG_CCR_DISABLE_RX = 0x43 REG_CCR_DISABLE_RX = 0x43
}; };
enum enum
{ {
REG_CMR1_PARITY = 0x20, REG_CMR1_PARITY = 0x20,
REG_CMR1_PMMODE_MASK = 0x18, REG_CMR1_PMMODE_MASK = 0x18,
REG_CMR1_PMMODE_NONE = 0x00, REG_CMR1_PMMODE_NONE = 0x00,
REG_CMR1_PMMODE_RES = 0x01, REG_CMR1_PMMODE_RES = 0x01,
REG_CMR1_PMMODE_PARITY = 0x10, REG_CMR1_PMMODE_PARITY = 0x10,
REG_CMR1_PMMODE_FORCED = 0x11, REG_CMR1_PMMODE_FORCED = 0x11,
REG_CMR1_CPMODE_MASK = 0x07, REG_CMR1_CPMODE_MASK = 0x07,
REG_CMR1_CPMODE_ASYNC = 0x07 REG_CMR1_CPMODE_ASYNC = 0x07
}; };
enum enum
@ -301,129 +301,129 @@ protected:
enum enum
{ {
REG_RPR_DATA_BITS_MASK = 0x03, REG_RPR_DATA_BITS_MASK = 0x03,
REG_RPR_DATA_BITS_5BIT = 0x00, REG_RPR_DATA_BITS_5BIT = 0x00,
REG_RPR_DATA_BITS_6BIT = 0x01, REG_RPR_DATA_BITS_6BIT = 0x01,
REG_RPR_DATA_BITS_7BIT = 0x02, REG_RPR_DATA_BITS_7BIT = 0x02,
REG_RPR_DATA_BITS_8BIT = 0x03, REG_RPR_DATA_BITS_8BIT = 0x03,
REG_RPR_DCD = 0x04, REG_RPR_DCD = 0x04,
REG_RPR_STRIP_PARITY = 0x08, REG_RPR_STRIP_PARITY = 0x08,
REG_RPR_RTS = 0x10 REG_RPR_RTS = 0x10
}; };
enum enum
{ {
REG_TPR_DATA_BITS_MASK = 0x03, REG_TPR_DATA_BITS_MASK = 0x03,
REG_TPR_DATA_BITS_5BIT = 0x00, REG_TPR_DATA_BITS_5BIT = 0x00,
REG_TPR_DATA_BITS_6BIT = 0x01, REG_TPR_DATA_BITS_6BIT = 0x01,
REG_TPR_DATA_BITS_7BIT = 0x02, REG_TPR_DATA_BITS_7BIT = 0x02,
REG_TPR_DATA_BITS_8BIT = 0x03, REG_TPR_DATA_BITS_8BIT = 0x03,
REG_TPR_CTS = 0x04, REG_TPR_CTS = 0x04,
REG_TPR_RTS = 0x08, REG_TPR_RTS = 0x08,
REG_TPR_STOP_BITS_MASK = 0xf0 REG_TPR_STOP_BITS_MASK = 0xf0
}; };
enum enum
{ {
REG_TTR_EXT = 0x80, REG_TTR_EXT = 0x80,
REG_TTR_TXCLK_MASK = 0x70, REG_TTR_TXCLK_MASK = 0x70,
REG_TTR_TXCLK_1XEXT = 0x00, REG_TTR_TXCLK_1XEXT = 0x00,
REG_TTR_TXCLK_16XEXT = 0x10, REG_TTR_TXCLK_16XEXT = 0x10,
REG_TTR_TXCLK_DPLL = 0x20, REG_TTR_TXCLK_DPLL = 0x20,
REG_TTR_TXCLK_BRG = 0x30, REG_TTR_TXCLK_BRG = 0x30,
REG_TTR_TXCLK_2X_OTHER = 0x40, REG_TTR_TXCLK_2X_OTHER = 0x40,
REG_TTR_TXCLK_32X_OTHER = 0x50, REG_TTR_TXCLK_32X_OTHER = 0x50,
REG_TTR_TXCLK_2X_OWN = 0x60, REG_TTR_TXCLK_2X_OWN = 0x60,
REG_TTR_TXCLK_32X_OWN = 0x70, REG_TTR_TXCLK_32X_OWN = 0x70,
REG_TTR_BRG_RATE_MASK = 0x0f, REG_TTR_BRG_RATE_MASK = 0x0f,
}; };
enum enum
{ {
REG_RTR_EXT = 0x80, REG_RTR_EXT = 0x80,
REG_RTR_RXCLK_MASK = 0x70, REG_RTR_RXCLK_MASK = 0x70,
REG_RTR_RXCLK_1XEXT = 0x00, REG_RTR_RXCLK_1XEXT = 0x00,
REG_RTR_RXCLK_16XEXT = 0x10, REG_RTR_RXCLK_16XEXT = 0x10,
REG_RTR_RXCLK_BRG = 0x20, REG_RTR_RXCLK_BRG = 0x20,
REG_RTR_RXCLK_CT = 0x30, REG_RTR_RXCLK_CT = 0x30,
REG_RTR_RXCLK_DPLL_64X_X1 = 0x40, REG_RTR_RXCLK_DPLL_64X_X1 = 0x40,
REG_RTR_RXCLK_DPLL_32X_EXT = 0x50, REG_RTR_RXCLK_DPLL_32X_EXT = 0x50,
REG_RTR_RXCLK_DPLL_32X_BRG = 0x60, REG_RTR_RXCLK_DPLL_32X_BRG = 0x60,
REG_RTR_RXCLK_DPLL_32X_CT = 0x70, REG_RTR_RXCLK_DPLL_32X_CT = 0x70,
REG_RTR_BRG_RATE_MASK = 0x0f, REG_RTR_BRG_RATE_MASK = 0x0f,
}; };
enum enum
{ {
REG_PCR_X2_IDC = 0x80, REG_PCR_X2_IDC = 0x80,
REG_PCR_GP02_RTS = 0x40, REG_PCR_GP02_RTS = 0x40,
REG_PCR_SYNOUT_RTS = 0x20, REG_PCR_SYNOUT_RTS = 0x20,
REG_PCR_RTXC_MASK = 0x18, REG_PCR_RTXC_MASK = 0x18,
REG_PCR_RTXC_INPUT = 0x00, REG_PCR_RTXC_INPUT = 0x00,
REG_PCR_RTXC_CNTR_OUT = 0x08, REG_PCR_RTXC_CNTR_OUT = 0x08,
REG_PCR_RTXC_TXCLK_OUT = 0x10, REG_PCR_RTXC_TXCLK_OUT = 0x10,
REG_PCR_RTXC_RXCLK_OUT = 0x18, REG_PCR_RTXC_RXCLK_OUT = 0x18,
REG_PCR_TRXC_MASK = 0x07, REG_PCR_TRXC_MASK = 0x07,
REG_PCR_TRXC_INPUT = 0x00, REG_PCR_TRXC_INPUT = 0x00,
REG_PCR_TRXC_CRYST_OUT = 0x01, REG_PCR_TRXC_CRYST_OUT = 0x01,
REG_PCR_TRXC_DPLL_OUT = 0x02, REG_PCR_TRXC_DPLL_OUT = 0x02,
REG_PCR_TRXC_CNTR_OUT = 0x03, REG_PCR_TRXC_CNTR_OUT = 0x03,
REG_PCR_TRXC_TXBRG_OUT = 0x04, REG_PCR_TRXC_TXBRG_OUT = 0x04,
REG_PCR_TRXC_RXBRG_OUT = 0x05, REG_PCR_TRXC_RXBRG_OUT = 0x05,
REG_PCR_TRXC_TXCLK_OUT = 0x06, REG_PCR_TRXC_TXCLK_OUT = 0x06,
REG_PCR_TRXC_RXCLK_OUT = 0x07, REG_PCR_TRXC_RXCLK_OUT = 0x07,
}; };
enum enum
{ {
REG_OMR_TXRCL_MASK = 0xe0, REG_OMR_TXRCL_MASK = 0xe0,
REG_OMR_TXRCL_8BIT = 0xe0, REG_OMR_TXRCL_8BIT = 0xe0,
REG_OMR_TXRDY_ACTIVATED = 0x10, REG_OMR_TXRDY_ACTIVATED = 0x10,
REG_OMR_RXRDY_ACTIVATED = 0x08, REG_OMR_RXRDY_ACTIVATED = 0x08,
REG_OMR_GP02 = 0x04, REG_OMR_GP02 = 0x04,
REG_OMR_GP01 = 0x02, REG_OMR_GP01 = 0x02,
REG_OMR_RTS = 0x01, REG_OMR_RTS = 0x01,
}; };
enum enum
{ {
REG_RSR_OVERRUN_ERROR = 0x20, REG_RSR_OVERRUN_ERROR = 0x20,
}; };
enum enum
{ {
REG_ICTSR_DELTA_CTS = 0x10, REG_ICTSR_DELTA_CTS = 0x10,
REG_ICTSR_DCD = 0x08, REG_ICTSR_DCD = 0x08,
REG_ICTSR_CTS = 0x04, REG_ICTSR_CTS = 0x04,
}; };
enum enum
{ {
REG_GSR_CHAN_A_RXREADY = 0x01, REG_GSR_CHAN_A_RXREADY = 0x01,
REG_GSR_CHAN_B_RXREADY = 0x10, REG_GSR_CHAN_B_RXREADY = 0x10,
REG_GSR_CHAN_A_TXREADY = 0x02, REG_GSR_CHAN_A_TXREADY = 0x02,
REG_GSR_CHAN_B_TXREADY = 0x20, REG_GSR_CHAN_B_TXREADY = 0x20,
}; };
// Register offsets, stripped from channel bit 0x20 but including A7 bit // Register offsets, stripped from channel bit 0x20 but including A7 bit
enum enum
{ {
REG_CMR1 = 0x00, REG_CMR1 = 0x00,
REG_CMR2 = 0x01, REG_CMR2 = 0x01,
REG_S1R = 0x02, REG_S1R = 0x02,
REG_S2R = 0x03, REG_S2R = 0x03,
REG_TPR = 0x04, REG_TPR = 0x04,
REG_TTR = 0x05, REG_TTR = 0x05,
REG_RPR = 0x06, REG_RPR = 0x06,
REG_RTR = 0x07, REG_RTR = 0x07,
REG_CTPRH = 0x08, REG_CTPRH = 0x08,
REG_CTPRL = 0x09, REG_CTPRL = 0x09,
REG_CTCR = 0x0a, REG_CTCR = 0x0a,
REG_OMR = 0x0b, REG_OMR = 0x0b,
REG_CTH = 0x0c, REG_CTH = 0x0c,
REG_CTL = 0x0d, REG_CTL = 0x0d,
REG_PCR = 0x0e, REG_PCR = 0x0e,
REG_CCR = 0x0f, REG_CCR = 0x0f,
REG_TXFIFO_0= 0x10, REG_TXFIFO_0= 0x10,
REG_TXFIFO_1= 0x11, REG_TXFIFO_1= 0x11,
REG_TXFIFO_2= 0x12, REG_TXFIFO_2= 0x12,
@ -432,26 +432,26 @@ protected:
REG_RXFIFO_1= 0x15, REG_RXFIFO_1= 0x15,
REG_RXFIFO_2= 0x16, REG_RXFIFO_2= 0x16,
REG_RXFIFO_3= 0x17, REG_RXFIFO_3= 0x17,
REG_RSR = 0x18, REG_RSR = 0x18,
REG_TRSR = 0x19, REG_TRSR = 0x19,
REG_ICTSR = 0x1a, REG_ICTSR = 0x1a,
REG_GSR = 0x1b, REG_GSR = 0x1b,
REG_IER = 0x1c, REG_IER = 0x1c,
REG_REA = 0x1d, REG_REA = 0x1d,
REG_CID = 0x1d, REG_CID = 0x1d,
REG_IVR = 0x1e, REG_IVR = 0x1e,
REG_ICR = 0x1f, REG_ICR = 0x1f,
REG_SEA = 0x1d, REG_SEA = 0x1d,
REG_IVRM = 0x1e, REG_IVRM = 0x1e,
REG_MRR = 0x1f, REG_MRR = 0x1f,
REG_IER1 = 0x42, REG_IER1 = 0x42,
REG_IER2 = 0x43, REG_IER2 = 0x43,
REG_IER3 = 0x45, REG_IER3 = 0x45,
REG_TRCR = 0x47, REG_TRCR = 0x47,
REG_RFLR = 0x4e, REG_RFLR = 0x4e,
REG_FTLR = 0x5c, REG_FTLR = 0x5c,
REG_TRMSR = 0x5e, REG_TRMSR = 0x5e,
REG_TELR = 0x5f, REG_TELR = 0x5f,
}; };
enum enum
@ -471,22 +471,22 @@ protected:
{ {
switch (br) switch (br)
{ {
case 0x00: return 50; break; case 0x00: return 50; break;
case 0x01: return 75; break; case 0x01: return 75; break;
case 0x02: return 110; break; case 0x02: return 110; break;
case 0x03: return 134; break; case 0x03: return 134; break;
case 0x04: return 150; break; case 0x04: return 150; break;
case 0x05: return 200; break; case 0x05: return 200; break;
case 0x06: return 300; break; case 0x06: return 300; break;
case 0x07: return 600; break; case 0x07: return 600; break;
case 0x08: return 1050; break; case 0x08: return 1050; break;
case 0x09: return 1200; break; case 0x09: return 1200; break;
case 0x0a: return 2000; break; case 0x0a: return 2000; break;
case 0x0b: return 2400; break; case 0x0b: return 2400; break;
case 0x0c: return 4800; break; case 0x0c: return 4800; break;
case 0x0d: return 9600; break; case 0x0d: return 9600; break;
case 0x0e: return 19200; break; case 0x0e: return 19200; break;
case 0x0f: return 38400; break; case 0x0f: return 38400; break;
}; };
return 0; return 0;
} }
@ -503,47 +503,47 @@ protected:
/* FIFOs and rx/tx status */ /* FIFOs and rx/tx status */
/* Receiver */ /* Receiver */
UINT8 m_rx_data_fifo[16]; // data FIFO UINT8 m_rx_data_fifo[16]; // data FIFO
UINT8 m_rx_error_fifo[16]; // error FIFO UINT8 m_rx_error_fifo[16]; // error FIFO
int m_rx_fifo_rp; // FIFO read pointer int m_rx_fifo_rp; // FIFO read pointer
int m_rx_fifo_wp; // FIFO write pointer int m_rx_fifo_wp; // FIFO write pointer
int m_rx_fifo_sz; // FIFO size int m_rx_fifo_sz; // FIFO size
UINT8 m_rx_error; // current error UINT8 m_rx_error; // current error
/* Transmitter */ /* Transmitter */
UINT8 m_tx_data_fifo[16]; // data FIFO UINT8 m_tx_data_fifo[16]; // data FIFO
UINT8 m_tx_error_fifo[16]; // error FIFO UINT8 m_tx_error_fifo[16]; // error FIFO
int m_tx_fifo_rp; // FIFO read pointer int m_tx_fifo_rp; // FIFO read pointer
int m_tx_fifo_wp; // FIFO write pointer int m_tx_fifo_wp; // FIFO write pointer
int m_tx_fifo_sz; // FIFO size int m_tx_fifo_sz; // FIFO size
UINT8 m_tx_error; // current error UINT8 m_tx_error; // current error
int m_rx_clock; // receive clock pulse count int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received int m_rx_first; // first character received
int m_rx_break; // receive break condition int m_rx_break; // receive break condition
// UINT8 m_rx_rr0_latch; // read register 0 latched // UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd; int m_rxd;
int m_ri; // ring indicator latch int m_ri; // ring indicator latch
int m_cts; // clear to send latch int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch int m_dcd; // data carrier detect latch
// transmitter state // transmitter state
UINT8 m_tx_data; // transmit data register UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count int m_tx_clock; // transmit clock pulse count
int m_dtr; // data terminal ready int m_dtr; // data terminal ready
int m_rts; // request to send int m_rts; // request to send
// synchronous state // synchronous state
UINT16 m_sync; // sync character UINT16 m_sync; // sync character
int m_rcv_mode; int m_rcv_mode;
int m_index; int m_index;
duscc_device *m_uart; duscc_device *m_uart;
// CDUSCC specifics // CDUSCC specifics
int m_a7; // Access additional registers int m_a7; // Access additional registers
}; };
@ -551,7 +551,7 @@ protected:
class duscc_device : public device_t class duscc_device : public device_t
// ,public device_z80daisy_interface // ,public device_z80daisy_interface
{ {
friend class duscc_channel; friend class duscc_channel;
@ -585,7 +585,7 @@ public:
DECLARE_WRITE8_MEMBER( write ); DECLARE_WRITE8_MEMBER( write );
// interrupt acknowledge // interrupt acknowledge
// int m1_r(); // int m1_r();
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); } DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); }
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); } DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); }
@ -596,7 +596,7 @@ public:
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); } DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); } DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); }
#if 0 #if 0
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); } DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); } DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); } DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); } DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); }

22
src/devices/machine/z80scc.h
View File

@ -536,18 +536,18 @@ protected:
int get_tx_word_length(); int get_tx_word_length();
// receiver state // receiver state
UINT8 m_rx_data_fifo[8]; // receive data FIFO UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer //int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size int m_rx_fifo_sz; // receive FIFO size
int m_rx_clock; // receive clock pulse count int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received int m_rx_first; // first character received
int m_rx_break; // receive break condition int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd; int m_rxd;
int m_ri; // ring indicator latch int m_ri; // ring indicator latch

45
src/devices/video/zeus2.cpp
View File

@ -38,7 +38,7 @@ TIMER_CALLBACK_MEMBER(zeus2_device::display_irq_off)
///* if zero, adjust to next frame, otherwise we may get stuck in an infinite loop */ ///* if zero, adjust to next frame, otherwise we may get stuck in an infinite loop */
//if (vblank_period == attotime::zero) //if (vblank_period == attotime::zero)
// vblank_period = m_screen->frame_period(); // vblank_period = m_screen->frame_period();
//vblank_timer->adjust(vblank_period); //vblank_timer->adjust(vblank_period);
vblank_timer->adjust(m_screen->time_until_vblank_start()); vblank_timer->adjust(m_screen->time_until_vblank_start());
//machine().scheduler().timer_set(attotime::from_hz(30000000), timer_expired_delegate(FUNC(zeus2_device::display_irq), this)); //machine().scheduler().timer_set(attotime::from_hz(30000000), timer_expired_delegate(FUNC(zeus2_device::display_irq), this));
@ -66,7 +66,6 @@ TIMER_CALLBACK_MEMBER(zeus2_device::int_timer_callback)
void zeus2_device::device_start() void zeus2_device::device_start()
{ {
/* allocate memory for "wave" RAM */ /* allocate memory for "wave" RAM */
waveram[0] = auto_alloc_array(machine(), UINT32, WAVERAM0_WIDTH * WAVERAM0_HEIGHT * 8/4); waveram[0] = auto_alloc_array(machine(), UINT32, WAVERAM0_WIDTH * WAVERAM0_HEIGHT * 8/4);
//waveram[1] = auto_alloc_array(machine(), UINT32, WAVERAM1_WIDTH * WAVERAM1_HEIGHT * 12/4); //waveram[1] = auto_alloc_array(machine(), UINT32, WAVERAM1_WIDTH * WAVERAM1_HEIGHT * 12/4);
@ -585,16 +584,16 @@ void zeus2_device::zeus2_register_update(offs_t offset, UINT32 oldval, int logit
/* thegrid uses this to write either left or right halves of pixels */ /* thegrid uses this to write either left or right halves of pixels */
//if (m_zeusbase[0x50] == 0x00e90000) //if (m_zeusbase[0x50] == 0x00e90000)
//{ //{
// UINT32 addr = frame_addr_from_reg51(); // UINT32 addr = frame_addr_from_reg51();
// if (m_zeusbase[0x57] & 1) // if (m_zeusbase[0x57] & 1)
// m_frameColor[addr] = m_zeusbase[0x58]; // m_frameColor[addr] = m_zeusbase[0x58];
// if (m_zeusbase[0x57] & 4) // if (m_zeusbase[0x57] & 4)
// m_frameColor[addr+1] = m_zeusbase[0x59]; // m_frameColor[addr+1] = m_zeusbase[0x59];
//} //}
///* make sure we log anything else */ ///* make sure we log anything else */
//else if (logit) //else if (logit)
// logerror("\t[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]); // logerror("\t[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
break; break;
case 0x58: case 0x58:
@ -1246,39 +1245,39 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texdata, i
//case 0x95d: /* crusnexo */ //case 0x95d: /* crusnexo */
//case 0xc1d: /* crusnexo */ //case 0xc1d: /* crusnexo */
//case 0xc5d: /* crusnexo */ //case 0xc5d: /* crusnexo */
// extra.texwidth = 256; // extra.texwidth = 256;
// break; // break;
//case 0x18a: // atlantis //case 0x18a: // atlantis
//case 0x059: /* crusnexo */ //case 0x059: /* crusnexo */
//case 0x0d9: /* crusnexo */ //case 0x0d9: /* crusnexo */
//case 0x119: /* crusnexo: license plates */ //case 0x119: /* crusnexo: license plates */
//case 0x159: /* crusnexo */ //case 0x159: /* crusnexo */
// extra.texwidth = 128; // extra.texwidth = 128;
// break; // break;
//case 0x055: /* crusnexo */ //case 0x055: /* crusnexo */
//case 0x145: // atlantis //case 0x145: // atlantis
//case 0x155: /* crusnexo */ //case 0x155: /* crusnexo */
// extra.texwidth = 64; // extra.texwidth = 64;
// break; // break;
//case 0x000: // thegrid guess //case 0x000: // thegrid guess
//case 0x120: // thegrid guess //case 0x120: // thegrid guess
//case 0x140: // atlantis //case 0x140: // atlantis
//case 0x141: // atlantis //case 0x141: // atlantis
// extra.texwidth = 32; // extra.texwidth = 32;
// break; // break;
//default: //default:
//{ //{
// static UINT8 hits[0x10000]; // static UINT8 hits[0x10000];
// if (!hits[(texdata & 0xffff)]) // if (!hits[(texdata & 0xffff)])
// { // {
// hits[(texdata & 0xffff)] = 1; // hits[(texdata & 0xffff)] = 1;
// printf("texMode = %04X\n", (texdata & 0xffff)); // printf("texMode = %04X\n", (texdata & 0xffff));
// } // }
// break; // break;
//} //}
//} //}

30
src/emu/debug/debugcmd.cpp
View File

@ -94,8 +94,8 @@ UINT64 debugger_commands::cheat_read_extended(const cheat_system *cheatsys, addr
debugger_commands::debugger_commands(running_machine& machine, debugger_cpu& cpu, debugger_console& console) debugger_commands::debugger_commands(running_machine& machine, debugger_cpu& cpu, debugger_console& console)
: m_machine(machine) : m_machine(machine)
, m_cpu(cpu) , m_cpu(cpu)
, m_console(console) , m_console(console)
{ {
m_global_array = auto_alloc_array_clear(m_machine, global_entry, MAX_GLOBALS); m_global_array = auto_alloc_array_clear(m_machine, global_entry, MAX_GLOBALS);
@ -271,7 +271,7 @@ debugger_commands::debugger_commands(running_machine& machine, debugger_cpu& cpu
/* set up the initial debugscript if specified */ /* set up the initial debugscript if specified */
const char* name = m_machine.options().debug_script(); const char* name = m_machine.options().debug_script();
if (name[0] != 0) if (name[0] != 0)
m_cpu.source_script(name); m_cpu.source_script(name);
m_cheat.cpu[0] = m_cheat.cpu[1] = 0; m_cheat.cpu[0] = m_cheat.cpu[1] = 0;
} }
@ -683,7 +683,7 @@ void debugger_commands::execute_tracelog(int ref, int params, const char *param[
/* then do a printf */ /* then do a printf */
char buffer[1024]; char buffer[1024];
if (mini_printf(buffer, param[0], params - 1, &values[1])) if (mini_printf(buffer, param[0], params - 1, &values[1]))
m_cpu.get_visible_cpu()->debug()->trace_printf("%s", buffer); m_cpu.get_visible_cpu()->debug()->trace_printf("%s", buffer);
} }
@ -720,7 +720,7 @@ void debugger_commands::execute_step(int ref, int params, const char *param[])
if (!validate_number_parameter(param[0], &steps)) if (!validate_number_parameter(param[0], &steps))
return; return;
m_cpu.get_visible_cpu()->debug()->single_step(steps); m_cpu.get_visible_cpu()->debug()->single_step(steps);
} }
@ -735,7 +735,7 @@ void debugger_commands::execute_over(int ref, int params, const char *param[])
if (!validate_number_parameter(param[0], &steps)) if (!validate_number_parameter(param[0], &steps))
return; return;
m_cpu.get_visible_cpu()->debug()->single_step_over(steps); m_cpu.get_visible_cpu()->debug()->single_step_over(steps);
} }
@ -745,7 +745,7 @@ void debugger_commands::execute_over(int ref, int params, const char *param[])
void debugger_commands::execute_out(int ref, int params, const char *param[]) void debugger_commands::execute_out(int ref, int params, const char *param[])
{ {
m_cpu.get_visible_cpu()->debug()->single_step_out(); m_cpu.get_visible_cpu()->debug()->single_step_out();
} }
@ -761,7 +761,7 @@ void debugger_commands::execute_go(int ref, int params, const char *param[])
if (!validate_number_parameter(param[0], &addr)) if (!validate_number_parameter(param[0], &addr))
return; return;
m_cpu.get_visible_cpu()->debug()->go(addr); m_cpu.get_visible_cpu()->debug()->go(addr);
} }
@ -772,7 +772,7 @@ void debugger_commands::execute_go(int ref, int params, const char *param[])
void debugger_commands::execute_go_vblank(int ref, int params, const char *param[]) void debugger_commands::execute_go_vblank(int ref, int params, const char *param[])
{ {
m_cpu.get_visible_cpu()->debug()->go_vblank(); m_cpu.get_visible_cpu()->debug()->go_vblank();
} }
@ -788,7 +788,7 @@ void debugger_commands::execute_go_interrupt(int ref, int params, const char *pa
if (!validate_number_parameter(param[0], &irqline)) if (!validate_number_parameter(param[0], &irqline))
return; return;
m_cpu.get_visible_cpu()->debug()->go_interrupt(irqline); m_cpu.get_visible_cpu()->debug()->go_interrupt(irqline);
} }
@ -804,7 +804,7 @@ void debugger_commands::execute_go_time(int ref, int params, const char *param[]
if (!validate_number_parameter(param[0], &milliseconds)) if (!validate_number_parameter(param[0], &milliseconds))
return; return;
m_cpu.get_visible_cpu()->debug()->go_milliseconds(milliseconds); m_cpu.get_visible_cpu()->debug()->go_milliseconds(milliseconds);
} }
@ -814,7 +814,7 @@ void debugger_commands::execute_go_time(int ref, int params, const char *param[]
void debugger_commands::execute_next(int ref, int params, const char *param[]) void debugger_commands::execute_next(int ref, int params, const char *param[])
{ {
m_cpu.get_visible_cpu()->debug()->go_next_device(); m_cpu.get_visible_cpu()->debug()->go_next_device();
} }
@ -1651,7 +1651,7 @@ void debugger_commands::execute_load(int ref, int params, const char *param[])
/* check if end of file has been reached and stop loading if it has */ /* check if end of file has been reached and stop loading if it has */
if (feof(f)) if (feof(f))
break; break;
m_cpu.write_byte(*space, i, byte, true); m_cpu.write_byte(*space, i, byte, true);
} }
/* close the file */ /* close the file */
fclose(f); fclose(f);
@ -2513,7 +2513,7 @@ void debugger_commands::execute_traceover(int ref, int params, const char *param
void debugger_commands::execute_traceflush(int ref, int params, const char *param[]) void debugger_commands::execute_traceflush(int ref, int params, const char *param[])
{ {
m_cpu.flush_traces(); m_cpu.flush_traces();
} }
@ -2733,7 +2733,7 @@ void debugger_commands::execute_snap(int ref, int params, const char *param[])
void debugger_commands::execute_source(int ref, int params, const char *param[]) void debugger_commands::execute_source(int ref, int params, const char *param[])
{ {
m_cpu.source_script(param[0]); m_cpu.source_script(param[0]);
} }

6
src/emu/debug/debugcmd.h
View File

@ -157,9 +157,9 @@ private:
void execute_input(int ref, int params, const char **param); void execute_input(int ref, int params, const char **param);
void execute_dumpkbd(int ref, int params, const char **param); void execute_dumpkbd(int ref, int params, const char **param);
running_machine& m_machine; running_machine& m_machine;
debugger_cpu& m_cpu; debugger_cpu& m_cpu;
debugger_console& m_console; debugger_console& m_console;
global_entry *m_global_array; global_entry *m_global_array;
cheat_system m_cheat; cheat_system m_cheat;

8
src/emu/debug/debugcon.h
View File

@ -124,12 +124,12 @@ private:
int maxparams; int maxparams;
}; };
running_machine &m_machine; running_machine &m_machine;
text_buffer *m_console_textbuf; text_buffer *m_console_textbuf;
text_buffer *m_errorlog_textbuf; text_buffer *m_errorlog_textbuf;
debug_command *m_commandlist; debug_command *m_commandlist;
}; };
#endif #endif

58
src/emu/debug/debugcpu.cpp
View File

@ -36,19 +36,19 @@ const size_t debugger_cpu::NUM_TEMP_VARIABLES = 10;
debugger_cpu::debugger_cpu(running_machine &machine) debugger_cpu::debugger_cpu(running_machine &machine)
: m_machine(machine) : m_machine(machine)
, m_livecpu(nullptr) , m_livecpu(nullptr)
, m_visiblecpu(nullptr) , m_visiblecpu(nullptr)
, m_breakcpu(nullptr) , m_breakcpu(nullptr)
, m_source_file(nullptr) , m_source_file(nullptr)
, m_symtable(nullptr) , m_symtable(nullptr)
, m_execution_state(EXECUTION_STATE_STOPPED) , m_execution_state(EXECUTION_STATE_STOPPED)
, m_bpindex(1) , m_bpindex(1)
, m_wpindex(1) , m_wpindex(1)
, m_rpindex(1) , m_rpindex(1)
, m_wpdata(0) , m_wpdata(0)
, m_wpaddr(0) , m_wpaddr(0)
, m_last_periodic_update_time(0) , m_last_periodic_update_time(0)
, m_comments_loaded(false) , m_comments_loaded(false)
{ {
screen_device *first_screen = m_machine.first_screen(); screen_device *first_screen = m_machine.first_screen();
@ -392,11 +392,11 @@ UINT8 debugger_cpu::read_byte(address_space &space, offs_t address, int apply_tr
result = 0xff; result = 0xff;
} }
else if (space.device().memory().read(space.spacenum(), address, 1, custom)) else if (space.device().memory().read(space.spacenum(), address, 1, custom))
{ /* if there is a custom read handler, and it returns true, use that value */ { /* if there is a custom read handler, and it returns true, use that value */
result = custom; result = custom;
} }
else else
{ /* otherwise, call the byte reading function for the translated address */ { /* otherwise, call the byte reading function for the translated address */
result = space.read_byte(address); result = space.read_byte(address);
} }
@ -419,7 +419,7 @@ UINT16 debugger_cpu::read_word(address_space &space, offs_t address, int apply_t
UINT16 result; UINT16 result;
if (!WORD_ALIGNED(address)) if (!WORD_ALIGNED(address))
{ /* if this is misaligned read, or if there are no word readers, just read two bytes */ { /* if this is misaligned read, or if there are no word readers, just read two bytes */
UINT8 byte0 = read_byte(space, address + 0, apply_translation); UINT8 byte0 = read_byte(space, address + 0, apply_translation);
UINT8 byte1 = read_byte(space, address + 1, apply_translation); UINT8 byte1 = read_byte(space, address + 1, apply_translation);
@ -430,7 +430,7 @@ UINT16 debugger_cpu::read_word(address_space &space, offs_t address, int apply_t
result = byte1 | (byte0 << 8); result = byte1 | (byte0 << 8);
} }
else else
{ /* otherwise, this proceeds like the byte case */ { /* otherwise, this proceeds like the byte case */
/* all accesses from this point on are for the debugger */ /* all accesses from this point on are for the debugger */
m_debugger_access = true; m_debugger_access = true;
@ -443,11 +443,11 @@ UINT16 debugger_cpu::read_word(address_space &space, offs_t address, int apply_t
result = 0xffff; result = 0xffff;
} }
else if (space.device().memory().read(space.spacenum(), address, 2, custom)) else if (space.device().memory().read(space.spacenum(), address, 2, custom))
{ /* if there is a custom read handler, and it returns true, use that value */ { /* if there is a custom read handler, and it returns true, use that value */
result = custom; result = custom;
} }
else else
{ /* otherwise, call the byte reading function for the translated address */ { /* otherwise, call the byte reading function for the translated address */
result = space.read_word(address); result = space.read_word(address);
} }
@ -472,7 +472,7 @@ UINT32 debugger_cpu::read_dword(address_space &space, offs_t address, int apply_
UINT32 result; UINT32 result;
if (!DWORD_ALIGNED(address)) if (!DWORD_ALIGNED(address))
{ /* if this is a misaligned read, or if there are no dword readers, just read two words */ { /* if this is a misaligned read, or if there are no dword readers, just read two words */
UINT16 word0 = read_word(space, address + 0, apply_translation); UINT16 word0 = read_word(space, address + 0, apply_translation);
UINT16 word1 = read_word(space, address + 2, apply_translation); UINT16 word1 = read_word(space, address + 2, apply_translation);
@ -483,7 +483,7 @@ UINT32 debugger_cpu::read_dword(address_space &space, offs_t address, int apply_
result = word1 | (word0 << 16); result = word1 | (word0 << 16);
} }
else else
{ /* otherwise, this proceeds like the byte case */ { /* otherwise, this proceeds like the byte case */
/* all accesses from this point on are for the debugger */ /* all accesses from this point on are for the debugger */
m_debugger_access = true; m_debugger_access = true;
@ -491,15 +491,15 @@ UINT32 debugger_cpu::read_dword(address_space &space, offs_t address, int apply_
UINT64 custom; UINT64 custom;
if (apply_translation && !translate(space, TRANSLATE_READ_DEBUG, &address)) if (apply_translation && !translate(space, TRANSLATE_READ_DEBUG, &address))
{ /* translate if necessary; if not mapped, return 0xffffffff */ { /* translate if necessary; if not mapped, return 0xffffffff */
result = 0xffffffff; result = 0xffffffff;
} }
else if (space.device().memory().read(space.spacenum(), address, 4, custom)) else if (space.device().memory().read(space.spacenum(), address, 4, custom))
{ /* if there is a custom read handler, and it returns true, use that value */ { /* if there is a custom read handler, and it returns true, use that value */
result = custom; result = custom;
} }
else else
{ /* otherwise, call the byte reading function for the translated address */ { /* otherwise, call the byte reading function for the translated address */
result = space.read_dword(address); result = space.read_dword(address);
} }
@ -524,7 +524,7 @@ UINT64 debugger_cpu::read_qword(address_space &space, offs_t address, int apply_
UINT64 result; UINT64 result;
if (!QWORD_ALIGNED(address)) if (!QWORD_ALIGNED(address))
{ /* if this is a misaligned read, or if there are no qword readers, just read two dwords */ { /* if this is a misaligned read, or if there are no qword readers, just read two dwords */
UINT32 dword0 = read_dword(space, address + 0, apply_translation); UINT32 dword0 = read_dword(space, address + 0, apply_translation);
UINT32 dword1 = read_dword(space, address + 4, apply_translation); UINT32 dword1 = read_dword(space, address + 4, apply_translation);
@ -535,7 +535,7 @@ UINT64 debugger_cpu::read_qword(address_space &space, offs_t address, int apply_
result = dword1 | ((UINT64)dword0 << 32); result = dword1 | ((UINT64)dword0 << 32);
} }
else else
{ /* otherwise, this proceeds like the byte case */ { /* otherwise, this proceeds like the byte case */
/* all accesses from this point on are for the debugger */ /* all accesses from this point on are for the debugger */
m_debugger_access = true; m_debugger_access = true;
@ -548,11 +548,11 @@ UINT64 debugger_cpu::read_qword(address_space &space, offs_t address, int apply_
result = ~(UINT64)0; result = ~(UINT64)0;
} }
else if (space.device().memory().read(space.spacenum(), address, 8, custom)) else if (space.device().memory().read(space.spacenum(), address, 8, custom))
{ /* if there is a custom read handler, and it returns true, use that value */ { /* if there is a custom read handler, and it returns true, use that value */
result = custom; result = custom;
} }
else else
{ /* otherwise, call the byte reading function for the translated address */ { /* otherwise, call the byte reading function for the translated address */
result = space.read_qword(address); result = space.read_qword(address);
} }
@ -1528,13 +1528,13 @@ void debugger_cpu::start_hook(device_t *device, bool stop_on_vblank)
if (m_execution_state != EXECUTION_STATE_STOPPED) if (m_execution_state != EXECUTION_STATE_STOPPED)
{ {
if (device == m_visiblecpu && osd_ticks() > m_last_periodic_update_time + osd_ticks_per_second() / 4) if (device == m_visiblecpu && osd_ticks() > m_last_periodic_update_time + osd_ticks_per_second() / 4)
{ // check for periodic updates { // check for periodic updates
m_machine.debug_view().update_all(); m_machine.debug_view().update_all();
m_machine.debug_view().flush_osd_updates(); m_machine.debug_view().flush_osd_updates();
m_last_periodic_update_time = osd_ticks(); m_last_periodic_update_time = osd_ticks();
} }
else if (device == m_breakcpu) else if (device == m_breakcpu)
{ // check for pending breaks { // check for pending breaks
m_execution_state = EXECUTION_STATE_STOPPED; m_execution_state = EXECUTION_STATE_STOPPED;
m_breakcpu = nullptr; m_breakcpu = nullptr;
} }

39
src/emu/debug/debugcpu.h
View File

@ -603,36 +603,35 @@ private:
/* internal helpers */ /* internal helpers */
void on_vblank(screen_device &device, bool vblank_state); void on_vblank(screen_device &device, bool vblank_state);
running_machine& m_machine; running_machine& m_machine;
device_t * m_livecpu; device_t * m_livecpu;
device_t * m_visiblecpu; device_t * m_visiblecpu;
device_t * m_breakcpu; device_t * m_breakcpu;
FILE * m_source_file; // script source file FILE * m_source_file; // script source file
std::unique_ptr<symbol_table> m_symtable; // global symbol table std::unique_ptr<symbol_table> m_symtable; // global symbol table
bool m_within_instruction_hook; bool m_within_instruction_hook;
bool m_vblank_occurred; bool m_vblank_occurred;
bool m_memory_modified; bool m_memory_modified;
bool m_debugger_access; bool m_debugger_access;
int m_execution_state; int m_execution_state;
device_t * m_stop_when_not_device; // stop execution when the device ceases to be this device_t * m_stop_when_not_device; // stop execution when the device ceases to be this
UINT32 m_bpindex; UINT32 m_bpindex;
UINT32 m_wpindex; UINT32 m_wpindex;
UINT32 m_rpindex; UINT32 m_rpindex;
UINT64 m_wpdata; UINT64 m_wpdata;
UINT64 m_wpaddr; UINT64 m_wpaddr;
std::unique_ptr<UINT64[]> m_tempvar; std::unique_ptr<UINT64[]> m_tempvar;
osd_ticks_t m_last_periodic_update_time; osd_ticks_t m_last_periodic_update_time;
bool m_comments_loaded; bool m_comments_loaded;
}; };
#endif #endif

2
src/emu/debugger.cpp
View File

@ -125,7 +125,7 @@ debugger_manager::debugger_manager(running_machine &machine)
/* initialize the submodules */ /* initialize the submodules */
m_cpu = std::make_unique<debugger_cpu>(machine); m_cpu = std::make_unique<debugger_cpu>(machine);
m_console = std::make_unique<debugger_console>(machine); m_console = std::make_unique<debugger_console>(machine);
m_commands = std::make_unique<debugger_commands>(machine, cpu(), console()); m_commands = std::make_unique<debugger_commands>(machine, cpu(), console());
g_machine = &machine; g_machine = &machine;

2
src/emu/emumem.cpp
View File

@ -4474,7 +4474,7 @@ void handler_entry::description(char *buffer) const
m_subunit_infos[i].m_shift, m_subunit_infos[i].m_shift,
m_subunit_infos[i].m_offset, m_subunit_infos[i].m_offset,
m_subunit_infos[i].m_multiplier, m_subunit_infos[i].m_multiplier,
m_subunit_infos[i].m_bytemask, m_subunit_infos[i].m_bytemask,
subunit_name(i)); subunit_name(i));
} }
} }

4
src/emu/emumem.h
View File

@ -150,7 +150,7 @@ public:
direct_range(): m_bytestart(0),m_byteend(~0) { } direct_range(): m_bytestart(0),m_byteend(~0) { }
inline bool operator==(direct_range val) noexcept inline bool operator==(direct_range val) noexcept
{ // return true if _Left and _Right identify the same thread { // return true if _Left and _Right identify the same thread
return (m_bytestart == val.m_bytestart) && (m_byteend == val.m_byteend); return (m_bytestart == val.m_bytestart) && (m_byteend == val.m_byteend);
} }
@ -521,7 +521,7 @@ class memory_bank
// construction/destruction // construction/destruction
bank_reference(address_space &space, read_or_write readorwrite) bank_reference(address_space &space, read_or_write readorwrite)
: m_space(space), : m_space(space),
m_readorwrite(readorwrite) { } m_readorwrite(readorwrite) { }
// getters // getters
address_space &space() const { return m_space; } address_space &space() const { return m_space; }

4
src/frontend/mame/cheat.cpp
View File

@ -401,7 +401,7 @@ void cheat_script::save(emu_file &cheatfile) const
cheat_script::script_entry::script_entry(cheat_manager &manager, symbol_table &symbols, const char *filename, xml_data_node &entrynode, bool isaction) cheat_script::script_entry::script_entry(cheat_manager &manager, symbol_table &symbols, const char *filename, xml_data_node &entrynode, bool isaction)
: m_condition(&symbols), : m_condition(&symbols),
m_expression(&symbols) m_expression(&symbols)
{ {
const char *expression = nullptr; const char *expression = nullptr;
try try
@ -610,7 +610,7 @@ void cheat_script::script_entry::validate_format(const char *filename, int line)
cheat_script::script_entry::output_argument::output_argument(cheat_manager &manager, symbol_table &symbols, const char *filename, xml_data_node &argnode) cheat_script::script_entry::output_argument::output_argument(cheat_manager &manager, symbol_table &symbols, const char *filename, xml_data_node &argnode)
: m_expression(&symbols), : m_expression(&symbols),
m_count(0) m_count(0)
{ {
// first extract attributes // first extract attributes
m_count = xml_get_attribute_int(&argnode, "count", 1); m_count = xml_get_attribute_int(&argnode, "count", 1);

18
src/frontend/mame/cheat.h
View File

@ -100,7 +100,7 @@ private:
// construction/destruction // construction/destruction
item(const char *text, UINT64 value, int valformat) item(const char *text, UINT64 value, int valformat)
: m_text(text), : m_text(text),
m_value(value, valformat) { } m_value(value, valformat) { }
// getters // getters
const number_and_format &value() const { return m_value; } const number_and_format &value() const { return m_value; }
@ -175,12 +175,12 @@ private:
void validate_format(const char *filename, int line); void validate_format(const char *filename, int line);
// internal state // internal state
parsed_expression m_condition; // condition under which this is executed parsed_expression m_condition; // condition under which this is executed
parsed_expression m_expression; // expression to execute parsed_expression m_expression; // expression to execute
std::string m_format; // string format to print std::string m_format; // string format to print
std::vector<std::unique_ptr<output_argument>> m_arglist; // list of arguments std::vector<std::unique_ptr<output_argument>> m_arglist; // list of arguments
INT8 m_line; // which line to print on INT8 m_line; // which line to print on
ui::text_layout::text_justify m_justify; // justification when printing ui::text_layout::text_justify m_justify; // justification when printing
// constants // constants
static const int MAX_ARGUMENTS = 32; static const int MAX_ARGUMENTS = 32;
@ -306,12 +306,12 @@ private:
std::vector<std::unique_ptr<cheat_entry>> m_cheatlist; // cheat list std::vector<std::unique_ptr<cheat_entry>> m_cheatlist; // cheat list
UINT64 m_framecount; // frame count UINT64 m_framecount; // frame count
std::vector<std::string> m_output; // array of output strings std::vector<std::string> m_output; // array of output strings
std::vector<ui::text_layout::text_justify> m_justify; // justification for each string std::vector<ui::text_layout::text_justify> m_justify; // justification for each string
UINT8 m_numlines; // number of lines available for output UINT8 m_numlines; // number of lines available for output
INT8 m_lastline; // last line used for output INT8 m_lastline; // last line used for output
bool m_disabled; // true if the cheat engine is disabled bool m_disabled; // true if the cheat engine is disabled
symbol_table m_symtable; // global symbol table symbol_table m_symtable; // global symbol table
std::unique_ptr<debugger_cpu> m_cpu; // debugger interface for cpus/memory std::unique_ptr<debugger_cpu> m_cpu; // debugger interface for cpus/memory
// constants // constants
static constexpr int CHEAT_VERSION = 1; static constexpr int CHEAT_VERSION = 1;

1
src/frontend/mame/ui/auditmenu.cpp
View File

@ -18,7 +18,6 @@
extern const char UI_VERSION_TAG[]; extern const char UI_VERSION_TAG[];
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// sort // sort
//------------------------------------------------- //-------------------------------------------------

1
src/frontend/mame/ui/auditmenu.h
View File

@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// class audit menu // class audit menu
//------------------------------------------------- //-------------------------------------------------

1
src/frontend/mame/ui/barcode.cpp
View File

@ -14,7 +14,6 @@
#include "ui/ui.h" #include "ui/ui.h"
namespace ui { namespace ui {
// itemrefs for key menu items // itemrefs for key menu items
#define ITEMREF_NEW_BARCODE ((void *) 0x0001) #define ITEMREF_NEW_BARCODE ((void *) 0x0001)
#define ITEMREF_ENTER_BARCODE ((void *) 0x0002) #define ITEMREF_ENTER_BARCODE ((void *) 0x0002)

1
src/frontend/mame/ui/barcode.h
View File

@ -17,7 +17,6 @@
#include "ui/devctrl.h" #include "ui/devctrl.h"
namespace ui { namespace ui {
class menu_barcode_reader : public menu_device_control<barcode_reader_device> { class menu_barcode_reader : public menu_device_control<barcode_reader_device> {
public: public:
menu_barcode_reader(mame_ui_manager &mui, render_container *container, barcode_reader_device *device); menu_barcode_reader(mame_ui_manager &mui, render_container *container, barcode_reader_device *device);

1
src/frontend/mame/ui/cheatopt.cpp
View File

@ -18,7 +18,6 @@
namespace ui { namespace ui {
// itemrefs for key menu items // itemrefs for key menu items
#define ITEMREF_CHEATS_RESET_ALL ((void *) 0x0001) #define ITEMREF_CHEATS_RESET_ALL ((void *) 0x0001)
#define ITEMREF_CHEATS_RELOAD_ALL ((void *) 0x0002) #define ITEMREF_CHEATS_RELOAD_ALL ((void *) 0x0002)

1
src/frontend/mame/ui/cheatopt.h
View File

@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
class menu_cheat : public menu class menu_cheat : public menu
{ {
public: public:

1
src/frontend/mame/ui/custmenu.cpp
View File

@ -18,7 +18,6 @@
namespace ui { namespace ui {
/************************************************** /**************************************************
MENU CUSTOM FILTER MENU CUSTOM FILTER
**************************************************/ **************************************************/

1
src/frontend/mame/ui/custmenu.h
View File

@ -18,7 +18,6 @@
#include "ui/utils.h" #include "ui/utils.h"
namespace ui { namespace ui {
// Software region // Software region
struct c_sw_region struct c_sw_region
{ {

1
src/frontend/mame/ui/custui.cpp
View File

@ -20,7 +20,6 @@
#include "osdepend.h" #include "osdepend.h"
namespace ui { namespace ui {
const char *const menu_custom_ui::hide_status[] = { const char *const menu_custom_ui::hide_status[] = {
__("Show All"), __("Show All"),
__("Hide Filters"), __("Hide Filters"),

1
src/frontend/mame/ui/custui.h
View File

@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// Custom UI menu // Custom UI menu
//------------------------------------------------- //-------------------------------------------------

1
src/frontend/mame/ui/datmenu.cpp
View File

@ -20,7 +20,6 @@
#include "softlist.h" #include "softlist.h"
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// ctor / dtor // ctor / dtor
//------------------------------------------------- //-------------------------------------------------

1
src/frontend/mame/ui/datmenu.h
View File

@ -23,7 +23,6 @@
struct ui_software_info; struct ui_software_info;
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// class dats menu // class dats menu
//------------------------------------------------- //-------------------------------------------------

1
src/frontend/mame/ui/devctrl.h
View File

@ -26,7 +26,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
template<class DeviceType> template<class DeviceType>
class menu_device_control : public menu class menu_device_control : public menu
{ {

1
src/frontend/mame/ui/devopt.cpp
View File

@ -14,7 +14,6 @@
namespace ui { namespace ui {
/*------------------------------------------------- /*-------------------------------------------------
device_config - handle the game information device_config - handle the game information
menu menu

1
src/frontend/mame/ui/devopt.h
View File

@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
class menu_device_config : public menu class menu_device_config : public menu
{ {
public: public:

1
src/frontend/mame/ui/dirmenu.cpp
View File

@ -21,7 +21,6 @@
namespace ui { namespace ui {
static int ADDING = 1; static int ADDING = 1;
static int CHANGE = 2; static int CHANGE = 2;

1
src/frontend/mame/ui/dirmenu.h
View File

@ -19,7 +19,6 @@
#include <vector> #include <vector>
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// class directory menu // class directory menu
//------------------------------------------------- //-------------------------------------------------

1
src/frontend/mame/ui/filemngr.cpp
View File

@ -23,7 +23,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
FILE MANAGER FILE MANAGER
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/filemngr.h
View File

@ -14,7 +14,6 @@
#define MAME_FRONTEND_UI_FILEMNGR_H #define MAME_FRONTEND_UI_FILEMNGR_H
namespace ui { namespace ui {
class menu_file_manager : public menu class menu_file_manager : public menu
{ {
public: public:

1
src/frontend/mame/ui/filesel.cpp
View File

@ -25,7 +25,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
CONSTANTS CONSTANTS
***************************************************************************/ ***************************************************************************/

3
src/frontend/mame/ui/filesel.h
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@ -18,7 +18,6 @@
class floppy_image_format_t; class floppy_image_format_t;
namespace ui { namespace ui {
// ======================> menu_confirm_save_as // ======================> menu_confirm_save_as
class menu_confirm_save_as : public menu class menu_confirm_save_as : public menu
@ -101,7 +100,7 @@ private:
bool m_has_create; bool m_has_create;
int * m_result; int * m_result;
file_selector_entry * m_entrylist; file_selector_entry * m_entrylist;
std::string m_hover_directory; std::string m_hover_directory;
char m_filename_buffer[1024]; char m_filename_buffer[1024];
// methods // methods

1
src/frontend/mame/ui/floppycntrl.cpp
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@ -15,7 +15,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
IMPLEMENTATION IMPLEMENTATION
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/floppycntrl.h
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@ -17,7 +17,6 @@
#include "formats/flopimg.h" #include "formats/flopimg.h"
namespace ui { namespace ui {
class menu_control_floppy_image : public menu_control_device_image class menu_control_floppy_image : public menu_control_device_image
{ {
public: public:

1
src/frontend/mame/ui/imgcntrl.cpp
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@ -24,7 +24,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
IMPLEMENTATION IMPLEMENTATION
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/imgcntrl.h
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@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
// ======================> menu_control_device_image // ======================> menu_control_device_image
class menu_control_device_image : public menu class menu_control_device_image : public menu

1
src/frontend/mame/ui/info.cpp
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@ -16,7 +16,6 @@
#include "softlist.h" #include "softlist.h"
namespace ui { namespace ui {
/*------------------------------------------------- /*-------------------------------------------------
menu_game_info - handle the game information menu_game_info - handle the game information
menu menu

1
src/frontend/mame/ui/info.h
View File

@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
class menu_game_info : public menu class menu_game_info : public menu
{ {
public: public:

1
src/frontend/mame/ui/info_pty.cpp
View File

@ -14,7 +14,6 @@
namespace ui { namespace ui {
menu_pty_info::menu_pty_info(mame_ui_manager &mui, render_container *container) : menu_pty_info::menu_pty_info(mame_ui_manager &mui, render_container *container) :
menu(mui, container) menu(mui, container)
{ {

1
src/frontend/mame/ui/info_pty.h
View File

@ -16,7 +16,6 @@
#include "ui/menu.h" #include "ui/menu.h"
namespace ui { namespace ui {
class menu_pty_info : public menu class menu_pty_info : public menu
{ {
public: public:

1
src/frontend/mame/ui/inputmap.cpp
View File

@ -17,7 +17,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
CONSTANTS CONSTANTS
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/inputmap.h
View File

@ -17,7 +17,6 @@
namespace ui { namespace ui {
class menu_input_groups : public menu class menu_input_groups : public menu
{ {
public: public:

1
src/frontend/mame/ui/mainmenu.cpp
View File

@ -36,7 +36,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
MENU HANDLERS MENU HANDLERS
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/mainmenu.h
View File

@ -14,7 +14,6 @@
#define MAME_FRONTEND_UI_MAINMENU_H #define MAME_FRONTEND_UI_MAINMENU_H
namespace ui { namespace ui {
class menu_main : public menu class menu_main : public menu
{ {
public: public:

3
src/frontend/mame/ui/menu.cpp
View File

@ -29,7 +29,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
CONSTANTS CONSTANTS
***************************************************************************/ ***************************************************************************/
@ -2948,7 +2947,7 @@ void menu::extra_text_draw_box(float origx1, float origx2, float origy, float ys
//------------------------------------------------- //-------------------------------------------------
// extra_text_position - given extra text that has // extra_text_position - given extra text that has
// been put into a layout, position it // been put into a layout, position it
//------------------------------------------------- //-------------------------------------------------
void menu::extra_text_position(float origx1, float origx2, float origy, float yspan, text_layout &layout, void menu::extra_text_position(float origx1, float origx2, float origy, float yspan, text_layout &layout,

1
src/frontend/mame/ui/menu.h
View File

@ -23,7 +23,6 @@
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
TYPE DEFINITIONS TYPE DEFINITIONS
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/menuitem.h
View File

@ -17,7 +17,6 @@
#include "emu.h" #include "emu.h"
namespace ui { namespace ui {
// special menu item for separators // special menu item for separators
#define MENU_SEPARATOR_ITEM "---" #define MENU_SEPARATOR_ITEM "---"

1
src/frontend/mame/ui/miscmenu.cpp
View File

@ -24,7 +24,6 @@
#include "ui/submenu.h" #include "ui/submenu.h"
namespace ui { namespace ui {
/*************************************************************************** /***************************************************************************
MENU HANDLERS MENU HANDLERS
***************************************************************************/ ***************************************************************************/

1
src/frontend/mame/ui/miscmenu.h
View File

@ -21,7 +21,6 @@
namespace ui { namespace ui {
class menu_keyboard_mode : public menu class menu_keyboard_mode : public menu
{ {
public: public:

1
src/frontend/mame/ui/optsmenu.cpp
View File

@ -27,7 +27,6 @@
#include "rendfont.h" #include "rendfont.h"
namespace ui { namespace ui {
//------------------------------------------------- //-------------------------------------------------
// ctor // ctor
//------------------------------------------------- //-------------------------------------------------

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