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(MESS) osborne1.c: Cleanupss (nw)

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This commit is contained in:
Wilbert Pol 2013-01-25 19:07:58 +00:00
parent bfa2993010
commit 6411967b8e
2 changed files with 76 additions and 38 deletions
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44
src/mess/includes/osborne1.h
View File

@ -23,14 +23,27 @@ class osborne1_state : public driver_device
{ {
public: public:
osborne1_state(const machine_config &mconfig, device_type type, const char *tag) osborne1_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag), : driver_device(mconfig, type, tag)
m_maincpu(*this, "maincpu"), , m_maincpu(*this, "maincpu")
m_pia0(*this, "pia_0"), , m_pia0(*this, "pia_0")
m_pia1(*this, "pia_1"), , m_pia1(*this, "pia_1")
m_fdc(*this, "mb8877"), , m_fdc(*this, "mb8877")
m_beep(*this, BEEPER_TAG), , m_beep(*this, BEEPER_TAG)
m_ram(*this, RAM_TAG), , m_ram(*this, RAM_TAG)
m_ieee(*this, IEEE488_TAG) , m_ieee(*this, IEEE488_TAG)
, m_row0(*this, "ROW0")
, m_row1(*this, "ROW1")
, m_row2(*this, "ROW2")
, m_row3(*this, "ROW3")
, m_row4(*this, "ROW4")
, m_row5(*this, "ROW5")
, m_row6(*this, "ROW6")
, m_row7(*this, "ROW7")
, m_bank1(*this, "bank1")
, m_bank2(*this, "bank2")
, m_bank3(*this, "bank3")
, m_bank4(*this, "bank4")
, m_region_maincpu(*this, "maincpu")
{ } { }
virtual void video_start(); virtual void video_start();
@ -84,6 +97,21 @@ public:
virtual void palette_init(); virtual void palette_init();
TIMER_CALLBACK_MEMBER(osborne1_video_callback); TIMER_CALLBACK_MEMBER(osborne1_video_callback);
TIMER_CALLBACK_MEMBER(setup_osborne1); TIMER_CALLBACK_MEMBER(setup_osborne1);
protected:
required_ioport m_row0;
required_ioport m_row1;
required_ioport m_row2;
required_ioport m_row3;
required_ioport m_row4;
required_ioport m_row5;
required_ioport m_row6;
required_ioport m_row7;
required_memory_bank m_bank1;
required_memory_bank m_bank2;
required_memory_bank m_bank3;
required_memory_bank m_bank4;
required_memory_region m_region_maincpu;
}; };

70
src/mess/machine/osborne1.c
View File

@ -23,7 +23,9 @@ WRITE8_MEMBER( osborne1_state::osborne1_0000_w )
{ {
/* Check whether regular RAM is enabled */ /* Check whether regular RAM is enabled */
if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) ) if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) )
machine().device<ram_device>(RAM_TAG)->pointer()[ offset ] = data; {
m_ram->pointer()[ offset ] = data;
}
} }
@ -31,7 +33,9 @@ WRITE8_MEMBER( osborne1_state::osborne1_1000_w )
{ {
/* Check whether regular RAM is enabled */ /* Check whether regular RAM is enabled */
if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) ) if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) )
machine().device<ram_device>(RAM_TAG)->pointer()[ 0x1000 + offset ] = data; {
m_ram->pointer()[ 0x1000 + offset ] = data;
}
} }
@ -41,7 +45,9 @@ READ8_MEMBER( osborne1_state::osborne1_2000_r )
/* Check whether regular RAM is enabled */ /* Check whether regular RAM is enabled */
if ( ! m_bank2_enabled ) if ( ! m_bank2_enabled )
data = machine().device<ram_device>(RAM_TAG)->pointer()[ 0x2000 + offset ]; {
data = m_ram->pointer()[ 0x2000 + offset ];
}
else else
{ {
switch( offset & 0x0F00 ) switch( offset & 0x0F00 )
@ -51,21 +57,21 @@ READ8_MEMBER( osborne1_state::osborne1_2000_r )
break; break;
case 0x200: /* Keyboard */ case 0x200: /* Keyboard */
/* Row 0 */ /* Row 0 */
if ( offset & 0x01 ) data &= ioport("ROW0")->read(); if ( offset & 0x01 ) data &= m_row0->read();
/* Row 1 */ /* Row 1 */
if ( offset & 0x02 ) data &= ioport("ROW1")->read(); if ( offset & 0x02 ) data &= m_row1->read();
/* Row 2 */ /* Row 2 */
if ( offset & 0x04 ) data &= ioport("ROW3")->read(); if ( offset & 0x04 ) data &= m_row3->read();
/* Row 3 */ /* Row 3 */
if ( offset & 0x08 ) data &= ioport("ROW4")->read(); if ( offset & 0x08 ) data &= m_row4->read();
/* Row 4 */ /* Row 4 */
if ( offset & 0x10 ) data &= ioport("ROW5")->read(); if ( offset & 0x10 ) data &= m_row5->read();
/* Row 5 */ /* Row 5 */
if ( offset & 0x20 ) data &= ioport("ROW2")->read(); if ( offset & 0x20 ) data &= m_row2->read();
/* Row 6 */ /* Row 6 */
if ( offset & 0x40 ) data &= ioport("ROW6")->read(); if ( offset & 0x40 ) data &= m_row6->read();
/* Row 7 */ /* Row 7 */
if ( offset & 0x80 ) data &= ioport("ROW7")->read(); if ( offset & 0x80 ) data &= m_row7->read();
break; break;
case 0x900: /* IEEE488 PIA */ case 0x900: /* IEEE488 PIA */
data = m_pia0->read(space, offset & 0x03 ); data = m_pia0->read(space, offset & 0x03 );
@ -85,12 +91,14 @@ WRITE8_MEMBER( osborne1_state::osborne1_2000_w )
{ {
/* Check whether regular RAM is enabled */ /* Check whether regular RAM is enabled */
if ( ! m_bank2_enabled ) if ( ! m_bank2_enabled )
machine().device<ram_device>(RAM_TAG)->pointer()[ 0x2000 + offset ] = data; {
m_ram->pointer()[ 0x2000 + offset ] = data;
}
else else
{ {
if ( m_in_irq_handler && m_bankswitch == RAMMODE ) if ( m_in_irq_handler && m_bankswitch == RAMMODE )
{ {
machine().device<ram_device>(RAM_TAG)->pointer()[ 0x2000 + offset ] = data; m_ram->pointer()[ 0x2000 + offset ] = data;
} }
/* Handle writes to the I/O area */ /* Handle writes to the I/O area */
switch( offset & 0x0F00 ) switch( offset & 0x0F00 )
@ -115,7 +123,9 @@ WRITE8_MEMBER( osborne1_state::osborne1_3000_w )
{ {
/* Check whether regular RAM is enabled */ /* Check whether regular RAM is enabled */
if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) ) if ( ! m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE ) )
machine().device<ram_device>(RAM_TAG)->pointer()[ 0x3000 + offset ] = data; {
m_ram->pointer()[ 0x3000 + offset ] = data;
}
} }
@ -152,18 +162,18 @@ WRITE8_MEMBER( osborne1_state::osborne1_bankswitch_w )
} }
if ( m_bank2_enabled ) if ( m_bank2_enabled )
{ {
membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() ); m_bank1->set_base(m_region_maincpu->base() );
membank("bank2")->set_base(m_empty_4K ); m_bank2->set_base(m_empty_4K );
membank("bank3")->set_base(m_empty_4K ); m_bank3->set_base(m_empty_4K );
} }
else else
{ {
membank("bank1")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() ); m_bank1->set_base(m_ram->pointer() );
membank("bank2")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() + 0x1000 ); m_bank2->set_base(m_ram->pointer() + 0x1000 );
membank("bank3")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() + 0x3000 ); m_bank3->set_base(m_ram->pointer() + 0x3000 );
} }
m_bank4_ptr = machine().device<ram_device>(RAM_TAG)->pointer() + ( ( m_bank3_enabled ) ? 0x10000 : 0xF000 ); m_bank4_ptr = m_ram->pointer() + ( ( m_bank3_enabled ) ? 0x10000 : 0xF000 );
membank("bank4")->set_base(m_bank4_ptr ); m_bank4->set_base(m_bank4_ptr );
m_bankswitch = offset; m_bankswitch = offset;
m_in_irq_handler = 0; m_in_irq_handler = 0;
} }
@ -175,7 +185,7 @@ DIRECT_UPDATE_MEMBER(osborne1_state::osborne1_opbase)
{ {
if ( ! m_bank2_enabled ) if ( ! m_bank2_enabled )
{ {
direct.explicit_configure(0x2000, 0x2fff, 0x0fff, machine().device<ram_device>(RAM_TAG)->pointer() + 0x2000); direct.explicit_configure(0x2000, 0x2fff, 0x0fff, m_ram->pointer() + 0x2000);
return ~0; return ~0;
} }
} }
@ -186,7 +196,7 @@ DIRECT_UPDATE_MEMBER(osborne1_state::osborne1_opbase)
WRITE_LINE_MEMBER( osborne1_state::ieee_pia_irq_a_func ) WRITE_LINE_MEMBER( osborne1_state::ieee_pia_irq_a_func )
{ {
m_pia_0_irq_state = state; m_pia_0_irq_state = state;
machine().device("maincpu")->execute().set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE); m_maincpu->set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
} }
@ -297,7 +307,7 @@ WRITE8_MEMBER( osborne1_state::video_pia_port_b_w )
WRITE_LINE_MEMBER( osborne1_state::video_pia_irq_a_func ) WRITE_LINE_MEMBER( osborne1_state::video_pia_irq_a_func )
{ {
m_pia_1_irq_state = state; m_pia_1_irq_state = state;
machine().device("maincpu")->execute().set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE); m_maincpu->set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
} }
@ -357,8 +367,8 @@ TIMER_CALLBACK_MEMBER(osborne1_state::osborne1_video_callback)
for ( x = 0; x < 52; x++ ) for ( x = 0; x < 52; x++ )
{ {
chr = machine().device<ram_device>(RAM_TAG)->pointer()[ 0xF000 + ( (ma+x) & 0xFFF ) ]; chr = m_ram->pointer()[ 0xF000 + ( (ma+x) & 0xFFF ) ];
dim = machine().device<ram_device>(RAM_TAG)->pointer()[ 0x10000 + ( (ma+x) & 0xFFF ) ] & 0x80; dim = m_ram->pointer()[ 0x10000 + ( (ma+x) & 0xFFF ) ] & 0x80;
if ( (chr & 0x80) && (ra == 9) ) if ( (chr & 0x80) && (ra == 9) )
gfx = 0xFF; gfx = 0xFF;
@ -424,7 +434,7 @@ static void osborne1_load_proc(device_image_interface &image)
void osborne1_state::machine_reset() void osborne1_state::machine_reset()
{ {
int drive; int drive;
address_space& space = machine().device("maincpu")->memory().space(AS_PROGRAM); address_space& space = m_maincpu->space(AS_PROGRAM);
/* Initialize memory configuration */ /* Initialize memory configuration */
osborne1_bankswitch_w( space, 0x00, 0 ); osborne1_bankswitch_w( space, 0x00, 0 );
@ -434,7 +444,7 @@ void osborne1_state::machine_reset()
m_p_chargen = memregion( "chargen" )->base(); m_p_chargen = memregion( "chargen" )->base();
memset( machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000, 0xFF, 0x1000 ); memset( m_ram->pointer() + 0x10000, 0xFF, 0x1000 );
for(drive=0;drive<2;drive++) for(drive=0;drive<2;drive++)
floppy_install_load_proc(floppy_get_device(machine(), drive), osborne1_load_proc); floppy_install_load_proc(floppy_get_device(machine(), drive), osborne1_load_proc);
@ -521,7 +531,7 @@ int osborne1_daisy_device::z80daisy_irq_ack()
osborne1_state *state = machine().driver_data<osborne1_state>(); osborne1_state *state = machine().driver_data<osborne1_state>();
/* Enable ROM and I/O when IRQ is acknowledged */ /* Enable ROM and I/O when IRQ is acknowledged */
UINT8 old_bankswitch = state->m_bankswitch; UINT8 old_bankswitch = state->m_bankswitch;
address_space& space = device().machine().device("maincpu")->memory().space(AS_PROGRAM); address_space& space = state->m_maincpu->space(AS_PROGRAM);
state->osborne1_bankswitch_w( space, 0, 0 ); state->osborne1_bankswitch_w( space, 0, 0 );
state->m_bankswitch = old_bankswitch; state->m_bankswitch = old_bankswitch;