Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-06-30 07:58:56 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

m68705: disassemble memory addresses symbolically

Browse Source
This commit is contained in:
Vas Crabb 2017-01-14 19:48:04 +11:00
parent 348afca60c
commit 6413971c76
4 changed files with 254 additions and 137 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

317
src/devices/cpu/m6805/6805dasm.cpp
View File

@ -11,20 +11,23 @@
*/ */
#include "emu.h" #include "emu.h"
#include "debugger.h"
#include "m6805.h" #include "m6805.h"
enum addr_mode { #include "debugger.h"
md_imp=0, /* implicit */
md_btr, /* bit test and relative */ namespace {
md_bit, /* bit set/clear */
md_rel, /* relative */ enum class md {
md_imm, /* immediate */ IMP, // implicit
md_dir, /* direct address */ BTR, // bit test and relative
md_ext, /* extended address */ BIT, // bit set/clear
md_idx, /* indexed */ REL, // relative
md_ix1, /* indexed + byte offset */ IMM, // immediate
md_ix2 /* indexed + word offset */ DIR, // direct address
EXT, // extended address
IDX, // indexed
IX1, // indexed + byte offset
IX2 // indexed + word offset
}; };
enum op_names { enum op_names {
@ -41,7 +44,7 @@ enum op_names {
tstx, txa tstx, txa
}; };
static const char *const op_name_str[] = { char const *const op_name_str[] = {
"adca", "adda", "anda", "asl", "asla", "aslx", "asr", "asra", "adca", "adda", "anda", "asl", "asla", "aslx", "asr", "asra",
"asrx", "bcc", "bclr", "bcs", "beq", "bhcc", "bhcs", "bhi", "asrx", "bcc", "bclr", "bcs", "beq", "bhcc", "bhcs", "bhi",
"bih", "bil", "bita", "bls", "bmc", "bmi", "bms", "bne", "bih", "bil", "bita", "bls", "bmc", "bmi", "bms", "bne",
@ -55,75 +58,75 @@ static const char *const op_name_str[] = {
"tstx", "txa" "tstx", "txa"
}; };
static const unsigned char disasm[0x100][2] = { struct { u8 op; md mode; } const disasm[0x100] = {
{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr},/* 00 */ {brset,md::BTR}, {brclr,md::BTR}, {brset,md::BTR}, {brclr,md::BTR}, // 00
{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr}, {brset,md::BTR}, {brclr,md::BTR}, {brset,md::BTR}, {brclr,md::BTR},
{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr}, {brset,md::BTR}, {brclr,md::BTR}, {brset,md::BTR}, {brclr,md::BTR},
{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr}, {brset,md::BTR}, {brclr,md::BTR}, {brset,md::BTR}, {brclr,md::BTR},
{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit},/* 10 */ {bset, md::BIT}, {bclr, md::BIT}, {bset, md::BIT}, {bclr, md::BIT}, // 10
{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit}, {bset, md::BIT}, {bclr, md::BIT}, {bset, md::BIT}, {bclr, md::BIT},
{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit}, {bset, md::BIT}, {bclr, md::BIT}, {bset, md::BIT}, {bclr, md::BIT},
{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit}, {bset, md::BIT}, {bclr, md::BIT}, {bset, md::BIT}, {bclr, md::BIT},
{bra, md_rel},{brn, md_rel},{bhi, md_rel},{bls, md_rel},/* 20 */ {bra, md::REL}, {brn, md::REL}, {bhi, md::REL}, {bls, md::REL}, // 20
{bcc, md_rel},{bcs, md_rel},{bne, md_rel},{beq, md_rel}, {bcc, md::REL}, {bcs, md::REL}, {bne, md::REL}, {beq, md::REL},
{bhcc, md_rel},{bhcs, md_rel},{bpl, md_rel},{bmi, md_rel}, {bhcc, md::REL}, {bhcs, md::REL}, {bpl, md::REL}, {bmi, md::REL},
{bmc, md_rel},{bms, md_rel},{bil, md_rel},{bih, md_rel}, {bmc, md::REL}, {bms, md::REL}, {bil, md::REL}, {bih, md::REL},
{neg, md_dir},{ill, md_imp},{ill, md_imp},{com, md_dir},/* 30 */ {neg, md::DIR}, {ill, md::IMP}, {ill, md::IMP}, {com, md::DIR}, // 30
{lsr, md_dir},{ill, md_imp},{ror, md_dir},{asr, md_dir}, {lsr, md::DIR}, {ill, md::IMP}, {ror, md::DIR}, {asr, md::DIR},
{asl, md_dir},{rol, md_dir},{dec, md_dir},{ill, md_imp}, {asl, md::DIR}, {rol, md::DIR}, {dec, md::DIR}, {ill, md::IMP},
{inc, md_dir},{tst, md_dir},{ill, md_imp},{clr, md_dir}, {inc, md::DIR}, {tst, md::DIR}, {ill, md::IMP}, {clr, md::DIR},
{nega, md_imp},{ill, md_imp},{ill, md_imp},{coma, md_imp},/* 40 */ {nega, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {coma, md::IMP}, // 40
{lsra, md_imp},{ill, md_imp},{rora, md_imp},{asra, md_imp}, {lsra, md::IMP}, {ill, md::IMP}, {rora, md::IMP}, {asra, md::IMP},
{asla, md_imp},{rola, md_imp},{deca, md_imp},{ill, md_imp}, {asla, md::IMP}, {rola, md::IMP}, {deca, md::IMP}, {ill, md::IMP},
{inca, md_imp},{tsta, md_imp},{ill, md_imp},{clra, md_imp}, {inca, md::IMP}, {tsta, md::IMP}, {ill, md::IMP}, {clra, md::IMP},
{negx, md_imp},{ill, md_imp},{ill, md_imp},{comx, md_imp},/* 50 */ {negx, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {comx, md::IMP}, // 50
{lsrx, md_imp},{ill, md_imp},{rorx, md_imp},{asrx, md_imp}, {lsrx, md::IMP}, {ill, md::IMP}, {rorx, md::IMP}, {asrx, md::IMP},
{aslx, md_imp},{rolx, md_imp},{decx, md_imp},{ill, md_imp}, {aslx, md::IMP}, {rolx, md::IMP}, {decx, md::IMP}, {ill, md::IMP},
{incx, md_imp},{tstx, md_imp},{ill, md_imp},{clrx, md_imp}, {incx, md::IMP}, {tstx, md::IMP}, {ill, md::IMP}, {clrx, md::IMP},
{neg, md_ix1},{ill, md_imp},{ill, md_imp},{com, md_ix1},/* 60 */ {neg, md::IX1}, {ill, md::IMP}, {ill, md::IMP}, {com, md::IX1}, // 60
{lsr, md_ix1},{ill, md_imp},{ror, md_ix1},{asr, md_ix1}, {lsr, md::IX1}, {ill, md::IMP}, {ror, md::IX1}, {asr, md::IX1},
{asl, md_ix1},{rol, md_ix1},{dec, md_ix1},{ill, md_imp}, {asl, md::IX1}, {rol, md::IX1}, {dec, md::IX1}, {ill, md::IMP},
{inc, md_ix1},{tst, md_ix1},{jmp, md_ix1},{clr, md_ix1}, {inc, md::IX1}, {tst, md::IX1}, {jmp, md::IX1}, {clr, md::IX1},
{neg, md_idx},{ill, md_imp},{ill, md_imp},{com, md_idx},/* 70 */ {neg, md::IDX}, {ill, md::IMP}, {ill, md::IMP}, {com, md::IDX}, // 70
{lsr, md_idx},{ill, md_imp},{ror, md_idx},{asr, md_idx}, {lsr, md::IDX}, {ill, md::IMP}, {ror, md::IDX}, {asr, md::IDX},
{asl, md_idx},{rol, md_idx},{dec, md_idx},{ill, md_imp}, {asl, md::IDX}, {rol, md::IDX}, {dec, md::IDX}, {ill, md::IMP},
{inc, md_idx},{tst, md_idx},{jmp, md_idx},{clr, md_idx}, {inc, md::IDX}, {tst, md::IDX}, {jmp, md::IDX}, {clr, md::IDX},
{rti, md_imp},{rts, md_imp},{ill, md_imp},{swi, md_imp},/* 80 */ {rti, md::IMP}, {rts, md::IMP}, {ill, md::IMP}, {swi, md::IMP}, // 80
{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP},
{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP},
{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP},
{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp},/* 90 */ {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, // 90
{ill, md_imp},{ill, md_imp},{ill, md_imp},{tax, md_imp}, {ill, md::IMP}, {ill, md::IMP}, {ill, md::IMP}, {tax, md::IMP},
{clc, md_imp},{sec, md_imp},{cli, md_imp},{sei, md_imp}, {clc, md::IMP}, {sec, md::IMP}, {cli, md::IMP}, {sei, md::IMP},
{rsp, md_imp},{nop, md_imp},{ill, md_imp},{txa, md_imp}, {rsp, md::IMP}, {nop, md::IMP}, {ill, md::IMP}, {txa, md::IMP},
{suba, md_imm},{cmpa, md_imm},{sbca, md_imm},{cpx, md_imm},/* a0 */ {suba, md::IMM}, {cmpa, md::IMM}, {sbca, md::IMM}, {cpx, md::IMM}, // a0
{anda, md_imm},{bita, md_imm},{lda, md_imm},{ill, md_imp}, {anda, md::IMM}, {bita, md::IMM}, {lda, md::IMM}, {ill, md::IMP},
{eora, md_imm},{adca, md_imm},{ora, md_imm},{adda, md_imm}, {eora, md::IMM}, {adca, md::IMM}, {ora, md::IMM}, {adda, md::IMM},
{ill, md_imp},{bsr, md_rel},{ldx, md_imm},{ill, md_imp}, {ill, md::IMP}, {bsr, md::REL}, {ldx, md::IMM}, {ill, md::IMP},
{suba, md_dir},{cmpa, md_dir},{sbca, md_dir},{cpx, md_dir},/* b0 */ {suba, md::DIR}, {cmpa, md::DIR}, {sbca, md::DIR}, {cpx, md::DIR}, // b0
{anda, md_dir},{bita, md_dir},{lda, md_dir},{sta, md_dir}, {anda, md::DIR}, {bita, md::DIR}, {lda, md::DIR}, {sta, md::DIR},
{eora, md_dir},{adca, md_dir},{ora, md_dir},{adda, md_dir}, {eora, md::DIR}, {adca, md::DIR}, {ora, md::DIR}, {adda, md::DIR},
{jmp, md_dir},{jsr, md_dir},{ldx, md_dir},{stx, md_dir}, {jmp, md::DIR}, {jsr, md::DIR}, {ldx, md::DIR}, {stx, md::DIR},
{suba, md_ext},{cmpa, md_ext},{sbca, md_ext},{cpx, md_ext},/* c0 */ {suba, md::EXT}, {cmpa, md::EXT}, {sbca, md::EXT}, {cpx, md::EXT}, // c0
{anda, md_ext},{bita, md_ext},{lda, md_ext},{sta, md_ext}, {anda, md::EXT}, {bita, md::EXT}, {lda, md::EXT}, {sta, md::EXT},
{eora, md_ext},{adca, md_ext},{ora, md_ext},{adda, md_ext}, {eora, md::EXT}, {adca, md::EXT}, {ora, md::EXT}, {adda, md::EXT},
{jmp, md_ext},{jsr, md_ext},{ldx, md_ext},{stx, md_ext}, {jmp, md::EXT}, {jsr, md::EXT}, {ldx, md::EXT}, {stx, md::EXT},
{suba, md_ix2},{cmpa, md_ix2},{sbca, md_ix2},{cpx, md_ix2},/* d0 */ {suba, md::IX2}, {cmpa, md::IX2}, {sbca, md::IX2}, {cpx, md::IX2}, // d0
{anda, md_ix2},{bita, md_ix2},{lda, md_ix2},{sta, md_ix2}, {anda, md::IX2}, {bita, md::IX2}, {lda, md::IX2}, {sta, md::IX2},
{eora, md_ix2},{adca, md_ix2},{ora, md_ix2},{adda, md_ix2}, {eora, md::IX2}, {adca, md::IX2}, {ora, md::IX2}, {adda, md::IX2},
{jmp, md_ix2},{jsr, md_ix2},{ldx, md_ix2},{stx, md_ix2}, {jmp, md::IX2}, {jsr, md::IX2}, {ldx, md::IX2}, {stx, md::IX2},
{suba, md_ix1},{cmpa, md_ix1},{sbca, md_ix1},{cpx, md_ix1},/* e0 */ {suba, md::IX1}, {cmpa, md::IX1}, {sbca, md::IX1}, {cpx, md::IX1}, // e0
{anda, md_ix1},{bita, md_ix1},{lda, md_ix1},{sta, md_ix1}, {anda, md::IX1}, {bita, md::IX1}, {lda, md::IX1}, {sta, md::IX1},
{eora, md_ix1},{adca, md_ix1},{ora, md_ix1},{adda, md_ix1}, {eora, md::IX1}, {adca, md::IX1}, {ora, md::IX1}, {adda, md::IX1},
{jmp, md_ix1},{jsr, md_ix1},{ldx, md_ix1},{stx, md_ix1}, {jmp, md::IX1}, {jsr, md::IX1}, {ldx, md::IX1}, {stx, md::IX1},
{suba, md_idx},{cmpa, md_idx},{sbca, md_idx},{cpx, md_idx},/* f0 */ {suba, md::IDX}, {cmpa, md::IDX}, {sbca, md::IDX}, {cpx, md::IDX}, // f0
{anda, md_idx},{bita, md_idx},{lda, md_idx},{sta, md_idx}, {anda, md::IDX}, {bita, md::IDX}, {lda, md::IDX}, {sta, md::IDX},
{eora, md_idx},{adca, md_idx},{ora, md_idx},{adda, md_idx}, {eora, md::IDX}, {adca, md::IDX}, {ora, md::IDX}, {adda, md::IDX},
{jmp, md_idx},{jsr, md_idx},{ldx, md_idx},{stx, md_idx} {jmp, md::IDX}, {jsr, md::IDX}, {ldx, md::IDX}, {stx, md::IDX}
}; };
#if 0 #if 0
static const char *const opcode_strings[0x0100] = char const *const opcode_strings[0x0100] =
{ {
"brset0", "brclr0", "brset1", "brclr1", "brset2", "brclr2", "brset3", "brclr3", /*00*/ "brset0", "brclr0", "brset1", "brclr1", "brset2", "brclr2", "brset3", "brclr3", /*00*/
"brset4", "brclr4", "brset5", "brclr5", "brset6", "brclr6", "brset7", "brclr7", "brset4", "brclr4", "brset5", "brclr5", "brset6", "brclr6", "brset7", "brclr7",
@ -160,67 +163,109 @@ static const char *const opcode_strings[0x0100] =
}; };
#endif #endif
CPU_DISASSEMBLE(m6805)
template <typename T>
void format_address(
std::ostream& stream,
T address,
std::pair<u16, char const *> const symbols[],
std::size_t symbol_count)
{ {
int code, bit; auto const symbol= std::lower_bound(
uint16_t ea; &symbols[0],
&symbols[symbol_count],
address,
[] (auto const &sym, u16 addr) { return sym.first < addr; });
if ((symbol_count != (symbol - symbols)) && (symbol->first == address))
stream << symbol->second;
else
util::stream_format(stream, "$%0*X", 2 * sizeof(T), address);
}
} // anonymous namespace
offs_t CPU_DISASSEMBLE_NAME(m6805)(
cpu_device *device,
std::ostream &stream,
offs_t pc,
const u8 *oprom,
const u8 *opram,
int options,
std::pair<u16, char const *> const symbols[],
std::size_t symbol_count)
{
u8 const code = oprom[0];
uint32_t flags = 0; uint32_t flags = 0;
offs_t result; switch (disasm[code].op)
code = oprom[0];
if (disasm[code][0] == bsr || disasm[code][0] == jsr)
flags = DASMFLAG_STEP_OVER;
else if (disasm[code][0] == rts || disasm[code][0] == rti)
flags = DASMFLAG_STEP_OUT;
util::stream_format(stream, "%-6s", op_name_str[disasm[code][0]]);
switch( disasm[code][1] )
{ {
case md_btr: /* bit test and relative branch */ case bsr:
bit = (code >> 1) & 7; case jsr:
util::stream_format(stream, "%d,$%02X,$%03X", bit, opram[1], pc + 3 + (int8_t)opram[2]); flags = DASMFLAG_STEP_OVER;
result = 3 | flags | DASMFLAG_SUPPORTED;
break; break;
case md_bit: /* bit test */ case rts:
bit = (code >> 1) & 7; case rti:
util::stream_format(stream, "%d,$%03X", bit, opram[1]); flags = DASMFLAG_STEP_OUT;
result = 2 | flags | DASMFLAG_SUPPORTED;
break;
case md_rel: /* relative */
util::stream_format(stream, "$%03X", pc + 2 + (int8_t)opram[1]);
result = 2 | flags | DASMFLAG_SUPPORTED;
break;
case md_imm: /* immediate */
util::stream_format(stream, "#$%02X", opram[1]);
result = 2 | flags | DASMFLAG_SUPPORTED;
break;
case md_dir: /* direct (zero page address) */
util::stream_format(stream, "$%02X", opram[1]);
result = 2 | flags | DASMFLAG_SUPPORTED;
break;
case md_ext: /* extended (16 bit address) */
ea = (opram[1] << 8) + opram[2];
util::stream_format(stream, "$%04X", ea);
result = 3 | flags | DASMFLAG_SUPPORTED;
break;
case md_idx: /* indexed */
util::stream_format(stream, "(x)");
result = 1 | flags | DASMFLAG_SUPPORTED;
break;
case md_ix1: /* indexed + byte (zero page) */
util::stream_format(stream, "(x+$%02X)", opram[1]);
result = 2 | flags | DASMFLAG_SUPPORTED;
break;
case md_ix2: /* indexed + word (16 bit address) */
ea = (opram[1] << 8) + opram[2];
util::stream_format(stream, "(x+$%04X)", ea);
result = 3 | flags | DASMFLAG_SUPPORTED;
break;
default: /* implicit */
result = 1 | flags | DASMFLAG_SUPPORTED;
break; break;
} }
return result;
util::stream_format(stream, "%-6s", op_name_str[disasm[code].op]);
int bit;
u16 ea;
switch (disasm[code].mode)
{
case md::IMP: // implicit
return 1 | flags | DASMFLAG_SUPPORTED;
case md::BTR: // bit test and relative branch
bit = (code >> 1) & 7;
util::stream_format(stream, "%d,", bit);
format_address(stream, opram[1], symbols, symbol_count);
util::stream_format(stream, ",$%03X", pc + 3 + (int8_t)opram[2]);
return 3 | flags | DASMFLAG_SUPPORTED;
case md::BIT: // bit test
bit = (code >> 1) & 7;
util::stream_format(stream, "%d,", bit);
format_address(stream, opram[1], symbols, symbol_count);
return 2 | flags | DASMFLAG_SUPPORTED;
case md::REL: // relative
util::stream_format(stream, "$%03X", pc + 2 + (int8_t)opram[1]);
return 2 | flags | DASMFLAG_SUPPORTED;
case md::IMM: // immediate
util::stream_format(stream, "#$%02X", opram[1]);
return 2 | flags | DASMFLAG_SUPPORTED;
case md::DIR: // direct (zero page address)
format_address(stream, opram[1], symbols, symbol_count);
return 2 | flags | DASMFLAG_SUPPORTED;
case md::EXT: // extended (16 bit address)
ea = (opram[1] << 8) + opram[2];
format_address(stream, ea, symbols, symbol_count);
return 3 | flags | DASMFLAG_SUPPORTED;
case md::IDX: // indexed
util::stream_format(stream, "(x)");
return 1 | flags | DASMFLAG_SUPPORTED;
case md::IX1: // indexed + byte (zero page)
util::stream_format(stream, "(x+$%02X)", opram[1]);
return 2 | flags | DASMFLAG_SUPPORTED;
case md::IX2: // indexed + word (16 bit address)
ea = (opram[1] << 8) + opram[2];
util::stream_format(stream, "(x+$%04X)", ea);
return 3 | flags | DASMFLAG_SUPPORTED;
}
// if we fall off the switch statement something is very wrong
throw false;
} }
CPU_DISASSEMBLE(m6805) { return CPU_DISASSEMBLE_NAME(m6805)(device, stream, pc, oprom, opram, options, nullptr, 0); }

23
src/devices/cpu/m6805/m6805defs.h
View File

@ -128,4 +128,27 @@
/* pre-clear a PAIR union; clearing h2 and h3 only might be faster? */ /* pre-clear a PAIR union; clearing h2 and h3 only might be faster? */
#define CLEAR_PAIR(p) p->d = 0 #define CLEAR_PAIR(p) p->d = 0
offs_t CPU_DISASSEMBLE_NAME(m6805)(
cpu_device *device,
std::ostream &stream,
offs_t pc,
const u8 *oprom,
const u8 *opram,
int options,
std::pair<u16, char const *> const symbols[],
std::size_t symbol_count);
template <size_t N>
inline offs_t CPU_DISASSEMBLE_NAME(m6805)(
cpu_device *device,
std::ostream &stream,
offs_t pc,
const u8 *oprom,
const u8 *opram,
int options,
std::pair<u16, char const *> const (&symbols)[N])
{
return CPU_DISASSEMBLE_NAME(m6805)(device, stream, pc, oprom, opram, options, symbols, N);
}
#endif // MAME_CPU_M6805_M6805DEFS_H #endif // MAME_CPU_M6805_M6805DEFS_H

38
src/devices/cpu/m6805/m68705.cpp
View File

@ -4,6 +4,22 @@
namespace { namespace {
std::pair<u16, char const *> const m68705p_syms[] = {
{ 0x0000, "PORTA" }, { 0x0001, "PORTB" }, { 0x0002, "PORTC" },
{ 0x0004, "DDRA" }, { 0x0005, "DDRB" }, { 0x0006, "DDRC" },
{ 0x0008, "TDR" }, { 0x0009, "TCR" },
{ 0x000b, "PCR" },
{ 0x0784, "MOR" } };
std::pair<u16, char const *> const m68705u_syms[] = {
{ 0x0000, "PORTA" }, { 0x0001, "PORTB" }, { 0x0002, "PORTC" }, { 0x0003, "PORTD" },
{ 0x0004, "DDRA" }, { 0x0005, "DDRB" }, { 0x0006, "DDRC" },
{ 0x0008, "TDR" }, { 0x0009, "TCR" },
{ 0x000a, "MISC" },
{ 0x000b, "PCR" },
{ 0x0f38, "MOR" } };
ROM_START( m68705p3 ) ROM_START( m68705p3 )
ROM_REGION(0x0073, "bootstrap", 0) ROM_REGION(0x0073, "bootstrap", 0)
ROM_LOAD("bootstrap.bin", 0x0000, 0x0073, CRC(696e1383) SHA1(45104fe1dbd683d251ed2b9411b1f4befbb5aff4)) ROM_LOAD("bootstrap.bin", 0x0000, 0x0073, CRC(696e1383) SHA1(45104fe1dbd683d251ed2b9411b1f4befbb5aff4))
@ -462,7 +478,7 @@ void m68705_new_device::nvram_write(emu_file &file)
/**************************************************************************** /****************************************************************************
* M68705P3x family * M68705Px family
****************************************************************************/ ****************************************************************************/
DEVICE_ADDRESS_MAP_START( p_map, 8, m68705p_device ) DEVICE_ADDRESS_MAP_START( p_map, 8, m68705p_device )
@ -504,6 +520,16 @@ m68705p_device::m68705p_device(
set_port_mask<3>(0xff); // Port D isn't present set_port_mask<3>(0xff); // Port D isn't present
} }
offs_t m68705p_device::disasm_disassemble(
std::ostream &stream,
offs_t pc,
const uint8_t *oprom,
const uint8_t *opram,
uint32_t options)
{
return CPU_DISASSEMBLE_NAME(m6805)(this, stream, pc, oprom, opram, options, m68705p_syms);
}
/**************************************************************************** /****************************************************************************
* M68705P3 device * M68705P3 device
@ -573,3 +599,13 @@ tiny_rom_entry const *m68705u3_device::device_rom_region() const
{ {
return ROM_NAME(m68705u3); return ROM_NAME(m68705u3);
} }
offs_t m68705u3_device::disasm_disassemble(
std::ostream &stream,
offs_t pc,
const uint8_t *oprom,
const uint8_t *opram,
uint32_t options)
{
return CPU_DISASSEMBLE_NAME(m6805)(this, stream, pc, oprom, opram, options, m68705u_syms);
}

13
src/devices/cpu/m6805/m68705.h
View File

@ -189,6 +189,13 @@ protected:
char const *name, char const *name,
char const *shortname, char const *shortname,
char const *source); char const *source);
virtual offs_t disasm_disassemble(
std::ostream &stream,
offs_t pc,
const uint8_t *oprom,
const uint8_t *opram,
uint32_t options) override;
}; };
@ -232,6 +239,12 @@ protected:
DECLARE_ADDRESS_MAP(u_map, 8); DECLARE_ADDRESS_MAP(u_map, 8);
virtual tiny_rom_entry const *device_rom_region() const override; virtual tiny_rom_entry const *device_rom_region() const override;
virtual offs_t disasm_disassemble(
std::ostream &stream,
offs_t pc,
const uint8_t *oprom,
const uint8_t *opram,
uint32_t options) override;
}; };