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h8_timer16: status flags are set no matter the irq enable flags, add trampolines for h8/325

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hap 2024-02-07 13:53:08 +01:00
parent 6853c9e811
commit 642c42ae95
7 changed files with 54 additions and 20 deletions
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11
src/devices/cpu/h8/h8325.cpp
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@ -18,7 +18,7 @@ DEFINE_DEVICE_TYPE(H83257, h83257_device, "h83257", "Hitachi H8/3257")
DEFINE_DEVICE_TYPE(H83256, h83256_device, "h83256", "Hitachi H8/3256")
DEFINE_DEVICE_TYPE(H8325, h8325_device, "h8325", "Hitachi H8/325")
DEFINE_DEVICE_TYPE(H8324, h8324_device, "h8324", "Hitachi H8/324")
DEFINE_DEVICE_TYPE(H8323, h8323_device, "h8322", "Hitachi H8/323")
DEFINE_DEVICE_TYPE(H8323, h8323_device, "h8323", "Hitachi H8/323")
DEFINE_DEVICE_TYPE(H8322, h8322_device, "h8322", "Hitachi H8/322")
@ -76,10 +76,11 @@ void h8325_device::map(address_map &map)
map(m_ram_start, 0xff7f).ram();
map(0xff90, 0xff90).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tcr_r), FUNC(h8325_timer16_channel_device::tcr_w));
map(0xff91, 0xff91).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tsr_r), FUNC(h8325_timer16_channel_device::tsr_w)); // TCSR
map(0xff92, 0xff93).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tcnt_r), FUNC(h8325_timer16_channel_device::tcnt_w)); // FRC
map(0xff94, 0xff99).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tgr_r), FUNC(h8325_timer16_channel_device::tgr_w)); // OCRA/OCRB/ICR
map(0xff98, 0xff99).unmapw(); // ICR is read-only
map(0xff91, 0xff91).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tsr_r), FUNC(h8325_timer16_channel_device::tsr_w));
map(0xff92, 0xff93).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tcnt_r), FUNC(h8325_timer16_channel_device::tcnt_w));
map(0xff94, 0xff95).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::ocra_r), FUNC(h8325_timer16_channel_device::ocra_w));
map(0xff96, 0xff97).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::ocrb_r), FUNC(h8325_timer16_channel_device::ocrb_w));
map(0xff98, 0xff99).r(m_timer16_0, FUNC(h8325_timer16_channel_device::icr_r));
map(0xffb0, 0xffb0).w(m_port1, FUNC(h8_port_device::ddr_w));
map(0xffb1, 0xffb1).w(m_port2, FUNC(h8_port_device::ddr_w));

6
src/devices/cpu/h8/h8_intc.cpp
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@ -136,7 +136,7 @@ void h8_intc_device::check_level_irqs(bool force_update)
{
logerror("irq_input=%02x\n", m_irq_input);
bool update = force_update;
for(int i=0; i<8; i++) {
for(int i=0; i<m_irq_vector_count; i++) {
unsigned char mask = 1 << i;
if(m_irq_type[i] == IRQ_LEVEL && (m_irq_input & mask) && !(m_isr & mask)) {
m_isr |= mask;
@ -162,7 +162,7 @@ void h8_intc_device::iscr_w(uint8_t data)
void h8_intc_device::update_irq_types()
{
for(int i=0; i<8; i++)
for(int i=0; i<m_irq_vector_count; i++)
switch((m_iscr >> (i)) & 1) {
case 0:
m_irq_type[i] = IRQ_LEVEL;
@ -306,7 +306,7 @@ void h8h_intc_device::iscrl_w(uint8_t data)
void h8h_intc_device::update_irq_types()
{
for(int i=0; i<8; i++)
for(int i=0; i<m_irq_vector_count; i++)
switch((m_iscr >> (2*i)) & 3) {
case 0:
m_irq_type[i] = IRQ_LEVEL;

24
src/devices/cpu/h8/h8_timer16.cpp
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@ -1,5 +1,19 @@
// license:BSD-3-Clause
// copyright-holders:Olivier Galibert
/***************************************************************************
h8_timer16.cpp
H8 16 bits timer
TODO:
- IRQs are level triggered? eg. when an interrupt enable flag gets set
while an overflow or compare match flag is 1, will it trigger an IRQ?
- H8/325 16-bit timer is shoehorned in and may have a bug lurking?
It doesn't have TGR registers, but functionally equivalent OCR/ICR.
***************************************************************************/
#include "emu.h"
#include "h8_timer16.h"
@ -226,13 +240,15 @@ void h8_timer16_channel_device::update_counter(uint64_t cur_time)
m_tcnt = tt % m_counter_cycle;
for(int i=0; i<m_tgr_count; i++)
if((m_ier & (1 << i)) && (tt == m_tgr[i] || m_tcnt == m_tgr[i]) && m_interrupt[i] != -1) {
if(!(m_isr & (1 << i)) && (tt == m_tgr[i] || m_tcnt == m_tgr[i])) {
m_isr |= 1 << i;
m_intc->internal_interrupt(m_interrupt[i]);
if (m_ier & (1 << i) && m_interrupt[i] != -1)
m_intc->internal_interrupt(m_interrupt[i]);
}
if(tt >= 0x10000 && (m_ier & IRQ_V) && m_interrupt[4] != -1) {
if(tt >= 0x10000 && !(m_isr & IRQ_V)) {
m_isr |= IRQ_V;
m_intc->internal_interrupt(m_interrupt[4]);
if (m_ier & IRQ_V && m_interrupt[4] != -1)
m_intc->internal_interrupt(m_interrupt[4]);
}
} else
m_tcnt = (((m_tcnt ^ 0xffff) + new_time - base_time) % m_counter_cycle) ^ 0xffff;

7
src/devices/cpu/h8/h8_timer16.h
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@ -6,7 +6,6 @@
H8 16 bits timer
***************************************************************************/
#ifndef MAME_CPU_H8_H8_TIMER16_H
@ -147,6 +146,12 @@ public:
virtual ~h8325_timer16_channel_device();
uint16_t ocra_r() { return tgr_r(0); }
void ocra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) { tgr_w(0, data, mem_mask); }
uint16_t ocrb_r() { return tgr_r(1); }
void ocrb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) { tgr_w(1, data, mem_mask); }
uint16_t icr_r() { return tgr_r(2); }
protected:
virtual void tcr_update() override;
virtual void isr_update(uint8_t value) override;

12
src/devices/cpu/h8/h8_timer8.cpp
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@ -1,5 +1,17 @@
// license:BSD-3-Clause
// copyright-holders:Olivier Galibert
/***************************************************************************
h8_timer8.cpp
H8 8 bits timer
TODO:
- IRQs are level triggered? eg. when an interrupt enable flag gets set
while an overflow or compare match flag is 1, will it trigger an IRQ?
***************************************************************************/
#include "emu.h"
#include "h8_timer8.h"

1
src/devices/cpu/h8/h8_timer8.h
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@ -6,7 +6,6 @@
H8 8 bits timer
***************************************************************************/
#ifndef MAME_CPU_H8_H8_TIMER8_H

13
src/mame/saitek/prisma.cpp
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@ -14,8 +14,9 @@ Hardware notes:
It was also sold by Tandy as Chess Champion 2150L, with a slower CPU (16MHz XTAL).
TODO:
- does not work, it's unresponsive and will lock up after pressing buttons
(hold S to boot it up for now, that's not how it's supposed to be)
- does not work, it's unresponsive and will lock up after pressing buttons, irq
or opcode bug? (hold S to boot it up for now, that's not how it's supposed to be)
- add nvram, should be internal to H8, but it's missing standby emulation
- everything else
*******************************************************************************/
@ -173,7 +174,7 @@ u8 prisma_state::p5_r()
// P53: battery status
data |= m_inputs[3]->read() << 3;
return (data ^ 7) | 0xf0;
return ~data | 0xf0;
}
void prisma_state::p5_w(u8 data)
@ -249,9 +250,9 @@ static INPUT_PORTS_START( prisma )
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_K) // +
PORT_START("IN.3")
PORT_CONFNAME( 0x01, 0x00, "Battery Status" )
PORT_CONFSETTING( 0x01, "Low" )
PORT_CONFSETTING( 0x00, DEF_STR( Normal ) )
PORT_CONFNAME( 0x01, 0x01, "Battery Status" )
PORT_CONFSETTING( 0x00, "Low" )
PORT_CONFSETTING( 0x01, DEF_STR( Normal ) )
INPUT_PORTS_END