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https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
cmmb: some minor investigation. game is super weird. (nw)
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@ -17,10 +17,13 @@ TODO:
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- finish video emulation;
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- trackball inputs
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- sound;
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- NVRAM (EEPROM) at U8 or U11 on PCB
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- NVRAM (flash ROM, as per NVRAM test at 0xC2A7).
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- untangle switch-cases for inputs;
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- Is the W65C02S the same as the 65SC02 core or are there any
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extra Op-codes & addressing modes?
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- One bit of the control register seems to want to bank the flash into 2000-7FFF
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which would require bankdev if verified.
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- IRQ handler is super-strange, it wants to JMP ($7FFE) and JMP ($3FFE) a lot,
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which currently sends the game off into the weeds.
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- In fact, the game goes off into the weeds anyway right now due to doing that.
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Probably on the CPLD (CY39100V208B) - Quoted from Cosmodog's website:
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"Instead, we used a programmable chip that we could reconfigure very
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@ -80,6 +83,16 @@ public:
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DECLARE_WRITE8_MEMBER(flash_dbg_0_w);
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DECLARE_WRITE8_MEMBER(flash_dbg_1_w);
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DECLARE_WRITE8_MEMBER(irq_ack_w)
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{
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m_maincpu->set_input_line(0, CLEAR_LINE);
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}
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DECLARE_WRITE8_MEMBER(irq_enable_w)
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{
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m_irq_mask = data & 0x80;
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}
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//DECLARE_READ8_MEMBER(kludge_r);
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virtual void machine_reset() override;
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virtual void video_start() override;
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@ -159,7 +172,9 @@ WRITE8_MEMBER(cmmb_state::cmmb_output_w)
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// m_irq_mask = data & 0x80;
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break;
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case 0x02:
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// bit 7 toggled - watchdog/eeprom?
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// bit 7 toggled - watchdog or status LED
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// toggled by code at E3DB in IRQ handler - it's on when the frame count & 0x30 is 1 and off otherwise
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// bit 6 set means accessing flash ROM, possibly that entire 2000-7FFF banks over to the flash?
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break;
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case 0x03:
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@ -197,16 +212,19 @@ static ADDRESS_MAP_START( cmmb_map, AS_PROGRAM, 8, cmmb_state )
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AM_RANGE(0x2001, 0x2001) AM_READ_PORT("IN4")
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AM_RANGE(0x2011, 0x2011) AM_READ_PORT("IN5")
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AM_RANGE(0x2480, 0x249f) AM_RAM_DEVWRITE("palette", palette_device, write8) AM_SHARE("palette")
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AM_RANGE(0x2505, 0x2505) AM_WRITE(irq_enable_w)
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AM_RANGE(0x2600, 0x2600) AM_WRITE(irq_ack_w)
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//AM_RANGE(0x4000, 0x400f) AM_READWRITE(cmmb_input_r,cmmb_output_w)
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//AM_RANGE(0x4900, 0x4900) AM_READ(kludge_r)
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AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
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AM_RANGE(0x8000, 0xffff) AM_ROM
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AM_RANGE(0x8000, 0x9fff) AM_ROM AM_REGION("maincpu", 0x18000)
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AM_RANGE(0xa000, 0xafff) AM_RAM
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AM_RANGE(0xb000, 0xbfff) AM_READWRITE(cmmb_charram_r,cmmb_charram_w)
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AM_RANGE(0xc000, 0xc00f) AM_READWRITE(cmmb_input_r,cmmb_output_w)
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// debugging, to be removed
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AM_RANGE(0x2aaa, 0x2aaa) AM_WRITE(flash_dbg_0_w)
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AM_RANGE(0x5555, 0x5555) AM_WRITE(flash_dbg_1_w)
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// AM_RANGE(0x2aaa, 0x2aaa) AM_WRITE(flash_dbg_0_w)
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// AM_RANGE(0x5555, 0x5555) AM_WRITE(flash_dbg_1_w)
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AM_RANGE(0xc010, 0xffff) AM_ROM AM_REGION("maincpu", 0x1c010)
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ADDRESS_MAP_END
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@ -373,12 +391,17 @@ GFXDECODE_END
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INTERRUPT_GEN_MEMBER(cmmb_state::vblank_irq)
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{
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// if(machine().input().code_pressed_once(KEYCODE_Z))
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// device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
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#if 0
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if (m_irq_mask & 0x80)
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{
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m_maincpu->set_input_line(0, ASSERT_LINE);
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}
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#endif
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}
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void cmmb_state::machine_reset()
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{
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m_irq_mask = 0;
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}
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@ -419,7 +442,8 @@ ROM_START( cmmb162 )
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ROM_REGION( 0x50000, "maincpu", 0 )
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ROM_LOAD( "cmmb162.u2", 0x10000, 0x40000, CRC(71a5a75d) SHA1(0ad7b97580082cda98cb1e8aab8efcf491d0ed25) )
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ROM_COPY( "maincpu", 0x18000, 0x08000, 0x08000 )
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ROM_FILL( 0x0c124, 2, 0xea ) // temporary patch, how irqs works for this?
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ROM_FILL( 0x1c124, 2, 0xea ) // temporary patch to avoid waiting on IRQs
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ROM_FILL( 0x1e3c3, 3, 0xea ) // patch out weird IRQ handler code that causes reboot each IRQ
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ROM_REGION( 0x1000, "gfx", ROMREGION_ERASE00 )
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ROM_END
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