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Fix for regressions (no whatsnew)

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This commit is contained in:
Miodrag Milanovic 2012-10-04 10:40:45 +00:00
parent b4525a2cf3
commit 64c8feb6ad
3 changed files with 5 additions and 5 deletions
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2
src/mess/drivers/bw12.c
View File

@ -543,7 +543,7 @@ static Z80DART_INTERFACE( sio_intf )
WRITE_LINE_MEMBER(bw12_state::pit_out0_w)
{
device_t *device = machine().device("DEVCB_DRIVER_LINE_MEMBER(Z80SIO_TAG, bw12_state,pit_out0_w)");
device_t *device = machine().device(Z80SIO_TAG);
z80dart_txca_w(device, state);
z80dart_rxca_w(device, state);
}

2
src/mess/drivers/v1050.c
View File

@ -598,7 +598,7 @@ WRITE_LINE_MEMBER(v1050_state::pic_int_w)
{
if (state == ASSERT_LINE)
{
execute().set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
machine().device(Z80_TAG)->execute().set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
}
}

6
src/mess/machine/compis.c
View File

@ -1302,9 +1302,9 @@ static void compis_cpu_init(running_machine &machine)
state->m_i186.timer[0].int_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(compis_state::internal_timer_int),state));
state->m_i186.timer[1].int_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(compis_state::internal_timer_int),state));
state->m_i186.timer[2].int_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(compis_state::internal_timer_int),state));
state->m_i186.timer[0].time_timer = machine.scheduler().timer_alloc(timer_expired_delegate());
state->m_i186.timer[1].time_timer = machine.scheduler().timer_alloc(timer_expired_delegate());
state->m_i186.timer[2].time_timer = machine.scheduler().timer_alloc(timer_expired_delegate());
state->m_i186.timer[0].time_timer = machine.scheduler().timer_alloc(FUNC_NULL);
state->m_i186.timer[1].time_timer = machine.scheduler().timer_alloc(FUNC_NULL);
state->m_i186.timer[2].time_timer = machine.scheduler().timer_alloc(FUNC_NULL);
state->m_i186.dma[0].finish_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(compis_state::dma_timer_callback),state));
state->m_i186.dma[1].finish_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(compis_state::dma_timer_callback),state));
}