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unidasm: Add Interdata Series 16 disassembler
This commit is contained in:
AJR
parent
fa4ea8e951
commit
6543248641
@ -3778,3 +3778,13 @@ if opt_tool(CPUS, "NOVA") then
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table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/nova/novadasm.cpp")
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table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/nova/novadasm.h")
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end
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--------------------------------------------------
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-- Interdata Series 16, disassembler only
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--@src/devices/cpu/interdata16/interdata16.h,CPUS["INTERDATA16"] = true
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--------------------------------------------------
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if opt_tool(CPUS, "INTERDATA16") then
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table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/interdata16/dasm16.cpp")
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table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/interdata16/dasm16.h")
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end
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428
src/devices/cpu/interdata16/dasm16.cpp
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428
src/devices/cpu/interdata16/dasm16.cpp
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@ -0,0 +1,428 @@
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// license:BSD-3-Clause
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// copyright-holders:AJR
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/***************************************************************************
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Interdata/Perkin-Elmer Series 16 disassembler
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The instrution set supported here is that of the Model 8/16E Processor,
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which is backward-compatible with practically all of its predecessors.
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Only SETM(R) and the double-precision floating point instructions were
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relatively late additions to the 16-bit architecture; most others were
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supported as least as far back as the Model 5 (1970), though
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multiply/divide and floating point support were optional on a few
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subsequent models. Interdata's first-generation Models 3 & 4 lacked
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short-form instructions and list processing, which likely made these
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processors incompatible with most later software.
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Not supported here are the unique instruction set of the low-end
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Model 1, the unusual extended instructions provided on some Model 4 and
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Model 50 configurations, or the only partially compatible instruction
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set and extended addressing modes of Interdata's 32-bit series.
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***************************************************************************/
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#include "emu.h"
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#include "dasm16.h"
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interdata16_disassembler::interdata16_disassembler()
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: util::disasm_interface()
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{
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}
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u32 interdata16_disassembler::opcode_alignment() const
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{
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return 2;
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}
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namespace {
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static constexpr offs_t STEP_COND = interdata16_disassembler::STEP_COND;
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static constexpr offs_t STEP_OVER = interdata16_disassembler::STEP_OVER;
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static constexpr offs_t STEP_OUT = interdata16_disassembler::STEP_OUT;
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using namespace std::literals;
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static const std::pair<std::string_view, offs_t> s_inst_table[0x100] =
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{
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// 00-0F
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{ {}, 0 },
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{ "BALR"sv, STEP_OVER },
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{ "BTCR"sv, STEP_COND },
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{ "BFCR"sv, STEP_COND },
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{ "NHR"sv, 0 },
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{ "CLHR"sv, 0 },
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{ "OHR"sv, 0 },
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{ "XHR"sv, 0 },
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{ "LHR"sv, 0 },
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{ "CHR"sv, 0 },
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{ "AHR"sv, 0 },
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{ "SHR"sv, 0 },
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{ "MHR"sv, 0 },
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{ "DHR"sv, 0 },
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{ "ACHR"sv, 0 },
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{ "SCHR"sv, 0 },
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// 10-1F
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "SETMR"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// 20-2F
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{ "BTBS"sv, STEP_COND },
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{ "BTFS"sv, STEP_COND },
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{ "BFBS"sv, STEP_COND },
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{ "BFFS"sv, STEP_COND },
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{ "LIS"sv, 0 },
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{ "LCS"sv, 0 },
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{ "AIS"sv, 0 },
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{ "SIS"sv, 0 },
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{ "LER"sv, 0 },
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{ "CER"sv, 0 },
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{ "AER"sv, 0 },
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{ "SER"sv, 0 },
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{ "MER"sv, 0 },
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{ "DER"sv, 0 },
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{ "FXR"sv, 0 },
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{ "FLR"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "LPSR"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "LDR"sv, 0 },
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{ "CDR"sv, 0 },
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{ "ADR"sv, 0 },
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{ "SDR"sv, 0 },
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{ "MDR"sv, 0 },
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{ "DDR"sv, 0 },
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{ "FXDR"sv, 0 },
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{ "FLDR"sv, 0 },
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// 40-4F
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{ "STH"sv, 0 },
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{ "BAL"sv, STEP_OVER },
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{ "BTC"sv, STEP_COND },
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{ "BFC"sv, STEP_COND },
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{ "NH"sv, 0 },
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{ "CLH"sv, 0 },
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{ "OH"sv, 0 },
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{ "XH"sv, 0 },
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{ "LH"sv, 0 },
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{ "CH"sv, 0 },
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{ "AH"sv, 0 },
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{ "SH"sv, 0 },
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{ "MH"sv, 0 },
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{ "DH"sv, 0 },
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{ "ACH"sv, 0 },
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{ "SCH"sv, 0 },
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// 50-5F
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "SETM"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// 60-6F
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{ "STE"sv, 0 },
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{ "AHM"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "ATL"sv, 0 },
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{ "ABL"sv, 0 },
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{ "RTL"sv, 0 },
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{ "RBL"sv, 0 },
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{ "LE"sv, 0 },
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{ "CE"sv, 0 },
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{ "AE"sv, 0 },
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{ "SE"sv, 0 },
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{ "ME"sv, 0 },
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{ "DE"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// 70-7F
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{ "STD"sv, 0 },
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{ "STME"sv, 0 },
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{ "LME", 0 },
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{ "LPS", 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "LD"sv, 0 },
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{ "CD"sv, 0 },
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{ "AD"sv, 0 },
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{ "SD"sv, 0 },
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{ "MD"sv, 0 },
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{ "DD"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// 80-8F
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// 90-9F
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{ "SRLS"sv, 0 },
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{ "SLLS"sv, 0 },
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{ "STBR"sv, 0 },
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{ "LBR"sv, 0 },
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{ "EXBR"sv, 0 },
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{ "EPSR"sv, 0 },
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{ "WBR"sv, 0 },
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{ "RBR"sv, 0 },
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{ "WHR"sv, 0 },
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{ "RHR"sv, 0 },
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{ "WDR"sv, 0 },
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{ "RDR"sv, 0 },
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{ "MHUR"sv, 0 },
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{ "SSR"sv, 0 },
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{ "OCR"sv, 0 },
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{ "AIR"sv, 0 },
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// A0-AF
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// B0-BF
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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// C0-CF
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{ "BXH"sv, 0 },
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{ "BXLE"sv, 0 },
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{ "LPSW"sv, STEP_OUT },
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{ "THI"sv, 0 },
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{ "NHI"sv, 0 },
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{ "CLHI"sv, 0 },
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{ "OHI"sv, 0 },
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{ "XHI"sv, 0 },
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{ "LHI"sv, 0 },
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{ "CHI"sv, 0 },
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{ "AHI"sv, 0 },
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{ "SHI"sv, 0 },
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{ "SRHL"sv, 0 },
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{ "SLHL"sv, 0 },
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{ "SRHA"sv, 0 },
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{ "SLHA"sv, 0 },
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// D0-DF
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{ "STM"sv, 0 },
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{ "LM"sv, 0 },
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{ "STB"sv, 0 },
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{ "LB"sv, 0 },
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{ "CLB"sv, 0 },
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{ "AL"sv, 0 },
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{ "WB"sv, 0 },
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{ "RB"sv, 0 },
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{ "WH"sv, 0 },
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{ "RH"sv, 0 },
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{ "WD"sv, 0 },
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{ "RD"sv, 0 },
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{ "MHU"sv, 0 },
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{ "SS"sv, 0 },
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{ "OC"sv, 0 },
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{ "AI"sv, 0 },
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// E0-EF
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{ {}, 0 },
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{ "SVC"sv, STEP_OVER },
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{ "SINT"sv, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ "RRL"sv, 0 },
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{ "RLL"sv, 0 },
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{ "SRL"sv, 0 },
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{ "SLL"sv, 0 },
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{ "SRA"sv, 0 },
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{ "SLA"sv, 0 },
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// F0-FF
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 },
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{ {}, 0 }
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};
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static const std::string_view s_b_mnemonics[32] =
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{
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"NOP"sv, "BM"sv, "BP"sv, "BNZ"sv, "BO"sv, {}, {}, {}, "BC"sv, {}, {}, {}, {}, {}, {}, {},
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"B"sv, "BNM"sv, "BNP"sv, "BZ"sv, "BNO"sv, {}, {}, {}, "BNC"sv, {}, {}, {}, {}, {}, {}, {}
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};
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} // anonymous namespace
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void interdata16_disassembler::format_s16(std::ostream &stream, s16 halfword)
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{
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if (halfword < 0)
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{
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stream << '-';
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halfword = -halfword;
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}
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if (u16(halfword) <= 9)
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util::stream_format(stream, "%d", halfword);
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else
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util::stream_format(stream, "X'%X'", u16(halfword));
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}
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offs_t interdata16_disassembler::disassemble(std::ostream &stream, offs_t pc, const interdata16_disassembler::data_buffer &opcodes, const interdata16_disassembler::data_buffer ¶ms)
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{
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const u16 i = opcodes.r16(pc);
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auto const inst = s_inst_table[BIT(i, 8, 8)];
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offs_t flags = inst.second;
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if (inst.first.empty())
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{
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// Illegal opcodes
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util::stream_format(stream, "%-6sX'%04X'", "DC", i);
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return 2 | SUPPORTED;
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}
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else if ((i & 0xfc00) == 0x2000)
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{
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// Short conditional branches
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const std::string_view bm = s_b_mnemonics[(i & 0x0200) >> 5 | (i & 0x00f0) >> 4];
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if (!bm.empty())
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util::stream_format(stream, "%-6sX'%04X'", util::string_format("%sS", bm), (BIT(i, 8) ? pc + BIT(i, 0, 4) * 2 : pc - BIT(i, 0, 4) * 2) & 0xffff);
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else
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util::stream_format(stream, "%-6s%d,%d", inst.first, BIT(i, 4, 4), BIT(i, 0, 4));
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if (BIT(i, 4, 4) == 0)
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flags = 0;
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return 2 | flags | SUPPORTED;
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}
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else
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{
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if ((i & 0xbe00) == 0x0200)
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{
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// Conditional branches
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const std::string_view bm = s_b_mnemonics[BIT(i, 4, 5)];
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if (!bm.empty())
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{
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if (BIT(i, 14))
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util::stream_format(stream, "%-6s", bm);
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else
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util::stream_format(stream, "%-6s", util::string_format("%sR", bm));
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if (BIT(i, 4, 4) == 0)
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flags = 0;
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}
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else
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util::stream_format(stream, "%-6s%d,", inst.first, BIT(i, 4, 4));
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}
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else if ((i & 0xbf00) == 0x3300 || (i & 0xdf00) == 0xc200 || (i & 0xff00) == 0xd500) // LPS(R), LPSW, SINT, AL
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util::stream_format(stream, "%-6s", inst.first, BIT(i, 4, 4));
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else if ((i & 0xff00) == 0xe100) // SVC
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util::stream_format(stream, "%-6s%d,", inst.first, BIT(i, 4, 4));
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else
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util::stream_format(stream, "%-6sR%d,", inst.first, BIT(i, 4, 4));
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if (BIT(i, 14))
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{
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// RX or RI
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if (BIT(i, 0, 4) != 0)
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{
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format_s16(stream, opcodes.r16(pc + 2));
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util::stream_format(stream, "(R%d)", BIT(i, 0, 4));
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}
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else if ((i >= 0xc900 && i < 0xd000) || i >= 0xea00)
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format_s16(stream, opcodes.r16(pc + 2));
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else
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util::stream_format(stream, "X'%04X'", opcodes.r16(pc + 2));
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return 4 | flags | SUPPORTED;
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}
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else
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{
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// RR or SF
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if ((i & 0xf800) == 0x2000 || (i & 0xfe00) == 0x9000)
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util::stream_format(stream, "%d", BIT(i, 0, 4));
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else
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util::stream_format(stream, "R%d", BIT(i, 0, 4));
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return 2 | flags | SUPPORTED;
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}
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}
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}
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25
src/devices/cpu/interdata16/dasm16.h
Normal file
25
src/devices/cpu/interdata16/dasm16.h
Normal file
@ -0,0 +1,25 @@
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// license:BSD-3-Clause
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// copyright-holders:AJR
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#ifndef MAME_CPU_INTERDATA16_DASM16_H
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#define MAME_CPU_INTERDATA16_DASM16_H
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#pragma once
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class interdata16_disassembler : public util::disasm_interface
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{
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public:
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// construction/destruction
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interdata16_disassembler();
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protected:
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// util::disasm_interface overrides
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virtual u32 opcode_alignment() const override;
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virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override;
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private:
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// formatting helpers
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static void format_s16(std::ostream &stream, s16 halfword);
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};
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#endif // MAME_CPU_INTERDATA16_DASM16_H
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@ -76,6 +76,7 @@ using util::BIT;
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#include "cpu/i960/i960dis.h"
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#include "cpu/ibm1800/ibm1800d.h"
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#include "cpu/ie15/ie15dasm.h"
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#include "cpu/interdata16/dasm16.h"
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#include "cpu/jaguar/jagdasm.h"
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#include "cpu/ks0164/ks0164d.h"
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#include "cpu/lc57/lc57d.h"
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@ -484,6 +485,7 @@ static const dasm_table_entry dasm_table[] =
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||||
{ "ibm1130", be, -1, []() -> util::disasm_interface * { return new ibm1130_disassembler; } },
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||||
{ "ibm1800", be, -1, []() -> util::disasm_interface * { return new ibm1800_disassembler; } },
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{ "ie15", le, 0, []() -> util::disasm_interface * { return new ie15_disassembler; } },
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||||
{ "interdata16", be, 0, []() -> util::disasm_interface * { return new interdata16_disassembler; } },
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{ "jaguardsp", be, 0, []() -> util::disasm_interface * { return new jaguar_disassembler(jaguar_disassembler::variant::DSP); } },
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{ "jaguargpu", be, 0, []() -> util::disasm_interface * { return new jaguar_disassembler(jaguar_disassembler::variant::GPU); } },
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||||
{ "konami", be, 0, []() -> util::disasm_interface * { return new konami_disassembler; } },
|
||||
|
||||
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Reference in New Issue
Block a user