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srcclean (nw)
This commit is contained in:
parent
482cb17d57
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hash/gba.xml
66
hash/gba.xml
@ -1,4 +1,4 @@
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<?xml version="1.0"?>
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<?xml version="1.0"?>
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<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
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<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
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<softwarelist name="gba" description="Nintendo Game Boy Advance cartridges">
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<softwarelist name="gba" description="Nintendo Game Boy Advance cartridges">
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@ -3525,7 +3525,7 @@
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</software>
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</software>
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (a figurine)
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (a figurine)
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contains just press different switches on the cradle to be readed as a simple ID (the toys constains no electronics). -->
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contains just press different switches on the cradle to be readed as a simple ID (the toys constains no electronics). -->
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<software name="plustw">
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<software name="plustw">
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<description>Bouken Yuuki Pluster World - Densetsu no Plust Gate (Jpn)</description>
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<description>Bouken Yuuki Pluster World - Densetsu no Plust Gate (Jpn)</description>
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<year>2003</year>
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<year>2003</year>
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@ -3548,7 +3548,7 @@
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</software>
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</software>
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (a figurine)
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (a figurine)
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contains just press different switches on the cradle to be readed as a simple ID (the toys constains no electronics). -->
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contains just press different switches on the cradle to be readed as a simple ID (the toys constains no electronics). -->
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<software name="plustwex">
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<software name="plustwex">
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<description>Bouken Yuuki Pluster World - Densetsu no Plust Gate EX (Jpn)</description>
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<description>Bouken Yuuki Pluster World - Densetsu no Plust Gate EX (Jpn)</description>
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<year>2003</year>
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<year>2003</year>
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@ -3568,7 +3568,7 @@
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</software>
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</software>
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (a figurine)
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (a figurine)
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contains just press different switches on the cradle to be readed as a simple ID (the toys constains no electronics). -->
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contains just press different switches on the cradle to be readed as a simple ID (the toys constains no electronics). -->
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<software name="plustwgp">
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<software name="plustwgp">
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<description>Bouken Yuuki Pluster World - Pluston GP (Jpn)</description>
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<description>Bouken Yuuki Pluster World - Pluston GP (Jpn)</description>
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<year>2003</year>
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<year>2003</year>
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@ -6302,7 +6302,7 @@
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</software>
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</software>
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<!-- This games uses the GBA IR adapter (Nintendo P/N AGB-006) to connect to real Zoids toys.
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<!-- This games uses the GBA IR adapter (Nintendo P/N AGB-006) to connect to real Zoids toys.
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Two toys supported: CDZ-01 (Diablotiger) and CDZ-02 (Cyclops). -->
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Two toys supported: CDZ-01 (Diablotiger) and CDZ-02 (Cyclops). -->
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<software name="cybzoids">
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<software name="cybzoids">
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<description>Cyberdrive Zoids - Kijuu no Senshi Hyuu (Jpn)</description>
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<description>Cyberdrive Zoids - Kijuu no Senshi Hyuu (Jpn)</description>
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<year>2003</year>
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<year>2003</year>
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@ -16534,7 +16534,7 @@
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</software>
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</software>
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<!-- Telefang 2 is compatible with an accessory called "Power Antenna" (just like the GBC version). The "Power Antenna" is just a led light connected
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<!-- Telefang 2 is compatible with an accessory called "Power Antenna" (just like the GBC version). The "Power Antenna" is just a led light connected
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to the GBA accessories port. -->
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to the GBA accessories port. -->
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<software name="telfng2p">
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<software name="telfng2p">
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<description>Keitai Denjuu Telefang 2 - Power (Jpn)</description>
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<description>Keitai Denjuu Telefang 2 - Power (Jpn)</description>
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<year>2002</year>
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<year>2002</year>
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@ -18181,7 +18181,7 @@
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</software>
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</software>
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (shaped like a crystal with a frozen monster inside)
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (shaped like a crystal with a frozen monster inside)
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contains a serial EEPROM (probably with an ID and some data the game can read and write). -->
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contains a serial EEPROM (probably with an ID and some data the game can read and write). -->
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<software name="legendzs">
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<software name="legendzs">
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<description>Legendz - Sign of Nekuromu (Jpn)</description>
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<description>Legendz - Sign of Nekuromu (Jpn)</description>
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<year>2005</year>
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<year>2005</year>
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@ -18203,7 +18203,7 @@
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</software>
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</software>
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (shaped like a crystal with a frozen monster inside)
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<!-- This game supports interacting with real toys (using a cradle/reader connected to the GBA accessories port). Each toy (shaped like a crystal with a frozen monster inside)
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contains a serial EEPROM (probably with an ID and some data the game can read and write). -->
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contains a serial EEPROM (probably with an ID and some data the game can read and write). -->
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<software name="legendzy">
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<software name="legendzy">
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<description>Legendz - Yomigaeru Shiren no Shima (Jpn)</description>
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<description>Legendz - Yomigaeru Shiren no Shima (Jpn)</description>
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<year>2004</year>
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<year>2004</year>
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@ -27877,9 +27877,9 @@
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</part>
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</part>
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</software>
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</software>
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<!-- Compatible with "Battle Chips" (using the "Battle Chip Gate" (バトルチップゲート) connected to the GBA accessories port).
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<!-- Compatible with "Battle Chips" (using the "Battle Chip Gate" (バトルチップゲート) connected to the GBA accessories port).
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A Battle Chip looks like a memory card, but contains no memory, it's just an ID by shortcutting different pins on its edge connector.
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A Battle Chip looks like a memory card, but contains no memory, it's just an ID by shortcutting different pins on its edge connector.
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https://megaman.fandom.com/wiki/List_of_Advanced_PET_Battle_Chips -->
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https://megaman.fandom.com/wiki/List_of_Advanced_PET_Battle_Chips -->
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<software name="rockmx45">
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<software name="rockmx45">
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<description>Rockman EXE 4.5 - Real Operation (Jpn)</description>
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<description>Rockman EXE 4.5 - Real Operation (Jpn)</description>
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<year>2004</year>
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<year>2004</year>
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@ -29284,7 +29284,7 @@
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</dataarea>
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</dataarea>
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</part>
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</part>
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</software>
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</software>
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<!-- This game has an integrated UV sensor (AGB-013). -->
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<!-- This game has an integrated UV sensor (AGB-013). -->
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<software name="sboktai">
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<software name="sboktai">
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<description>Shin Bokura no Taiyou - Gyakushuu no Sabata (Jpn)</description>
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<description>Shin Bokura no Taiyou - Gyakushuu no Sabata (Jpn)</description>
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@ -30516,8 +30516,8 @@
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</part>
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</part>
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</software>
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</software>
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<!-- This comes from a proto cart: it is mostly similar to the final release, with single byte differences
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<!-- This comes from a proto cart: it is mostly similar to the final release, with single byte differences
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The cart also contained a non-empty SRAM save which we currently include in the set, even if we don't load it. -->
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The cart also contained a non-empty SRAM save which we currently include in the set, even if we don't load it. -->
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<software name="sonicup" cloneof="sonic" supported="partial">
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<software name="sonicup" cloneof="sonic" supported="partial">
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<description>Sonic Advance (USA, Prototype)</description>
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<description>Sonic Advance (USA, Prototype)</description>
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<year>2002</year>
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<year>2002</year>
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@ -36256,7 +36256,7 @@ The cart also contained a non-empty SRAM save which we currently include in the
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</software>
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</software>
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<!-- Game with rumble and gyroscope (AGB-019A).
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<!-- Game with rumble and gyroscope (AGB-019A).
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Has a sub-board (AGB-MOG-01) with "U1 CG-L43" (miniature angular rate sensor: https://4donline.ihs.com/images/VipMasterIC/IC/TOKN/TOKND00194/TOKND00194-23.pdf) -->
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Has a sub-board (AGB-MOG-01) with "U1 CG-L43" (miniature angular rate sensor: https://4donline.ihs.com/images/VipMasterIC/IC/TOKN/TOKND00194/TOKND00194-23.pdf) -->
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<software name="wariotws">
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<software name="wariotws">
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<description>WarioWare - Twisted! (USA)</description>
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<description>WarioWare - Twisted! (USA)</description>
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<year>2005</year>
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<year>2005</year>
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@ -39911,16 +39911,16 @@ The cart also contained a non-empty SRAM save which we currently include in the
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<!-- Misc Add-ons -->
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<!-- Misc Add-ons -->
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<!-- "Tony Hawk's Motion" for Nintendo DS uses an accessory called "Motion Pack" (Activision Part No. 83493.133) in form of GBA cart.
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<!-- "Tony Hawk's Motion" for Nintendo DS uses an accessory called "Motion Pack" (Activision Part No. 83493.133) in form of GBA cart.
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It serves as motion sensor. Its inside PCB is labeled "DS-2011 R1.2" and contains:
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It serves as motion sensor. Its inside PCB is labeled "DS-2011 R1.2" and contains:
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* Kionix KXSC4 high-performance, low-power, analog output tri-axis accelerometer (http://kionixfs.kionix.com/en/datasheet/KXSC4-2050%20Specifications%20Rev%203.pdf).
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* Kionix KXSC4 high-performance, low-power, analog output tri-axis accelerometer (http://kionixfs.kionix.com/en/datasheet/KXSC4-2050%20Specifications%20Rev%203.pdf).
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* Atmel TINY13V high Performance, Low Power AVR 8-Bit RISC Microcontroller [ROM not dumped] (http://ww1.microchip.com/downloads/en/devicedoc/doc2535.pdf) -->
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* Atmel TINY13V high Performance, Low Power AVR 8-Bit RISC Microcontroller [ROM not dumped] (http://ww1.microchip.com/downloads/en/devicedoc/doc2535.pdf) -->
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<!-- "Daigasso Band Brothers" (大合奏!バンドブラザーズ) for Nintendo DS uses a GBA cart (NTR-A-ZBBJ-JPN) called "Daigasso Request Selection" for adding new songs to the game.
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<!-- "Daigasso Band Brothers" (大合奏!バンドブラザーズ) for Nintendo DS uses a GBA cart (NTR-A-ZBBJ-JPN) called "Daigasso Request Selection" for adding new songs to the game.
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Inside there is an standard "AGB-E01-41" GBA cart PCB with "U1=GPIO MASK ROM [R27V810F-064]". -->
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Inside there is an standard "AGB-E01-41" GBA cart PCB with "U1=GPIO MASK ROM [R27V810F-064]". -->
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<!-- AM3 did a Nintendo officially lilcensed video player for GBA in form of a GBA cart with a SmartMedia slot.
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<!-- AM3 did a Nintendo officially lilcensed video player for GBA in form of a GBA cart with a SmartMedia slot.
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There were lot of pre-recorded SmartMedia cards with videos (Pokémon, Detective Conan, etc.), but also kiosk machines to download new videos to an empty card.
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There were lot of pre-recorded SmartMedia cards with videos (Pokémon, Detective Conan, etc.), but also kiosk machines to download new videos to an empty card.
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Inside this GBA cart the PCB is labeled "YGP2-AM1-01". The ROM and the video processor are behind the SmartMedia slot, but the label "U3 AM3-ASIC" is visible. -->
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Inside this GBA cart the PCB is labeled "YGP2-AM1-01". The ROM and the video processor are behind the SmartMedia slot, but the label "U3 AM3-ASIC" is visible. -->
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<software name="gbapo" supported="no">
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<software name="gbapo" supported="no">
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@ -40011,18 +40011,18 @@ The cart also contained a non-empty SRAM save which we currently include in the
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</software>
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</software>
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<!-- The video playback can be configured by placing a file named "play_yanmicro.ini" on the SD root folder, with the following content:
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<!-- The video playback can be configured by placing a file named "play_yanmicro.ini" on the SD root folder, with the following content:
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Property Value
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Property Value
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PLAY_YAN_Design 0 (default, pictogram mode) or 1 (Mario mode).
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PLAY_YAN_Design 0 (default, pictogram mode) or 1 (Mario mode).
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PLAY_YAN_StartMode 0 (movie mode) or 1 (default, music mode).
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PLAY_YAN_StartMode 0 (movie mode) or 1 (default, music mode).
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PLAY_YAN_VolumeAdd Integer from -19 to 9 (default is 0).
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PLAY_YAN_VolumeAdd Integer from -19 to 9 (default is 0).
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PLAY_YAN_AudioPlayMode 0 (default, ordered list without repeat), 1 (ordered list with repeat), 2 (random without repeat) or 3 (random with repeat).
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PLAY_YAN_AudioPlayMode 0 (default, ordered list without repeat), 1 (ordered list with repeat), 2 (random without repeat) or 3 (random with repeat).
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PLAY_YAN_AudioBass 0 (default) or 1 (bass boost).
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PLAY_YAN_AudioBass 0 (default) or 1 (bass boost).
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PLAY_YAN_AudioWide Integer from 0 to 6 (being 0 no wide sound effect and 6 maximum wide sound efect).
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PLAY_YAN_AudioWide Integer from 0 to 6 (being 0 no wide sound effect and 6 maximum wide sound efect).
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PLAY_YAN_VideoPlayMode 0 (default, single video playback), 1 (repeat over the selection video list), 2 (play all the stored video clips) or 3 (play all the stored video clips, with repeat).
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PLAY_YAN_VideoPlayMode 0 (default, single video playback), 1 (repeat over the selection video list), 2 (play all the stored video clips) or 3 (play all the stored video clips, with repeat).
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PLAY_YAN_VideoBright Integer from 0 to 5 (being 0 the default brightness value, and 6 the maximum brightness).
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PLAY_YAN_VideoBright Integer from 0 to 5 (being 0 the default brightness value, and 6 the maximum brightness).
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The game came bundled (on the deluxe edition) with Panasonic Media Stage 4.2 to allow users to encode their own videos.
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The game came bundled (on the deluxe edition) with Panasonic Media Stage 4.2 to allow users to encode their own videos.
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There was a free upgrade tp version V4.2L311 (https://panasonic.jp/support/software/mediastage/download/v42_nintendo.html).
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There was a free upgrade tp version V4.2L311 (https://panasonic.jp/support/software/mediastage/download/v42_nintendo.html).
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It supports SD cards up to 1GB (it won't recognize 2GB SD cards). -->
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It supports SD cards up to 1GB (it won't recognize 2GB SD cards). -->
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<software name="playyanm">
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<software name="playyanm">
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<description>Play-Yan Micro (Jpn)</description>
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<description>Play-Yan Micro (Jpn)</description>
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<year>2005</year>
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<year>2005</year>
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@ -1,4 +1,4 @@
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<?xml version="1.0"?>
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<?xml version="1.0"?>
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<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
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<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
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<!--
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<!--
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@ -9383,8 +9383,8 @@ Unreleased (music source code exists, possibly no prototypes exist)
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</software>
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</software>
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<software name="telefngp">
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<software name="telefngp">
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<!-- Notes: This game uses an accessory called "Power Antenna", which is just a LED light connected
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<!-- Notes: This game uses an accessory called "Power Antenna", which is just a LED light connected
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to the GB accessories port. It is used ingame to simulate a mobile phone. -->
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to the GB accessories port. It is used ingame to simulate a mobile phone. -->
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<description>Keitai Denjuu Telefang - Power Version (Jpn)</description>
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<description>Keitai Denjuu Telefang - Power Version (Jpn)</description>
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<year>2000</year>
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<year>2000</year>
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<publisher>Natsume</publisher>
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<publisher>Natsume</publisher>
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@ -12767,15 +12767,15 @@ Unreleased (music source code exists, possibly no prototypes exist)
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<software name="mobilglf">
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<software name="mobilglf">
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<!-- Notes: GBC only.
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<!-- Notes: GBC only.
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This game is compatible with the "Mobile System GB", a connected gaming system which uses an external adaptor
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This game is compatible with the "Mobile System GB", a connected gaming system which uses an external adaptor
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for connecting to a mobile phone (named "Mobile Adaptor GB" [CGB-005]) and then to an external server.
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for connecting to a mobile phone (named "Mobile Adaptor GB" [CGB-005]) and then to an external server.
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There are different models depending on the target cellular phone:
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There are different models depending on the target cellular phone:
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* Blue adapter can be used by the digital cellular phone terminal PDC. (MAX 9600bps)
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* Blue adapter can be used by the digital cellular phone terminal PDC. (MAX 9600bps)
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* Yellow adapter can be used by the CDMAOne portable telephone. (MAX 14.4kbps)
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* Yellow adapter can be used by the CDMAOne portable telephone. (MAX 14.4kbps)
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* Red adapter can be used by the DDI Pocket Telephone. (MAX 36.6kbps)
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* Red adapter can be used by the DDI Pocket Telephone. (MAX 36.6kbps)
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* Green adapter (unreleased) can be used by the PHS (Astel, NTT DoCoMo).
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* Green adapter (unreleased) can be used by the PHS (Astel, NTT DoCoMo).
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Internally, the "Mobile Adaptor GB" features a ML7060-01P ARM (internal ROM, if any, is undumped), and was
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Internally, the "Mobile Adaptor GB" features a ML7060-01P ARM (internal ROM, if any, is undumped), and was
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manufactured by Mitsumi. -->
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manufactured by Mitsumi. -->
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<description>Mobile Golf (Jpn)</description>
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<description>Mobile Golf (Jpn)</description>
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<year>2001</year>
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<year>2001</year>
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<publisher>Nintendo</publisher>
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<publisher>Nintendo</publisher>
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@ -12801,15 +12801,15 @@ Unreleased (music source code exists, possibly no prototypes exist)
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<!-- when it checks for the connection, it checks for a value of 06 in C27D -->
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<!-- when it checks for the connection, it checks for a value of 06 in C27D -->
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<software name="mobiltrn" supported="partial">
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<software name="mobiltrn" supported="partial">
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<!-- Notes: GBC only.
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<!-- Notes: GBC only.
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This game is compatible with the "Mobile System GB", a connected gaming system which uses an external adaptor
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This game is compatible with the "Mobile System GB", a connected gaming system which uses an external adaptor
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for connecting to a mobile phone (named "Mobile Adaptor GB" [CGB-005]) and then to an external server.
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for connecting to a mobile phone (named "Mobile Adaptor GB" [CGB-005]) and then to an external server.
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There are different models depending on the target cellular phone:
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There are different models depending on the target cellular phone:
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* Blue adapter can be used by the digital cellular phone terminal PDC. (MAX 9600bps)
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* Blue adapter can be used by the digital cellular phone terminal PDC. (MAX 9600bps)
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* Yellow adapter can be used by the CDMAOne portable telephone. (MAX 14.4kbps)
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* Yellow adapter can be used by the CDMAOne portable telephone. (MAX 14.4kbps)
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* Red adapter can be used by the DDI Pocket Telephone. (MAX 36.6kbps)
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* Red adapter can be used by the DDI Pocket Telephone. (MAX 36.6kbps)
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* Green adapter (unreleased) can be used by the PHS (Astel, NTT DoCoMo).
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* Green adapter (unreleased) can be used by the PHS (Astel, NTT DoCoMo).
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Internally, the "Mobile Adaptor GB" features a ML7060-01P ARM (internal ROM, if any, is undumped), and was
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Internally, the "Mobile Adaptor GB" features a ML7060-01P ARM (internal ROM, if any, is undumped), and was
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manufactured by Mitsumi. -->
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manufactured by Mitsumi. -->
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<description>Mobile Trainer (Jpn)</description>
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<description>Mobile Trainer (Jpn)</description>
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<year>2001</year>
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<year>2001</year>
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<publisher>Nintendo</publisher>
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<publisher>Nintendo</publisher>
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@ -13970,8 +13970,8 @@ Unreleased (music source code exists, possibly no prototypes exist)
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<software name="networka">
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<software name="networka">
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<!-- Notes: GBC only
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<!-- Notes: GBC only
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This game uses an accessory (same hardware as the Telefang "Power Antenna" but on differently shaped plastic case),
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This game uses an accessory (same hardware as the Telefang "Power Antenna" but on differently shaped plastic case),
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which is just a LED light connected to the GB accessories port. -->
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which is just a LED light connected to the GB accessories port. -->
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<description>Network Boukenki Bugsite - Alpha Version (Jpn)</description>
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<description>Network Boukenki Bugsite - Alpha Version (Jpn)</description>
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<year>2001</year>
|
<year>2001</year>
|
||||||
<publisher>Smilesoft</publisher>
|
<publisher>Smilesoft</publisher>
|
||||||
@ -13990,8 +13990,8 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
|
|
||||||
<software name="networkb">
|
<software name="networkb">
|
||||||
<!-- Notes: GBC only
|
<!-- Notes: GBC only
|
||||||
This game uses an accessory (same hardware as the Telefang "Power Antenna" but on differently shaped plastic case),
|
This game uses an accessory (same hardware as the Telefang "Power Antenna" but on differently shaped plastic case),
|
||||||
which is just a LED light connected to the GB accessories port. -->
|
which is just a LED light connected to the GB accessories port. -->
|
||||||
<description>Network Boukenki Bugsite - Beta Version (Jpn)</description>
|
<description>Network Boukenki Bugsite - Beta Version (Jpn)</description>
|
||||||
<year>2001</year>
|
<year>2001</year>
|
||||||
<publisher>Smilesoft</publisher>
|
<publisher>Smilesoft</publisher>
|
||||||
@ -14996,7 +14996,7 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
|
|
||||||
<software name="pockfam2">
|
<software name="pockfam2">
|
||||||
<!-- Notes: GBC only.
|
<!-- Notes: GBC only.
|
||||||
The game cart has an integrated speaker and a replaceable battery (CR2025). -->
|
The game cart has an integrated speaker and a replaceable battery (CR2025). -->
|
||||||
<description>Pocket Family GB2 (Jpn)</description>
|
<description>Pocket Family GB2 (Jpn)</description>
|
||||||
<year>1999</year>
|
<year>1999</year>
|
||||||
<publisher>Hudson Soft</publisher>
|
<publisher>Hudson Soft</publisher>
|
||||||
@ -15055,7 +15055,7 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="pockgtp" cloneof="pockrace">
|
<software name="pockgtp" cloneof="pockrace">
|
||||||
<description>Pocket GT (Eur, Prototype?)</description>
|
<description>Pocket GT (Eur, Prototype?)</description>
|
||||||
<year>1999</year>
|
<year>1999</year>
|
||||||
@ -15686,7 +15686,7 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
|
|
||||||
<software name="pokecardj" cloneof="pokecard">
|
<software name="pokecardj" cloneof="pokecard">
|
||||||
<!-- Notes: SGB enhanced.
|
<!-- Notes: SGB enhanced.
|
||||||
This game uses an integrated (on-cart) IR port por connected multiplayer gameplay. -->
|
This game uses an integrated (on-cart) IR port por connected multiplayer gameplay. -->
|
||||||
<description>Pokémon Card GB (Jpn)</description>
|
<description>Pokémon Card GB (Jpn)</description>
|
||||||
<year>1998</year>
|
<year>1998</year>
|
||||||
<publisher>Nintendo</publisher>
|
<publisher>Nintendo</publisher>
|
||||||
@ -17687,11 +17687,11 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="robopspc">
|
<software name="robopspc">
|
||||||
<!-- Notes: GBC only..
|
<!-- Notes: GBC only..
|
||||||
Supports "GBKiss". "GBKiss" is an integrated infrared port for cart-to-cart
|
Supports "GBKiss". "GBKiss" is an integrated infrared port for cart-to-cart
|
||||||
multiplayer play, but also for PC connection with the "GBKISS LINK" (Hudson Soft model No. HC-749), a parallel
|
multiplayer play, but also for PC connection with the "GBKISS LINK" (Hudson Soft model No. HC-749), a parallel
|
||||||
port (DB25) modem/adaptor for PC-DOS for transfering files between the game and a computer.
|
port (DB25) modem/adaptor for PC-DOS for transfering files between the game and a computer.
|
||||||
The cart also has an integrated speaker (conns PE1 and PE2 on the PCB). -->
|
The cart also has an integrated speaker (conns PE1 and PE2 on the PCB). -->
|
||||||
<description>Robot Ponkottsu - Comic Bom Bom Special Version (Jpn)</description>
|
<description>Robot Ponkottsu - Comic Bom Bom Special Version (Jpn)</description>
|
||||||
<year>1999?</year>
|
<year>1999?</year>
|
||||||
<publisher>Hudson Soft</publisher>
|
<publisher>Hudson Soft</publisher>
|
||||||
@ -17715,11 +17715,11 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="robopmon">
|
<software name="robopmon">
|
||||||
<!-- Notes: SGB enhanced.
|
<!-- Notes: SGB enhanced.
|
||||||
Supports "GBKiss". "GBKiss" is an integrated infrared port for cart-to-cart
|
Supports "GBKiss". "GBKiss" is an integrated infrared port for cart-to-cart
|
||||||
multiplayer play, but also for PC connection with the "GBKISS LINK" (Hudson Soft model No. HC-749), a parallel
|
multiplayer play, but also for PC connection with the "GBKISS LINK" (Hudson Soft model No. HC-749), a parallel
|
||||||
port (DB25) modem/adaptor for PC-DOS for transfering files between the game and a computer.
|
port (DB25) modem/adaptor for PC-DOS for transfering files between the game and a computer.
|
||||||
The cart also has an integrated speaker (conns PE1 and PE2 on the PCB). -->
|
The cart also has an integrated speaker (conns PE1 and PE2 on the PCB). -->
|
||||||
<description>Robot Ponkottsu - Moon Version (Jpn)</description>
|
<description>Robot Ponkottsu - Moon Version (Jpn)</description>
|
||||||
<year>1999</year>
|
<year>1999</year>
|
||||||
<publisher>Hudson Soft</publisher>
|
<publisher>Hudson Soft</publisher>
|
||||||
@ -17744,11 +17744,11 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="robopstr">
|
<software name="robopstr">
|
||||||
<!-- Notes: SGB enhanced.
|
<!-- Notes: SGB enhanced.
|
||||||
Supports "GBKiss". "GBKiss" is an integrated infrared port for cart-to-cart
|
Supports "GBKiss". "GBKiss" is an integrated infrared port for cart-to-cart
|
||||||
multiplayer play, but also for PC connection with the "GBKISS LINK" (Hudson Soft model No. HC-749), a parallel
|
multiplayer play, but also for PC connection with the "GBKISS LINK" (Hudson Soft model No. HC-749), a parallel
|
||||||
port (DB25) modem/adaptor for PC-DOS for transfering files between the game and a computer.
|
port (DB25) modem/adaptor for PC-DOS for transfering files between the game and a computer.
|
||||||
The cart also has an integrated speaker (conns PE1 and PE2 on the PCB). -->
|
The cart also has an integrated speaker (conns PE1 and PE2 on the PCB). -->
|
||||||
<description>Robot Ponkottsu - Star Version (Jpn)</description>
|
<description>Robot Ponkottsu - Star Version (Jpn)</description>
|
||||||
<year>1998</year>
|
<year>1998</year>
|
||||||
<publisher>Hudson Soft</publisher>
|
<publisher>Hudson Soft</publisher>
|
||||||
@ -18246,7 +18246,7 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="sakura">
|
<software name="sakura">
|
||||||
<!-- Notes: GBC only, 10 variant packs got released!
|
<!-- Notes: GBC only, 10 variant packs got released!
|
||||||
This game is compatible with an external pedometer named "Pocket Sakura" (same hardware as the Pokémon Pikachu Color / Pokémon Pikachu 2 GS pedometer)
|
This game is compatible with an external pedometer named "Pocket Sakura" (same hardware as the Pokémon Pikachu Color / Pokémon Pikachu 2 GS pedometer)
|
||||||
wich connects to the GBC via the console's IR port -->
|
wich connects to the GBC via the console's IR port -->
|
||||||
<description>Sakura Taisen GB - Geki Hana Gumi Nyuutai! (Jpn)</description>
|
<description>Sakura Taisen GB - Geki Hana Gumi Nyuutai! (Jpn)</description>
|
||||||
@ -23511,11 +23511,11 @@ Unreleased (music source code exists, possibly no prototypes exist)
|
|||||||
|
|
||||||
<software name="zokzok">
|
<software name="zokzok">
|
||||||
<!-- Notes: GBC only.
|
<!-- Notes: GBC only.
|
||||||
Zok Zok Heroes works with an external peripheral that acts like a motion controller.
|
Zok Zok Heroes works with an external peripheral that acts like a motion controller.
|
||||||
Internally, this device has a weighted analog joystick that moves when you shake the device.
|
Internally, this device has a weighted analog joystick that moves when you shake the device.
|
||||||
It has a Fujitsu MB89135L (undumped), four leds, a speaker and an IR emitter.
|
It has a Fujitsu MB89135L (undumped), four leds, a speaker and an IR emitter.
|
||||||
It connects with the Game Boy using the console IR, but just one way (device to console).
|
It connects with the Game Boy using the console IR, but just one way (device to console).
|
||||||
The peripheral device is named "Furu Changer". -->
|
The peripheral device is named "Furu Changer". -->
|
||||||
<description>Zok Zok Heroes (Jpn)</description>
|
<description>Zok Zok Heroes (Jpn)</description>
|
||||||
<year>2000</year>
|
<year>2000</year>
|
||||||
<publisher>Media Factory</publisher>
|
<publisher>Media Factory</publisher>
|
||||||
|
@ -3,214 +3,214 @@
|
|||||||
<softwarelist name="monon_color" description="M&D Monon Color cartridges">
|
<softwarelist name="monon_color" description="M&D Monon Color cartridges">
|
||||||
|
|
||||||
<!-- Known games list
|
<!-- Known games list
|
||||||
|
|
||||||
English Translation Romanization Dumped? Released? Item # Type? Full name
|
English Translation Romanization Dumped? Released? Item # Type? Full name
|
||||||
Purcell: Ares Fighting Spirit Sài ěr hào: Zhànshén dòu hún Y Y NO. 101 RPG 赛尔号:战神斗魂
|
Purcell: Ares Fighting Spirit Sài ěr hào: Zhànshén dòu hún Y Y NO. 101 RPG 赛尔号:战神斗魂
|
||||||
Locke Kingdom: Magic Array Luòkè wángguó-mófǎ zhèn Y Y NO. 102 PUZ/EDU 洛克王国-魔法阵
|
Locke Kingdom: Magic Array Luòkè wángguó-mófǎ zhèn Y Y NO. 102 PUZ/EDU 洛克王国-魔法阵
|
||||||
Mech Cyclone: Fighting Masters Jī jiǎ xuànfēng-gédòu dàshī Y Y NO. 103 FTG 机甲旋风-格斗大师
|
Mech Cyclone: Fighting Masters Jī jiǎ xuànfēng-gédòu dàshī Y Y NO. 103 FTG 机甲旋风-格斗大师
|
||||||
Zinba! : The lost relics Shén pò-shīluò de yíjī Y Y NO. 104 RPG 神魄-失落的遗迹
|
Zinba! : The lost relics Shén pò-shīluò de yíjī Y Y NO. 104 RPG 神魄-失落的遗迹
|
||||||
Purcell: Energy Battle Sài ěr hào-néngyuán dà zuòzhàn Y Y NO. 105 PUZ 赛尔号-能源大作战
|
Purcell: Energy Battle Sài ěr hào-néngyuán dà zuòzhàn Y Y NO. 105 PUZ 赛尔号-能源大作战
|
||||||
Iron Man: Hero Strike Gāngtiě xiá-yīngxióng fǎnjí zhàn Y Y No. 106 ACT 钢铁侠-英雄反击战
|
Iron Man: Hero Strike Gāngtiě xiá-yīngxióng fǎnjí zhàn Y Y No. 106 ACT 钢铁侠-英雄反击战
|
||||||
Zombie Hunter Jiāngshī lièrén Y Y NO. 107 ACT 僵尸猎人
|
Zombie Hunter Jiāngshī lièrén Y Y NO. 107 ACT 僵尸猎人
|
||||||
IELTS Adventure Yǎsī tǎ dà màoxiǎn N Y NO. 108 PUZ/EDU 雅思塔大冒险
|
IELTS Adventure Yǎsī tǎ dà màoxiǎn N Y NO. 108 PUZ/EDU 雅思塔大冒险
|
||||||
Ultimate Brain Power Nǎolì liánlián kàn N Y NO. 109 PUZ/EDU 脑力连连看
|
Ultimate Brain Power Nǎolì liánlián kàn N Y NO. 109 PUZ/EDU 脑力连连看
|
||||||
Locke Kingdom: Big Adventure Luòkè wángguó-dà màoxiǎn Y Y NO. 201 ACT 洛克王国-大冒险
|
Locke Kingdom: Big Adventure Luòkè wángguó-dà màoxiǎn Y Y NO. 201 ACT 洛克王国-大冒险
|
||||||
Locke Kingdom RPG: Ice Blue Luòkè wángguó-bīng zhī lán Y Y NO. 202 RPG 洛克王国-冰之蓝
|
Locke Kingdom RPG: Ice Blue Luòkè wángguó-bīng zhī lán Y Y NO. 202 RPG 洛克王国-冰之蓝
|
||||||
Locke Kingdom RPG: Black Fire Luòkè wángguó-hēi zhī yán Y Y NO. 203 RPG 洛克王国-黑之炎
|
Locke Kingdom RPG: Black Fire Luòkè wángguó-hēi zhī yán Y Y NO. 203 RPG 洛克王国-黑之炎
|
||||||
Locke Kingdom: Card Wars Luòkè wángguó-kǎ pái zhàn jì Y Y NO. 204 RPG 洛克王国-卡牌战纪
|
Locke Kingdom: Card Wars Luòkè wángguó-kǎ pái zhàn jì Y Y NO. 204 RPG 洛克王国-卡牌战纪
|
||||||
Armor Warrior Kǎijiǎ yǒngshì dàluàn dòu Y Y NO. 205 ACT 铠甲勇士大乱斗
|
Armor Warrior Kǎijiǎ yǒngshì dàluàn dòu Y Y NO. 205 ACT 铠甲勇士大乱斗
|
||||||
Locke Kingdom: The King's Badge Luòkè wángguó-wángzhě huīzhāng N Y NO. 206 RPG 洛克王国-王者徽章
|
Locke Kingdom: The King's Badge Luòkè wángguó-wángzhě huīzhāng N Y NO. 206 RPG 洛克王国-王者徽章
|
||||||
Laboratory Mathematica Olympiad Àoshù shíyàn shì N Y NO. 207 PUZ/EDU 奥数实验室
|
Laboratory Mathematica Olympiad Àoshù shíyàn shì N Y NO. 207 PUZ/EDU 奥数实验室
|
||||||
Logic Fight Luójí pīn yī pīn Y Y NO. 301 PUZ/EDU 逻辑拼一拼
|
Logic Fight Luójí pīn yī pīn Y Y NO. 301 PUZ/EDU 逻辑拼一拼
|
||||||
Pleasant goat and big big wolf's comet battle Xǐyángyáng yǔ huītàiláng-juézhàn miē xīng N Y NO. 302 PUZ/EDU 喜羊羊与灰太狼-决战咩星
|
Pleasant goat and big big wolf's comet battle Xǐyángyáng yǔ huītàiláng-juézhàn miē xīng N Y NO. 302 PUZ/EDU 喜羊羊与灰太狼-决战咩星
|
||||||
Dragon Ball: The Martial Arts Conference Lóngzhū-wǔdào dàhuì Y Y NO. 303 ACT 龙珠-武道大会
|
Dragon Ball: The Martial Arts Conference Lóngzhū-wǔdào dàhuì Y Y NO. 303 ACT 龙珠-武道大会
|
||||||
League of Legends: The Ultimate Fight Yīngxióng liánméng-zhōngjí gédòu Y Y NO. 304 FTG 英雄联盟-终极格斗
|
League of Legends: The Ultimate Fight Yīngxióng liánméng-zhōngjí gédòu Y Y NO. 304 FTG 英雄联盟-终极格斗
|
||||||
Ben 10: alien force .. N N? ACT BEN 10: ALIEN FORCE
|
Ben 10: alien force .. N N? ACT BEN 10: ALIEN FORCE
|
||||||
DIGIMON .. N N? RPG DIGIMON
|
DIGIMON .. N N? RPG DIGIMON
|
||||||
Jackie Chan fighting? (1) (unknown) N Y? NO. 308? FTG (unknown)
|
Jackie Chan fighting? (1) (unknown) N Y? NO. 308? FTG (unknown)
|
||||||
|
|
||||||
|
|
||||||
(1) (Note: One known to exist in the wild, was supposedly bought at a thrift store. Based around Jackie Chan fighting)
|
(1) (Note: One known to exist in the wild, was supposedly bought at a thrift store. Based around Jackie Chan fighting)
|
||||||
-->
|
-->
|
||||||
|
|
||||||
<software name="purcfs"> <!-- 101 - Purcell: Ares Fighting Spirit -->
|
<software name="purcfs"> <!-- 101 - Purcell: Ares Fighting Spirit -->
|
||||||
<description>Sài ěr hào: Zhànshén dòu hún</description>
|
<description>Sài ěr hào: Zhànshén dòu hún</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="赛尔号:战神斗魂"/>
|
<info name="alt_title" value="赛尔号:战神斗魂"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="101.bin" size="0x0800000" crc="7eced0cf" sha1="3e34abbaf1259094099f1587302dfbd84ffb8384" offset="0" />
|
<rom name="101.bin" size="0x0800000" crc="7eced0cf" sha1="3e34abbaf1259094099f1587302dfbd84ffb8384" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="lockmagi"> <!-- 102 - Locke Kingdom: Magic Array -->
|
<software name="lockmagi"> <!-- 102 - Locke Kingdom: Magic Array -->
|
||||||
<description>Luòkè wángguó-mófǎ zhèn</description>
|
<description>Luòkè wángguó-mófǎ zhèn</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="洛克王国-魔法阵"/>
|
<info name="alt_title" value="洛克王国-魔法阵"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="102.bin" size="0x0800000" crc="15ed170d" sha1="ce4832f57459acf01deae688c62d444cffaa271a" offset="0" />
|
<rom name="102.bin" size="0x0800000" crc="15ed170d" sha1="ce4832f57459acf01deae688c62d444cffaa271a" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="mechcycl"> <!-- 103 - Mech Cyclone: Fighting Masters -->
|
<software name="mechcycl"> <!-- 103 - Mech Cyclone: Fighting Masters -->
|
||||||
<description>Jī jiǎ xuànfēng-gédòu dàshī</description>
|
<description>Jī jiǎ xuànfēng-gédòu dàshī</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="机甲旋风-格斗大师"/>
|
<info name="alt_title" value="机甲旋风-格斗大师"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="103.bin" size="0x0800000" crc="441d5f9d" sha1="2ec85c5225b7ed0291b13f5d3bc57a9ef0153b5e" offset="0" />
|
<rom name="103.bin" size="0x0800000" crc="441d5f9d" sha1="2ec85c5225b7ed0291b13f5d3bc57a9ef0153b5e" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="zinba"> <!-- 104 - Zinba! : The lost relics -->
|
<software name="zinba"> <!-- 104 - Zinba! : The lost relics -->
|
||||||
<description>Shén pò-shīluò de yíjī</description>
|
<description>Shén pò-shīluò de yíjī</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="神魄-失落的遗迹"/>
|
<info name="alt_title" value="神魄-失落的遗迹"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="104.bin" size="0x0800000" crc="e7fd791a" sha1="7572d11ce5fae30a01ebe1053d8632329249fba8" offset="0" />
|
<rom name="104.bin" size="0x0800000" crc="e7fd791a" sha1="7572d11ce5fae30a01ebe1053d8632329249fba8" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="purceb"> <!-- 105 - Purcell: Energy Battle -->
|
<software name="purceb"> <!-- 105 - Purcell: Energy Battle -->
|
||||||
<description>Sài ěr hào-néngyuán dà zuòzhàn</description>
|
<description>Sài ěr hào-néngyuán dà zuòzhàn</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="赛尔号-能源大作战"/>
|
<info name="alt_title" value="赛尔号-能源大作战"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="105.bin" size="0x0400000" crc="47b4a312" sha1="c4600ce39fd2301df3778afe896936d510cbbd5b" offset="0" />
|
<rom name="105.bin" size="0x0400000" crc="47b4a312" sha1="c4600ce39fd2301df3778afe896936d510cbbd5b" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="ironmnhs"> <!-- 106 - Iron Man: Hero Strike -->
|
<software name="ironmnhs"> <!-- 106 - Iron Man: Hero Strike -->
|
||||||
<description>Gāngtiě xiá-yīngxióng fǎnjí zhàn</description>
|
<description>Gāngtiě xiá-yīngxióng fǎnjí zhàn</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="钢铁侠-英雄反击战"/>
|
<info name="alt_title" value="钢铁侠-英雄反击战"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="106.bin" size="0x0800000" crc="68517eea" sha1="e262f5ac691d8a3e30232a6b51d9428b73b9e8e2" offset="0" />
|
<rom name="106.bin" size="0x0800000" crc="68517eea" sha1="e262f5ac691d8a3e30232a6b51d9428b73b9e8e2" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="zombhunt"> <!-- 107 - Zombie Hunter -->
|
<software name="zombhunt"> <!-- 107 - Zombie Hunter -->
|
||||||
<description>Jiāngshī lièrén</description>
|
<description>Jiāngshī lièrén</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="僵尸猎人"/>
|
<info name="alt_title" value="僵尸猎人"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="107.bin" size="0x1000000" crc="cd9d372d" sha1="71b09bf181a5565e7cca4281def59364b270767e" offset="0" />
|
<rom name="107.bin" size="0x1000000" crc="cd9d372d" sha1="71b09bf181a5565e7cca4281def59364b270767e" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="lockba"> <!-- 201 - Locke Kingdom: Big Adventure -->
|
<software name="lockba"> <!-- 201 - Locke Kingdom: Big Adventure -->
|
||||||
<description>Luòkè wángguó-dà màoxiǎn</description>
|
<description>Luòkè wángguó-dà màoxiǎn</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="洛克王国-大冒险"/>
|
<info name="alt_title" value="洛克王国-大冒险"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="201.bin" size="0x1000000" crc="cf52653e" sha1="96aa826821d20af3edfe0f8058e6158841b7bf08" offset="0" />
|
<rom name="201.bin" size="0x1000000" crc="cf52653e" sha1="96aa826821d20af3edfe0f8058e6158841b7bf08" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="lockice"> <!-- 202 - Locke Kingdom RPG: Ice Blue -->
|
<software name="lockice"> <!-- 202 - Locke Kingdom RPG: Ice Blue -->
|
||||||
<description>Luòkè wángguó-bīng zhī lán</description>
|
<description>Luòkè wángguó-bīng zhī lán</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="冰之蓝"/>
|
<info name="alt_title" value="冰之蓝"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="202.bin" size="0x1000000" crc="554af334" sha1="94c54a7ad4828e95074ec341eef9278b552f655e" offset="0" />
|
<rom name="202.bin" size="0x1000000" crc="554af334" sha1="94c54a7ad4828e95074ec341eef9278b552f655e" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="lockfire"> <!-- 203 - Locke Kingdom RPG: Black Fire -->
|
<software name="lockfire"> <!-- 203 - Locke Kingdom RPG: Black Fire -->
|
||||||
<description>Luòkè wángguó-hēi zhī yán</description>
|
<description>Luòkè wángguó-hēi zhī yán</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="洛克王国-黑之炎"/>
|
<info name="alt_title" value="洛克王国-黑之炎"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="203.bin" size="0x1000000" crc="8541d04e" sha1="5fa6edc852622f6c2cca07ec9c7f377bea020f9b" offset="0" />
|
<rom name="203.bin" size="0x1000000" crc="8541d04e" sha1="5fa6edc852622f6c2cca07ec9c7f377bea020f9b" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="lockcard"> <!-- 204 - Locke Kingdom: Card Wars -->
|
<software name="lockcard"> <!-- 204 - Locke Kingdom: Card Wars -->
|
||||||
<description>Luòkè wángguó-kǎ pái zhàn jì</description>
|
<description>Luòkè wángguó-kǎ pái zhàn jì</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="卡牌战纪"/>
|
<info name="alt_title" value="卡牌战纪"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="204.bin" size="0x1000000" crc="0015d25c" sha1="50de7d969bead2df60e8ea4051f8518dd8989633" offset="0" />
|
<rom name="204.bin" size="0x1000000" crc="0015d25c" sha1="50de7d969bead2df60e8ea4051f8518dd8989633" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="armorwr"> <!-- 205 - Armor Warrior -->
|
<software name="armorwr"> <!-- 205 - Armor Warrior -->
|
||||||
<description>Kǎijiǎ yǒngshì dàluàn dòu</description>
|
<description>Kǎijiǎ yǒngshì dàluàn dòu</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="铠甲勇士大乱斗"/>
|
<info name="alt_title" value="铠甲勇士大乱斗"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="205.bin" size="0x1000000" crc="84d1224c" sha1="9c427031221dc69034275a359e87c0dda82ae295" offset="0" />
|
<rom name="205.bin" size="0x1000000" crc="84d1224c" sha1="9c427031221dc69034275a359e87c0dda82ae295" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="logicft"> <!-- 301 - Logic Fight -->
|
<software name="logicft"> <!-- 301 - Logic Fight -->
|
||||||
<description>Luójí pīn yī pīn</description>
|
<description>Luójí pīn yī pīn</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="逻辑拼一拼"/>
|
<info name="alt_title" value="逻辑拼一拼"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="301.bin" size="0x0400000" crc="e8f19fdc" sha1="330980c975e3fafea9b3dda1b010fdd469100919" offset="0" />
|
<rom name="301.bin" size="0x0400000" crc="e8f19fdc" sha1="330980c975e3fafea9b3dda1b010fdd469100919" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="drgnbma"> <!-- 303 - Dragon Ball: The Martial Arts Conference -->
|
<software name="drgnbma"> <!-- 303 - Dragon Ball: The Martial Arts Conference -->
|
||||||
<description>Lóngzhū-wǔdào dàhuì</description>
|
<description>Lóngzhū-wǔdào dàhuì</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="龙珠-武道大会"/>
|
<info name="alt_title" value="龙珠-武道大会"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="303.bin" size="0x1000000" crc="d5bd966e" sha1="792b22444a329d08520591e80599835d77f38b3c" offset="0" />
|
<rom name="303.bin" size="0x1000000" crc="d5bd966e" sha1="792b22444a329d08520591e80599835d77f38b3c" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
<software name="lolfight"> <!-- 304 - League of Legends: The Ultimate Fight -->
|
<software name="lolfight"> <!-- 304 - League of Legends: The Ultimate Fight -->
|
||||||
<description>Yīngxióng liánméng-zhōngjí gédòu</description>
|
<description>Yīngxióng liánméng-zhōngjí gédòu</description>
|
||||||
<year>2011</year>
|
<year>2011</year>
|
||||||
<publisher>M&D</publisher>
|
<publisher>M&D</publisher>
|
||||||
<info name="alt_title" value="英雄联盟"/>
|
<info name="alt_title" value="英雄联盟"/>
|
||||||
<part name="cart" interface="monon_color_cart">
|
<part name="cart" interface="monon_color_cart">
|
||||||
<dataarea name="rom" size="0x1000000">
|
<dataarea name="rom" size="0x1000000">
|
||||||
<rom name="304.bin" size="0x1000000" crc="e4833f82" sha1="877c28d188d19b882909b4b0934ce2f900d2ce30" offset="0" />
|
<rom name="304.bin" size="0x1000000" crc="e4833f82" sha1="877c28d188d19b882909b4b0934ce2f900d2ce30" offset="0" />
|
||||||
</dataarea>
|
</dataarea>
|
||||||
</part>
|
</part>
|
||||||
</software>
|
</software>
|
||||||
|
|
||||||
</softwarelist>
|
</softwarelist>
|
||||||
|
@ -1751,7 +1751,7 @@ files {
|
|||||||
MAME_DIR .. "src/mame/drivers/stlforce.cpp",
|
MAME_DIR .. "src/mame/drivers/stlforce.cpp",
|
||||||
MAME_DIR .. "src/mame/includes/stlforce.h",
|
MAME_DIR .. "src/mame/includes/stlforce.h",
|
||||||
MAME_DIR .. "src/mame/video/edevices.cpp",
|
MAME_DIR .. "src/mame/video/edevices.cpp",
|
||||||
MAME_DIR .. "src/mame/video/edevices.h",
|
MAME_DIR .. "src/mame/video/edevices.h",
|
||||||
MAME_DIR .. "src/mame/drivers/mugsmash.cpp",
|
MAME_DIR .. "src/mame/drivers/mugsmash.cpp",
|
||||||
MAME_DIR .. "src/mame/includes/mugsmash.h",
|
MAME_DIR .. "src/mame/includes/mugsmash.h",
|
||||||
MAME_DIR .. "src/mame/video/mugsmash.cpp",
|
MAME_DIR .. "src/mame/video/mugsmash.cpp",
|
||||||
|
@ -7,8 +7,8 @@
|
|||||||
|
|
||||||
**********************************************************************
|
**********************************************************************
|
||||||
|
|
||||||
Known Issues:
|
Known Issues:
|
||||||
- Currently the FC expansion port is emulated as a control port
|
- Currently the FC expansion port is emulated as a control port
|
||||||
|
|
||||||
**********************************************************************/
|
**********************************************************************/
|
||||||
|
|
||||||
|
@ -33,7 +33,7 @@ enum
|
|||||||
#define SINGLE_INSTRUCTION_MODE (0)
|
#define SINGLE_INSTRUCTION_MODE (0)
|
||||||
|
|
||||||
|
|
||||||
#define CACHE_SIZE (4 * 1024 * 1024) // FIXME
|
#define CACHE_SIZE (4 * 1024 * 1024) // FIXME
|
||||||
// FIXME!!!
|
// FIXME!!!
|
||||||
/* compilation boundaries -- how far back/forward does the analysis extend? */
|
/* compilation boundaries -- how far back/forward does the analysis extend? */
|
||||||
#define COMPILE_BACKWARDS_BYTES 128
|
#define COMPILE_BACKWARDS_BYTES 128
|
||||||
@ -54,46 +54,46 @@ enum
|
|||||||
// MACROS
|
// MACROS
|
||||||
//**************************************************************************
|
//**************************************************************************
|
||||||
|
|
||||||
//#define DSPI_FLAG_CC_CARRY 0x0001
|
//#define DSPI_FLAG_CC_CARRY 0x0001
|
||||||
//#define DSPI_FLAG_CC_ZERO 0x0002
|
//#define DSPI_FLAG_CC_ZERO 0x0002
|
||||||
//#define DSPI_FLAG_CC_NEG 0x0004
|
//#define DSPI_FLAG_CC_NEG 0x0004
|
||||||
//#define DSPI_FLAG_CC_OVER 0x0008
|
//#define DSPI_FLAG_CC_OVER 0x0008
|
||||||
//#define DSPI_FLAG_CC_EXACT 0x0010
|
//#define DSPI_FLAG_CC_EXACT 0x0010
|
||||||
//#define DSPI_FLAG_AUDLOCK 0x0020
|
//#define DSPI_FLAG_AUDLOCK 0x0020
|
||||||
//#define DSPI_FLAG_SLEEP 0x0040
|
//#define DSPI_FLAG_SLEEP 0x0040
|
||||||
//#define DSPI_FLAG_CC_MASK 0x001f
|
//#define DSPI_FLAG_CC_MASK 0x001f
|
||||||
|
|
||||||
#define DSPX_CONTROL_GWILLING 0x0001
|
#define DSPX_CONTROL_GWILLING 0x0001
|
||||||
#define DSPX_CONTROL_STEP_CYCLE 0x0002
|
#define DSPX_CONTROL_STEP_CYCLE 0x0002
|
||||||
#define DSPX_CONTROL_STEP_PC 0x0004
|
#define DSPX_CONTROL_STEP_PC 0x0004
|
||||||
#define DSPX_CONTROL_SNOOP 0x0008
|
#define DSPX_CONTROL_SNOOP 0x0008
|
||||||
|
|
||||||
#define DSPX_RESET_DSPP 0x0001
|
#define DSPX_RESET_DSPP 0x0001
|
||||||
#define DSPX_RESET_INPUT 0x0002
|
#define DSPX_RESET_INPUT 0x0002
|
||||||
#define DSPX_RESET_OUTPUT 0x0004
|
#define DSPX_RESET_OUTPUT 0x0004
|
||||||
|
|
||||||
#define DSPX_F_DMA_NEXTVALID 0x0001
|
#define DSPX_F_DMA_NEXTVALID 0x0001
|
||||||
#define DSPX_F_DMA_GO_FOREVER 0x0002
|
#define DSPX_F_DMA_GO_FOREVER 0x0002
|
||||||
#define DSPX_F_INT_DMANEXT_EN 0x0004
|
#define DSPX_F_INT_DMANEXT_EN 0x0004
|
||||||
#define DSPX_F_SHADOW_SET_DMANEXT 0x00040000
|
#define DSPX_F_SHADOW_SET_DMANEXT 0x00040000
|
||||||
#define DSPX_F_SHADOW_SET_FOREVER 0x00020000
|
#define DSPX_F_SHADOW_SET_FOREVER 0x00020000
|
||||||
#define DSPX_F_SHADOW_SET_NEXTVALID 0x00010000
|
#define DSPX_F_SHADOW_SET_NEXTVALID 0x00010000
|
||||||
#define DSPX_F_SHADOW_SET_ADDRESS_COUNT 0x80000000
|
#define DSPX_F_SHADOW_SET_ADDRESS_COUNT 0x80000000
|
||||||
|
|
||||||
#define DSPX_F_INT_TIMER 0x00000100
|
#define DSPX_F_INT_TIMER 0x00000100
|
||||||
#define DSPX_F_INT_INPUT_UNDER 0x00000080
|
#define DSPX_F_INT_INPUT_UNDER 0x00000080
|
||||||
#define DSPX_F_INT_INPUT_OVER 0x00000040
|
#define DSPX_F_INT_INPUT_OVER 0x00000040
|
||||||
#define DSPX_F_INT_OUTPUT_UNDER 0x00000020
|
#define DSPX_F_INT_OUTPUT_UNDER 0x00000020
|
||||||
#define DSPX_F_INT_OUTPUT_OVER 0x00000010
|
#define DSPX_F_INT_OUTPUT_OVER 0x00000010
|
||||||
#define DSPX_F_INT_UNDEROVER 0x00000008
|
#define DSPX_F_INT_UNDEROVER 0x00000008
|
||||||
#define DSPX_F_INT_CONSUMED 0x00000002
|
#define DSPX_F_INT_CONSUMED 0x00000002
|
||||||
#define DSPX_F_INT_DMANEXT 0x00000001
|
#define DSPX_F_INT_DMANEXT 0x00000001
|
||||||
|
|
||||||
#define DSPX_F_INT_ALL_DMA (DSPX_F_INT_DMANEXT | DSPX_F_INT_CONSUMED | DSPX_F_INT_UNDEROVER)
|
#define DSPX_F_INT_ALL_DMA (DSPX_F_INT_DMANEXT | DSPX_F_INT_CONSUMED | DSPX_F_INT_UNDEROVER)
|
||||||
|
|
||||||
#define DSPX_FLD_INT_SOFT_WIDTH 16 /* width of the field and the number of interrupts */
|
#define DSPX_FLD_INT_SOFT_WIDTH 16 /* width of the field and the number of interrupts */
|
||||||
#define DSPX_FLD_INT_SOFT_SHIFT 16
|
#define DSPX_FLD_INT_SOFT_SHIFT 16
|
||||||
#define DSPX_FLD_INT_SOFT_MASK (0xffff0000)
|
#define DSPX_FLD_INT_SOFT_MASK (0xffff0000)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -378,14 +378,14 @@ void dspp_device::state_string_export(const device_state_entry &entry, std::stri
|
|||||||
{
|
{
|
||||||
case STATE_GENFLAGS:
|
case STATE_GENFLAGS:
|
||||||
str = string_format("%c%c.%c%c%c%c%c",
|
str = string_format("%c%c.%c%c%c%c%c",
|
||||||
m_core->m_flag_audlock ? 'A' : '.',
|
m_core->m_flag_audlock ? 'A' : '.',
|
||||||
m_core->m_flag_sleep ? 'S' : '.',
|
m_core->m_flag_sleep ? 'S' : '.',
|
||||||
m_core->m_flag_carry ? 'C' : '.',
|
m_core->m_flag_carry ? 'C' : '.',
|
||||||
m_core->m_flag_zero ? 'Z' : '.',
|
m_core->m_flag_zero ? 'Z' : '.',
|
||||||
m_core->m_flag_neg ? 'N' : '.',
|
m_core->m_flag_neg ? 'N' : '.',
|
||||||
m_core->m_flag_over ? 'V' : '.',
|
m_core->m_flag_over ? 'V' : '.',
|
||||||
m_core->m_flag_exact ? 'E' : '.');
|
m_core->m_flag_exact ? 'E' : '.');
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -732,7 +732,7 @@ void dspp_device::execute_run()
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0);
|
bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0);
|
||||||
|
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
@ -742,8 +742,8 @@ void dspp_device::execute_run()
|
|||||||
// Only run if enabled
|
// Only run if enabled
|
||||||
if (m_dspx_control & DSPX_CONTROL_GWILLING)
|
if (m_dspx_control & DSPX_CONTROL_GWILLING)
|
||||||
{
|
{
|
||||||
if (check_debugger)
|
if (check_debugger)
|
||||||
debugger_instruction_hook(m_core->m_pc);
|
debugger_instruction_hook(m_core->m_pc);
|
||||||
|
|
||||||
m_core->m_op = read_op(m_core->m_pc);
|
m_core->m_op = read_op(m_core->m_pc);
|
||||||
update_pc();
|
update_pc();
|
||||||
@ -775,7 +775,7 @@ inline void dspp_device::exec_super_special()
|
|||||||
|
|
||||||
switch (sel)
|
switch (sel)
|
||||||
{
|
{
|
||||||
case 1: // BAC
|
case 1: // BAC
|
||||||
{
|
{
|
||||||
m_core->m_pc = m_core->m_acc >> 4;
|
m_core->m_pc = m_core->m_acc >> 4;
|
||||||
break;
|
break;
|
||||||
@ -1116,70 +1116,70 @@ inline void dspp_device::exec_arithmetic()
|
|||||||
|
|
||||||
switch (alu_op)
|
switch (alu_op)
|
||||||
{
|
{
|
||||||
case 0: // _TRA
|
case 0: // _TRA
|
||||||
{
|
{
|
||||||
alu_res = alu_a;
|
alu_res = alu_a;
|
||||||
m_core->m_flag_over = 0;
|
m_core->m_flag_over = 0;
|
||||||
m_core->m_flag_carry = 0;
|
m_core->m_flag_carry = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 1: // _NEG
|
case 1: // _NEG
|
||||||
{
|
{
|
||||||
alu_res = -alu_b;
|
alu_res = -alu_b;
|
||||||
m_core->m_flag_over = 0;
|
m_core->m_flag_over = 0;
|
||||||
m_core->m_flag_carry = 0;
|
m_core->m_flag_carry = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 2: // _+
|
case 2: // _+
|
||||||
{
|
{
|
||||||
alu_res = alu_a + alu_b;
|
alu_res = alu_a + alu_b;
|
||||||
m_core->m_flag_over = (((alu_a & 0x80000) == (alu_b & 0x80000) && (alu_a & 0x80000) != (alu_res & 0x80000)));
|
m_core->m_flag_over = (((alu_a & 0x80000) == (alu_b & 0x80000) && (alu_a & 0x80000) != (alu_res & 0x80000)));
|
||||||
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 3: // _+C
|
case 3: // _+C
|
||||||
{
|
{
|
||||||
alu_res = alu_a + (m_core->m_flag_carry << 4);
|
alu_res = alu_a + (m_core->m_flag_carry << 4);
|
||||||
m_core->m_flag_over = 0;
|
m_core->m_flag_over = 0;
|
||||||
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 4: // _-
|
case 4: // _-
|
||||||
{
|
{
|
||||||
alu_res = alu_a - alu_b;
|
alu_res = alu_a - alu_b;
|
||||||
m_core->m_flag_over = ((alu_a & 0x80000) == (~alu_b & 0x80000) && (alu_a & 0x80000) != (alu_res & 0x80000));
|
m_core->m_flag_over = ((alu_a & 0x80000) == (~alu_b & 0x80000) && (alu_a & 0x80000) != (alu_res & 0x80000));
|
||||||
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 5: // _-B
|
case 5: // _-B
|
||||||
{
|
{
|
||||||
alu_res = alu_a - (m_core->m_flag_carry << 4);
|
alu_res = alu_a - (m_core->m_flag_carry << 4);
|
||||||
m_core->m_flag_over = 0;
|
m_core->m_flag_over = 0;
|
||||||
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 6: // _++
|
case 6: // _++
|
||||||
{
|
{
|
||||||
alu_res = alu_a + 1;
|
alu_res = alu_a + 1;
|
||||||
m_core->m_flag_over = !(alu_a & 0x80000) && (alu_res & 0x80000);
|
m_core->m_flag_over = !(alu_a & 0x80000) && (alu_res & 0x80000);
|
||||||
m_core->m_flag_carry = 0;
|
m_core->m_flag_carry = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 7: // _--
|
case 7: // _--
|
||||||
{
|
{
|
||||||
alu_res = alu_a - 1;
|
alu_res = alu_a - 1;
|
||||||
m_core->m_flag_over = (alu_a & 0x80000) && !(alu_res & 0x80000);
|
m_core->m_flag_over = (alu_a & 0x80000) && !(alu_res & 0x80000);
|
||||||
m_core->m_flag_carry = 0;
|
m_core->m_flag_carry = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 8: // _TRL
|
case 8: // _TRL
|
||||||
{
|
{
|
||||||
alu_res = alu_a;
|
alu_res = alu_a;
|
||||||
m_core->m_flag_over = 0;
|
m_core->m_flag_over = 0;
|
||||||
m_core->m_flag_carry = 0;
|
m_core->m_flag_carry = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 9: // _NOT
|
case 9: // _NOT
|
||||||
{
|
{
|
||||||
alu_res = ~alu_a;
|
alu_res = ~alu_a;
|
||||||
m_core->m_flag_over = 0;
|
m_core->m_flag_over = 0;
|
||||||
@ -2630,17 +2630,17 @@ void dspp_device::dump_state()
|
|||||||
printf("DSPX_CHANNEL_SQXD: %08X %s\n", m_dspx_channel_sqxd, GetBinary(buffer, m_dspx_channel_sqxd, 32));
|
printf("DSPX_CHANNEL_SQXD: %08X %s\n", m_dspx_channel_sqxd, GetBinary(buffer, m_dspx_channel_sqxd, 32));
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
uint32_t m_dspx_shadow_current_addr;
|
uint32_t m_dspx_shadow_current_addr;
|
||||||
uint32_t m_dspx_shadow_current_count;
|
uint32_t m_dspx_shadow_current_count;
|
||||||
uint32_t m_dspx_shadow_next_addr;
|
uint32_t m_dspx_shadow_next_addr;
|
||||||
uint32_t m_dspx_shadow_next_count;
|
uint32_t m_dspx_shadow_next_count;
|
||||||
uint32_t m_dspx_dmanext_int;
|
uint32_t m_dspx_dmanext_int;
|
||||||
uint32_t m_dspx_dmanext_enable;
|
uint32_t m_dspx_dmanext_enable;
|
||||||
uint32_t m_dspx_consumed_int;
|
uint32_t m_dspx_consumed_int;
|
||||||
uint32_t m_dspx_consumed_enable;
|
uint32_t m_dspx_consumed_enable;
|
||||||
uint32_t m_dspx_underover_int;
|
uint32_t m_dspx_underover_int;
|
||||||
uint32_t m_dspx_underover_enable;
|
uint32_t m_dspx_underover_enable;
|
||||||
uint32_t m_dspx_audio_time;
|
uint32_t m_dspx_audio_time;
|
||||||
uint16_t m_dspx_audio_duration;
|
uint16_t m_dspx_audio_duration;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -105,9 +105,9 @@ private:
|
|||||||
static const uint32_t OUTPUT_FIFO_MASK = OUTPUT_FIFO_DEPTH - 1;
|
static const uint32_t OUTPUT_FIFO_MASK = OUTPUT_FIFO_DEPTH - 1;
|
||||||
|
|
||||||
// Handlers
|
// Handlers
|
||||||
devcb_write_line m_int_handler;
|
devcb_write_line m_int_handler;
|
||||||
devcb_read8 m_dma_read_handler;
|
devcb_read8 m_dma_read_handler;
|
||||||
devcb_write8 m_dma_write_handler;
|
devcb_write8 m_dma_write_handler;
|
||||||
|
|
||||||
// Internal functions
|
// Internal functions
|
||||||
uint16_t read_op(offs_t pc);
|
uint16_t read_op(offs_t pc);
|
||||||
@ -157,8 +157,8 @@ private:
|
|||||||
bool m_isdrc;
|
bool m_isdrc;
|
||||||
|
|
||||||
// Address spaces
|
// Address spaces
|
||||||
const address_space_config m_code_config;
|
const address_space_config m_code_config;
|
||||||
const address_space_config m_data_config;
|
const address_space_config m_data_config;
|
||||||
address_space * m_code;
|
address_space * m_code;
|
||||||
address_space * m_data;
|
address_space * m_data;
|
||||||
memory_access_cache<1, -1, ENDIANNESS_BIG> *m_code_cache;
|
memory_access_cache<1, -1, ENDIANNESS_BIG> *m_code_cache;
|
||||||
@ -167,26 +167,26 @@ private:
|
|||||||
struct dspp_internal_state
|
struct dspp_internal_state
|
||||||
{
|
{
|
||||||
// Internal state
|
// Internal state
|
||||||
int m_icount;
|
int m_icount;
|
||||||
uint16_t m_pc;
|
uint16_t m_pc;
|
||||||
uint16_t m_stack[PC_STACK_DEPTH];
|
uint16_t m_stack[PC_STACK_DEPTH];
|
||||||
uint32_t m_stack_ptr;
|
uint32_t m_stack_ptr;
|
||||||
uint16_t m_rbase[4];
|
uint16_t m_rbase[4];
|
||||||
uint32_t m_acc;
|
uint32_t m_acc;
|
||||||
uint32_t m_tclock;
|
uint32_t m_tclock;
|
||||||
|
|
||||||
uint32_t m_flag_carry;
|
uint32_t m_flag_carry;
|
||||||
uint32_t m_flag_zero;
|
uint32_t m_flag_zero;
|
||||||
uint32_t m_flag_neg;
|
uint32_t m_flag_neg;
|
||||||
uint32_t m_flag_over;
|
uint32_t m_flag_over;
|
||||||
uint32_t m_flag_exact;
|
uint32_t m_flag_exact;
|
||||||
uint32_t m_flag_audlock;
|
uint32_t m_flag_audlock;
|
||||||
uint32_t m_flag_sleep;
|
uint32_t m_flag_sleep;
|
||||||
|
|
||||||
uint32_t m_partial_int;
|
uint32_t m_partial_int;
|
||||||
uint16_t m_op;
|
uint16_t m_op;
|
||||||
uint32_t m_opidx;
|
uint32_t m_opidx;
|
||||||
int32_t m_writeback;
|
int32_t m_writeback;
|
||||||
|
|
||||||
const char *m_format;
|
const char *m_format;
|
||||||
uint32_t m_arg0;
|
uint32_t m_arg0;
|
||||||
@ -201,54 +201,54 @@ private:
|
|||||||
// DMA
|
// DMA
|
||||||
struct fifo_dma
|
struct fifo_dma
|
||||||
{
|
{
|
||||||
uint32_t m_current_addr;
|
uint32_t m_current_addr;
|
||||||
int32_t m_current_count;
|
int32_t m_current_count;
|
||||||
uint32_t m_next_addr;
|
uint32_t m_next_addr;
|
||||||
uint32_t m_next_count;
|
uint32_t m_next_count;
|
||||||
uint32_t m_prev_value;
|
uint32_t m_prev_value;
|
||||||
uint32_t m_prev_current;
|
uint32_t m_prev_current;
|
||||||
uint8_t m_go_forever;
|
uint8_t m_go_forever;
|
||||||
uint8_t m_next_valid;
|
uint8_t m_next_valid;
|
||||||
uint8_t m_reserved;
|
uint8_t m_reserved;
|
||||||
uint16_t m_fifo[DMA_FIFO_DEPTH];
|
uint16_t m_fifo[DMA_FIFO_DEPTH];
|
||||||
uint32_t m_dma_ptr;
|
uint32_t m_dma_ptr;
|
||||||
uint32_t m_dspi_ptr;
|
uint32_t m_dspi_ptr;
|
||||||
uint32_t m_depth;
|
uint32_t m_depth;
|
||||||
} m_fifo_dma[NUM_DMA_CHANNELS];
|
} m_fifo_dma[NUM_DMA_CHANNELS];
|
||||||
|
|
||||||
// Oscillator
|
// Oscillator
|
||||||
uint32_t m_last_frame_clock;
|
uint32_t m_last_frame_clock;
|
||||||
uint32_t m_last_osc_count;
|
uint32_t m_last_osc_count;
|
||||||
uint32_t m_osc_phase;
|
uint32_t m_osc_phase;
|
||||||
uint32_t m_osc_freq;
|
uint32_t m_osc_freq;
|
||||||
|
|
||||||
// Output FIFO
|
// Output FIFO
|
||||||
uint16_t m_outputs[NUM_OUTPUTS];
|
uint16_t m_outputs[NUM_OUTPUTS];
|
||||||
uint16_t m_output_fifo[OUTPUT_FIFO_DEPTH];
|
uint16_t m_output_fifo[OUTPUT_FIFO_DEPTH];
|
||||||
uint32_t m_output_fifo_start;
|
uint32_t m_output_fifo_start;
|
||||||
uint32_t m_output_fifo_count;
|
uint32_t m_output_fifo_count;
|
||||||
|
|
||||||
// External control registers
|
// External control registers
|
||||||
uint32_t m_dspx_control;
|
uint32_t m_dspx_control;
|
||||||
uint32_t m_dspx_reset;
|
uint32_t m_dspx_reset;
|
||||||
uint32_t m_dspx_int_enable;
|
uint32_t m_dspx_int_enable;
|
||||||
uint32_t m_dspx_channel_enable;
|
uint32_t m_dspx_channel_enable;
|
||||||
uint32_t m_dspx_channel_complete;
|
uint32_t m_dspx_channel_complete;
|
||||||
uint32_t m_dspx_channel_direction;
|
uint32_t m_dspx_channel_direction;
|
||||||
uint32_t m_dspx_channel_8bit;
|
uint32_t m_dspx_channel_8bit;
|
||||||
uint32_t m_dspx_channel_sqxd;
|
uint32_t m_dspx_channel_sqxd;
|
||||||
uint32_t m_dspx_shadow_current_addr;
|
uint32_t m_dspx_shadow_current_addr;
|
||||||
uint32_t m_dspx_shadow_current_count;
|
uint32_t m_dspx_shadow_current_count;
|
||||||
uint32_t m_dspx_shadow_next_addr;
|
uint32_t m_dspx_shadow_next_addr;
|
||||||
uint32_t m_dspx_shadow_next_count;
|
uint32_t m_dspx_shadow_next_count;
|
||||||
uint32_t m_dspx_dmanext_int;
|
uint32_t m_dspx_dmanext_int;
|
||||||
uint32_t m_dspx_dmanext_enable;
|
uint32_t m_dspx_dmanext_enable;
|
||||||
uint32_t m_dspx_consumed_int;
|
uint32_t m_dspx_consumed_int;
|
||||||
uint32_t m_dspx_consumed_enable;
|
uint32_t m_dspx_consumed_enable;
|
||||||
uint32_t m_dspx_underover_int;
|
uint32_t m_dspx_underover_int;
|
||||||
uint32_t m_dspx_underover_enable;
|
uint32_t m_dspx_underover_enable;
|
||||||
uint32_t m_dspx_audio_time;
|
uint32_t m_dspx_audio_time;
|
||||||
uint16_t m_dspx_audio_duration;
|
uint16_t m_dspx_audio_duration;
|
||||||
|
|
||||||
//
|
//
|
||||||
// DRC
|
// DRC
|
||||||
@ -256,11 +256,11 @@ private:
|
|||||||
|
|
||||||
// Core state
|
// Core state
|
||||||
/* internal stuff */
|
/* internal stuff */
|
||||||
bool m_cache_dirty;
|
bool m_cache_dirty;
|
||||||
drc_cache m_cache;
|
drc_cache m_cache;
|
||||||
std::unique_ptr<drcuml_state> m_drcuml;
|
std::unique_ptr<drcuml_state> m_drcuml;
|
||||||
std::unique_ptr<dspp_frontend> m_drcfe;
|
std::unique_ptr<dspp_frontend> m_drcfe;
|
||||||
uint32_t m_drcoptions;
|
uint32_t m_drcoptions;
|
||||||
|
|
||||||
/* internal compiler state */
|
/* internal compiler state */
|
||||||
struct compiler_state
|
struct compiler_state
|
||||||
@ -275,12 +275,12 @@ public: // TODO
|
|||||||
void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name);
|
void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name);
|
||||||
void load_fast_iregs(drcuml_block &block);
|
void load_fast_iregs(drcuml_block &block);
|
||||||
void save_fast_iregs(drcuml_block &block);
|
void save_fast_iregs(drcuml_block &block);
|
||||||
// void arm7_drc_init();
|
// void arm7_drc_init();
|
||||||
// void arm7_drc_exit();
|
// void arm7_drc_exit();
|
||||||
void execute_run_drc();
|
void execute_run_drc();
|
||||||
// void arm7drc_set_options(uint32_t options);
|
// void arm7drc_set_options(uint32_t options);
|
||||||
// void arm7drc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base);
|
// void arm7drc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base);
|
||||||
// void arm7drc_add_hotspot(offs_t pc, uint32_t opcode, uint32_t cycles);
|
// void arm7drc_add_hotspot(offs_t pc, uint32_t opcode, uint32_t cycles);
|
||||||
void flush_cache();
|
void flush_cache();
|
||||||
void compile_block(offs_t pc);
|
void compile_block(offs_t pc);
|
||||||
void cfunc_get_cycles();
|
void cfunc_get_cycles();
|
||||||
|
@ -23,7 +23,7 @@ using namespace uml;
|
|||||||
// map variables
|
// map variables
|
||||||
#define MAPVAR_PC M0
|
#define MAPVAR_PC M0
|
||||||
#define MAPVAR_CYCLES M1
|
#define MAPVAR_CYCLES M1
|
||||||
#define MAPVAR_ACC M2
|
#define MAPVAR_ACC M2
|
||||||
|
|
||||||
// exit codes
|
// exit codes
|
||||||
#define EXECUTE_OUT_OF_CYCLES 0
|
#define EXECUTE_OUT_OF_CYCLES 0
|
||||||
@ -59,8 +59,8 @@ static void cfunc_unimplemented(void *param)
|
|||||||
|
|
||||||
void dspp_device::cfunc_unimplemented()
|
void dspp_device::cfunc_unimplemented()
|
||||||
{
|
{
|
||||||
// uint64_t op = m_core->m_arg0;
|
// uint64_t op = m_core->m_arg0;
|
||||||
// fatalerror("PC=%08X: Unimplemented op %04X%08X\n", m_core->m_pc, (uint32_t)(op >> 32), (uint32_t)(op));
|
// fatalerror("PC=%08X: Unimplemented op %04X%08X\n", m_core->m_pc, (uint32_t)(op >> 32), (uint32_t)(op));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -408,7 +408,7 @@ void dspp_device::static_generate_entry_point()
|
|||||||
|
|
||||||
/* forward references */
|
/* forward references */
|
||||||
alloc_handle(m_drcuml.get(), &m_nocode, "nocode");
|
alloc_handle(m_drcuml.get(), &m_nocode, "nocode");
|
||||||
// alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt");
|
// alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt");
|
||||||
|
|
||||||
alloc_handle(m_drcuml.get(), &m_entry, "entry");
|
alloc_handle(m_drcuml.get(), &m_entry, "entry");
|
||||||
UML_HANDLE(block, *m_entry); // handle entry
|
UML_HANDLE(block, *m_entry); // handle entry
|
||||||
@ -427,11 +427,11 @@ void dspp_device::static_generate_entry_point()
|
|||||||
UML_JMPc(block, COND_Z, skip); // jz skip
|
UML_JMPc(block, COND_Z, skip); // jz skip
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// UML_MOV(block, I0, mem(&m_core->m_pc)); // mov i0,nextpc
|
// UML_MOV(block, I0, mem(&m_core->m_pc)); // mov i0,nextpc
|
||||||
// UML_MOV(block, I1, 0); // mov i1,0
|
// UML_MOV(block, I1, 0); // mov i1,0
|
||||||
// UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
|
// UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
|
||||||
|
|
||||||
// UML_LABEL(block, skip);
|
// UML_LABEL(block, skip);
|
||||||
|
|
||||||
/* generate a hash jump via the current mode and PC */
|
/* generate a hash jump via the current mode and PC */
|
||||||
UML_HASHJMP(block, 0, mem(&m_core->m_pc), *m_nocode); // hashjmp <mode>,<pc>,nocode
|
UML_HASHJMP(block, 0, mem(&m_core->m_pc), *m_nocode); // hashjmp <mode>,<pc>,nocode
|
||||||
@ -516,7 +516,7 @@ void dspp_device::generate_sequence_instruction(drcuml_block &block, compiler_st
|
|||||||
{
|
{
|
||||||
UML_MOV(block, mem(&m_core->m_pc), desc->pc); // mov [pc],desc->pc
|
UML_MOV(block, mem(&m_core->m_pc), desc->pc); // mov [pc],desc->pc
|
||||||
UML_DMOV(block, mem(&m_core->m_arg0), desc->opptr.q[0]); // dmov [m_arg0],*desc->opptr.q // FIXME
|
UML_DMOV(block, mem(&m_core->m_arg0), desc->opptr.q[0]); // dmov [m_arg0],*desc->opptr.q // FIXME
|
||||||
// UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
|
// UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -657,7 +657,7 @@ void adsp21062_device::generate_jump(drcuml_block &block, compiler_state *compil
|
|||||||
compiler->labelnum = compiler_temp.labelnum;
|
compiler->labelnum = compiler_temp.labelnum;
|
||||||
|
|
||||||
/* reset the mapvar to the current cycles and account for skipped slots */
|
/* reset the mapvar to the current cycles and account for skipped slots */
|
||||||
// compiler->cycles += desc->skipslots;
|
// compiler->cycles += desc->skipslots;
|
||||||
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
|
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -667,8 +667,8 @@ bool dspp_device::generate_complex_branch_opcode(drcuml_block &block, compiler_s
|
|||||||
|
|
||||||
code_label skip_label = compiler->labelnum++;
|
code_label skip_label = compiler->labelnum++;
|
||||||
|
|
||||||
// generate_branch_target(block, compiler, desc, op & 0x3ff, ef2);
|
// generate_branch_target(block, compiler, desc, op & 0x3ff, ef2);
|
||||||
// generate_condition(block, compiler, desc, ef1, true, skip_label, true);
|
// generate_condition(block, compiler, desc, ef1, true, skip_label, true);
|
||||||
generate_branch(block, compiler, desc);
|
generate_branch(block, compiler, desc);
|
||||||
UML_LABEL(block, skip_label);
|
UML_LABEL(block, skip_label);
|
||||||
|
|
||||||
@ -775,93 +775,93 @@ bool dspp_device::generate_arithmetic_opcode(drcuml_block &block, compiler_state
|
|||||||
// ACC_RESULT = I1?
|
// ACC_RESULT = I1?
|
||||||
switch (alu_op)
|
switch (alu_op)
|
||||||
{
|
{
|
||||||
case 0: // _TRA
|
case 0: // _TRA
|
||||||
// alu_res = alu_a;
|
// alu_res = alu_a;
|
||||||
UML_MOV(block, I2, I0);
|
UML_MOV(block, I2, I0);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 1: // _NEG
|
case 1: // _NEG
|
||||||
// alu_res = -alu_b;
|
// alu_res = -alu_b;
|
||||||
UML_SUB(block, I2, 0, I1);
|
UML_SUB(block, I2, 0, I1);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 2: // _+
|
case 2: // _+
|
||||||
// alu_res = alu_a + alu_b;
|
// alu_res = alu_a + alu_b;
|
||||||
UML_ADD(block, I2, I0, I1);
|
UML_ADD(block, I2, I0, I1);
|
||||||
|
|
||||||
// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
|
// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
|
||||||
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
// CC_V_MODIFIED(desc);
|
// CC_V_MODIFIED(desc);
|
||||||
// CC_C_MODIFIED(desc);
|
// CC_C_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 3: // _+C
|
case 3: // _+C
|
||||||
UML_ADD(block, I2, I0, mew);
|
UML_ADD(block, I2, I0, mew);
|
||||||
// alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
// alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
CC_C_USED(desc);
|
CC_C_USED(desc);
|
||||||
CC_C_MODIFIED(desc);
|
CC_C_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 4: // _-
|
case 4: // _-
|
||||||
// alu_res = alu_a - alu_b;
|
// alu_res = alu_a - alu_b;
|
||||||
UML_SUB(block, I2, I0, I1);
|
UML_SUB(block, I2, I0, I1);
|
||||||
|
|
||||||
// if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
|
// if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
|
||||||
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
CC_C_MODIFIED(desc);
|
CC_C_MODIFIED(desc);
|
||||||
CC_V_MODIFIED(desc);
|
CC_V_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 5: // _-B
|
case 5: // _-B
|
||||||
// alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
// alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
CC_C_USED(desc);
|
CC_C_USED(desc);
|
||||||
CC_C_MODIFIED(desc);
|
CC_C_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 6: // _++
|
case 6: // _++
|
||||||
UML_ADD(block, I2, I0, 1);
|
UML_ADD(block, I2, I0, 1);
|
||||||
// alu_res = alu_a + 1;
|
// alu_res = alu_a + 1;
|
||||||
|
|
||||||
// if (!(alu_a & 0x80000) && (alu_res & 0x80000))
|
// if (!(alu_a & 0x80000) && (alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
CC_V_MODIFIED(desc);
|
CC_V_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 7: // _--
|
case 7: // _--
|
||||||
// alu_res = alu_a - 1;
|
// alu_res = alu_a - 1;
|
||||||
UML_SUB(block, I2, I0, 1);
|
UML_SUB(block, I2, I0, 1);
|
||||||
|
|
||||||
// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
|
// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
CC_V_MODIFIED(desc);
|
CC_V_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 8: // _TRL
|
case 8: // _TRL
|
||||||
//alu_res = alu_a;
|
//alu_res = alu_a;
|
||||||
UML_MOV(block, I2, I0);
|
UML_MOV(block, I2, I0);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 9: // _NOT
|
case 9: // _NOT
|
||||||
//alu_res = ~alu_a;
|
//alu_res = ~alu_a;
|
||||||
UML_XOR(block, I2, I0, 0xffff);
|
UML_XOR(block, I2, I0, 0xffff);
|
||||||
break;
|
break;
|
||||||
@ -919,7 +919,7 @@ bool dspp_device::generate_arithmetic_opcode(drcuml_block &block, compiler_state
|
|||||||
if (alu_op < 8)
|
if (alu_op < 8)
|
||||||
{
|
{
|
||||||
// Arithmetic
|
// Arithmetic
|
||||||
// m_core->m_acc = sign_extend20(alu_res) >> shift;
|
// m_core->m_acc = sign_extend20(alu_res) >> shift;
|
||||||
|
|
||||||
// TODO: Sign Extend to 20-bits
|
// TODO: Sign Extend to 20-bits
|
||||||
UML_SHR(block, I2, I2, shift);
|
UML_SHR(block, I2, I2, shift);
|
||||||
@ -928,7 +928,7 @@ bool dspp_device::generate_arithmetic_opcode(drcuml_block &block, compiler_state
|
|||||||
else
|
else
|
||||||
{
|
{
|
||||||
// Logical
|
// Logical
|
||||||
// m_core->m_acc = (alu_res & 0xfffff) >> shift;
|
// m_core->m_acc = (alu_res & 0xfffff) >> shift;
|
||||||
UML_AND(block, I2, 0xfffff);
|
UML_AND(block, I2, 0xfffff);
|
||||||
UML_SHR(block, I2, I2, shift);
|
UML_SHR(block, I2, I2, shift);
|
||||||
UML_MAPVAR(block, MAPVAR_ACC, I2);
|
UML_MAPVAR(block, MAPVAR_ACC, I2);
|
||||||
|
@ -118,7 +118,7 @@ bool dspp_frontend::describe_special(uint16_t op, opcode_desc &desc)
|
|||||||
// Super-special
|
// Super-special
|
||||||
switch ((op >> 7) & 7)
|
switch ((op >> 7) & 7)
|
||||||
{
|
{
|
||||||
case 1: // BAC - TODO: MERGE?
|
case 1: // BAC - TODO: MERGE?
|
||||||
{
|
{
|
||||||
//desc.regin[0] = m_acc;
|
//desc.regin[0] = m_acc;
|
||||||
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
|
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
|
||||||
@ -167,8 +167,8 @@ bool dspp_frontend::describe_special(uint16_t op, opcode_desc &desc)
|
|||||||
case 3: // BFM
|
case 3: // BFM
|
||||||
{
|
{
|
||||||
// TODO: What sort of branch is this?
|
// TODO: What sort of branch is this?
|
||||||
// desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
|
// desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
|
||||||
// desc.targetpc = 0; // FIXME
|
// desc.targetpc = 0; // FIXME
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
case 4: // MOVEREG
|
case 4: // MOVEREG
|
||||||
@ -290,7 +290,7 @@ bool dspp_frontend::describe_arithmetic(uint16_t op, opcode_desc &desc)
|
|||||||
// Does it read memory?
|
// Does it read memory?
|
||||||
// Does it write memory?
|
// Does it write memory?
|
||||||
|
|
||||||
// parse_operands(numops);
|
// parse_operands(numops);
|
||||||
|
|
||||||
if (muxa == 3 || muxb == 3)
|
if (muxa == 3 || muxb == 3)
|
||||||
{
|
{
|
||||||
@ -349,94 +349,94 @@ bool dspp_frontend::describe_arithmetic(uint16_t op, opcode_desc &desc)
|
|||||||
|
|
||||||
switch (alu_op)
|
switch (alu_op)
|
||||||
{
|
{
|
||||||
case 0: // _TRA
|
case 0: // _TRA
|
||||||
{
|
{
|
||||||
// alu_res = alu_a;
|
// alu_res = alu_a;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 1: // _NEG
|
case 1: // _NEG
|
||||||
{
|
{
|
||||||
// alu_res = -alu_b;
|
// alu_res = -alu_b;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 2: // _+
|
case 2: // _+
|
||||||
{
|
{
|
||||||
// alu_res = alu_a + alu_b;
|
// alu_res = alu_a + alu_b;
|
||||||
|
|
||||||
// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
|
// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
|
||||||
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
// CC_V_MODIFIED(desc);
|
// CC_V_MODIFIED(desc);
|
||||||
// CC_C_MODIFIED(desc);
|
// CC_C_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 3: // _+C
|
case 3: // _+C
|
||||||
{
|
{
|
||||||
// alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
// alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
CC_C_USED(desc);
|
CC_C_USED(desc);
|
||||||
CC_C_MODIFIED(desc);
|
CC_C_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 4: // _-
|
case 4: // _-
|
||||||
{
|
{
|
||||||
// alu_res = alu_a - alu_b;
|
// alu_res = alu_a - alu_b;
|
||||||
|
|
||||||
// if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
|
// if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
|
||||||
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
// (alu_a & 0x80000) != (alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
CC_C_MODIFIED(desc);
|
CC_C_MODIFIED(desc);
|
||||||
CC_V_MODIFIED(desc);
|
CC_V_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 5: // _-B
|
case 5: // _-B
|
||||||
{
|
{
|
||||||
// alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
// alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
|
||||||
|
|
||||||
// if (alu_res & 0x00100000)
|
// if (alu_res & 0x00100000)
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
|
||||||
|
|
||||||
CC_C_USED(desc);
|
CC_C_USED(desc);
|
||||||
CC_C_MODIFIED(desc);
|
CC_C_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 6: // _++
|
case 6: // _++
|
||||||
{
|
{
|
||||||
// alu_res = alu_a + 1;
|
// alu_res = alu_a + 1;
|
||||||
|
|
||||||
// if (!(alu_a & 0x80000) && (alu_res & 0x80000))
|
// if (!(alu_a & 0x80000) && (alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
CC_V_MODIFIED(desc);
|
CC_V_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 7: // _--
|
case 7: // _--
|
||||||
{
|
{
|
||||||
// alu_res = alu_a - 1;
|
// alu_res = alu_a - 1;
|
||||||
|
|
||||||
// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
|
// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
|
||||||
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
// m_core->m_flags |= DSPI_FLAG_CC_OVER;
|
||||||
|
|
||||||
CC_V_MODIFIED(desc);
|
CC_V_MODIFIED(desc);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 8: // _TRL
|
case 8: // _TRL
|
||||||
{
|
{
|
||||||
//alu_res = alu_a;
|
//alu_res = alu_a;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 9: // _NOT
|
case 9: // _NOT
|
||||||
{
|
{
|
||||||
//alu_res = ~alu_a;
|
//alu_res = ~alu_a;
|
||||||
break;
|
break;
|
||||||
|
@ -173,7 +173,7 @@
|
|||||||
#define N_SHIFT 2
|
#define N_SHIFT 2
|
||||||
#define V_SHIFT 3
|
#define V_SHIFT 3
|
||||||
#define S_SHIFT 18
|
#define S_SHIFT 18
|
||||||
#define ILC_SHIFT 19
|
#define ILC_SHIFT 19
|
||||||
|
|
||||||
/* SR flags */
|
/* SR flags */
|
||||||
#define GET_C ( SR & C_MASK) // bit 0 //CARRY
|
#define GET_C ( SR & C_MASK) // bit 0 //CARRY
|
||||||
|
@ -2,19 +2,19 @@
|
|||||||
// copyright-holders:David Haywood
|
// copyright-holders:David Haywood
|
||||||
/*****************************************************************************
|
/*****************************************************************************
|
||||||
|
|
||||||
AXC51-CORE (AppoTech Inc.)
|
AXC51-CORE (AppoTech Inc.)
|
||||||
|
|
||||||
used in
|
used in
|
||||||
|
|
||||||
AX208 SoC
|
AX208 SoC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Notes:
|
Notes:
|
||||||
|
|
||||||
AX208:
|
AX208:
|
||||||
The CPU has a bootloader that sets a few things up + copies data to RAM
|
The CPU has a bootloader that sets a few things up + copies data to RAM
|
||||||
from the Flash meomry. This will need to be simulated.
|
from the Flash meomry. This will need to be simulated.
|
||||||
|
|
||||||
*****************************************************************************/
|
*****************************************************************************/
|
||||||
|
|
||||||
|
@ -2,11 +2,11 @@
|
|||||||
// copyright-holders:David Haywood
|
// copyright-holders:David Haywood
|
||||||
/*****************************************************************************
|
/*****************************************************************************
|
||||||
|
|
||||||
AXC51-CORE (AppoTech Inc.)
|
AXC51-CORE (AppoTech Inc.)
|
||||||
|
|
||||||
used in
|
used in
|
||||||
|
|
||||||
AX208 SoC
|
AX208 SoC
|
||||||
|
|
||||||
*****************************************************************************/
|
*****************************************************************************/
|
||||||
|
|
||||||
|
@ -2,11 +2,11 @@
|
|||||||
// copyright-holders:David Haywood
|
// copyright-holders:David Haywood
|
||||||
/*****************************************************************************
|
/*****************************************************************************
|
||||||
|
|
||||||
AXC51-CORE (AppoTech Inc.)
|
AXC51-CORE (AppoTech Inc.)
|
||||||
|
|
||||||
used in
|
used in
|
||||||
|
|
||||||
AX208 SoC
|
AX208 SoC
|
||||||
|
|
||||||
*****************************************************************************/
|
*****************************************************************************/
|
||||||
|
|
||||||
@ -17,12 +17,12 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
|
|
||||||
// SFR Registers
|
// SFR Registers
|
||||||
//0x80 -
|
//0x80 -
|
||||||
{ 0x81, "SP" }, // Stack Pointer
|
{ 0x81, "SP" }, // Stack Pointer
|
||||||
//0x82 -
|
//0x82 -
|
||||||
//0x83 -
|
//0x83 -
|
||||||
//0x84 -
|
//0x84 -
|
||||||
//0x85 -
|
//0x85 -
|
||||||
{ 0x86, "DPCON" }, // Data Pointer Configure Register
|
{ 0x86, "DPCON" }, // Data Pointer Configure Register
|
||||||
{ 0x87, "PCON0" }, // Power Control 0
|
{ 0x87, "PCON0" }, // Power Control 0
|
||||||
//0x88 -
|
//0x88 -
|
||||||
//0x89 -
|
//0x89 -
|
||||||
@ -37,7 +37,7 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
//0x92 -
|
//0x92 -
|
||||||
//0x93 -
|
//0x93 -
|
||||||
//0x94 -
|
//0x94 -
|
||||||
{ 0x95, "IE2" }, // Interrupt Enable 2
|
{ 0x95, "IE2" }, // Interrupt Enable 2
|
||||||
{ 0x96, "UARTBAUDH" }, // UART Baud (high)
|
{ 0x96, "UARTBAUDH" }, // UART Baud (high)
|
||||||
{ 0x97, "PWKEN" }, // Port Wakeup Enable
|
{ 0x97, "PWKEN" }, // Port Wakeup Enable
|
||||||
{ 0x98, "PWKPND" }, //Port Wakeup Flag
|
{ 0x98, "PWKPND" }, //Port Wakeup Flag
|
||||||
@ -54,14 +54,14 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
{ 0xA3, "GP2" }, // (General Purpose Register 2)
|
{ 0xA3, "GP2" }, // (General Purpose Register 2)
|
||||||
{ 0xA4, "GP3" }, // (General Purpose Register 3)
|
{ 0xA4, "GP3" }, // (General Purpose Register 3)
|
||||||
{ 0xA5, "DACCON" }, // DAC Control Register
|
{ 0xA5, "DACCON" }, // DAC Control Register
|
||||||
{ 0xA6, "DACLCH" }, // DAC Left Channel
|
{ 0xA6, "DACLCH" }, // DAC Left Channel
|
||||||
{ 0xA7, "DACRCH" }, // DAC Right Channel
|
{ 0xA7, "DACRCH" }, // DAC Right Channel
|
||||||
{ 0xA8, "IE0" }, // Interrupt Enable 0
|
{ 0xA8, "IE0" }, // Interrupt Enable 0
|
||||||
{ 0xA9, "IE1" }, // Interrupt Enable 1
|
{ 0xA9, "IE1" }, // Interrupt Enable 1
|
||||||
//0xAA -
|
//0xAA -
|
||||||
//0xAB -
|
//0xAB -
|
||||||
{ 0xAC, "TMR3CON" }, // Timer3 Control
|
{ 0xAC, "TMR3CON" }, // Timer3 Control
|
||||||
{ 0xAD, "TMR3CNT" }, // Timer3 Counter
|
{ 0xAD, "TMR3CNT" }, // Timer3 Counter
|
||||||
{ 0xAE, "TMR3PR" }, // Timer3 Period
|
{ 0xAE, "TMR3PR" }, // Timer3 Period
|
||||||
{ 0xAF, "TMR3PSR" }, // Timer3 Pre-scalar
|
{ 0xAF, "TMR3PSR" }, // Timer3 Pre-scalar
|
||||||
//0xB0 -
|
//0xB0 -
|
||||||
@ -87,25 +87,25 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
//0xC4 -
|
//0xC4 -
|
||||||
//0xC5 -
|
//0xC5 -
|
||||||
//0xC6 -
|
//0xC6 -
|
||||||
{ 0xC7, "LCDPR" }, // LCD CS Pulse Width Register
|
{ 0xC7, "LCDPR" }, // LCD CS Pulse Width Register
|
||||||
{ 0xC8, "LCDTCON" }, // LCD WR Pulse Timing Control Register
|
{ 0xC8, "LCDTCON" }, // LCD WR Pulse Timing Control Register
|
||||||
//0xC9 -
|
//0xC9 -
|
||||||
//0xCA -
|
//0xCA -
|
||||||
//0xCB -
|
//0xCB -
|
||||||
//0xCC -
|
//0xCC -
|
||||||
//0xCD -
|
//0xCD -
|
||||||
//0xCE -
|
//0xCE -
|
||||||
{ 0xCF, "MICCON" }, // MIC Control
|
{ 0xCF, "MICCON" }, // MIC Control
|
||||||
{ 0xD0, "PSW" }, // Processor Status Word
|
{ 0xD0, "PSW" }, // Processor Status Word
|
||||||
{ 0xD1, "PGCON" }, // Power Gate Control Register
|
{ 0xD1, "PGCON" }, // Power Gate Control Register
|
||||||
{ 0xD2, "ADCCON" }, // SARADC Control
|
{ 0xD2, "ADCCON" }, // SARADC Control
|
||||||
{ 0xD3, "PCON2" }, // Power Control 2
|
{ 0xD3, "PCON2" }, // Power Control 2
|
||||||
{ 0xD4, "ADCDATAL" }, // SARADC Buffer Low Byte Control
|
{ 0xD4, "ADCDATAL" }, // SARADC Buffer Low Byte Control
|
||||||
{ 0xD5, "ADCDATAH" }, // SARADC Buffer High Byte Control
|
{ 0xD5, "ADCDATAH" }, // SARADC Buffer High Byte Control
|
||||||
{ 0xD6, "SPIDMAADDR" }, // SPI DMA Start Address
|
{ 0xD6, "SPIDMAADDR" }, // SPI DMA Start Address
|
||||||
{ 0xD7, "SPIDMACNT" }, // SPI DMA counter
|
{ 0xD7, "SPIDMACNT" }, // SPI DMA counter
|
||||||
{ 0xD8, "SPICON" }, // SPI Control
|
{ 0xD8, "SPICON" }, // SPI Control
|
||||||
{ 0xD9, "SPIBUF" }, // SPI Data Buffer
|
{ 0xD9, "SPIBUF" }, // SPI Data Buffer
|
||||||
{ 0xDA, "SPIBAUD" }, // SPI Baud Rate
|
{ 0xDA, "SPIBAUD" }, // SPI Baud Rate
|
||||||
{ 0xDB, "CLKCON" }, // Clock Control
|
{ 0xDB, "CLKCON" }, // Clock Control
|
||||||
// 0xDC -
|
// 0xDC -
|
||||||
@ -122,7 +122,7 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
{ 0xE7, "ER01" }, // ER01 /
|
{ 0xE7, "ER01" }, // ER01 /
|
||||||
{ 0xE8, "ER10" }, // ER10 \- ER1 (16-bit)
|
{ 0xE8, "ER10" }, // ER10 \- ER1 (16-bit)
|
||||||
{ 0xE9, "ER11" }, // ER11 /
|
{ 0xE9, "ER11" }, // ER11 /
|
||||||
{ 0XEA, "ER20" }, // ER20 \- ER2 (16-bit)
|
{ 0xEA, "ER20" }, // ER20 \- ER2 (16-bit)
|
||||||
{ 0xEB, "ER21" }, // ER21 /
|
{ 0xEB, "ER21" }, // ER21 /
|
||||||
{ 0xEC, "ER30" }, // ER30 \- ER3 (16-bit)
|
{ 0xEC, "ER30" }, // ER30 \- ER3 (16-bit)
|
||||||
{ 0xED, "ER31" }, // ER31 /
|
{ 0xED, "ER31" }, // ER31 /
|
||||||
@ -138,12 +138,12 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
{ 0xF7, "WDTCON" }, // Watchdog Control
|
{ 0xF7, "WDTCON" }, // Watchdog Control
|
||||||
{ 0xF8, "TMR0CON" }, // Timer0 Control
|
{ 0xF8, "TMR0CON" }, // Timer0 Control
|
||||||
{ 0xF9, "TMR0CNT" }, // Timer0 Counter
|
{ 0xF9, "TMR0CNT" }, // Timer0 Counter
|
||||||
{ 0xFA, "TMR0PR" }, // Timer0 Period
|
{ 0xFA, "TMR0PR" }, // Timer0 Period
|
||||||
{ 0xFB, "TMR0PSR" }, // Timer0 Pre-scalar
|
{ 0xFB, "TMR0PSR" }, // Timer0 Pre-scalar
|
||||||
{ 0xFC, "UARTSTA" }, // UART Status
|
{ 0xFC, "UARTSTA" }, // UART Status
|
||||||
{ 0xFD, "UARTCON" }, // UART Control
|
{ 0xFD, "UARTCON" }, // UART Control
|
||||||
{ 0xFE, "UARTBAUD" }, // UART Baud (low)
|
{ 0xFE, "UARTBAUD" }, // UART Baud (low)
|
||||||
{ 0xFF, "UARTDATA" }, // UART Communication Data
|
{ 0xFF, "UARTDATA" }, // UART Communication Data
|
||||||
|
|
||||||
// Upper Registers
|
// Upper Registers
|
||||||
|
|
||||||
@ -163,7 +163,7 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
|
|||||||
|
|
||||||
{ 0x3040, "ADCBAUD" }, //S ARADC Baud
|
{ 0x3040, "ADCBAUD" }, //S ARADC Baud
|
||||||
|
|
||||||
{ 0x3070, "DACPTR" }, // DAC DMA Pointer
|
{ 0x3070, "DACPTR" }, // DAC DMA Pointer
|
||||||
{ 0x3071, "DACCNT" }, // DAC DMA Counter
|
{ 0x3071, "DACCNT" }, // DAC DMA Counter
|
||||||
|
|
||||||
{ -1 }
|
{ -1 }
|
||||||
@ -175,104 +175,104 @@ axc51core_disassembler::axc51core_disassembler() : mcs51_disassembler(axc51core_
|
|||||||
/* Extended 16-bit Opcodes
|
/* Extended 16-bit Opcodes
|
||||||
|
|
||||||
Opcode/params | Operation | Flags touched
|
Opcode/params | Operation | Flags touched
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
INCDPi | |
|
INCDPi | |
|
||||||
| DPTRi = DPTRi + 1 |
|
| DPTRi = DPTRi + 1 |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
DECDPi | |
|
DECDPi | |
|
||||||
| DPTRi = DPTRi - 1 |
|
| DPTRi = DPTRi - 1 |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ADDDPi | |
|
ADDDPi | |
|
||||||
| DPTRi = DPTRi + {R8, B} |
|
| DPTRi = DPTRi + {R8, B} |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
SUBDPi | |
|
SUBDPi | |
|
||||||
| DPTRi = DPTRi - {R8, B} |
|
| DPTRi = DPTRi - {R8, B} |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
INC2DPi | |
|
INC2DPi | |
|
||||||
| DPTRi = DPTRi + 2 |
|
| DPTRi = DPTRi + 2 |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
DEC2DPi | |
|
DEC2DPi | |
|
||||||
| DPTRi = DPTRi - 2 |
|
| DPTRi = DPTRi - 2 |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ROTR8 | |
|
ROTR8 | |
|
||||||
EACC, ER8 | Rotate Right ACC by R8 &0x3 bits |
|
EACC, ER8 | Rotate Right ACC by R8 &0x3 bits |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ROTL8 | |
|
ROTL8 | |
|
||||||
EACC, ER8 | Rotate Left ACC by R8 &0x3 bits |
|
EACC, ER8 | Rotate Left ACC by R8 &0x3 bits |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ADD16 | |
|
ADD16 | |
|
||||||
ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
|
ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
|
||||||
DPTRi, ERn, ERp | XRAM = ERn + ERp + EC |
|
DPTRi, ERn, ERp | XRAM = ERn + ERp + EC |
|
||||||
ERp, ERn, ERm | ERp = ERn + ERm + EC |
|
ERp, ERn, ERm | ERp = ERn + ERm + EC |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
SUB16 | |
|
SUB16 | |
|
||||||
ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
|
ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
|
||||||
DPTRi, ERn, ERp | XRAM = ERn - ERp - EC |
|
DPTRi, ERn, ERp | XRAM = ERn - ERp - EC |
|
||||||
ERp, ERn, ERm | ERp = ERn - ERm - EC |
|
ERp, ERn, ERm | ERp = ERn - ERm - EC |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
NOT16 | |
|
NOT16 | |
|
||||||
ERn | ERn = ~ERn |
|
ERn | ERn = ~ERn |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
CLR16 | |
|
CLR16 | |
|
||||||
ERn | ERn = 0 |
|
ERn | ERn = 0 |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
INC16 | |
|
INC16 | |
|
||||||
ERn | ERn = ERn + 1 | EZ
|
ERn | ERn = ERn + 1 | EZ
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
DEC16 | |
|
DEC16 | |
|
||||||
ERn | ERn = ERn - 1 | EZ
|
ERn | ERn = ERn - 1 | EZ
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ANL16 | |
|
ANL16 | |
|
||||||
ERn, DPTRi | ERn = XRAM & ERn | EZ
|
ERn, DPTRi | ERn = XRAM & ERn | EZ
|
||||||
DPTRi, ERn | XRAM = XRAM & ERn |
|
DPTRi, ERn | XRAM = XRAM & ERn |
|
||||||
ERn, ERm | ERn = ERn & ERm |
|
ERn, ERm | ERn = ERn & ERm |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ORL16 | |
|
ORL16 | |
|
||||||
ERn, DPTRi | ERn = XRAM | ERn | EZ
|
ERn, DPTRi | ERn = XRAM | ERn | EZ
|
||||||
DPTRi, ERn | XRAM = XRAM | ERn |
|
DPTRi, ERn | XRAM = XRAM | ERn |
|
||||||
ERn, ERm | ERn = ERn | ERm |
|
ERn, ERm | ERn = ERn | ERm |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
XRL16 | |
|
XRL16 | |
|
||||||
ERn, DPTRi | ERn = XRAM ^ ERn | EZ
|
ERn, DPTRi | ERn = XRAM ^ ERn | EZ
|
||||||
DPTRi, ERn | XRAM = XRAM ^ ERn |
|
DPTRi, ERn | XRAM = XRAM ^ ERn |
|
||||||
ERn, ERm | ERn = ERn ^ ERm |
|
ERn, ERm | ERn = ERn ^ ERm |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
MOV16 | |
|
MOV16 | |
|
||||||
ERn, DPTRi | ERn = XRAM | EZ
|
ERn, DPTRi | ERn = XRAM | EZ
|
||||||
DPTRi, ERn | XRAM = ERn |
|
DPTRi, ERn | XRAM = ERn |
|
||||||
ERn, ERm | ERn = ERm |
|
ERn, ERm | ERn = ERm |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
MUL16 (signed) | |
|
MUL16 (signed) | |
|
||||||
ERn, ERm | {ERn, ERm} = ERn * ERm |
|
ERn, ERm | {ERn, ERm} = ERn * ERm |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
MULS16 (sign, satur) | |
|
MULS16 (sign, satur) | |
|
||||||
ERn, ERm | {ERn, ERm} = ERn * ERm |
|
ERn, ERm | {ERn, ERm} = ERn * ERm |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ROTR16 | |
|
ROTR16 | |
|
||||||
ERn, ER8 | Rotate Right ERn by ER8 & 0xf bits |
|
ERn, ER8 | Rotate Right ERn by ER8 & 0xf bits |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ROTL16 | |
|
ROTL16 | |
|
||||||
ERn, ER8 | Rotate Left ERn by ER8 & 0xf bits |
|
ERn, ER8 | Rotate Left ERn by ER8 & 0xf bits |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
SHIFTL (lsl) | |
|
SHIFTL (lsl) | |
|
||||||
ERn, ER8 | ERn = ERn >> (ER8 & 0xf) |
|
ERn, ER8 | ERn = ERn >> (ER8 & 0xf) |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
SHIFTR (asr) | |
|
SHIFTR (asr) | |
|
||||||
ERn, ER8 | ERn = ERn >> (ER8 & 0xf) |
|
ERn, ER8 | ERn = ERn >> (ER8 & 0xf) |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
ADD16 (saturate) | |
|
ADD16 (saturate) | |
|
||||||
ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
|
ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
|
||||||
DPTRi, ERn, ERp | XRAM = ERn + ERp + EC |
|
DPTRi, ERn, ERp | XRAM = ERn + ERp + EC |
|
||||||
ERp, ERn, ERm | ERp = ERn + ERm + EC |
|
ERp, ERn, ERm | ERp = ERn + ERm + EC |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
SUB16 (saturate) | |
|
SUB16 (saturate) | |
|
||||||
ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
|
ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
|
||||||
DPTRi, ERn, ERp | XRAM = ERn - ERp - EC |
|
DPTRi, ERn, ERp | XRAM = ERn - ERp - EC |
|
||||||
ERp, ERn, ERm | ERp = ERn - ERm - EC |
|
ERp, ERn, ERm | ERp = ERn - ERm - EC |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
SWAP16 | |
|
SWAP16 | |
|
||||||
ERn | Swap upper and lower 8-bits of ERn |
|
ERn | Swap upper and lower 8-bits of ERn |
|
||||||
----------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
access to 16-bit registers is mapped in SFR space, from 0xE6 (note, changing SFR bank does NOT update the actual registers)
|
access to 16-bit registers is mapped in SFR space, from 0xE6 (note, changing SFR bank does NOT update the actual registers)
|
||||||
|
|
||||||
|
@ -2,11 +2,11 @@
|
|||||||
// copyright-holders:David Haywood
|
// copyright-holders:David Haywood
|
||||||
/*****************************************************************************
|
/*****************************************************************************
|
||||||
|
|
||||||
AXC51-CORE (AppoTech Inc.)
|
AXC51-CORE (AppoTech Inc.)
|
||||||
|
|
||||||
used in
|
used in
|
||||||
|
|
||||||
AX208 SoC
|
AX208 SoC
|
||||||
|
|
||||||
*****************************************************************************/
|
*****************************************************************************/
|
||||||
|
|
||||||
|
@ -303,10 +303,10 @@ enum
|
|||||||
#define MSR603_TGPR 0x00020000 /* Temporary GPR Remapping */
|
#define MSR603_TGPR 0x00020000 /* Temporary GPR Remapping */
|
||||||
|
|
||||||
/* ESA Save and Restore Register bits - 602 */
|
/* ESA Save and Restore Register bits - 602 */
|
||||||
#define SPR602_ESASRR_EE 0x00000001 /* External Interrupt Enable */
|
#define SPR602_ESASRR_EE 0x00000001 /* External Interrupt Enable */
|
||||||
#define SPR602_ESASRR_SA 0x00000002 /* Supervisor access mode */
|
#define SPR602_ESASRR_SA 0x00000002 /* Supervisor access mode */
|
||||||
#define SPR602_ESASRR_AP 0x00000004 /* Access privilege state */
|
#define SPR602_ESASRR_AP 0x00000004 /* Access privilege state */
|
||||||
#define SPR602_ESASRR_PR 0x00000008 /* Privilege Level */
|
#define SPR602_ESASRR_PR 0x00000008 /* Privilege Level */
|
||||||
|
|
||||||
/* DSISR bits for DSI/alignment exceptions */
|
/* DSISR bits for DSI/alignment exceptions */
|
||||||
#define DSISR_DIRECT 0x80000000 /* DSI: direct-store error interrupt */
|
#define DSISR_DIRECT 0x80000000 /* DSI: direct-store error interrupt */
|
||||||
|
@ -578,7 +578,7 @@ static void cfunc_ppccom_mismatch(void *param)
|
|||||||
|
|
||||||
void ppc_device::ppc_cfunc_ppccom_mismatch()
|
void ppc_device::ppc_cfunc_ppccom_mismatch()
|
||||||
{
|
{
|
||||||
// printf("cfunc_ppccom_mismatch %08X\n", m_core->pc);
|
// printf("cfunc_ppccom_mismatch %08X\n", m_core->pc);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void cfunc_ppccom_tlb_fill(void *param)
|
static void cfunc_ppccom_tlb_fill(void *param)
|
||||||
|
@ -27,11 +27,11 @@
|
|||||||
ND - unknown - Wireless Air 60
|
ND - unknown - Wireless Air 60
|
||||||
ND - Likely many more
|
ND - Likely many more
|
||||||
|
|
||||||
Also on this hardware:
|
Also on this hardware:
|
||||||
|
|
||||||
name PCB ID ROM width TSOP pads ROM size SEEPROM die markings
|
name PCB ID ROM width TSOP pads ROM size SEEPROM die markings
|
||||||
Radica Play TV Football 2 L7278 x16 48 not dumped no Sunplus
|
Radica Play TV Football 2 L7278 x16 48 not dumped no Sunplus
|
||||||
Dream Life ? x16 48 not dumped no Sunplus
|
Dream Life ? x16 48 not dumped no Sunplus
|
||||||
|
|
||||||
**********************************************************************/
|
**********************************************************************/
|
||||||
|
|
||||||
|
@ -797,8 +797,8 @@ void t10mmc::WriteData( uint8_t *data, int dataLength )
|
|||||||
m_device->logerror("Ch 1 route: %x vol: %x\n", data[10], data[11]);
|
m_device->logerror("Ch 1 route: %x vol: %x\n", data[10], data[11]);
|
||||||
m_device->logerror("Ch 2 route: %x vol: %x\n", data[12], data[13]);
|
m_device->logerror("Ch 2 route: %x vol: %x\n", data[12], data[13]);
|
||||||
m_device->logerror("Ch 3 route: %x vol: %x\n", data[14], data[15]);
|
m_device->logerror("Ch 3 route: %x vol: %x\n", data[14], data[15]);
|
||||||
m_cdda->set_output_gain(0, data[17] ? 1.0f : 0.0f);
|
m_cdda->set_output_gain(0, data[17] ? 1.0f : 0.0f);
|
||||||
m_cdda->set_output_gain(1, data[19] ? 1.0f : 0.0f);
|
m_cdda->set_output_gain(1, data[19] ? 1.0f : 0.0f);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -160,7 +160,7 @@ void SCSPDSP::Step()
|
|||||||
else if (IRA <= 0x2F)
|
else if (IRA <= 0x2F)
|
||||||
INPUTS = MIXS[IRA - 0x20] << 4; //MIXS is 20 bit
|
INPUTS = MIXS[IRA - 0x20] << 4; //MIXS is 20 bit
|
||||||
else if (IRA <= 0x31)
|
else if (IRA <= 0x31)
|
||||||
INPUTS = EXTS[IRA - 0x30] << 8; //EXTS is 16 bit
|
INPUTS = EXTS[IRA - 0x30] << 8; //EXTS is 16 bit
|
||||||
else
|
else
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
@ -117,7 +117,7 @@
|
|||||||
offset is o << 10. There are no alignment issues, e.g. you can have
|
offset is o << 10. There are no alignment issues, e.g. you can have
|
||||||
a buffer at 0x28000 which is 0x10000 samples long.
|
a buffer at 0x28000 which is 0x10000 samples long.
|
||||||
|
|
||||||
|
|
||||||
fp<nnn> fixed point 2.14 value associated with instruction nnn
|
fp<nnn> fixed point 2.14 value associated with instruction nnn
|
||||||
of<nn> 16-bits offset associated with instruction 3*nn
|
of<nn> 16-bits offset associated with instruction 3*nn
|
||||||
lfo<nn> LFO registers
|
lfo<nn> LFO registers
|
||||||
@ -561,7 +561,7 @@ u16 swp30_device::freq_r(offs_t offset)
|
|||||||
void swp30_device::freq_w(offs_t offset, u16 data)
|
void swp30_device::freq_w(offs_t offset, u16 data)
|
||||||
{
|
{
|
||||||
u8 chan = offset >> 6;
|
u8 chan = offset >> 6;
|
||||||
// delta is 4*256 per octave, positive means higher freq, e.g 4.10 format.
|
// delta is 4*256 per octave, positive means higher freq, e.g 4.10 format.
|
||||||
s16 v = data & 0x2000 ? data | 0xc000 : data;
|
s16 v = data & 0x2000 ? data | 0xc000 : data;
|
||||||
if(0 && m_freq[chan] != data)
|
if(0 && m_freq[chan] != data)
|
||||||
logerror("snd chan %02x freq %c%c %d.%03x\n", chan, data & 0x8000 ? '#' : '.', data & 0x4000 ? '#' : '.', v / 1024, (v < 0 ? -v : v) & 0x3ff);
|
logerror("snd chan %02x freq %c%c %d.%03x\n", chan, data & 0x8000 ? '#' : '.', data & 0x4000 ? '#' : '.', v / 1024, (v < 0 ? -v : v) & 0x3ff);
|
||||||
@ -697,8 +697,8 @@ template<int sel> void swp30_device::prg_lfo_w(offs_t offset, u16 data)
|
|||||||
offs_t adr = (offset >> 6)*2 + sel;
|
offs_t adr = (offset >> 6)*2 + sel;
|
||||||
m_program_plfo[adr] = data;
|
m_program_plfo[adr] = data;
|
||||||
|
|
||||||
static const int dt[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 };
|
static const int dt[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 };
|
||||||
static const int sh[8] = { 0, 0, 1, 2, 3, 4, 5, 6 };
|
static const int sh[8] = { 0, 0, 1, 2, 3, 4, 5, 6 };
|
||||||
|
|
||||||
int scale = (data >> 5) & 7;
|
int scale = (data >> 5) & 7;
|
||||||
int step = ((data & 31) << sh[scale]) + dt[scale];
|
int step = ((data & 31) << sh[scale]) + dt[scale];
|
||||||
|
@ -18,7 +18,7 @@
|
|||||||
//**************************************************************************
|
//**************************************************************************
|
||||||
|
|
||||||
#define I82730_UPDATE_ROW(name) \
|
#define I82730_UPDATE_ROW(name) \
|
||||||
void name(bitmap_rgb32 &bitmap, uint16_t *data, uint8_t lc, uint16_t y, int x_count)
|
void name(bitmap_rgb32 &bitmap, uint16_t *data, uint8_t lc, uint16_t y, int x_count)
|
||||||
|
|
||||||
// ======================> i82730_device
|
// ======================> i82730_device
|
||||||
|
|
||||||
|
@ -638,9 +638,9 @@ void mario_state::masao_sound_map(address_map &map)
|
|||||||
void mario_state::mario_audio(machine_config &config)
|
void mario_state::mario_audio(machine_config &config)
|
||||||
{
|
{
|
||||||
#if USE_8039
|
#if USE_8039
|
||||||
i8039_device &audiocpu(I8039(config, "audiocpu", I8035_CLOCK)); /* 730 kHz */
|
i8039_device &audiocpu(I8039(config, "audiocpu", I8035_CLOCK)); /* 730 kHz */
|
||||||
#else
|
#else
|
||||||
m58715_device &audiocpu(M58715(config, m_audiocpu, I8035_CLOCK)); /* 730 kHz */
|
m58715_device &audiocpu(M58715(config, m_audiocpu, I8035_CLOCK)); /* 730 kHz */
|
||||||
#endif
|
#endif
|
||||||
audiocpu.set_addrmap(AS_PROGRAM, &mario_state::mario_sound_map);
|
audiocpu.set_addrmap(AS_PROGRAM, &mario_state::mario_sound_map);
|
||||||
audiocpu.set_addrmap(AS_IO, &mario_state::mario_sound_io_map);
|
audiocpu.set_addrmap(AS_IO, &mario_state::mario_sound_io_map);
|
||||||
|
@ -2279,7 +2279,7 @@ ROM_END
|
|||||||
-Pin 11 : CHANNEL A
|
-Pin 11 : CHANNEL A
|
||||||
-Pin 12 : CHANNEL B
|
-Pin 12 : CHANNEL B
|
||||||
-Pin 13 : key (unused)
|
-Pin 13 : key (unused)
|
||||||
-Pin 14 : GND
|
-Pin 14 : GND
|
||||||
*/
|
*/
|
||||||
ROM_START( triviaes4 )
|
ROM_START( triviaes4 )
|
||||||
ROM_REGION( 0x20000, "maincpu", 0 ) // all 27256, ROM loading order probably wrong
|
ROM_REGION( 0x20000, "maincpu", 0 ) // all 27256, ROM loading order probably wrong
|
||||||
|
@ -766,7 +766,7 @@ ROM_START( darwin )
|
|||||||
|
|
||||||
// A PCB has been found with the first PROM substituted with a TBP28S42 (4b56a744) SHA1(5fdc336d90c8a289c146c66f241dd217fc11bf35), see brkthrut ROM loading for how they did it.
|
// A PCB has been found with the first PROM substituted with a TBP28S42 (4b56a744) SHA1(5fdc336d90c8a289c146c66f241dd217fc11bf35), see brkthrut ROM loading for how they did it.
|
||||||
// With that in mind, there's a one byte difference at 0x55 (0xf0 instead of 0x70). It is unknown if it's bitrot or if it's intended.
|
// With that in mind, there's a one byte difference at 0x55 (0xf0 instead of 0x70). It is unknown if it's bitrot or if it's intended.
|
||||||
ROM_REGION( 0x0200, "proms", 0 )
|
ROM_REGION( 0x0200, "proms", 0 )
|
||||||
ROM_LOAD( "df.12", 0x0000, 0x0100, CRC(89b952ef) SHA1(77dc4020a2e25f81fae1182d58993cf09d13af00) ) /* red and green component */
|
ROM_LOAD( "df.12", 0x0000, 0x0100, CRC(89b952ef) SHA1(77dc4020a2e25f81fae1182d58993cf09d13af00) ) /* red and green component */
|
||||||
ROM_LOAD( "df.13", 0x0100, 0x0100, CRC(d595e91d) SHA1(5e9793f6602455c79afdc855cd13183a7f48ab1e) ) /* blue component */
|
ROM_LOAD( "df.13", 0x0100, 0x0100, CRC(d595e91d) SHA1(5e9793f6602455c79afdc855cd13183a7f48ab1e) ) /* blue component */
|
||||||
|
|
||||||
|
@ -692,7 +692,7 @@ void esripsys_state::esripsys(machine_config &config)
|
|||||||
/* Video hardware */
|
/* Video hardware */
|
||||||
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
||||||
m_screen->set_raw(ESRIPSYS_PIXEL_CLOCK, ESRIPSYS_HTOTAL, ESRIPSYS_HBLANK_END, ESRIPSYS_HBLANK_START,
|
m_screen->set_raw(ESRIPSYS_PIXEL_CLOCK, ESRIPSYS_HTOTAL, ESRIPSYS_HBLANK_END, ESRIPSYS_HBLANK_START,
|
||||||
ESRIPSYS_VTOTAL, ESRIPSYS_VBLANK_END, ESRIPSYS_VBLANK_START);
|
ESRIPSYS_VTOTAL, ESRIPSYS_VBLANK_END, ESRIPSYS_VBLANK_START);
|
||||||
m_screen->set_screen_update(FUNC(esripsys_state::screen_update_esripsys));
|
m_screen->set_screen_update(FUNC(esripsys_state::screen_update_esripsys));
|
||||||
m_screen->set_video_attributes(VIDEO_ALWAYS_UPDATE);
|
m_screen->set_video_attributes(VIDEO_ALWAYS_UPDATE);
|
||||||
|
|
||||||
|
@ -129,7 +129,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(fastinvaders_state::scanline_timer)
|
|||||||
{
|
{
|
||||||
//logerror("scanline\n");
|
//logerror("scanline\n");
|
||||||
m_dma8257->dreq1_w(0x01);
|
m_dma8257->dreq1_w(0x01);
|
||||||
m_dma8257->hlda_w(1);
|
m_dma8257->hlda_w(1);
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
}
|
}
|
||||||
@ -204,7 +204,7 @@ WRITE8_MEMBER(fastinvaders_state::dark_2_clr)
|
|||||||
m_dma8257->dreq2_w(0x00);
|
m_dma8257->dreq2_w(0x00);
|
||||||
}
|
}
|
||||||
/* if (!data)
|
/* if (!data)
|
||||||
{
|
{
|
||||||
m_dma1 = 0;
|
m_dma1 = 0;
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
|
@ -4517,24 +4517,24 @@ ROM_END
|
|||||||
New Biliard 98
|
New Biliard 98
|
||||||
|
|
||||||
CPUs:
|
CPUs:
|
||||||
1x R65C02P2 u1 8-bit Microprocessor - main
|
1x R65C02P2 u1 8-bit Microprocessor - main
|
||||||
1x MC68B45P u8 CRT Controller (CRTC)
|
1x MC68B45P u8 CRT Controller (CRTC)
|
||||||
2x MC68B21CP u29, u30 Peripheral Interface Adapter
|
2x MC68B21CP u29, u30 Peripheral Interface Adapter
|
||||||
1x 89C10 u34 Programmable Sound Generator - sound
|
1x 89C10 u34 Programmable Sound Generator - sound
|
||||||
1x TDA2003 u33 Audio Amplifier - sound
|
1x TDA2003 u33 Audio Amplifier - sound
|
||||||
1x oscillator 16.000000MHz os1
|
1x oscillator 16.000000MHz os1
|
||||||
|
|
||||||
ROMs:
|
ROMs:
|
||||||
3x 27C256 u2, u20, u21 dumped
|
3x 27C256 u2, u20, u21 dumped
|
||||||
1x AM27S29PC u25 dumped
|
1x AM27S29PC u25 dumped
|
||||||
|
|
||||||
RAMs:
|
RAMs:
|
||||||
1x KM6264BL-10L-12 u13
|
1x KM6264BL-10L-12 u13
|
||||||
1x GM76C28A-10 u3
|
1x GM76C28A-10 u3
|
||||||
|
|
||||||
PLDs:
|
PLDs:
|
||||||
2x GAL20V8A-25LP u22, u23 read protected
|
2x GAL20V8A-25LP u22, u23 read protected
|
||||||
1x PALCE16V8H-15PC/4 u5 read protected
|
1x PALCE16V8H-15PC/4 u5 read protected
|
||||||
|
|
||||||
Others:
|
Others:
|
||||||
1x 28x2 JAMMA edge connector
|
1x 28x2 JAMMA edge connector
|
||||||
@ -4544,7 +4544,7 @@ ROM_END
|
|||||||
|
|
||||||
Notes:
|
Notes:
|
||||||
PCB is marked: "top" and "C.M.C. POOL 10" on component side
|
PCB is marked: "top" and "C.M.C. POOL 10" on component side
|
||||||
PCB is marked: "bottom" and "POOL 10 C.M.C" on solder side
|
PCB is marked: "bottom" and "POOL 10 C.M.C" on solder side
|
||||||
|
|
||||||
*/
|
*/
|
||||||
ROM_START( biliard )
|
ROM_START( biliard )
|
||||||
|
@ -799,8 +799,8 @@ WRITE8_MEMBER(goldstar_state::cm_coincount_w)
|
|||||||
machine().bookkeeping().coin_counter_w(3, data & 0x08); /* Counter 4 Coin D */
|
machine().bookkeeping().coin_counter_w(3, data & 0x08); /* Counter 4 Coin D */
|
||||||
machine().bookkeeping().coin_counter_w(4, data & 0x01); /* Counter 5 Payout */
|
machine().bookkeeping().coin_counter_w(4, data & 0x01); /* Counter 5 Payout */
|
||||||
|
|
||||||
// if (data & 0x86) // triggered by fb2010
|
// if (data & 0x86) // triggered by fb2010
|
||||||
// popmessage("counters: %02X", data);
|
// popmessage("counters: %02X", data);
|
||||||
}
|
}
|
||||||
|
|
||||||
void cmaster_state::cm_portmap(address_map &map)
|
void cmaster_state::cm_portmap(address_map &map)
|
||||||
@ -5057,125 +5057,125 @@ static INPUT_PORTS_START( fb2010 ) // hit 'start1' to init NVRAM for first time
|
|||||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
|
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
|
||||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats")
|
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats")
|
||||||
PORT_START("DSW1")
|
PORT_START("DSW1")
|
||||||
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:1")
|
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:1")
|
||||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:2")
|
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:2")
|
||||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
|
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
|
||||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:4")
|
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:4")
|
||||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:5")
|
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:5")
|
||||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:6")
|
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:6")
|
||||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:7")
|
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:7")
|
||||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
|
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
|
||||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_START("DSW2")
|
PORT_START("DSW2")
|
||||||
PORT_DIPNAME( 0x01, 0x01, "Double Up" ) PORT_DIPLOCATION("DSW2:1")
|
PORT_DIPNAME( 0x01, 0x01, "Double Up" ) PORT_DIPLOCATION("DSW2:1")
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x02, 0x02, "Skill Spin" ) PORT_DIPLOCATION("DSW2:2")
|
PORT_DIPNAME( 0x02, 0x02, "Skill Spin" ) PORT_DIPLOCATION("DSW2:2")
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:3")
|
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:3")
|
||||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:4")
|
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:4")
|
||||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:5")
|
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:5")
|
||||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:6")
|
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:6")
|
||||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:7")
|
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:7")
|
||||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
|
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
|
||||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_START("DSW3")
|
PORT_START("DSW3")
|
||||||
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:1")
|
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:1")
|
||||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:2")
|
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:2")
|
||||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:3")
|
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:3")
|
||||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:4")
|
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:4")
|
||||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:5")
|
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:5")
|
||||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:6")
|
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:6")
|
||||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:7")
|
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:7")
|
||||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:8")
|
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:8")
|
||||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_START("DSW4")
|
PORT_START("DSW4")
|
||||||
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:1")
|
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:1")
|
||||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:2")
|
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:2")
|
||||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:3")
|
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:3")
|
||||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:4")
|
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:4")
|
||||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:5")
|
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:5")
|
||||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:6")
|
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:6")
|
||||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7")
|
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7")
|
||||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:8")
|
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:8")
|
||||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_START("DSW5")
|
PORT_START("DSW5")
|
||||||
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:1")
|
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:1")
|
||||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:2")
|
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:2")
|
||||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:3")
|
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:3")
|
||||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x08, 0x08, "Show Odds / Title" ) PORT_DIPLOCATION("DSW5:4")
|
PORT_DIPNAME( 0x08, 0x08, "Show Odds / Title" ) PORT_DIPLOCATION("DSW5:4")
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:5")
|
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:5")
|
||||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:6")
|
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:6")
|
||||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:7")
|
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:7")
|
||||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x80, 0x80, "Show 'Game' Text" ) PORT_DIPLOCATION("DSW5:8") // causes corruption in D-Up game?
|
PORT_DIPNAME( 0x80, 0x80, "Show 'Game' Text" ) PORT_DIPLOCATION("DSW5:8") // causes corruption in D-Up game?
|
||||||
|
@ -692,7 +692,7 @@ static INPUT_PORTS_START( gsword )
|
|||||||
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) ) PORT_DIPLOCATION("A:2")
|
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) ) PORT_DIPLOCATION("A:2")
|
||||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||||
PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("A:3,4,5")
|
PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("A:3,4,5")
|
||||||
PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
|
PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
|
||||||
PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
|
PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
|
||||||
PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
|
PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
|
||||||
|
@ -1523,7 +1523,7 @@ void harddriv_state::driver_msp(machine_config &config)
|
|||||||
m_msp->set_pixel_clock(5000000);
|
m_msp->set_pixel_clock(5000000);
|
||||||
m_msp->set_pixels_per_clock(2);
|
m_msp->set_pixels_per_clock(2);
|
||||||
m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
|
m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
|
||||||
m_msp->set_screen("screen");
|
m_msp->set_screen("screen");
|
||||||
|
|
||||||
config.device_remove("slapstic");
|
config.device_remove("slapstic");
|
||||||
}
|
}
|
||||||
@ -1550,18 +1550,18 @@ void harddriv_state::multisync_nomsp(machine_config &config)
|
|||||||
/* Multisync board with MSP (used by Hard Drivin' compact) */
|
/* Multisync board with MSP (used by Hard Drivin' compact) */
|
||||||
void harddriv_state::multisync_msp(machine_config &config)
|
void harddriv_state::multisync_msp(machine_config &config)
|
||||||
{
|
{
|
||||||
multisync_nomsp(config);
|
multisync_nomsp(config);
|
||||||
|
|
||||||
/* basic machine hardware */
|
/* basic machine hardware */
|
||||||
TMS34010(config, m_msp, XTAL(50'000'000));
|
TMS34010(config, m_msp, XTAL(50'000'000));
|
||||||
m_msp->set_addrmap(AS_PROGRAM, &harddriv_state::driver_msp_map);
|
m_msp->set_addrmap(AS_PROGRAM, &harddriv_state::driver_msp_map);
|
||||||
m_msp->set_halt_on_reset(true);
|
m_msp->set_halt_on_reset(true);
|
||||||
m_msp->set_pixel_clock(5000000);
|
m_msp->set_pixel_clock(5000000);
|
||||||
m_msp->set_pixels_per_clock(2);
|
m_msp->set_pixels_per_clock(2);
|
||||||
m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
|
m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
|
||||||
m_msp->set_screen("screen");
|
m_msp->set_screen("screen");
|
||||||
|
|
||||||
config.device_remove("slapstic");
|
config.device_remove("slapstic");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -6121,19 +6121,19 @@ void bshipb_state::bshipb(machine_config &config)
|
|||||||
/* sound hardware */
|
/* sound hardware */
|
||||||
SPEAKER(config, "mono").front_center();
|
SPEAKER(config, "mono").front_center();
|
||||||
SN76477(config, m_sn);
|
SN76477(config, m_sn);
|
||||||
m_sn->set_noise_params(RES_K(47), RES_K(100), CAP_P(47)); // R18, R17, C8
|
m_sn->set_noise_params(RES_K(47), RES_K(100), CAP_P(47)); // R18, R17, C8
|
||||||
m_sn->set_decay_res(RES_M(3.3)); // R16
|
m_sn->set_decay_res(RES_M(3.3)); // R16
|
||||||
m_sn->set_attack_params(CAP_U(0.47), RES_K(15)); // C7, R20
|
m_sn->set_attack_params(CAP_U(0.47), RES_K(15)); // C7, R20
|
||||||
m_sn->set_amp_res(RES_K(100)); // R19
|
m_sn->set_amp_res(RES_K(100)); // R19
|
||||||
m_sn->set_feedback_res(RES_K(39)); // R7
|
m_sn->set_feedback_res(RES_K(39)); // R7
|
||||||
m_sn->set_vco_params(5.0 * RES_VOLTAGE_DIVIDER(RES_K(47), RES_K(33)), CAP_U(0.01), RES_K(270)); // R15/R14, C5, switchable R5/R3/R4
|
m_sn->set_vco_params(5.0 * RES_VOLTAGE_DIVIDER(RES_K(47), RES_K(33)), CAP_U(0.01), RES_K(270)); // R15/R14, C5, switchable R5/R3/R4
|
||||||
m_sn->set_pitch_voltage(5.0);
|
m_sn->set_pitch_voltage(5.0);
|
||||||
m_sn->set_slf_params(CAP_U(22), RES_K(750)); // switchable C4, switchable R13/R12
|
m_sn->set_slf_params(CAP_U(22), RES_K(750)); // switchable C4, switchable R13/R12
|
||||||
m_sn->set_oneshot_params(0, RES_INF); // NC, switchable R11
|
m_sn->set_oneshot_params(0, RES_INF); // NC, switchable R11
|
||||||
m_sn->set_vco_mode(0); // switchable
|
m_sn->set_vco_mode(0); // switchable
|
||||||
m_sn->set_mixer_params(0, 0, 0); // switchable, GND, GND
|
m_sn->set_mixer_params(0, 0, 0); // switchable, GND, GND
|
||||||
m_sn->set_envelope_params(1, 0); // Vreg, GND
|
m_sn->set_envelope_params(1, 0); // Vreg, GND
|
||||||
m_sn->set_enable(0); // switchable
|
m_sn->set_enable(0); // switchable
|
||||||
m_sn->add_route(ALL_OUTPUTS, "mono", 0.35);
|
m_sn->add_route(ALL_OUTPUTS, "mono", 0.35);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -531,8 +531,8 @@ void hikaru_state::hikaru(machine_config &config)
|
|||||||
|
|
||||||
PALETTE(config, "palette", 0x1000);
|
PALETTE(config, "palette", 0x1000);
|
||||||
|
|
||||||
// SPEAKER(config, "lspeaker").front_left();
|
// SPEAKER(config, "lspeaker").front_left();
|
||||||
// SPEAKER(config, "rspeaker").front_right();
|
// SPEAKER(config, "rspeaker").front_right();
|
||||||
|
|
||||||
// MCFG_DEVICE_ADD("aica", AICA, (XTAL(33'868'800)*2)/3) // 67.7376MHz(2*33.8688MHz), div 3 for audio block // 33.8688MHz on Board
|
// MCFG_DEVICE_ADD("aica", AICA, (XTAL(33'868'800)*2)/3) // 67.7376MHz(2*33.8688MHz), div 3 for audio block // 33.8688MHz on Board
|
||||||
// MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
|
// MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
|
||||||
|
@ -11,7 +11,7 @@
|
|||||||
*
|
*
|
||||||
* Current status : runs, AD LINK ERROR on stock ROM due to unimplemented AD link
|
* Current status : runs, AD LINK ERROR on stock ROM due to unimplemented AD link
|
||||||
* - patching the AD comms, we get to a mostly functional state (for patch examples,
|
* - patching the AD comms, we get to a mostly functional state (for patch examples,
|
||||||
* see https://github.com/fenugrec/hp3478a_rompatch )
|
* see https://github.com/fenugrec/hp3478a_rompatch )
|
||||||
*
|
*
|
||||||
* TODO
|
* TODO
|
||||||
* - split out LCD driver code. It seems common to other HP equipment of the
|
* - split out LCD driver code. It seems common to other HP equipment of the
|
||||||
@ -34,7 +34,7 @@ ROM : 2764 (64kbit, org 8kB)
|
|||||||
RAM : 5101 , 256 * 4bit (!), battery-backed calibration data
|
RAM : 5101 , 256 * 4bit (!), battery-backed calibration data
|
||||||
GPIB: i8291
|
GPIB: i8291
|
||||||
Display : unknown; similar protocol for HP 3457A documented on
|
Display : unknown; similar protocol for HP 3457A documented on
|
||||||
http://www.eevblog.com/forum/projects/led-display-for-hp-3457a-multimeter-i-did-it-)/25/
|
http://www.eevblog.com/forum/projects/led-display-for-hp-3457a-multimeter-i-did-it-)/25/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -47,7 +47,7 @@ P20 : disp.clk1
|
|||||||
P21 : !CS for GPIB, and disp.IWA
|
P21 : !CS for GPIB, and disp.IWA
|
||||||
P22 : !CS for DIPswitch; disp.ISA (for instructions)
|
P22 : !CS for DIPswitch; disp.ISA (for instructions)
|
||||||
P23 = !OE for RAM ; disp.sync (enable instruction)
|
P23 = !OE for RAM ; disp.sync (enable instruction)
|
||||||
P24 = disp.PWO (enable)
|
P24 = disp.PWO (enable)
|
||||||
P25 = disp.clk2
|
P25 = disp.clk2
|
||||||
P26 : address bit12 ! (0x1000) => hardware banking
|
P26 : address bit12 ! (0x1000) => hardware banking
|
||||||
P27 : data out thru isol, to analog CPU
|
P27 : data out thru isol, to analog CPU
|
||||||
@ -65,18 +65,18 @@ T1 : data in thru isol, from analog CPU (opcodes jt1 / jnt1)
|
|||||||
#define CPU_CLOCK XTAL(5'856'000)
|
#define CPU_CLOCK XTAL(5'856'000)
|
||||||
|
|
||||||
/* port pin/bit defs. Would be nice if mcs48.h had these */
|
/* port pin/bit defs. Would be nice if mcs48.h had these */
|
||||||
#define P20 (1 << 0)
|
#define P20 (1 << 0)
|
||||||
#define P21 (1 << 1)
|
#define P21 (1 << 1)
|
||||||
#define P22 (1 << 2)
|
#define P22 (1 << 2)
|
||||||
#define P23 (1 << 3)
|
#define P23 (1 << 3)
|
||||||
#define P24 (1 << 4)
|
#define P24 (1 << 4)
|
||||||
#define P25 (1 << 5)
|
#define P25 (1 << 5)
|
||||||
#define P26 (1 << 6)
|
#define P26 (1 << 6)
|
||||||
#define P27 (1 << 7)
|
#define P27 (1 << 7)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#define A12_PIN P26
|
#define A12_PIN P26
|
||||||
#define CALRAM_CS P23
|
#define CALRAM_CS P23
|
||||||
#define DIPSWITCH_CS P22
|
#define DIPSWITCH_CS P22
|
||||||
#define GPIB_CS P21
|
#define GPIB_CS P21
|
||||||
@ -87,7 +87,7 @@ T1 : data in thru isol, from analog CPU (opcodes jt1 / jnt1)
|
|||||||
#define DISP_IWA P21
|
#define DISP_IWA P21
|
||||||
#define DISP_CK1 P20
|
#define DISP_CK1 P20
|
||||||
//don't care about CK2 since it's supposed to be a delayed copy of CK1
|
//don't care about CK2 since it's supposed to be a delayed copy of CK1
|
||||||
#define DISP_MASK (DISP_PWO | DISP_SYNC | DISP_ISA | DISP_IWA | DISP_CK1) //used for edge detection
|
#define DISP_MASK (DISP_PWO | DISP_SYNC | DISP_ISA | DISP_IWA | DISP_CK1) //used for edge detection
|
||||||
|
|
||||||
// IO banking : indexes of m_iobank maps
|
// IO banking : indexes of m_iobank maps
|
||||||
#define CALRAM_ENTRY 0
|
#define CALRAM_ENTRY 0
|
||||||
@ -97,13 +97,13 @@ T1 : data in thru isol, from analog CPU (opcodes jt1 / jnt1)
|
|||||||
/**** optional debug outputs, must be before #include logmacro.*/
|
/**** optional debug outputs, must be before #include logmacro.*/
|
||||||
#define DEBUG_PORTS (LOG_GENERAL << 1)
|
#define DEBUG_PORTS (LOG_GENERAL << 1)
|
||||||
#define DEBUG_BANKING (LOG_GENERAL << 2)
|
#define DEBUG_BANKING (LOG_GENERAL << 2)
|
||||||
#define DEBUG_BUS (LOG_GENERAL << 3) //not used after all
|
#define DEBUG_BUS (LOG_GENERAL << 3) //not used after all
|
||||||
#define DEBUG_KEYPAD (LOG_GENERAL << 4)
|
#define DEBUG_KEYPAD (LOG_GENERAL << 4)
|
||||||
#define DEBUG_LCD (LOG_GENERAL << 5) //low level
|
#define DEBUG_LCD (LOG_GENERAL << 5) //low level
|
||||||
#define DEBUG_LCD2 (LOG_GENERAL << 6)
|
#define DEBUG_LCD2 (LOG_GENERAL << 6)
|
||||||
#define DEBUG_CAL (LOG_GENERAL << 7)
|
#define DEBUG_CAL (LOG_GENERAL << 7)
|
||||||
|
|
||||||
#define VERBOSE (DEBUG_BUS) //can be combined, like (DEBUG_CAL | DEBUG_KEYPAD)
|
#define VERBOSE (DEBUG_BUS) //can be combined, like (DEBUG_CAL | DEBUG_KEYPAD)
|
||||||
|
|
||||||
#include "logmacro.h"
|
#include "logmacro.h"
|
||||||
|
|
||||||
@ -130,7 +130,7 @@ public:
|
|||||||
|
|
||||||
protected:
|
protected:
|
||||||
virtual void machine_start() override;
|
virtual void machine_start() override;
|
||||||
//virtual void machine_reset() override; //not needed?
|
//virtual void machine_reset() override; //not needed?
|
||||||
|
|
||||||
DECLARE_READ8_MEMBER(p1read);
|
DECLARE_READ8_MEMBER(p1read);
|
||||||
DECLARE_WRITE8_MEMBER(p1write);
|
DECLARE_WRITE8_MEMBER(p1write);
|
||||||
@ -176,14 +176,14 @@ protected:
|
|||||||
REG_C,
|
REG_C,
|
||||||
DISCARD
|
DISCARD
|
||||||
} m_lcdiwa;
|
} m_lcdiwa;
|
||||||
uint8_t m_lcd_chrbuf[12]; //raw digits (not ASCII)
|
uint8_t m_lcd_chrbuf[12]; //raw digits (not ASCII)
|
||||||
uint8_t m_lcd_text[13]; //mapped to ASCII, only for debug output
|
uint8_t m_lcd_text[13]; //mapped to ASCII, only for debug output
|
||||||
uint32_t m_lcd_segdata[12];
|
uint32_t m_lcd_segdata[12];
|
||||||
///////////////////////////
|
///////////////////////////
|
||||||
|
|
||||||
|
|
||||||
uint8_t m_p2_oldstate; //used to detect edges on Port2 IO pins. Should be saveable ?
|
uint8_t m_p2_oldstate; //used to detect edges on Port2 IO pins. Should be saveable ?
|
||||||
uint8_t m_p1_oldstate; //for P17 edge detection (WDT reset)
|
uint8_t m_p1_oldstate; //for P17 edge detection (WDT reset)
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -200,7 +200,7 @@ READ8_MEMBER( hp3478a_state::p1read )
|
|||||||
// for each column, set Px=0 for pressed buttons (active low)
|
// for each column, set Px=0 for pressed buttons (active low)
|
||||||
for (i = 0; i < 4; i++) {
|
for (i = 0; i < 4; i++) {
|
||||||
if (!(data & (0x10 << i))) {
|
if (!(data & (0x10 << i))) {
|
||||||
data &= (0xF0 | m_keypad[i]->read()); //not sure if the undefined upper bits will read as 1 ?
|
data &= (0xF0 | m_keypad[i]->read()); //not sure if the undefined upper bits will read as 1 ?
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
LOGMASKED(DEBUG_KEYPAD, "port1 read: 0x%02X\n", data);
|
LOGMASKED(DEBUG_KEYPAD, "port1 read: 0x%02X\n", data);
|
||||||
@ -383,8 +383,8 @@ void hp3478a_state::lcd_map_chars()
|
|||||||
int i;
|
int i;
|
||||||
LOGMASKED(DEBUG_LCD2, "LCD : map ");
|
LOGMASKED(DEBUG_LCD2, "LCD : map ");
|
||||||
for (i=0; i < 12; i++) {
|
for (i=0; i < 12; i++) {
|
||||||
bool dp = m_lcd_chrbuf[i] & 0x40; //check decimal point. Needs to be mapped to seg_bit16
|
bool dp = m_lcd_chrbuf[i] & 0x40; //check decimal point. Needs to be mapped to seg_bit16
|
||||||
bool comma = m_lcd_chrbuf[i] & 0x80; //check comma, maps to seg17
|
bool comma = m_lcd_chrbuf[i] & 0x80; //check comma, maps to seg17
|
||||||
m_lcd_text[i] = (m_lcd_chrbuf[i] & 0x3F) + 0x40;
|
m_lcd_text[i] = (m_lcd_chrbuf[i] & 0x3F) + 0x40;
|
||||||
m_lcd_segdata[i] = hpcharset[m_lcd_chrbuf[i] & 0x3F] | (dp << 16) | (comma << 17);
|
m_lcd_segdata[i] = hpcharset[m_lcd_chrbuf[i] & 0x3F] | (dp << 16) | (comma << 17);
|
||||||
LOGMASKED(DEBUG_LCD2, "[%02X>%04X] ", m_lcd_chrbuf[i] & 0x3F, m_lcd_segdata[i]);
|
LOGMASKED(DEBUG_LCD2, "[%02X>%04X] ", m_lcd_chrbuf[i] & 0x3F, m_lcd_segdata[i]);
|
||||||
@ -399,10 +399,10 @@ uint32_t hp3478a_state::lcd_set_display(uint32_t segin)
|
|||||||
}
|
}
|
||||||
|
|
||||||
// ISA command bytes
|
// ISA command bytes
|
||||||
#define DISP_ISA_WANNUN 0xBC //annunciators
|
#define DISP_ISA_WANNUN 0xBC //annunciators
|
||||||
#define DISP_ISA_WA 0x0A //low nibbles
|
#define DISP_ISA_WA 0x0A //low nibbles
|
||||||
#define DISP_ISA_WB 0x1A //hi nib
|
#define DISP_ISA_WB 0x1A //hi nib
|
||||||
#define DISP_ISA_WC 0x2A // "extended bit" ?
|
#define DISP_ISA_WC 0x2A // "extended bit" ?
|
||||||
|
|
||||||
/** LCD serial interface state machine. I cheat and don't implement all commands.
|
/** LCD serial interface state machine. I cheat and don't implement all commands.
|
||||||
* Also, it's not clear when exactly the display should be updated. After each regA/regB write
|
* Also, it's not clear when exactly the display should be updated. After each regA/regB write
|
||||||
@ -413,14 +413,14 @@ void hp3478a_state::lcd_interface(uint8_t p2new)
|
|||||||
bool pwo_state, sync_state, isa_state, iwa_state;
|
bool pwo_state, sync_state, isa_state, iwa_state;
|
||||||
|
|
||||||
pwo_state = p2new & DISP_PWO;
|
pwo_state = p2new & DISP_PWO;
|
||||||
sync_state = p2new & DISP_SYNC;
|
sync_state = p2new & DISP_SYNC;
|
||||||
isa_state = p2new & DISP_ISA;
|
isa_state = p2new & DISP_ISA;
|
||||||
iwa_state = p2new & DISP_IWA;
|
iwa_state = p2new & DISP_IWA;
|
||||||
|
|
||||||
if (!((p2new ^ m_p2_oldstate) & DISP_CK1)) {
|
if (!((p2new ^ m_p2_oldstate) & DISP_CK1)) {
|
||||||
// no clock edge : boring.
|
// no clock edge : boring.
|
||||||
//LOGMASKED(DEBUG_LCD, "LCD : pwo(%d), sync(%d), isa(%d), iwa(%d)\n",
|
//LOGMASKED(DEBUG_LCD, "LCD : pwo(%d), sync(%d), isa(%d), iwa(%d)\n",
|
||||||
// pwo_state, sync_state, isa_state, iwa_state);
|
// pwo_state, sync_state, isa_state, iwa_state);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -490,7 +490,7 @@ void hp3478a_state::lcd_interface(uint8_t p2new)
|
|||||||
m_lcdiwa = lcd_iwatype::ANNUNS;
|
m_lcdiwa = lcd_iwatype::ANNUNS;
|
||||||
break;
|
break;
|
||||||
case DISP_ISA_WA:
|
case DISP_ISA_WA:
|
||||||
m_lcd_want = 100; //no, doesn't fit in a uint64, but only the first 36 bits are significant.
|
m_lcd_want = 100; //no, doesn't fit in a uint64, but only the first 36 bits are significant.
|
||||||
m_lcdiwa = lcd_iwatype::REG_A;
|
m_lcdiwa = lcd_iwatype::REG_A;
|
||||||
break;
|
break;
|
||||||
case DISP_ISA_WB:
|
case DISP_ISA_WB:
|
||||||
@ -551,7 +551,7 @@ void hp3478a_state::lcd_interface(uint8_t p2new)
|
|||||||
//shouldn't get extra bits, but we have nothing better to do so just reset the shiftreg.
|
//shouldn't get extra bits, but we have nothing better to do so just reset the shiftreg.
|
||||||
m_lcd_bitcount = 0;
|
m_lcd_bitcount = 0;
|
||||||
m_lcd_bitbuf = 0;
|
m_lcd_bitbuf = 0;
|
||||||
break; //case SELECTED_IWA
|
break; //case SELECTED_IWA
|
||||||
}
|
}
|
||||||
|
|
||||||
return;
|
return;
|
||||||
@ -578,7 +578,7 @@ void hp3478a_state::machine_start()
|
|||||||
|
|
||||||
void hp3478a_state::i8039_map(address_map &map)
|
void hp3478a_state::i8039_map(address_map &map)
|
||||||
{
|
{
|
||||||
map(0x0000, 0x0fff).bankr("bank0"); // CPU address space (4kB), banked according to P26 pin
|
map(0x0000, 0x0fff).bankr("bank0"); // CPU address space (4kB), banked according to P26 pin
|
||||||
}
|
}
|
||||||
|
|
||||||
void hp3478a_state::i8039_io(address_map &map)
|
void hp3478a_state::i8039_io(address_map &map)
|
||||||
@ -595,7 +595,7 @@ void hp3478a_state::io_bank(address_map &map)
|
|||||||
{
|
{
|
||||||
map.unmap_value_high();
|
map.unmap_value_high();
|
||||||
map(0x000, 0x0ff).ram().region("nvram", 0).share("nvram").w(FUNC(hp3478a_state::nvwrite));
|
map(0x000, 0x0ff).ram().region("nvram", 0).share("nvram").w(FUNC(hp3478a_state::nvwrite));
|
||||||
map(0x100, 0x107).ram().share("gpibregs"); //XXX TODO : connect to i8291.cpp
|
map(0x100, 0x107).ram().share("gpibregs"); //XXX TODO : connect to i8291.cpp
|
||||||
map(0x200, 0x2ff).portr("DIP");
|
map(0x200, 0x2ff).portr("DIP");
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -605,17 +605,17 @@ void hp3478a_state::io_bank(address_map &map)
|
|||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
static INPUT_PORTS_START( hp3478a )
|
static INPUT_PORTS_START( hp3478a )
|
||||||
/* keypad bit matrix:
|
/* keypad bit matrix:
|
||||||
0x08|0x04|0x02|0x01
|
0x08|0x04|0x02|0x01
|
||||||
col.0 : (nc)|shift|ACA|DCA
|
col.0 : (nc)|shift|ACA|DCA
|
||||||
col.1 : 4W|2W|ACV|DCV
|
col.1 : 4W|2W|ACV|DCV
|
||||||
col.2 : int|dn|up|auto
|
col.2 : int|dn|up|auto
|
||||||
col.3 : (nc)|loc|srq|sgl
|
col.3 : (nc)|loc|srq|sgl
|
||||||
*/
|
*/
|
||||||
PORT_START("COL.0")
|
PORT_START("COL.0")
|
||||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("DCA")
|
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("DCA")
|
||||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("ACA")
|
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("ACA")
|
||||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("SHIFT")
|
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("SHIFT")
|
||||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
|
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
|
||||||
PORT_START("COL.1")
|
PORT_START("COL.1")
|
||||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("DCV")
|
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("DCV")
|
||||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("ACV")
|
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("ACV")
|
||||||
@ -630,7 +630,7 @@ static INPUT_PORTS_START( hp3478a )
|
|||||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON12 ) PORT_NAME("SGL")
|
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON12 ) PORT_NAME("SGL")
|
||||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON13 ) PORT_NAME("SRQ")
|
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON13 ) PORT_NAME("SRQ")
|
||||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON14 ) PORT_NAME("LOC")
|
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON14 ) PORT_NAME("LOC")
|
||||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
|
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
|
||||||
|
|
||||||
PORT_START("CAL_EN")
|
PORT_START("CAL_EN")
|
||||||
PORT_CONFNAME(1, 0, "CAL")
|
PORT_CONFNAME(1, 0, "CAL")
|
||||||
@ -713,9 +713,9 @@ void hp3478a_state::hp3478a(machine_config &config)
|
|||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
ROM_START( hp3478a )
|
ROM_START( hp3478a )
|
||||||
ROM_REGION( 0x2000, "maincpu", 0 )
|
ROM_REGION( 0x2000, "maincpu", 0 )
|
||||||
ROM_LOAD("rom_dc118.bin", 0, 0x2000, CRC(10097ced) SHA1(bd665cf7e07e63f825b2353c8322ed8a4376b3bd)) //main CPU ROM, can match other datecodes too
|
ROM_LOAD("rom_dc118.bin", 0, 0x2000, CRC(10097ced) SHA1(bd665cf7e07e63f825b2353c8322ed8a4376b3bd)) //main CPU ROM, can match other datecodes too
|
||||||
|
|
||||||
ROM_REGION( 0x100, "nvram", 0 ) /* Calibration RAM, battery-backed */
|
ROM_REGION( 0x100, "nvram", 0 ) /* Calibration RAM, battery-backed */
|
||||||
ROM_LOAD( "calram.bin", 0, 0x100, NO_DUMP)
|
ROM_LOAD( "calram.bin", 0, 0x100, NO_DUMP)
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
|
@ -17,19 +17,19 @@
|
|||||||
DAC (1 channel; can be used as tone generator)
|
DAC (1 channel; can be used as tone generator)
|
||||||
512KB or 1MB of RAM
|
512KB or 1MB of RAM
|
||||||
1MB of BIOS ROM (banked)
|
1MB of BIOS ROM (banked)
|
||||||
P/N 18-5301 ABD \\ HN62318BFC26
|
P/N 18-5301 ABD \\ HN62318BFC26
|
||||||
LCD, 240x128 pixels (40x16 chars in MDA-compatible text mode)
|
LCD, 240x128 pixels (40x16 chars in MDA-compatible text mode)
|
||||||
|
|
||||||
To do:
|
To do:
|
||||||
- blue on green LCD palette
|
- blue on green LCD palette
|
||||||
- native keyboard
|
- native keyboard
|
||||||
- 1MB model
|
- 1MB model
|
||||||
- identify RTC core
|
- identify RTC core
|
||||||
- everything else
|
- everything else
|
||||||
|
|
||||||
Technical info:
|
Technical info:
|
||||||
- http://web.archive.org/web/20071012040320/http://www.daniel-hertrich.de/download/95lx_devguide.zip
|
- http://web.archive.org/web/20071012040320/http://www.daniel-hertrich.de/download/95lx_devguide.zip
|
||||||
- http://cd.textfiles.com/blackphilesii/PHILES/HP95/HP95DEV.ZIP
|
- http://cd.textfiles.com/blackphilesii/PHILES/HP95/HP95DEV.ZIP
|
||||||
|
|
||||||
Useful links:
|
Useful links:
|
||||||
- https://hermocom.com/hplx/view-all-hp-palmtop-articles/41-95lx
|
- https://hermocom.com/hplx/view-all-hp-palmtop-articles/41-95lx
|
||||||
@ -43,12 +43,12 @@
|
|||||||
- http://web.archive.org/web/20150423014908/http://www.sp.uconn.edu/~mchem1/HPLX.shtml
|
- http://web.archive.org/web/20150423014908/http://www.sp.uconn.edu/~mchem1/HPLX.shtml
|
||||||
HPLX-L mailing list archive
|
HPLX-L mailing list archive
|
||||||
|
|
||||||
Software:
|
Software:
|
||||||
- http://www.retroisle.com/others/hp95lx/software.php
|
- http://www.retroisle.com/others/hp95lx/software.php
|
||||||
- http://www.mizj.com/
|
- http://www.mizj.com/
|
||||||
- http://www.hp200lx.net/
|
- http://www.hp200lx.net/
|
||||||
- http://www.nic.funet.fi/index/misc/hp95lx/Index
|
- http://www.nic.funet.fi/index/misc/hp95lx/Index
|
||||||
- http://cd.textfiles.com/blackphilesii/PHILES/HP95/
|
- http://cd.textfiles.com/blackphilesii/PHILES/HP95/
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
@ -614,12 +614,12 @@ WRITE8_MEMBER(hp95lx_state::video_register_w)
|
|||||||
m_disp_start_addr = ((data & 0x3f) << 8) | (m_disp_start_addr & 0x00ff);
|
m_disp_start_addr = ((data & 0x3f) << 8) | (m_disp_start_addr & 0x00ff);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x0d:
|
case 0x0d:
|
||||||
m_disp_start_addr = ((data & 0xff) << 0) | (m_disp_start_addr & 0xff00);
|
m_disp_start_addr = ((data & 0xff) << 0) | (m_disp_start_addr & 0xff00);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x0e:
|
case 0x0e:
|
||||||
m_cursor_addr = ((data & 0x3f) << 8) | (m_cursor_addr & 0x00ff);
|
m_cursor_addr = ((data & 0x3f) << 8) | (m_cursor_addr & 0x00ff);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x0f:
|
case 0x0f:
|
||||||
@ -699,9 +699,9 @@ void hp95lx_state::hp95lx_io(address_map &map)
|
|||||||
map(0x0020, 0x002f).rw("pic8259", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
|
map(0x0020, 0x002f).rw("pic8259", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
|
||||||
map(0x0040, 0x004f).rw("pit8254", FUNC(pit8254_device::read), FUNC(pit8254_device::write));
|
map(0x0040, 0x004f).rw("pit8254", FUNC(pit8254_device::read), FUNC(pit8254_device::write));
|
||||||
map(0x0060, 0x0063).rw(FUNC(hp95lx_state::keyboard_r), FUNC(hp95lx_state::keyboard_w));
|
map(0x0060, 0x0063).rw(FUNC(hp95lx_state::keyboard_r), FUNC(hp95lx_state::keyboard_w));
|
||||||
// map(0x0090, 0x009f).w(FUNC(hp95lx_state::debug_w));
|
// map(0x0090, 0x009f).w(FUNC(hp95lx_state::debug_w));
|
||||||
map(0x03b0, 0x03bf).rw(FUNC(hp95lx_state::video_r), FUNC(hp95lx_state::video_w));
|
map(0x03b0, 0x03bf).rw(FUNC(hp95lx_state::video_r), FUNC(hp95lx_state::video_w));
|
||||||
// map(0x0070, 0x007f) RTC
|
// map(0x0070, 0x007f) RTC
|
||||||
map(0xd300, 0xd30f).rw(FUNC(hp95lx_state::d300_r), FUNC(hp95lx_state::d300_w));
|
map(0xd300, 0xd30f).rw(FUNC(hp95lx_state::d300_r), FUNC(hp95lx_state::d300_w));
|
||||||
map(0xe300, 0xe30f).rw(FUNC(hp95lx_state::e300_r), FUNC(hp95lx_state::e300_w));
|
map(0xe300, 0xe30f).rw(FUNC(hp95lx_state::e300_r), FUNC(hp95lx_state::e300_w));
|
||||||
map(0xf300, 0xf31f).rw(FUNC(hp95lx_state::f300_r), FUNC(hp95lx_state::f300_w));
|
map(0xf300, 0xf31f).rw(FUNC(hp95lx_state::f300_r), FUNC(hp95lx_state::f300_w));
|
||||||
@ -748,7 +748,7 @@ MACHINE_CONFIG_START(hp95lx_state::hp95lx)
|
|||||||
NVRAM(config, "nvram2", nvram_device::DEFAULT_ALL_0); // RAM
|
NVRAM(config, "nvram2", nvram_device::DEFAULT_ALL_0); // RAM
|
||||||
NVRAM(config, "nvram3", nvram_device::DEFAULT_ALL_0); // card slot
|
NVRAM(config, "nvram3", nvram_device::DEFAULT_ALL_0); // card slot
|
||||||
|
|
||||||
// XXX When the AC adapter is plugged in, the LCD refresh rate is 73.14 Hz.
|
// XXX When the AC adapter is plugged in, the LCD refresh rate is 73.14 Hz.
|
||||||
// XXX When the AC adapter is not plugged in (ie, running off of batteries) the refresh rate is 56.8 Hz.
|
// XXX When the AC adapter is not plugged in (ie, running off of batteries) the refresh rate is 56.8 Hz.
|
||||||
MCFG_SCREEN_ADD_MONOCHROME("screen", LCD, rgb_t::white())
|
MCFG_SCREEN_ADD_MONOCHROME("screen", LCD, rgb_t::white())
|
||||||
MCFG_SCREEN_UPDATE_DRIVER(hp95lx_state, screen_update)
|
MCFG_SCREEN_UPDATE_DRIVER(hp95lx_state, screen_update)
|
||||||
|
@ -7,37 +7,37 @@
|
|||||||
|
|
||||||
driver by Phil Bennett
|
driver by Phil Bennett
|
||||||
|
|
||||||
NOTE:
|
NOTE:
|
||||||
|
|
||||||
* All games are marked MACHINE_NOT_WORKING due to the rare case
|
* All games are marked MACHINE_NOT_WORKING due to the rare case
|
||||||
where the PowerPC DRC blows up, causing MAME to crash. In reality,
|
where the PowerPC DRC blows up, causing MAME to crash. In reality,
|
||||||
there is a good chance of being able to play through a round or
|
there is a good chance of being able to play through a round or
|
||||||
three with no issues on all of the parent sets.
|
three with no issues on all of the parent sets.
|
||||||
|
|
||||||
TODO:
|
TODO:
|
||||||
|
|
||||||
* Fix DRC crashes
|
* Fix DRC crashes
|
||||||
o Crashes on DRC translation of 0x40028604
|
o Crashes on DRC translation of 0x40028604
|
||||||
* Fix texture compression
|
* Fix texture compression
|
||||||
* Sort out CD images
|
* Sort out CD images
|
||||||
* Fix Polystars blending issues
|
* Fix Polystars blending issues
|
||||||
* Fix PowerPC 602 Protection Only mode handling.
|
* Fix PowerPC 602 Protection Only mode handling.
|
||||||
* Implement CDDA muting
|
* Implement CDDA muting
|
||||||
|
|
||||||
DONE
|
DONE
|
||||||
* Fix Polystars blending
|
* Fix Polystars blending
|
||||||
* Fix missing music in Polystars
|
* Fix missing music in Polystars
|
||||||
* Fix music playing too early
|
* Fix music playing too early
|
||||||
* Fix missing music and sound in Hell Night/Evil Night
|
* Fix missing music and sound in Hell Night/Evil Night
|
||||||
* Fix incorrect speed in Heat of 11 and Total Vice (partially)
|
* Fix incorrect speed in Heat of 11 and Total Vice (partially)
|
||||||
|
|
||||||
// Polystars/Total Vice
|
// Polystars/Total Vice
|
||||||
if (pc == 0x40035958)
|
if (pc == 0x40035958)
|
||||||
gpr[11] = 1;
|
gpr[11] = 1;
|
||||||
|
|
||||||
// Everything else
|
// Everything else
|
||||||
if (pc == 0x400385c8)
|
if (pc == 0x400385c8)
|
||||||
gpr[11] = 0;
|
gpr[11] = 0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -243,9 +243,9 @@ Notes:
|
|||||||
#include "screen.h"
|
#include "screen.h"
|
||||||
#include "speaker.h"
|
#include "speaker.h"
|
||||||
|
|
||||||
#define M2_CLOCK XTAL(66'666'700)
|
#define M2_CLOCK XTAL(66'666'700)
|
||||||
|
|
||||||
#define ENABLE_SDBG 0
|
#define ENABLE_SDBG 0
|
||||||
|
|
||||||
|
|
||||||
/*************************************
|
/*************************************
|
||||||
@ -323,7 +323,7 @@ public:
|
|||||||
{
|
{
|
||||||
// 8000 = /Reset
|
// 8000 = /Reset
|
||||||
// 4000 = C000 ... DOIO DMA ... 4000
|
// 4000 = C000 ... DOIO DMA ... 4000
|
||||||
// m_ata->write_dmack(data & 0x4000 ? ASSERT_LINE : CLEAR_LINE);
|
// m_ata->write_dmack(data & 0x4000 ? ASSERT_LINE : CLEAR_LINE);
|
||||||
|
|
||||||
if (!(data & 0x8000))
|
if (!(data & 0x8000))
|
||||||
{
|
{
|
||||||
@ -365,9 +365,9 @@ private:
|
|||||||
cdrom_file *m_available_cdroms;
|
cdrom_file *m_available_cdroms;
|
||||||
|
|
||||||
// Konami SIO
|
// Konami SIO
|
||||||
uint16_t m_sio_data;
|
uint16_t m_sio_data;
|
||||||
|
|
||||||
uint32_t m_ata_int; // TEST
|
uint32_t m_ata_int; // TEST
|
||||||
emu_timer *m_atapi_timer;
|
emu_timer *m_atapi_timer;
|
||||||
|
|
||||||
TIMER_CALLBACK_MEMBER( atapi_delay )
|
TIMER_CALLBACK_MEMBER( atapi_delay )
|
||||||
@ -435,7 +435,7 @@ WRITE16_MEMBER( konamim2_state::rdac_out )
|
|||||||
|
|
||||||
WRITE_LINE_MEMBER( konamim2_state::ata_int )
|
WRITE_LINE_MEMBER( konamim2_state::ata_int )
|
||||||
{
|
{
|
||||||
// m_atapi_timer->adjust( attotime::from_msec(10), state );
|
// m_atapi_timer->adjust( attotime::from_msec(10), state );
|
||||||
m_ata_int = state;
|
m_ata_int = state;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -448,14 +448,14 @@ WRITE_LINE_MEMBER( konamim2_state::ata_int )
|
|||||||
|
|
||||||
READ16_MEMBER( konamim2_state::konami_io0_r )
|
READ16_MEMBER( konamim2_state::konami_io0_r )
|
||||||
{
|
{
|
||||||
// printf("IO R: %08X\n", offset);
|
// printf("IO R: %08X\n", offset);
|
||||||
|
|
||||||
switch (offset)
|
switch (offset)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
0 = 160
|
0 = 160
|
||||||
1 = 32
|
1 = 32
|
||||||
2 = -96
|
2 = -96
|
||||||
10 = -1888
|
10 = -1888
|
||||||
FF = -32480
|
FF = -32480
|
||||||
|
|
||||||
@ -503,7 +503,7 @@ READ16_MEMBER( konamim2_state::konami_io0_r )
|
|||||||
case 5: return 0; // P2 Y
|
case 5: return 0; // P2 Y
|
||||||
case 6: return 0; // P3 Y?
|
case 6: return 0; // P3 Y?
|
||||||
case 7: return 0; //??
|
case 7: return 0; //??
|
||||||
case 8: return ioport("P5")->read();
|
case 8: return ioport("P5")->read();
|
||||||
}
|
}
|
||||||
|
|
||||||
//return rand();
|
//return rand();
|
||||||
@ -513,7 +513,7 @@ READ16_MEMBER( konamim2_state::konami_io0_r )
|
|||||||
WRITE16_MEMBER( konamim2_state::konami_io0_w )
|
WRITE16_MEMBER( konamim2_state::konami_io0_w )
|
||||||
{
|
{
|
||||||
// 9: 0000, 0xFFF
|
// 9: 0000, 0xFFF
|
||||||
// printf("IO W: %08x %08x\n", offset, data);
|
// printf("IO W: %08x %08x\n", offset, data);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -545,7 +545,7 @@ READ16_MEMBER( konamim2_state::konami_io1_r )
|
|||||||
{
|
{
|
||||||
uint16_t data = 0;
|
uint16_t data = 0;
|
||||||
|
|
||||||
// printf("%s: PORT R: [%x] MASK:%.8x\n", machine().describe_context(), offset, mem_mask);
|
// printf("%s: PORT R: [%x] MASK:%.8x\n", machine().describe_context(), offset, mem_mask);
|
||||||
|
|
||||||
switch (offset)
|
switch (offset)
|
||||||
{
|
{
|
||||||
@ -609,13 +609,13 @@ WRITE16_MEMBER( konamim2_state::konami_io1_w )
|
|||||||
// 0x8000 = ?
|
// 0x8000 = ?
|
||||||
logerror("%s: PORT W: [%x] %x, MASK:%.8x\n", machine().describe_context(), offset, data, mem_mask);
|
logerror("%s: PORT W: [%x] %x, MASK:%.8x\n", machine().describe_context(), offset, data, mem_mask);
|
||||||
|
|
||||||
// printf("CDDA is: %s\n", data & 0x2000 ? "ENABLED" : "MUTE");
|
// printf("CDDA is: %s\n", data & 0x2000 ? "ENABLED" : "MUTE");
|
||||||
|
|
||||||
machine().bookkeeping().coin_counter_w(0, (data >> 11) & 1);
|
machine().bookkeeping().coin_counter_w(0, (data >> 11) & 1);
|
||||||
machine().bookkeeping().coin_counter_w(1, (data >> 12) & 1);
|
machine().bookkeeping().coin_counter_w(1, (data >> 12) & 1);
|
||||||
|
|
||||||
// m_cdda->set_output_gain(0, data & 0x2000 ? 1.0 : 0.0);
|
// m_cdda->set_output_gain(0, data & 0x2000 ? 1.0 : 0.0);
|
||||||
// m_cdda->set_output_gain(1, data & 0x2000 ? 1.0 : 0.0);
|
// m_cdda->set_output_gain(1, data & 0x2000 ? 1.0 : 0.0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -762,7 +762,7 @@ void konamim2_state::m2_map(address_map &map)
|
|||||||
map(0x37c00010, 0x37c0001f).rw(FUNC(konamim2_state::konami_sio_r), FUNC(konamim2_state::konami_sio_w));
|
map(0x37c00010, 0x37c0001f).rw(FUNC(konamim2_state::konami_sio_r), FUNC(konamim2_state::konami_sio_w));
|
||||||
map(0x37e00000, 0x37e0000f).rw(FUNC(konamim2_state::konami_io1_r), FUNC(konamim2_state::konami_io1_w));
|
map(0x37e00000, 0x37e0000f).rw(FUNC(konamim2_state::konami_io1_r), FUNC(konamim2_state::konami_io1_w));
|
||||||
map(0x3f000000, 0x3fffffff).rw(FUNC(konamim2_state::konami_ide_r), FUNC(konamim2_state::konami_ide_w)); // Endian flipped???
|
map(0x3f000000, 0x3fffffff).rw(FUNC(konamim2_state::konami_ide_r), FUNC(konamim2_state::konami_ide_w)); // Endian flipped???
|
||||||
// map(0x3f000000, 0x3fffffff).rw("ata", FUNC(ata_interface_device::read_cs0), FUNC(ata_interface_device::write_cs0));
|
// map(0x3f000000, 0x3fffffff).rw("ata", FUNC(ata_interface_device::read_cs0), FUNC(ata_interface_device::write_cs0));
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
map(0x36c00000, 0x36cfffff).rw(m48t58_r, m48t58_w)
|
map(0x36c00000, 0x36cfffff).rw(m48t58_r, m48t58_w)
|
||||||
@ -770,10 +770,10 @@ void konamim2_state::m2_map(address_map &map)
|
|||||||
map(0x37400000, 0x37400003).w(eeprom_w)
|
map(0x37400000, 0x37400003).w(eeprom_w)
|
||||||
map(0x37600000, 0x37600000).w(atapi_dma_w)
|
map(0x37600000, 0x37600000).w(atapi_dma_w)
|
||||||
map(0x37a00000, 0x37a0003f).rw(kacio_r, kacio_w)
|
map(0x37a00000, 0x37a0003f).rw(kacio_r, kacio_w)
|
||||||
map(0x37c00010, 0x37c0001f).rw(sio_r, sio_w) // Konami 11k
|
map(0x37c00010, 0x37c0001f).rw(sio_r, sio_w) // Konami 11k
|
||||||
map(0x37e00000, 0x37e0000f).rw(port_r, port_w) // Konami? - 37e00006 = Read
|
map(0x37e00000, 0x37e0000f).rw(port_r, port_w) // Konami? - 37e00006 = Read
|
||||||
map(0x3e000000, 0x3effffff).rw(ymz0_r, ymz0_w) // Konami - Evil Night / Total Vice
|
map(0x3e000000, 0x3effffff).rw(ymz0_r, ymz0_w) // Konami - Evil Night / Total Vice
|
||||||
map(0x3e900000, 0x3e9fffff).rw(ymz1_r, ymz1_w) // Konami
|
map(0x3e900000, 0x3e9fffff).rw(ymz1_r, ymz1_w) // Konami
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1205,7 +1205,7 @@ void konamim2_state::konamim2(machine_config &config)
|
|||||||
|
|
||||||
void konamim2_state::set_ntsc(machine_config &config)
|
void konamim2_state::set_ntsc(machine_config &config)
|
||||||
{
|
{
|
||||||
// m_screen->set_raw(11750000, 766, 126, 126+640, 260, 20, 20+240); // TODO
|
// m_screen->set_raw(11750000, 766, 126, 126+640, 260, 20, 20+240); // TODO
|
||||||
m_screen->set_refresh_hz(59.360001);
|
m_screen->set_refresh_hz(59.360001);
|
||||||
m_screen->set_size(768, 262);
|
m_screen->set_size(768, 262);
|
||||||
m_screen->set_visarea(126, 126+640-1, 20, 20+240-1);
|
m_screen->set_visarea(126, 126+640-1, 20, 20+240-1);
|
||||||
@ -1255,7 +1255,7 @@ void konamim2_state::totlvice(machine_config &config)
|
|||||||
{
|
{
|
||||||
konamim2(config);
|
konamim2(config);
|
||||||
add_ymz280b(config);
|
add_ymz280b(config);
|
||||||
// set_arcres(config);
|
// set_arcres(config);
|
||||||
set_ntsc2(config);
|
set_ntsc2(config);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1353,8 +1353,8 @@ ROM_START( evilngt )
|
|||||||
ROM_REGION64_BE( 0x200000, "boot", 0 )
|
ROM_REGION64_BE( 0x200000, "boot", 0 )
|
||||||
ROM_LOAD16_WORD( "636a01.8q", 0x000000, 0x200000, CRC(7b1dc738) SHA1(32ae8e7ddd38fcc70b4410275a2cc5e9a0d7d33b) )
|
ROM_LOAD16_WORD( "636a01.8q", 0x000000, 0x200000, CRC(7b1dc738) SHA1(32ae8e7ddd38fcc70b4410275a2cc5e9a0d7d33b) )
|
||||||
|
|
||||||
ROM_REGION16_BE( 0x80, "eeprom", 0 ) /* EEPROM default contents */
|
ROM_REGION16_BE( 0x80, "eeprom", 0 ) /* EEPROM default contents */
|
||||||
ROM_LOAD( "93c46.7k", 0x000000, 0x000080, CRC(60ae825e) SHA1(fd61db9667c53dd12700a0fe202fcd1e3d35d206) )
|
ROM_LOAD( "93c46.7k", 0x000000, 0x000080, CRC(60ae825e) SHA1(fd61db9667c53dd12700a0fe202fcd1e3d35d206) )
|
||||||
|
|
||||||
ROM_REGION( 0x2000, "m48t58", 0 ) /* timekeeper SRAM */
|
ROM_REGION( 0x2000, "m48t58", 0 ) /* timekeeper SRAM */
|
||||||
ROM_LOAD( "m48t58y.9n", 0x000000, 0x002000, CRC(e887ca1f) SHA1(54205f01b1ceba1d5f4d979fc30be1add8116e90) )
|
ROM_LOAD( "m48t58y.9n", 0x000000, 0x002000, CRC(e887ca1f) SHA1(54205f01b1ceba1d5f4d979fc30be1add8116e90) )
|
||||||
@ -1489,7 +1489,7 @@ void konamim2_state::install_m48t58()
|
|||||||
void konamim2_state::install_ymz280b()
|
void konamim2_state::install_ymz280b()
|
||||||
{
|
{
|
||||||
read8_delegate read_delegate(FUNC(ymz280b_device::read), &(*m_ymz280b));
|
read8_delegate read_delegate(FUNC(ymz280b_device::read), &(*m_ymz280b));
|
||||||
write8_delegate write_delegate(FUNC(ymz280b_device::write), &(*m_ymz280b));
|
write8_delegate write_delegate(FUNC(ymz280b_device::write), &(*m_ymz280b));
|
||||||
|
|
||||||
m_ppc1->space(AS_PROGRAM).install_readwrite_handler(0x3e800000, 0x3e80000f, read_delegate, write_delegate, 0xff00ff0000000000ULL);
|
m_ppc1->space(AS_PROGRAM).install_readwrite_handler(0x3e800000, 0x3e80000f, read_delegate, write_delegate, 0xff00ff0000000000ULL);
|
||||||
m_ppc2->space(AS_PROGRAM).install_readwrite_handler(0x3e800000, 0x3e80000f, read_delegate, write_delegate, 0xff00ff0000000000ULL);
|
m_ppc2->space(AS_PROGRAM).install_readwrite_handler(0x3e800000, 0x3e80000f, read_delegate, write_delegate, 0xff00ff0000000000ULL);
|
||||||
@ -1674,19 +1674,19 @@ void konamim2_state::dump_task_command(int ref, const std::vector<std::string> &
|
|||||||
task.t_DefaultMsgPort = cpu.read_dword(space, address + offsetof(Task, t_DefaultMsgPort), true);
|
task.t_DefaultMsgPort = cpu.read_dword(space, address + offsetof(Task, t_DefaultMsgPort), true);
|
||||||
task.pt_UserData = cpu.read_dword(space, address + offsetof(Task, pt_UserData), true);
|
task.pt_UserData = cpu.read_dword(space, address + offsetof(Task, pt_UserData), true);
|
||||||
|
|
||||||
// m2ptr pt_ThreadTask; /* I am a thread of what task? */
|
// m2ptr pt_ThreadTask; /* I am a thread of what task? */
|
||||||
// uint32_t t_WaitBits; /* signals being waited for */
|
// uint32_t t_WaitBits; /* signals being waited for */
|
||||||
// uint32_t t_SigBits; /* signals received */
|
// uint32_t t_SigBits; /* signals received */
|
||||||
// uint32_t t_AllocatedSigs; /* signals allocated */
|
// uint32_t t_AllocatedSigs; /* signals allocated */
|
||||||
// m2ptr pt_StackBase; /* base of stack */
|
// m2ptr pt_StackBase; /* base of stack */
|
||||||
// int32_t t_StackSize; /* size of stack */
|
// int32_t t_StackSize; /* size of stack */
|
||||||
// uint32_t t_MaxUSecs; /* quantum length in usecs */
|
// uint32_t t_MaxUSecs; /* quantum length in usecs */
|
||||||
// TimerTicks t_ElapsedTime; /* time spent running this task */
|
// TimerTicks t_ElapsedTime; /* time spent running this task */
|
||||||
// uint32_t t_NumTaskLaunch; /* # times launched this task */
|
// uint32_t t_NumTaskLaunch; /* # times launched this task */
|
||||||
// uint32_t t_Flags; /* task flags */
|
// uint32_t t_Flags; /* task flags */
|
||||||
// Item t_Module; /* the module we live within */
|
// Item t_Module; /* the module we live within */
|
||||||
// Item t_DefaultMsgPort; /* default task msgport */
|
// Item t_DefaultMsgPort; /* default task msgport */
|
||||||
// m2ptr pt_UserData; /* user-private data */
|
// m2ptr pt_UserData; /* user-private data */
|
||||||
|
|
||||||
con.printf("**** Task Info @ %08X ****\n", address);
|
con.printf("**** Task Info @ %08X ****\n", address);
|
||||||
con.printf("Next: %08X\n", task.t.pn_Next);
|
con.printf("Next: %08X\n", task.t.pn_Next);
|
||||||
@ -1712,7 +1712,7 @@ void konamim2_state::dump_task_command(int ref, const std::vector<std::string> &
|
|||||||
con.printf("StackSize: %08X\n", task.t_StackSize);
|
con.printf("StackSize: %08X\n", task.t_StackSize);
|
||||||
con.printf("MaxUSecs: %08X\n", task.t_MaxUSecs);
|
con.printf("MaxUSecs: %08X\n", task.t_MaxUSecs);
|
||||||
con.printf("ElapsedTime: %016llu\n", (uint64_t)task.t_ElapsedTime.tt_Lo + ((uint64_t)task.t_ElapsedTime.tt_Hi << 32ull));
|
con.printf("ElapsedTime: %016llu\n", (uint64_t)task.t_ElapsedTime.tt_Lo + ((uint64_t)task.t_ElapsedTime.tt_Hi << 32ull));
|
||||||
con.printf("NumTaskLaunch: %u\n", task.t_NumTaskLaunch);
|
con.printf("NumTaskLaunch: %u\n", task.t_NumTaskLaunch);
|
||||||
con.printf("Flags: %08X\n", task.t_Flags);
|
con.printf("Flags: %08X\n", task.t_Flags);
|
||||||
con.printf("Module: %08X\n", task.t_Module);
|
con.printf("Module: %08X\n", task.t_Module);
|
||||||
con.printf("DefaultMsgPort: %08X\n", task.t_DefaultMsgPort);
|
con.printf("DefaultMsgPort: %08X\n", task.t_DefaultMsgPort);
|
||||||
|
@ -3,14 +3,14 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
|
|
||||||
Olivetti M24 emulation
|
Olivetti M24 emulation
|
||||||
|
|
||||||
http://olivettim24.hadesnet.org/index.html
|
http://olivettim24.hadesnet.org/index.html
|
||||||
https://sites.google.com/site/att6300shrine/Home
|
https://sites.google.com/site/att6300shrine/Home
|
||||||
http://www.ti99.com/exelvision/website/index.php?page=logabax-persona-1600
|
http://www.ti99.com/exelvision/website/index.php?page=logabax-persona-1600
|
||||||
|
|
||||||
The AT&T PC6300, the Xerox 6060 and the Logabax Persona 1600 were badge
|
The AT&T PC6300, the Xerox 6060 and the Logabax Persona 1600 were badge
|
||||||
engineered Olivetti M24s.
|
engineered Olivetti M24s.
|
||||||
|
|
||||||
|
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
@ -317,12 +317,12 @@ ROM_START( m24 )
|
|||||||
ROM_SYSTEM_BIOS(1,"v1.21","v1.21")
|
ROM_SYSTEM_BIOS(1,"v1.21","v1.21")
|
||||||
ROMX_LOAD("m24_bios121h.rom",0x4001, 0x2000, CRC(93292715) SHA1(863eccfb3beca6e64c5b0cc070c64394bad7da82), ROM_SKIP(1) | ROM_BIOS(1))
|
ROMX_LOAD("m24_bios121h.rom",0x4001, 0x2000, CRC(93292715) SHA1(863eccfb3beca6e64c5b0cc070c64394bad7da82), ROM_SKIP(1) | ROM_BIOS(1))
|
||||||
ROMX_LOAD("m24_bios121l.rom", 0x4000, 0x2000, CRC(1acbc9d7) SHA1(d3696e38853cea31e70ffa4e13e127ec7551bf57), ROM_SKIP(1) | ROM_BIOS(1))
|
ROMX_LOAD("m24_bios121l.rom", 0x4000, 0x2000, CRC(1acbc9d7) SHA1(d3696e38853cea31e70ffa4e13e127ec7551bf57), ROM_SKIP(1) | ROM_BIOS(1))
|
||||||
|
|
||||||
ROM_SYSTEM_BIOS(2,"v1.36","v1.36")
|
ROM_SYSTEM_BIOS(2,"v1.36","v1.36")
|
||||||
ROMX_LOAD("m24_bios136h.rom",0x4001, 0x2000, CRC(25cbf8ba) SHA1(1ab90985852544d2c12b47bb7f20f9faccabdf88), ROM_SKIP(1) | ROM_BIOS(2))
|
ROMX_LOAD("m24_bios136h.rom",0x4001, 0x2000, CRC(25cbf8ba) SHA1(1ab90985852544d2c12b47bb7f20f9faccabdf88), ROM_SKIP(1) | ROM_BIOS(2))
|
||||||
ROMX_LOAD("m24_bios136l.rom", 0x4000, 0x2000, CRC(e2f738c0) SHA1(da9771325a5021cf9908997e0e0d14e47258125f), ROM_SKIP(1) | ROM_BIOS(2))
|
ROMX_LOAD("m24_bios136l.rom", 0x4000, 0x2000, CRC(e2f738c0) SHA1(da9771325a5021cf9908997e0e0d14e47258125f), ROM_SKIP(1) | ROM_BIOS(2))
|
||||||
|
|
||||||
ROM_SYSTEM_BIOS(3,"v1.43","v1.43")
|
ROM_SYSTEM_BIOS(3,"v1.43","v1.43")
|
||||||
ROMX_LOAD("olivetti_m24_version_1.43_high.bin",0x4001, 0x2000, CRC(04e697ba) SHA1(1066dcc849e6289b5ac6372c84a590e456d497a6), ROM_SKIP(1) | ROM_BIOS(3))
|
ROMX_LOAD("olivetti_m24_version_1.43_high.bin",0x4001, 0x2000, CRC(04e697ba) SHA1(1066dcc849e6289b5ac6372c84a590e456d497a6), ROM_SKIP(1) | ROM_BIOS(3))
|
||||||
ROMX_LOAD("olivetti_m24_version_1.43_low.bin", 0x4000, 0x2000, CRC(ff7e0f10) SHA1(13423011a9bae3f3193e8c199f98a496cab48c0f), ROM_SKIP(1) | ROM_BIOS(3))
|
ROMX_LOAD("olivetti_m24_version_1.43_low.bin", 0x4000, 0x2000, CRC(ff7e0f10) SHA1(13423011a9bae3f3193e8c199f98a496cab48c0f), ROM_SKIP(1) | ROM_BIOS(3))
|
||||||
|
|
||||||
|
@ -5,13 +5,13 @@
|
|||||||
mupid M-Disk Comp.-A
|
mupid M-Disk Comp.-A
|
||||||
Grundig FL-100
|
Grundig FL-100
|
||||||
|
|
||||||
Floppy disk station, usually connected to a mupid C2D2/C2A2 or the
|
Floppy disk station, usually connected to a mupid C2D2/C2A2 or the
|
||||||
Grundig PTC-100.
|
Grundig PTC-100.
|
||||||
|
|
||||||
Everything here is guessed based on the software and a PCB image. You
|
Everything here is guessed based on the software and a PCB image. You
|
||||||
can see garbled output when you connect the builtin terminal to the
|
can see garbled output when you connect the builtin terminal to the
|
||||||
first serial port ('ser'). It does boot from floppy too, so presumely
|
first serial port ('ser'). It does boot from floppy too, so presumely
|
||||||
only needs an emulated main system to work.
|
only needs an emulated main system to work.
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
|
@ -3070,7 +3070,7 @@ ROM_START( iganinjub )
|
|||||||
ROM_LOAD16_BYTE( "19.a12", 0x000000, 0x010000, CRC(6b4c16ac) SHA1(edb5fe3b3e4e94e59348c0a7034df9df6ef157d3) )
|
ROM_LOAD16_BYTE( "19.a12", 0x000000, 0x010000, CRC(6b4c16ac) SHA1(edb5fe3b3e4e94e59348c0a7034df9df6ef157d3) )
|
||||||
ROM_LOAD16_BYTE( "23.13", 0x000001, 0x010000, CRC(03bfda29) SHA1(ced6ddcbb86d3109bcfb8e1982a5f666ca7dc10e) )
|
ROM_LOAD16_BYTE( "23.13", 0x000001, 0x010000, CRC(03bfda29) SHA1(ced6ddcbb86d3109bcfb8e1982a5f666ca7dc10e) )
|
||||||
ROM_LOAD16_BYTE( "20.a13", 0x020000, 0x010000, CRC(fa0705fb) SHA1(110ebca62a57f9d8e355a339a99819faf1fe57f1) )
|
ROM_LOAD16_BYTE( "20.a13", 0x020000, 0x010000, CRC(fa0705fb) SHA1(110ebca62a57f9d8e355a339a99819faf1fe57f1) )
|
||||||
ROM_LOAD16_BYTE( "24.12", 0x020001, 0x010000, CRC(2de40303) SHA1(5c841295c0d804163a7da3c122dd40af7780d1f2) )
|
ROM_LOAD16_BYTE( "24.12", 0x020001, 0x010000, CRC(2de40303) SHA1(5c841295c0d804163a7da3c122dd40af7780d1f2) )
|
||||||
ROM_LOAD16_BYTE( "c", 0x040000, 0x010000, CRC(de5937ad) SHA1(d3039e5391feb925ea10f33a1363bf3ffc1ebb3d) )
|
ROM_LOAD16_BYTE( "c", 0x040000, 0x010000, CRC(de5937ad) SHA1(d3039e5391feb925ea10f33a1363bf3ffc1ebb3d) )
|
||||||
ROM_LOAD16_BYTE( "b", 0x040001, 0x010000, CRC(afaf0480) SHA1(b8d0ec859a94941650bdd2b01e98d054d49fef67) )
|
ROM_LOAD16_BYTE( "b", 0x040001, 0x010000, CRC(afaf0480) SHA1(b8d0ec859a94941650bdd2b01e98d054d49fef67) )
|
||||||
|
|
||||||
|
@ -598,12 +598,12 @@ void midtunit_state::tunit_core(machine_config &config)
|
|||||||
/* basic machine hardware */
|
/* basic machine hardware */
|
||||||
TMS34010(config, m_maincpu, CPU_CLOCK);
|
TMS34010(config, m_maincpu, CPU_CLOCK);
|
||||||
m_maincpu->set_addrmap(AS_PROGRAM, &midtunit_state::main_map);
|
m_maincpu->set_addrmap(AS_PROGRAM, &midtunit_state::main_map);
|
||||||
m_maincpu->set_halt_on_reset(false); /* halt on reset */
|
m_maincpu->set_halt_on_reset(false); /* halt on reset */
|
||||||
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
|
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
|
||||||
m_maincpu->set_pixels_per_clock(2); /* pixels per clock */
|
m_maincpu->set_pixels_per_clock(2); /* pixels per clock */
|
||||||
m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
|
m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
|
||||||
m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
|
m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
|
||||||
m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
|
m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
|
||||||
m_maincpu->set_screen("screen");
|
m_maincpu->set_screen("screen");
|
||||||
|
|
||||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||||
|
@ -630,12 +630,12 @@ void midwunit_state::wunit(machine_config &config)
|
|||||||
|
|
||||||
TMS34010(config, m_maincpu, 50000000);
|
TMS34010(config, m_maincpu, 50000000);
|
||||||
m_maincpu->set_addrmap(AS_PROGRAM, &midwunit_state::main_map);
|
m_maincpu->set_addrmap(AS_PROGRAM, &midwunit_state::main_map);
|
||||||
m_maincpu->set_halt_on_reset(false); /* halt on reset */
|
m_maincpu->set_halt_on_reset(false); /* halt on reset */
|
||||||
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
|
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
|
||||||
m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
|
m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
|
||||||
m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
|
m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
|
||||||
m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
|
m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
|
||||||
m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
|
m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
|
||||||
m_maincpu->set_screen("screen");
|
m_maincpu->set_screen("screen");
|
||||||
|
|
||||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||||
|
@ -248,12 +248,12 @@ void midxunit_state::midxunit(machine_config &config)
|
|||||||
/* basic machine hardware */
|
/* basic machine hardware */
|
||||||
TMS34020(config, m_maincpu, 40000000);
|
TMS34020(config, m_maincpu, 40000000);
|
||||||
m_maincpu->set_addrmap(AS_PROGRAM, &midxunit_state::main_map);
|
m_maincpu->set_addrmap(AS_PROGRAM, &midxunit_state::main_map);
|
||||||
m_maincpu->set_halt_on_reset(false); /* halt on reset */
|
m_maincpu->set_halt_on_reset(false); /* halt on reset */
|
||||||
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
|
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
|
||||||
m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
|
m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
|
||||||
m_maincpu->set_scanline_ind16_callback("video", FUNC(midxunit_video_device::scanline_update)); /* scanline updater (indexed16) */
|
m_maincpu->set_scanline_ind16_callback("video", FUNC(midxunit_video_device::scanline_update)); /* scanline updater (indexed16) */
|
||||||
m_maincpu->set_shiftreg_in_callback("video", FUNC(midxunit_video_device::to_shiftreg)); /* write to shiftreg function */
|
m_maincpu->set_shiftreg_in_callback("video", FUNC(midxunit_video_device::to_shiftreg)); /* write to shiftreg function */
|
||||||
m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
|
m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
|
||||||
m_maincpu->set_screen("screen");
|
m_maincpu->set_screen("screen");
|
||||||
|
|
||||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||||
|
@ -116,7 +116,7 @@ void minivideo_state::minivideo(machine_config &config)
|
|||||||
/*
|
/*
|
||||||
PCB is marked: "MINIVIDEO 1.3" on component side
|
PCB is marked: "MINIVIDEO 1.3" on component side
|
||||||
PCB is marked: "MINIVIDEO 1.3" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
|
PCB is marked: "MINIVIDEO 1.3" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
|
||||||
PCB is labelled: "LF1.3" on component side
|
PCB is labelled: "LF1.3" on component side
|
||||||
*/
|
*/
|
||||||
ROM_START( fiches )
|
ROM_START( fiches )
|
||||||
ROM_REGION(0x8000, "maincpu", 0)
|
ROM_REGION(0x8000, "maincpu", 0)
|
||||||
@ -130,7 +130,7 @@ ROM_END
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
PCB is marked: "MINIVIDEO 1.2" on component side
|
PCB is marked: "MINIVIDEO 1.2" on component side
|
||||||
PCB is marked: "MINIVIDEO 1.2" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
|
PCB is marked: "MINIVIDEO 1.2" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
|
||||||
*/
|
*/
|
||||||
ROM_START( fiches12 )
|
ROM_START( fiches12 )
|
||||||
ROM_REGION(0x8000, "maincpu", 0)
|
ROM_REGION(0x8000, "maincpu", 0)
|
||||||
|
@ -64,29 +64,29 @@ void monon_color_state::machine_start()
|
|||||||
memcpy(maincpu, flash+0x200, 0x1e00); // 0x4000-0x5dff fixed code?
|
memcpy(maincpu, flash+0x200, 0x1e00); // 0x4000-0x5dff fixed code?
|
||||||
|
|
||||||
// there are a whole bunch of blocks that map at 0x5e00 (boot code jumps straight to 0x5e00)
|
// there are a whole bunch of blocks that map at 0x5e00 (boot code jumps straight to 0x5e00)
|
||||||
|
|
||||||
memcpy(maincpu+0x1e00, flash+0x2000, 0x1000); // clears RAM, sets up stack etc. but then jumps to 0x9xxx where we have nothing (probably the correct initial block tho)
|
memcpy(maincpu+0x1e00, flash+0x2000, 0x1000); // clears RAM, sets up stack etc. but then jumps to 0x9xxx where we have nothing (probably the correct initial block tho)
|
||||||
// memcpy(maincpu+0x1e00, flash+0x4200, 0x1000); // just set register + a jump (to function that writes to UART)
|
// memcpy(maincpu+0x1e00, flash+0x4200, 0x1000); // just set register + a jump (to function that writes to UART)
|
||||||
// memcpy(maincpu+0x1e00, flash+0x4c00, 0x1000);
|
// memcpy(maincpu+0x1e00, flash+0x4c00, 0x1000);
|
||||||
// memcpy(maincpu+0x1e00, flash+0x5600, 0x1000);
|
// memcpy(maincpu+0x1e00, flash+0x5600, 0x1000);
|
||||||
// memcpy(maincpu+0x1e00, flash+0x6000, 0x1000); // ends up reting with nothing on the stack
|
// memcpy(maincpu+0x1e00, flash+0x6000, 0x1000); // ends up reting with nothing on the stack
|
||||||
// memcpy(maincpu+0x1e00, flash+0x6a00, 0x1000);
|
// memcpy(maincpu+0x1e00, flash+0x6a00, 0x1000);
|
||||||
// memcpy(maincpu+0x1e00, flash+0x7e00, 0x1000);
|
// memcpy(maincpu+0x1e00, flash+0x7e00, 0x1000);
|
||||||
// memcpy(maincpu+0x1e00, flash+0x8800, 0x1000);
|
// memcpy(maincpu+0x1e00, flash+0x8800, 0x1000);
|
||||||
// memcpy(maincpu+0x1e00, flash+0x9200, 0x1000);
|
// memcpy(maincpu+0x1e00, flash+0x9200, 0x1000);
|
||||||
|
|
||||||
/* block starting at e000 in flash is not code? (or encrypted?)
|
/* block starting at e000 in flash is not code? (or encrypted?)
|
||||||
no code to map at 0x9000 in address space (possible BIOS?)
|
no code to map at 0x9000 in address space (possible BIOS?)
|
||||||
no code in flash ROM past the first 64kb(?) which is basically the same on all games, must be some kind of script interpreter? J2ME maybe?
|
no code in flash ROM past the first 64kb(?) which is basically the same on all games, must be some kind of script interpreter? J2ME maybe?
|
||||||
|
|
||||||
there are 4 different 'versions' of the code in the dumped ROMs, where the code is the same the roms match up until 0x50000 after which the game specific data starts
|
there are 4 different 'versions' of the code in the dumped ROMs, where the code is the same the roms match up until 0x50000 after which the game specific data starts
|
||||||
|
|
||||||
by game number:
|
by game number:
|
||||||
|
|
||||||
101,102,103,104,105 (1st revision)
|
101,102,103,104,105 (1st revision)
|
||||||
106,107 (2nd revision)
|
106,107 (2nd revision)
|
||||||
201 (3rd revision)
|
201 (3rd revision)
|
||||||
202,203,204,205,301,303,304 (4th revision)
|
202,203,204,205,301,303,304 (4th revision)
|
||||||
*/
|
*/
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3,13 +3,13 @@
|
|||||||
/***************************************************************************
|
/***************************************************************************
|
||||||
|
|
||||||
mupid/Infonova C2A2
|
mupid/Infonova C2A2
|
||||||
Grundig PTC-100
|
Grundig PTC-100
|
||||||
|
|
||||||
- Z80
|
- Z80
|
||||||
- 128 + 8 KB RAM
|
- 128 + 8 KB RAM
|
||||||
- Z80 SIO/0
|
- Z80 SIO/0
|
||||||
- 8035
|
- 8035
|
||||||
- M58990P-1 ADC
|
- M58990P-1 ADC
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
@ -112,24 +112,24 @@ INPUT_PORTS_END
|
|||||||
|
|
||||||
READ8_MEMBER(mupid2_state::kbd_bus_r)
|
READ8_MEMBER(mupid2_state::kbd_bus_r)
|
||||||
{
|
{
|
||||||
// logerror("kbd_bus_r\n");
|
// logerror("kbd_bus_r\n");
|
||||||
return 0xff;
|
return 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
READ8_MEMBER(mupid2_state::kbd_p1_r)
|
READ8_MEMBER(mupid2_state::kbd_p1_r)
|
||||||
{
|
{
|
||||||
// logerror("kbd_p1_r\n");
|
// logerror("kbd_p1_r\n");
|
||||||
return 0xff;
|
return 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE8_MEMBER(mupid2_state::kbd_p1_w)
|
WRITE8_MEMBER(mupid2_state::kbd_p1_w)
|
||||||
{
|
{
|
||||||
// logerror("kbd_p1_w: %02x\n", data);
|
// logerror("kbd_p1_w: %02x\n", data);
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE8_MEMBER(mupid2_state::kbd_p2_w)
|
WRITE8_MEMBER(mupid2_state::kbd_p2_w)
|
||||||
{
|
{
|
||||||
// logerror("kbd_p2_w: %02x\n", data);
|
// logerror("kbd_p2_w: %02x\n", data);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -61,7 +61,7 @@ void nes_state::nes(machine_config &config)
|
|||||||
// non-rendering scanlines, we compensate. This ends up being 2500 cycles for the non-rendering portion, 2273
|
// non-rendering scanlines, we compensate. This ends up being 2500 cycles for the non-rendering portion, 2273
|
||||||
// cycles for the actual vblank period.
|
// cycles for the actual vblank period.
|
||||||
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(NTSC_APU_CLOCK.dvalue()/1000000)) *
|
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(NTSC_APU_CLOCK.dvalue()/1000000)) *
|
||||||
(ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
(ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
||||||
m_screen->set_size(32*8, 262);
|
m_screen->set_size(32*8, 262);
|
||||||
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
||||||
m_screen->set_screen_update(FUNC(nes_state::screen_update_nes));
|
m_screen->set_screen_update(FUNC(nes_state::screen_update_nes));
|
||||||
@ -103,7 +103,7 @@ void nes_state::nespal(machine_config &config)
|
|||||||
/* video hardware */
|
/* video hardware */
|
||||||
m_screen->set_refresh_hz(50.0070);
|
m_screen->set_refresh_hz(50.0070);
|
||||||
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
|
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
|
||||||
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
||||||
m_screen->set_size(32*8, 312);
|
m_screen->set_size(32*8, 312);
|
||||||
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
||||||
}
|
}
|
||||||
@ -136,7 +136,7 @@ void nes_state::nespalc(machine_config &config)
|
|||||||
/* video hardware */
|
/* video hardware */
|
||||||
m_screen->set_refresh_hz(50.0070);
|
m_screen->set_refresh_hz(50.0070);
|
||||||
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(PALC_APU_CLOCK.dvalue()/1000000)) *
|
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(PALC_APU_CLOCK.dvalue()/1000000)) *
|
||||||
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE_PALC+1+2)));
|
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE_PALC+1+2)));
|
||||||
}
|
}
|
||||||
|
|
||||||
void nes_state::famipalc(machine_config &config)
|
void nes_state::famipalc(machine_config &config)
|
||||||
|
@ -1361,7 +1361,7 @@ void nes_vt_state::nes_vt_base(machine_config &config)
|
|||||||
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
||||||
m_screen->set_refresh_hz(60.0988);
|
m_screen->set_refresh_hz(60.0988);
|
||||||
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(NTSC_APU_CLOCK.dvalue()/1000000)) *
|
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(NTSC_APU_CLOCK.dvalue()/1000000)) *
|
||||||
(ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
(ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
||||||
m_screen->set_size(32*8, 262);
|
m_screen->set_size(32*8, 262);
|
||||||
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
||||||
m_screen->set_screen_update("ppu", FUNC(ppu2c0x_device::screen_update));
|
m_screen->set_screen_update("ppu", FUNC(ppu2c0x_device::screen_update));
|
||||||
@ -1454,7 +1454,7 @@ void nes_vt_state::nes_vt_dg(machine_config &config)
|
|||||||
|
|
||||||
m_screen->set_refresh_hz(50.0070);
|
m_screen->set_refresh_hz(50.0070);
|
||||||
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
|
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
|
||||||
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
||||||
m_screen->set_size(32*8, 312);
|
m_screen->set_size(32*8, 312);
|
||||||
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
||||||
}
|
}
|
||||||
@ -1477,7 +1477,7 @@ void nes_vt_state::nes_vt_hh(machine_config &config)
|
|||||||
/* video hardware */
|
/* video hardware */
|
||||||
m_screen->set_refresh_hz(50.0070);
|
m_screen->set_refresh_hz(50.0070);
|
||||||
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
|
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
|
||||||
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
(ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
|
||||||
m_screen->set_size(32*8, 312);
|
m_screen->set_size(32*8, 312);
|
||||||
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
|
||||||
}
|
}
|
||||||
|
@ -340,8 +340,8 @@ void overdriv_state::overdriv(machine_config &config)
|
|||||||
|
|
||||||
MC6809E(config, m_audiocpu, XTAL(3'579'545)); /* 1.789 MHz?? This might be the right speed, but ROM testing */
|
MC6809E(config, m_audiocpu, XTAL(3'579'545)); /* 1.789 MHz?? This might be the right speed, but ROM testing */
|
||||||
m_audiocpu->set_addrmap(AS_PROGRAM, &overdriv_state::overdriv_sound_map); /* takes a little too much (the counter wraps from 0000 to 9999). */
|
m_audiocpu->set_addrmap(AS_PROGRAM, &overdriv_state::overdriv_sound_map); /* takes a little too much (the counter wraps from 0000 to 9999). */
|
||||||
/* This might just mean that the video refresh rate is less than */
|
/* This might just mean that the video refresh rate is less than */
|
||||||
/* 60 fps, that's how I fixed it for now. */
|
/* 60 fps, that's how I fixed it for now. */
|
||||||
|
|
||||||
config.m_minimum_quantum = attotime::from_hz(12000);
|
config.m_minimum_quantum = attotime::from_hz(12000);
|
||||||
|
|
||||||
|
@ -16,7 +16,7 @@
|
|||||||
Reading fdc has been commented out, until the code can be modified to
|
Reading fdc has been commented out, until the code can be modified to
|
||||||
work with new upd765 (was causing a hang at boot).
|
work with new upd765 (was causing a hang at boot).
|
||||||
|
|
||||||
Schematics: https://archive.org/details/Io19839/page/n331
|
Schematics: https://archive.org/details/Io19839/page/n331
|
||||||
|
|
||||||
***************************************************************************************************/
|
***************************************************************************************************/
|
||||||
|
|
||||||
|
@ -1356,7 +1356,7 @@ READ32_MEMBER(pgm2_state::ddpdojt_speedup_r)
|
|||||||
/*
|
/*
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
logerror("pc is %08x\n", pc);
|
logerror("pc is %08x\n", pc);
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -1375,7 +1375,7 @@ READ32_MEMBER(pgm2_state::ddpdojt_speedup2_r)
|
|||||||
/*
|
/*
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
logerror("pc is %08x\n", pc);
|
logerror("pc is %08x\n", pc);
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
@ -1,9 +1,9 @@
|
|||||||
// license:GPL-2.0+
|
// license:GPL-2.0+
|
||||||
// copyright-holders:Peter Trauner
|
// copyright-holders:Peter Trauner
|
||||||
/******************************************************************************
|
/******************************************************************************
|
||||||
Sharp pocket computers
|
Sharp pocket computers
|
||||||
PC1401/PC1403
|
PC1401/PC1403
|
||||||
PeT mess@utanet.at May 2000
|
PeT mess@utanet.at May 2000
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
||||||
#include "emu.h"
|
#include "emu.h"
|
||||||
|
@ -542,8 +542,8 @@ void psx1_state::psx_base(machine_config &config)
|
|||||||
SPEAKER(config, "lspeaker").front_left();
|
SPEAKER(config, "lspeaker").front_left();
|
||||||
SPEAKER(config, "rspeaker").front_right();
|
SPEAKER(config, "rspeaker").front_right();
|
||||||
spu_device &spu(SPU(config, "spu", XTAL(67'737'600)/2, m_maincpu.target()));
|
spu_device &spu(SPU(config, "spu", XTAL(67'737'600)/2, m_maincpu.target()));
|
||||||
spu.add_route(0, "lspeaker", 1.00);
|
spu.add_route(0, "lspeaker", 1.00);
|
||||||
spu.add_route(1, "rspeaker", 1.00);
|
spu.add_route(1, "rspeaker", 1.00);
|
||||||
|
|
||||||
quickload_image_device &quickload(QUICKLOAD(config, "quickload", 0));
|
quickload_image_device &quickload(QUICKLOAD(config, "quickload", 0));
|
||||||
quickload.set_handler(snapquick_load_delegate(&QUICKLOAD_LOAD_NAME(psx1_state, psx_exe_load), this), "cpe,exe,psf,psx", 0);
|
quickload.set_handler(snapquick_load_delegate(&QUICKLOAD_LOAD_NAME(psx1_state, psx_exe_load), this), "cpe,exe,psf,psx", 0);
|
||||||
|
@ -781,9 +781,9 @@ private:
|
|||||||
// THIS MACRO * RESETS * the PATTERN TO DEFAULT.
|
// THIS MACRO * RESETS * the PATTERN TO DEFAULT.
|
||||||
// NOTE 2: m_patmult MUST BE LOADED BEFORE !!
|
// NOTE 2: m_patmult MUST BE LOADED BEFORE !!
|
||||||
#define OPTION_RESET_PATTERNS \
|
#define OPTION_RESET_PATTERNS \
|
||||||
m_vpat = 0xff; \
|
m_vpat = 0xff; \
|
||||||
if (m_patmult == 0) m_patmult = 0x01; \
|
if (m_patmult == 0) m_patmult = 0x01; \
|
||||||
if (m_patcnt == 0) m_patcnt = m_patmult; \
|
if (m_patcnt == 0) m_patcnt = m_patmult; \
|
||||||
if (m_patidx == 0) m_patidx = 7;
|
if (m_patidx == 0) m_patidx = 7;
|
||||||
|
|
||||||
|
|
||||||
@ -793,8 +793,8 @@ private:
|
|||||||
m_monitor_suggested = m_inp13->read(); \
|
m_monitor_suggested = m_inp13->read(); \
|
||||||
m_gdc_indirect_register = 0; \
|
m_gdc_indirect_register = 0; \
|
||||||
m_gdc_color_map_index = 0; \
|
m_gdc_color_map_index = 0; \
|
||||||
for (int i = 0; i < 256; i++) \
|
for (int i = 0; i < 256; i++) \
|
||||||
m_gdc_scroll_buffer[i] = i; \
|
m_gdc_scroll_buffer[i] = i; \
|
||||||
m_gdc_scroll_index = 0; \
|
m_gdc_scroll_index = 0; \
|
||||||
m_gdc_write_buffer_index = 0; \
|
m_gdc_write_buffer_index = 0; \
|
||||||
m_gdc_write_mask = 0x00; \
|
m_gdc_write_mask = 0x00; \
|
||||||
@ -2175,11 +2175,11 @@ READ8_MEMBER(rainbow_state::system_parameter_r)
|
|||||||
return ((m_inp5->read() == 1 ? 0 : 1) |
|
return ((m_inp5->read() == 1 ? 0 : 1) |
|
||||||
(m_inp7->read() == 1 ? 0 : 4) | // Floppy is always present (bit 1 zero)
|
(m_inp7->read() == 1 ? 0 : 4) | // Floppy is always present (bit 1 zero)
|
||||||
#ifdef OLD_RAM_BOARD_PRESENT
|
#ifdef OLD_RAM_BOARD_PRESENT
|
||||||
(m_inp8->read() > MOTHERBOARD_RAM ? 0 : 8) |
|
(m_inp8->read() > MOTHERBOARD_RAM ? 0 : 8) |
|
||||||
#else
|
#else
|
||||||
8 | // unverified
|
8 | // unverified
|
||||||
#endif
|
#endif
|
||||||
16 | 32 | 64 | 128); // unverified
|
16 | 32 | 64 | 128); // unverified
|
||||||
}
|
}
|
||||||
|
|
||||||
// [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** )
|
// [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** )
|
||||||
@ -2198,7 +2198,7 @@ READ8_MEMBER(rainbow_state::comm_control_r)
|
|||||||
is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED);
|
is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED);
|
||||||
|
|
||||||
return (m_comm_port->ri_r() ? 0x01 : 0x00) |
|
return (m_comm_port->ri_r() ? 0x01 : 0x00) |
|
||||||
(m_comm_port->si_r() ? 0x02 : 0x00) |
|
(m_comm_port->si_r() ? 0x02 : 0x00) |
|
||||||
(m_comm_port->dsr_r() ? 0x04 : 0x00) |
|
(m_comm_port->dsr_r() ? 0x04 : 0x00) |
|
||||||
(m_comm_port->cts_r() ? 0x08 : 0x00) |
|
(m_comm_port->cts_r() ? 0x08 : 0x00) |
|
||||||
(m_comm_port->dcd_r() ? 0x10 : 0x00) |
|
(m_comm_port->dcd_r() ? 0x10 : 0x00) |
|
||||||
@ -2355,13 +2355,13 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
|
|||||||
}
|
}
|
||||||
// logerror(" RDY:%x WG:%d ",fdc_ready,fdc_write_gate);
|
// logerror(" RDY:%x WG:%d ",fdc_ready,fdc_write_gate);
|
||||||
int data = (fdc_step ? 0x00 : 0x80) |
|
int data = (fdc_step ? 0x00 : 0x80) |
|
||||||
(fdc_write_gate ? 0x00 : 0x40) |
|
(fdc_write_gate ? 0x00 : 0x40) |
|
||||||
(tk00 ? 0x20 : 0x00) | // ***** ALL LOW ACTIVE - EXCEPT tk00 :
|
(tk00 ? 0x20 : 0x00) | // ***** ALL LOW ACTIVE - EXCEPT tk00 :
|
||||||
(last_dir ? 0x00 : 0x10) |
|
(last_dir ? 0x00 : 0x10) |
|
||||||
(fdc_ready ? 0x00 : 0x08) |
|
(fdc_ready ? 0x00 : 0x08) |
|
||||||
(m_int88 ? 0x00 : 0x04) |
|
(m_int88 ? 0x00 : 0x04) |
|
||||||
(m_intz80 ? 0x00 : 0x02) |
|
(m_intz80 ? 0x00 : 0x02) |
|
||||||
(m_zflip ? 0x00 : 0x01);
|
(m_zflip ? 0x00 : 0x01);
|
||||||
|
|
||||||
return data;
|
return data;
|
||||||
}
|
}
|
||||||
@ -3151,7 +3151,7 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
|
|||||||
// NEXT: 32 BYTE COLOR MAP, LOADED TO $51
|
// NEXT: 32 BYTE COLOR MAP, LOADED TO $51
|
||||||
|
|
||||||
//if (m_gdc_indirect_register & GDC_SELECT_MODE_REGISTER) // 0x40
|
//if (m_gdc_indirect_register & GDC_SELECT_MODE_REGISTER) // 0x40
|
||||||
// logerror(" *** SELECT MODE REGISTER");
|
// logerror(" *** SELECT MODE REGISTER");
|
||||||
|
|
||||||
if (m_gdc_indirect_register & GDC_SELECT_SCROLL_MAP) // 0x80
|
if (m_gdc_indirect_register & GDC_SELECT_SCROLL_MAP) // 0x80
|
||||||
{
|
{
|
||||||
|
@ -21,7 +21,7 @@
|
|||||||
|
|
||||||
PCB specs: Hardware not available
|
PCB specs: Hardware not available
|
||||||
|
|
||||||
|
|
||||||
*********************************************************************
|
*********************************************************************
|
||||||
|
|
||||||
Edge Connector:
|
Edge Connector:
|
||||||
@ -72,7 +72,7 @@
|
|||||||
+---------------------------------------+-----+-----+-----+-----------------------------+
|
+---------------------------------------+-----+-----+-----+-----------------------------+
|
||||||
| Demo No | | | OFF | |
|
| Demo No | | | OFF | |
|
||||||
| Si | | | ON | |
|
| Si | | | ON | |
|
||||||
+---------------------------------------+-----+-----+-----+-----+-----------------------+
|
+---------------------------------------+-----+-----+-----+-----+-----------------------+
|
||||||
| Acceso a Pagina No | | OFF | |
|
| Acceso a Pagina No | | OFF | |
|
||||||
| (settings access) Si | | ON | |
|
| (settings access) Si | | ON | |
|
||||||
+---------------------------------------+-----------------+-----+-----+-----------------+
|
+---------------------------------------+-----------------+-----+-----+-----------------+
|
||||||
@ -96,18 +96,18 @@
|
|||||||
-------------------
|
-------------------
|
||||||
|
|
||||||
(You must enable "LAMPS" layout for this procedure)
|
(You must enable "LAMPS" layout for this procedure)
|
||||||
|
|
||||||
When the game runs by the very first time (no nvram yet), it will
|
When the game runs by the very first time (no nvram yet), it will
|
||||||
complain about "DATA ERROR" in a blue message window. After a few
|
complain about "DATA ERROR" in a blue message window. After a few
|
||||||
seconds, it will bring up another red window with the "HARD ERROR 02"
|
seconds, it will bring up another red window with the "HARD ERROR 02"
|
||||||
message.
|
message.
|
||||||
|
|
||||||
So, we must initialize the game following the next instructions:
|
So, we must initialize the game following the next instructions:
|
||||||
|
|
||||||
1.- Toggle ON "Operator Key" (turn to green).
|
1.- Toggle ON "Operator Key" (turn to green).
|
||||||
|
|
||||||
2.- Press once "Page Key". It will show a green window titled
|
2.- Press once "Page Key". It will show a green window titled
|
||||||
"CONTROL ADMINISTRATIVO" and a message with a security token.
|
"CONTROL ADMINISTRATIVO" and a message with a security token.
|
||||||
|
|
||||||
3.- Press again "Page Key". It will bring up a new window where we
|
3.- Press again "Page Key". It will bring up a new window where we
|
||||||
must type a password. At this time, in the layout, under the
|
must type a password. At this time, in the layout, under the
|
||||||
@ -115,25 +115,25 @@
|
|||||||
|
|
||||||
4.- Enter the required paswword using the credits in (IN1....IN6)
|
4.- Enter the required paswword using the credits in (IN1....IN6)
|
||||||
and credits out (OUT1...OUT6) buttons following the key assignment
|
and credits out (OUT1...OUT6) buttons following the key assignment
|
||||||
indications located under the password field.
|
indications located under the password field.
|
||||||
Use the "E" button to finish once all numbers were typed.
|
Use the "E" button to finish once all numbers were typed.
|
||||||
Use the "B" button clear last digit typed, in case of mistake.
|
Use the "B" button clear last digit typed, in case of mistake.
|
||||||
|
|
||||||
5.- Once finished that, the game will reboot and will be ready
|
5.- Once finished that, the game will reboot and will be ready
|
||||||
to play. Also, password showed on layout will dissapear.
|
to play. Also, password showed on layout will dissapear.
|
||||||
|
|
||||||
In case that (by unknown reason) the game asks for
|
In case that (by unknown reason) the game asks for
|
||||||
"CONTROL ADMINISTRATIVO" again, follow the instructions starting
|
"CONTROL ADMINISTRATIVO" again, follow the instructions starting
|
||||||
from step "1". After that, we will can play again.
|
from step "1". After that, we will can play again.
|
||||||
|
|
||||||
|
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
|
|
||||||
|
|
||||||
/*********************************************************************
|
/*********************************************************************
|
||||||
|
|
||||||
Dev notes:
|
Dev notes:
|
||||||
|
|
||||||
Again, this driver was written based on a couple of ROM dumps and a
|
Again, this driver was written based on a couple of ROM dumps and a
|
||||||
lot of reverse engineering, with no harware available, but guessing
|
lot of reverse engineering, with no harware available, but guessing
|
||||||
that this firmware and hardware are similar to others well known
|
that this firmware and hardware are similar to others well known
|
||||||
@ -141,30 +141,30 @@
|
|||||||
|
|
||||||
The most exciting part of this work was discover that this game runs
|
The most exciting part of this work was discover that this game runs
|
||||||
with an electromechanical roulette, not a tipical LED roulette. It
|
with an electromechanical roulette, not a tipical LED roulette. It
|
||||||
added an extra challenge to the work, wich implies a full develop
|
added an extra challenge to the work, wich implies a full develop
|
||||||
of an electromechanical part simulation, objective that finally
|
of an electromechanical part simulation, objective that finally
|
||||||
could be reached.
|
could be reached.
|
||||||
|
|
||||||
Surprisingly, this game firmware includes a full communications
|
Surprisingly, this game firmware includes a full communications
|
||||||
module, accesible via RS232 serial interface, that let the users
|
module, accesible via RS232 serial interface, that let the users
|
||||||
some useful things like reconfigure hardware and game options or
|
some useful things like reconfigure hardware and game options or
|
||||||
get different kinds of reports, like accounting, statistics and
|
get different kinds of reports, like accounting, statistics and
|
||||||
many other technical items. All this tasks are performed from a
|
many other technical items. All this tasks are performed from a
|
||||||
PC running a D.O.S. program provided by the maker and fortunately
|
PC running a D.O.S. program provided by the maker and fortunately
|
||||||
still available. Even more, there is another standalone D.O.S.
|
still available. Even more, there is another standalone D.O.S.
|
||||||
software provided by the manufacturer (also still available) to
|
software provided by the manufacturer (also still available) to
|
||||||
get the passwords needed when hardware fails or administrative
|
get the passwords needed when hardware fails or administrative
|
||||||
tasks are required.
|
tasks are required.
|
||||||
|
|
||||||
Another interesting thing found on this game is that it can be
|
Another interesting thing found on this game is that it can be
|
||||||
configured for a single or a double zero roulette, depending on
|
configured for a single or a double zero roulette, depending on
|
||||||
what kind of roulette has attached.
|
what kind of roulette has attached.
|
||||||
|
|
||||||
|
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
|
|
||||||
|
|
||||||
#define CPU_CLOCK XTAL(8'000'000) // guess
|
#define CPU_CLOCK XTAL(8'000'000) // guess
|
||||||
#define VID_CLOCK XTAL(21'477'272) // guess
|
#define VID_CLOCK XTAL(21'477'272) // guess
|
||||||
#define TMS_CLOCK (CPU_CLOCK / 4) // guess
|
#define TMS_CLOCK (CPU_CLOCK / 4) // guess
|
||||||
#define VDP_MEM 0x20000 // 4x 4464 (64K x 4 DRAM)
|
#define VDP_MEM 0x20000 // 4x 4464 (64K x 4 DRAM)
|
||||||
@ -311,7 +311,7 @@ void rulechan_state::main_io(address_map &map)
|
|||||||
map(0x31, 0x31).rw(FUNC(rulechan_state::port31_r),FUNC(rulechan_state::port31_w)); // wheel control - read: Must be 0x00 at power-up.
|
map(0x31, 0x31).rw(FUNC(rulechan_state::port31_r),FUNC(rulechan_state::port31_w)); // wheel control - read: Must be 0x00 at power-up.
|
||||||
map(0x32, 0x32).w(FUNC(rulechan_state::port32_w)); // wheel control.
|
map(0x32, 0x32).w(FUNC(rulechan_state::port32_w)); // wheel control.
|
||||||
map(0x40, 0x43).nopr().nopw();
|
map(0x40, 0x43).nopr().nopw();
|
||||||
map(0x60, 0x60).nopw(); // Watchdog.
|
map(0x60, 0x60).nopw(); // Watchdog.
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -334,7 +334,7 @@ READ8_MEMBER(rulechan_state::port3_r)
|
|||||||
return 0xff;
|
return 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
/******************************
|
/******************************
|
||||||
Port 30 - Wheel control *
|
Port 30 - Wheel control *
|
||||||
* bit 2 - ball detector *
|
* bit 2 - ball detector *
|
||||||
* bit 3 - step detector *
|
* bit 3 - step detector *
|
||||||
@ -397,7 +397,7 @@ WRITE8_MEMBER(rulechan_state::port31_w)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if(BIT(m_p31, 7)) // Shoot ball.
|
if(BIT(m_p31, 7)) // Shoot ball.
|
||||||
{
|
{
|
||||||
m_p30 &= 0xdf; // ball out....
|
m_p30 &= 0xdf; // ball out....
|
||||||
m_num = machine().rand() % 37; // sort winning number.
|
m_num = machine().rand() % 37; // sort winning number.
|
||||||
|
|
||||||
@ -426,7 +426,7 @@ void rulechan_state::sound_off()
|
|||||||
{
|
{
|
||||||
m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
|
m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
|
||||||
m_maincpu->space(AS_IO).write_byte(0x11, m_maincpu->space(AS_PROGRAM).read_byte(SND_FLG) | 0x20);
|
m_maincpu->space(AS_IO).write_byte(0x11, m_maincpu->space(AS_PROGRAM).read_byte(SND_FLG) | 0x20);
|
||||||
m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
|
m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
|
||||||
}
|
}
|
||||||
|
|
||||||
void rulechan_state::sound_sort()
|
void rulechan_state::sound_sort()
|
||||||
@ -436,9 +436,9 @@ void rulechan_state::sound_sort()
|
|||||||
m_maincpu->space(AS_IO).write_byte(0x10, m_sndsrt[(2 * i)]);
|
m_maincpu->space(AS_IO).write_byte(0x10, m_sndsrt[(2 * i)]);
|
||||||
m_maincpu->space(AS_IO).write_byte(0x11, m_sndsrt[(2 * i) + 1]);
|
m_maincpu->space(AS_IO).write_byte(0x11, m_sndsrt[(2 * i) + 1]);
|
||||||
}
|
}
|
||||||
m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
|
m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
|
||||||
m_maincpu->space(AS_IO).write_byte(0x11, m_maincpu->space(AS_PROGRAM).read_byte(SND_FLG) & 0xdf);
|
m_maincpu->space(AS_IO).write_byte(0x11, m_maincpu->space(AS_PROGRAM).read_byte(SND_FLG) & 0xdf);
|
||||||
m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
|
m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -451,24 +451,24 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
|
|||||||
if(m_step == 0)
|
if(m_step == 0)
|
||||||
{
|
{
|
||||||
if((BIT4) & (m_updn4 == 0))
|
if((BIT4) & (m_updn4 == 0))
|
||||||
{
|
{
|
||||||
m_p30 &= 0xef;
|
m_p30 &= 0xef;
|
||||||
m_updn4 = 1;
|
m_updn4 = 1;
|
||||||
|
|
||||||
//logerror("1:port_p30:- Reset bit 4 pulse start -%2x cont_pasos:%2d\n",m_p30, m_step);
|
//logerror("1:port_p30:- Reset bit 4 pulse start -%2x cont_pasos:%2d\n",m_p30, m_step);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if((!BIT4) & (m_updn4 == 1))
|
if((!BIT4) & (m_updn4 == 1))
|
||||||
{
|
{
|
||||||
m_p30 |= 0x10;
|
m_p30 |= 0x10;
|
||||||
|
|
||||||
//logerror("2:port_p30:- Set bit 4 -%2x cont_pasos:%2d\n",m_p30, m_step);
|
//logerror("2:port_p30:- Set bit 4 -%2x cont_pasos:%2d\n",m_p30, m_step);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if((BIT4) & (m_updn4 == 1))
|
if((BIT4) & (m_updn4 == 1))
|
||||||
{
|
{
|
||||||
m_updn4 = 0;
|
m_updn4 = 0;
|
||||||
m_step++;
|
m_step++;
|
||||||
|
|
||||||
@ -485,9 +485,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
|
|||||||
//logerror("4:port_p30:-reset bit 3 -%2x cont_pasos:%2d\n",m_p30, m_step);
|
//logerror("4:port_p30:-reset bit 3 -%2x cont_pasos:%2d\n",m_p30, m_step);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if(!BIT3 & (m_updn3 == 0))
|
if(!BIT3 & (m_updn3 == 0))
|
||||||
{
|
{
|
||||||
if(!BIT2)
|
if(!BIT2)
|
||||||
{
|
{
|
||||||
m_p30 |= 0x04;
|
m_p30 |= 0x04;
|
||||||
@ -497,13 +497,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
if((m_step - 1 == m_num) & (m_updn2 == 0))
|
if((m_step - 1 == m_num) & (m_updn2 == 0))
|
||||||
{
|
{
|
||||||
if(!BIT5) // ball in pocket?...
|
if(!BIT5) // ball in pocket?...
|
||||||
{
|
{
|
||||||
m_p30 &= 0xfb;
|
m_p30 &= 0xfb;
|
||||||
m_updn2 = 1;
|
m_updn2 = 1;
|
||||||
m_ballin++;
|
m_ballin++;
|
||||||
logerror("Ball In Pocket m_num:%2x\n", m_num);
|
logerror("Ball In Pocket m_num:%2x\n", m_num);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -513,18 +513,18 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
|
|||||||
m_updn2 = 0;
|
m_updn2 = 0;
|
||||||
m_updn3 = 1;
|
m_updn3 = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
if(!BIT3 & (m_updn3 == 1))
|
if(!BIT3 & (m_updn3 == 1))
|
||||||
{
|
{
|
||||||
m_p30 |= 0x08;
|
m_p30 |= 0x08;
|
||||||
m_updn3 = 0;
|
m_updn3 = 0;
|
||||||
m_step++;
|
m_step++;
|
||||||
|
|
||||||
if (m_step == 39)
|
if (m_step == 39)
|
||||||
{
|
{
|
||||||
m_step = 0;
|
m_step = 0;
|
||||||
m_p30 |= 0x1c;
|
m_p30 |= 0x1c;
|
||||||
}
|
}
|
||||||
|
|
||||||
//logerror("6:port_p30:-set bit 3 -%2x cont_pasos:%2d \n",m_p30, m_step);
|
//logerror("6:port_p30:-set bit 3 -%2x cont_pasos:%2d \n",m_p30, m_step);
|
||||||
return;
|
return;
|
||||||
@ -540,7 +540,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
|
|||||||
TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
|
TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
|
||||||
{
|
{
|
||||||
if(MOTORON)
|
if(MOTORON)
|
||||||
{
|
{
|
||||||
if(d_spin == 0)
|
if(d_spin == 0)
|
||||||
{
|
{
|
||||||
m_tspin++;
|
m_tspin++;
|
||||||
@ -550,18 +550,18 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
|
|||||||
{
|
{
|
||||||
m_tspin = 37; // breaking ball once per number step.
|
m_tspin = 37; // breaking ball once per number step.
|
||||||
}
|
}
|
||||||
|
|
||||||
if(m_tspin == 37)
|
if(m_tspin == 37)
|
||||||
{
|
{
|
||||||
m_tspin = 0;
|
m_tspin = 0;
|
||||||
m_spin++;
|
m_spin++;
|
||||||
d_spin = m_spin; // breaking ball once per round.
|
d_spin = m_spin; // breaking ball once per round.
|
||||||
}
|
}
|
||||||
|
|
||||||
if((!BALLIN) | (LEDNOTNUM & BALLIN ))
|
if((!BALLIN) | (LEDNOTNUM & BALLIN ))
|
||||||
{
|
{
|
||||||
m_led++;
|
m_led++;
|
||||||
|
|
||||||
if(m_led == 37)
|
if(m_led == 37)
|
||||||
{
|
{
|
||||||
m_led = 0;
|
m_led = 0;
|
||||||
@ -596,7 +596,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
|
|||||||
/* if needed, get pass and shows it on layout*/
|
/* if needed, get pass and shows it on layout*/
|
||||||
m_pass[0] = m_maincpu->space(AS_PROGRAM).read_byte(RAM_PSW);
|
m_pass[0] = m_maincpu->space(AS_PROGRAM).read_byte(RAM_PSW);
|
||||||
|
|
||||||
if((m_pass[0] <= 0x39) & (m_pass[0] >= 0x30))
|
if((m_pass[0] <= 0x39) & (m_pass[0] >= 0x30))
|
||||||
{
|
{
|
||||||
for(int i = 0; i < 6; i++)
|
for(int i = 0; i < 6; i++)
|
||||||
{
|
{
|
||||||
@ -687,7 +687,7 @@ static INPUT_PORTS_START( rulechan )
|
|||||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_TOGGLE PORT_CODE(KEYCODE_0)
|
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_TOGGLE PORT_CODE(KEYCODE_0)
|
||||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
|
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
|
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||||
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_93cxx_device, do_read) // bit 6 is EEPROM data.
|
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_93cxx_device, do_read) // bit 6 is EEPROM data.
|
||||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_CODE(KEYCODE_9)
|
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_CODE(KEYCODE_9)
|
||||||
|
|
||||||
PORT_START("DSW")
|
PORT_START("DSW")
|
||||||
@ -737,27 +737,27 @@ MACHINE_CONFIG_START(rulechan_state::rulechan)
|
|||||||
|
|
||||||
/* nvram */
|
/* nvram */
|
||||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||||
|
|
||||||
/* eeprom */
|
/* eeprom */
|
||||||
EEPROM_93C46_8BIT(config, "eeprom");
|
EEPROM_93C46_8BIT(config, "eeprom");
|
||||||
|
|
||||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("ball_speed", rulechan_state, ball_speed, attotime::from_hz(60))
|
MCFG_TIMER_DRIVER_ADD_PERIODIC("ball_speed", rulechan_state, ball_speed, attotime::from_hz(60))
|
||||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("wheel_speed", rulechan_state, wheel_speed, attotime::from_hz(60))
|
MCFG_TIMER_DRIVER_ADD_PERIODIC("wheel_speed", rulechan_state, wheel_speed, attotime::from_hz(60))
|
||||||
|
|
||||||
/* video hardware */
|
/* video hardware */
|
||||||
v9938_device &v9938(V9938(config, "v9938", VID_CLOCK));
|
v9938_device &v9938(V9938(config, "v9938", VID_CLOCK));
|
||||||
v9938.set_screen_ntsc("screen");
|
v9938.set_screen_ntsc("screen");
|
||||||
v9938.set_vram_size(VDP_MEM);
|
v9938.set_vram_size(VDP_MEM);
|
||||||
//v9938.int_cb().set_inputline("maincpu", 0);
|
//v9938.int_cb().set_inputline("maincpu", 0);
|
||||||
SCREEN(config, "screen", SCREEN_TYPE_RASTER);
|
SCREEN(config, "screen", SCREEN_TYPE_RASTER);
|
||||||
|
|
||||||
/* sound hardware */
|
/* sound hardware */
|
||||||
SPEAKER(config, "mono").front_center();
|
SPEAKER(config, "mono").front_center();
|
||||||
ay8910_device &ay_re900(AY8910(config, "ay8910", TMS_CLOCK));
|
ay8910_device &ay_re900(AY8910(config, "ay8910", TMS_CLOCK));
|
||||||
ay_re900.port_a_read_callback().set(FUNC(rulechan_state::psg_portA_r));
|
ay_re900.port_a_read_callback().set(FUNC(rulechan_state::psg_portA_r));
|
||||||
ay_re900.port_b_read_callback().set(FUNC(rulechan_state::psg_portB_r));
|
ay_re900.port_b_read_callback().set(FUNC(rulechan_state::psg_portB_r));
|
||||||
ay_re900.add_route(ALL_OUTPUTS, "mono", 0.5);
|
ay_re900.add_route(ALL_OUTPUTS, "mono", 0.5);
|
||||||
|
|
||||||
MACHINE_CONFIG_END
|
MACHINE_CONFIG_END
|
||||||
|
|
||||||
|
|
||||||
@ -788,7 +788,7 @@ ROM_END
|
|||||||
|
|
||||||
void rulechan_state::rulechan_init()
|
void rulechan_state::rulechan_init()
|
||||||
{
|
{
|
||||||
m_p30 = 0x3c;
|
m_p30 = 0x3c;
|
||||||
m_p32 = 0xf0; // Motor off at startup
|
m_p32 = 0xf0; // Motor off at startup
|
||||||
m_step = 0;
|
m_step = 0;
|
||||||
m_updn2 = 0;
|
m_updn2 = 0;
|
||||||
|
@ -515,7 +515,7 @@ void samcoupe_state::samcoupe(machine_config &config)
|
|||||||
/* video hardware */
|
/* video hardware */
|
||||||
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
||||||
m_screen->set_raw(SAMCOUPE_XTAL_X1/2, SAM_TOTAL_WIDTH, 0, SAM_BORDER_LEFT + SAM_SCREEN_WIDTH + SAM_BORDER_RIGHT,
|
m_screen->set_raw(SAMCOUPE_XTAL_X1/2, SAM_TOTAL_WIDTH, 0, SAM_BORDER_LEFT + SAM_SCREEN_WIDTH + SAM_BORDER_RIGHT,
|
||||||
SAM_TOTAL_HEIGHT, 0, SAM_BORDER_TOP + SAM_SCREEN_HEIGHT + SAM_BORDER_BOTTOM);
|
SAM_TOTAL_HEIGHT, 0, SAM_BORDER_TOP + SAM_SCREEN_HEIGHT + SAM_BORDER_BOTTOM);
|
||||||
m_screen->set_screen_update(FUNC(samcoupe_state::screen_update));
|
m_screen->set_screen_update(FUNC(samcoupe_state::screen_update));
|
||||||
m_screen->set_palette("palette");
|
m_screen->set_palette("palette");
|
||||||
|
|
||||||
|
@ -4346,7 +4346,7 @@ ROM_START( telpacfl )
|
|||||||
ROM_REGION( 0x800000, "unused", ROMREGION_ERASE00 ) // Sprites
|
ROM_REGION( 0x800000, "unused", ROMREGION_ERASE00 ) // Sprites
|
||||||
// not decoding the bad ROM is better than loading corrupt gfx data
|
// not decoding the bad ROM is better than loading corrupt gfx data
|
||||||
ROM_LOAD64_WORD( "mp3_cg-2__u21_v1.0.u21", 0x000004, 0x200000, BAD_DUMP CRC(54dc430b) SHA1(a2e55866249d01f6f2f2dd998421baf9fe0c6972) ) // physically damaged eprom
|
ROM_LOAD64_WORD( "mp3_cg-2__u21_v1.0.u21", 0x000004, 0x200000, BAD_DUMP CRC(54dc430b) SHA1(a2e55866249d01f6f2f2dd998421baf9fe0c6972) ) // physically damaged eprom
|
||||||
|
|
||||||
ROM_REGION( 0x100000, "x1snd", 0 ) // Samples
|
ROM_REGION( 0x100000, "x1snd", 0 ) // Samples
|
||||||
ROM_LOAD( "mp3_sound0__u111_v1.0.u111", 0x000000, 0x080000, CRC(711c915e) SHA1(d654a0c158cf54aab5faca913583c5620388aa46) )
|
ROM_LOAD( "mp3_sound0__u111_v1.0.u111", 0x000000, 0x080000, CRC(711c915e) SHA1(d654a0c158cf54aab5faca913583c5620388aa46) )
|
||||||
ROM_LOAD( "mp3_sound1__u112_v1.0.u112", 0x080000, 0x080000, CRC(27fd83cd) SHA1(d0261b2c5354ea17061e71bcea747d70efc18a49) )
|
ROM_LOAD( "mp3_sound1__u112_v1.0.u112", 0x080000, 0x080000, CRC(27fd83cd) SHA1(d0261b2c5354ea17061e71bcea747d70efc18a49) )
|
||||||
|
@ -1172,66 +1172,66 @@ void snesb_state::init_rushbets()
|
|||||||
|
|
||||||
void snesb_state::init_venom()
|
void snesb_state::init_venom()
|
||||||
{
|
{
|
||||||
uint8_t *src = memregion("user7")->base();
|
uint8_t *src = memregion("user7")->base();
|
||||||
uint8_t *dst = memregion("user3")->base();
|
uint8_t *dst = memregion("user3")->base();
|
||||||
|
|
||||||
static uint8_t address_tab_high[0x60] = {
|
static uint8_t address_tab_high[0x60] = {
|
||||||
0x00, 0x11, 0x02, 0x13, 0x04, 0x15, 0x06, 0x17, 0x08, 0x19, 0x0a, 0x1b, 0x0c, 0x1d, 0x0e, 0x1f,
|
0x00, 0x11, 0x02, 0x13, 0x04, 0x15, 0x06, 0x17, 0x08, 0x19, 0x0a, 0x1b, 0x0c, 0x1d, 0x0e, 0x1f,
|
||||||
0x20, 0x31, 0x22, 0x33, 0x24, 0x35, 0x26, 0x37, 0x28, 0x39, 0x2a, 0x3b, 0x2c, 0x3d, 0x2e, 0x3f,
|
0x20, 0x31, 0x22, 0x33, 0x24, 0x35, 0x26, 0x37, 0x28, 0x39, 0x2a, 0x3b, 0x2c, 0x3d, 0x2e, 0x3f,
|
||||||
0x10, 0x01, 0x12, 0x03, 0x14, 0x05, 0x16, 0x07, 0x18, 0x09, 0x1a, 0x0b, 0x1c, 0x0d, 0x1e, 0x0f,
|
0x10, 0x01, 0x12, 0x03, 0x14, 0x05, 0x16, 0x07, 0x18, 0x09, 0x1a, 0x0b, 0x1c, 0x0d, 0x1e, 0x0f,
|
||||||
0x30, 0x21, 0x32, 0x23, 0x34, 0x25, 0x36, 0x27, 0x38, 0x29, 0x3a, 0x2b, 0x3c, 0x2d, 0x3e, 0x2f,
|
0x30, 0x21, 0x32, 0x23, 0x34, 0x25, 0x36, 0x27, 0x38, 0x29, 0x3a, 0x2b, 0x3c, 0x2d, 0x3e, 0x2f,
|
||||||
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
|
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
|
||||||
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f
|
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f
|
||||||
};
|
};
|
||||||
|
|
||||||
static uint8_t address_tab_low[0x40] = {
|
static uint8_t address_tab_low[0x40] = {
|
||||||
0x14, 0x1d, 0x11, 0x3c, 0x0a, 0x29, 0x2d, 0x2e, 0x30, 0x32, 0x16, 0x36, 0x05, 0x25, 0x26, 0x37,
|
0x14, 0x1d, 0x11, 0x3c, 0x0a, 0x29, 0x2d, 0x2e, 0x30, 0x32, 0x16, 0x36, 0x05, 0x25, 0x26, 0x37,
|
||||||
0x20, 0x21, 0x27, 0x28, 0x33, 0x34, 0x23, 0x12, 0x1e, 0x1f, 0x3b, 0x24, 0x2c, 0x35, 0x38, 0x39,
|
0x20, 0x21, 0x27, 0x28, 0x33, 0x34, 0x23, 0x12, 0x1e, 0x1f, 0x3b, 0x24, 0x2c, 0x35, 0x38, 0x39,
|
||||||
0x3d, 0x0c, 0x2a, 0x0d, 0x22, 0x18, 0x19, 0x1a, 0x03, 0x08, 0x04, 0x3a, 0x0b, 0x0f, 0x15, 0x17,
|
0x3d, 0x0c, 0x2a, 0x0d, 0x22, 0x18, 0x19, 0x1a, 0x03, 0x08, 0x04, 0x3a, 0x0b, 0x0f, 0x15, 0x17,
|
||||||
0x1b, 0x13, 0x00, 0x1c, 0x2b, 0x01, 0x06, 0x2f, 0x07, 0x09, 0x02, 0x31, 0x10, 0x0e, 0x3f, 0x3e
|
0x1b, 0x13, 0x00, 0x1c, 0x2b, 0x01, 0x06, 0x2f, 0x07, 0x09, 0x02, 0x31, 0x10, 0x0e, 0x3f, 0x3e
|
||||||
};
|
};
|
||||||
|
|
||||||
static uint8_t data_table[0x100] = {
|
static uint8_t data_table[0x100] = {
|
||||||
0x6a, 0xf2, 0xe0, 0xea, 0xe8, 0x60, 0x62, 0xe2, 0x70, 0xfa, 0x7a, 0x78, 0xf0, 0x68, 0x72, 0xf8,
|
0x6a, 0xf2, 0xe0, 0xea, 0xe8, 0x60, 0x62, 0xe2, 0x70, 0xfa, 0x7a, 0x78, 0xf0, 0x68, 0x72, 0xf8,
|
||||||
0x4f, 0xd7, 0xc5, 0xcf, 0xcd, 0x45, 0x47, 0xc7, 0x55, 0xdf, 0x5f, 0x5d, 0xd5, 0x4d, 0x57, 0xdd,
|
0x4f, 0xd7, 0xc5, 0xcf, 0xcd, 0x45, 0x47, 0xc7, 0x55, 0xdf, 0x5f, 0x5d, 0xd5, 0x4d, 0x57, 0xdd,
|
||||||
0x0e, 0x96, 0x84, 0x8e, 0x8c, 0x04, 0x06, 0x86, 0x14, 0x9e, 0x1e, 0x1c, 0x94, 0x0c, 0x16, 0x9c,
|
0x0e, 0x96, 0x84, 0x8e, 0x8c, 0x04, 0x06, 0x86, 0x14, 0x9e, 0x1e, 0x1c, 0x94, 0x0c, 0x16, 0x9c,
|
||||||
0x6e, 0xf6, 0xe4, 0xee, 0xec, 0x64, 0x66, 0xe6, 0x74, 0xfe, 0x7e, 0x7c, 0xf4, 0x6c, 0x76, 0xfc,
|
0x6e, 0xf6, 0xe4, 0xee, 0xec, 0x64, 0x66, 0xe6, 0x74, 0xfe, 0x7e, 0x7c, 0xf4, 0x6c, 0x76, 0xfc,
|
||||||
0x2e, 0xb6, 0xa4, 0xae, 0xac, 0x24, 0x26, 0xa6, 0x34, 0xbe, 0x3e, 0x3c, 0xb4, 0x2c, 0x36, 0xbc,
|
0x2e, 0xb6, 0xa4, 0xae, 0xac, 0x24, 0x26, 0xa6, 0x34, 0xbe, 0x3e, 0x3c, 0xb4, 0x2c, 0x36, 0xbc,
|
||||||
0x0a, 0x92, 0x80, 0x8a, 0x88, 0x00, 0x02, 0x82, 0x10, 0x9a, 0x1a, 0x18, 0x90, 0x08, 0x12, 0x98,
|
0x0a, 0x92, 0x80, 0x8a, 0x88, 0x00, 0x02, 0x82, 0x10, 0x9a, 0x1a, 0x18, 0x90, 0x08, 0x12, 0x98,
|
||||||
0x4a, 0xd2, 0xc0, 0xca, 0xc8, 0x40, 0x42, 0xc2, 0x50, 0xda, 0x5a, 0x58, 0xd0, 0x48, 0x52, 0xd8,
|
0x4a, 0xd2, 0xc0, 0xca, 0xc8, 0x40, 0x42, 0xc2, 0x50, 0xda, 0x5a, 0x58, 0xd0, 0x48, 0x52, 0xd8,
|
||||||
0x4e, 0xd6, 0xc4, 0xce, 0xcc, 0x44, 0x46, 0xc6, 0x54, 0xde, 0x5e, 0x5c, 0xd4, 0x4c, 0x56, 0xdc,
|
0x4e, 0xd6, 0xc4, 0xce, 0xcc, 0x44, 0x46, 0xc6, 0x54, 0xde, 0x5e, 0x5c, 0xd4, 0x4c, 0x56, 0xdc,
|
||||||
0x0b, 0x93, 0x81, 0x8b, 0x89, 0x01, 0x03, 0x83, 0x11, 0x9b, 0x1b, 0x19, 0x91, 0x09, 0x13, 0x99,
|
0x0b, 0x93, 0x81, 0x8b, 0x89, 0x01, 0x03, 0x83, 0x11, 0x9b, 0x1b, 0x19, 0x91, 0x09, 0x13, 0x99,
|
||||||
0x6f, 0xf7, 0xe5, 0xef, 0xed, 0x65, 0x67, 0xe7, 0x75, 0xff, 0x7f, 0x7d, 0xf5, 0x6d, 0x77, 0xfd,
|
0x6f, 0xf7, 0xe5, 0xef, 0xed, 0x65, 0x67, 0xe7, 0x75, 0xff, 0x7f, 0x7d, 0xf5, 0x6d, 0x77, 0xfd,
|
||||||
0x6b, 0xf3, 0xe1, 0xeb, 0xe9, 0x61, 0x63, 0xe3, 0x71, 0xfb, 0x7b, 0x79, 0xf1, 0x69, 0x73, 0xf9,
|
0x6b, 0xf3, 0xe1, 0xeb, 0xe9, 0x61, 0x63, 0xe3, 0x71, 0xfb, 0x7b, 0x79, 0xf1, 0x69, 0x73, 0xf9,
|
||||||
0x2b, 0xb3, 0xa1, 0xab, 0xa9, 0x21, 0x23, 0xa3, 0x31, 0xbb, 0x3b, 0x39, 0xb1, 0x29, 0x33, 0xb9,
|
0x2b, 0xb3, 0xa1, 0xab, 0xa9, 0x21, 0x23, 0xa3, 0x31, 0xbb, 0x3b, 0x39, 0xb1, 0x29, 0x33, 0xb9,
|
||||||
0x0f, 0x97, 0x85, 0x8f, 0x8d, 0x05, 0x07, 0x87, 0x15, 0x9f, 0x1f, 0x1d, 0x95, 0x0d, 0x17, 0x9d,
|
0x0f, 0x97, 0x85, 0x8f, 0x8d, 0x05, 0x07, 0x87, 0x15, 0x9f, 0x1f, 0x1d, 0x95, 0x0d, 0x17, 0x9d,
|
||||||
0x2a, 0xb2, 0xa0, 0xaa, 0xa8, 0x20, 0x22, 0xa2, 0x30, 0xba, 0x3a, 0x38, 0xb0, 0x28, 0x32, 0xb8,
|
0x2a, 0xb2, 0xa0, 0xaa, 0xa8, 0x20, 0x22, 0xa2, 0x30, 0xba, 0x3a, 0x38, 0xb0, 0x28, 0x32, 0xb8,
|
||||||
0x4b, 0xd3, 0xc1, 0xcb, 0xc9, 0x41, 0x43, 0xc3, 0x51, 0xdb, 0x5b, 0x59, 0xd1, 0x49, 0x53, 0xd9,
|
0x4b, 0xd3, 0xc1, 0xcb, 0xc9, 0x41, 0x43, 0xc3, 0x51, 0xdb, 0x5b, 0x59, 0xd1, 0x49, 0x53, 0xd9,
|
||||||
0x2f, 0xb7, 0xa5, 0xaf, 0xad, 0x25, 0x27, 0xa7, 0x35, 0xbf, 0x3f, 0x3d, 0xb5, 0x2d, 0x37, 0xbd
|
0x2f, 0xb7, 0xa5, 0xaf, 0xad, 0x25, 0x27, 0xa7, 0x35, 0xbf, 0x3f, 0x3d, 0xb5, 0x2d, 0x37, 0xbd
|
||||||
};
|
};
|
||||||
|
|
||||||
for (int i = 0; i < 0x300000; i++)
|
for (int i = 0; i < 0x300000; i++)
|
||||||
{
|
{
|
||||||
int j = (address_tab_high[i >> 15] << 15) + (i & 0x7fc0) + address_tab_low[i & 0x3f];
|
int j = (address_tab_high[i >> 15] << 15) + (i & 0x7fc0) + address_tab_low[i & 0x3f];
|
||||||
|
|
||||||
dst[i] = data_table[src[j]];
|
dst[i] = data_table[src[j]];
|
||||||
|
|
||||||
if (i >= 0x00000 && i < 0x10000) {
|
if (i >= 0x00000 && i < 0x10000) {
|
||||||
dst[i] = bitswap<8>(dst[i], 6, 7, 0, 3, 1, 4, 2, 5) ^ 0xff;
|
dst[i] = bitswap<8>(dst[i], 6, 7, 0, 3, 1, 4, 2, 5) ^ 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (i >= 0x10000 && i < 0x20000) {
|
if (i >= 0x10000 && i < 0x20000) {
|
||||||
dst[i] = bitswap<8>(dst[i], 0, 1, 4, 5, 3, 7, 6, 2);
|
dst[i] = bitswap<8>(dst[i], 0, 1, 4, 5, 3, 7, 6, 2);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (i >= 0x20000 && i < 0x30000) {
|
if (i >= 0x20000 && i < 0x30000) {
|
||||||
dst[i] = bitswap<8>(dst[i], 1, 3, 2, 6, 5, 4, 0, 7) ^ 0xff;
|
dst[i] = bitswap<8>(dst[i], 1, 3, 2, 6, 5, 4, 0, 7) ^ 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (i >= 0x30000 && i < 0x40000) {
|
if (i >= 0x30000 && i < 0x40000) {
|
||||||
dst[i] = bitswap<8>(dst[i], 4, 0, 7, 6, 2, 1, 5, 3);
|
dst[i] = bitswap<8>(dst[i], 4, 0, 7, 6, 2, 1, 5, 3);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// boot vector
|
// boot vector
|
||||||
dst[0x7ffc] = 0x98;
|
dst[0x7ffc] = 0x98;
|
||||||
@ -1247,7 +1247,7 @@ void snesb_state::init_venom()
|
|||||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770073, 0x770073, read8_delegate(FUNC(snesb_state::snesb_dsw2_r),this));
|
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770073, 0x770073, read8_delegate(FUNC(snesb_state::snesb_dsw2_r),this));
|
||||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770079, 0x770079, read8_delegate(FUNC(snesb_state::snesb_coin_r),this));
|
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770079, 0x770079, read8_delegate(FUNC(snesb_state::snesb_coin_r),this));
|
||||||
|
|
||||||
init_snes();
|
init_snes();
|
||||||
}
|
}
|
||||||
|
|
||||||
ROM_START( kinstb )
|
ROM_START( kinstb )
|
||||||
@ -1449,10 +1449,10 @@ ROM_START( venom )
|
|||||||
ROM_REGION(0x800, "user6", ROMREGION_ERASEFF)
|
ROM_REGION(0x800, "user6", ROMREGION_ERASEFF)
|
||||||
|
|
||||||
ROM_REGION( 0x300000, "user7", 0 )
|
ROM_REGION( 0x300000, "user7", 0 )
|
||||||
ROM_LOAD( "u31.bin", 0x000000, 0x0100000, CRC(d1034a76) SHA1(541dd92197ca2e4eb686e426c840aad847d02be8) )
|
ROM_LOAD( "u31.bin", 0x000000, 0x0100000, CRC(d1034a76) SHA1(541dd92197ca2e4eb686e426c840aad847d02be8) )
|
||||||
ROM_LOAD( "u32.bin", 0x100000, 0x0100000, CRC(fbe865b0) SHA1(25467a6faa912bf180c5dd7aecee77c3b5f207f8) )
|
ROM_LOAD( "u32.bin", 0x100000, 0x0100000, CRC(fbe865b0) SHA1(25467a6faa912bf180c5dd7aecee77c3b5f207f8) )
|
||||||
ROM_LOAD( "u33.bin", 0x200000, 0x0080000, CRC(ed874ca2) SHA1(cfc90b38ea2eea07e990f0b72d7c1af2a7076beb) )
|
ROM_LOAD( "u33.bin", 0x200000, 0x0080000, CRC(ed874ca2) SHA1(cfc90b38ea2eea07e990f0b72d7c1af2a7076beb) )
|
||||||
ROM_LOAD( "u34.bin", 0x280000, 0x0080000, CRC(7a09c9e0) SHA1(794965d5501ec0e21f1f3a8cb8fd66f913d42760) )
|
ROM_LOAD( "u34.bin", 0x280000, 0x0080000, CRC(7a09c9e0) SHA1(794965d5501ec0e21f1f3a8cb8fd66f913d42760) )
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
GAME( 199?, kinstb, 0, kinstb, kinstb, snesb_state, init_kinstb, ROT0, "bootleg", "Killer Instinct (SNES bootleg)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
|
GAME( 199?, kinstb, 0, kinstb, kinstb, snesb_state, init_kinstb, ROT0, "bootleg", "Killer Instinct (SNES bootleg)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
|
||||||
|
@ -12,26 +12,26 @@
|
|||||||
|
|
||||||
To-Do:
|
To-Do:
|
||||||
|
|
||||||
Proper driver_device inheritance to untangle the mess of members
|
Proper driver_device inheritance to untangle the mess of members
|
||||||
|
|
||||||
Detailed list of bugs:
|
Detailed list of bugs:
|
||||||
|
|
||||||
All systems:
|
All systems:
|
||||||
Various inaccuracies in samples/envelopes.
|
Various inaccuracies in samples/envelopes.
|
||||||
|
|
||||||
walle:
|
walle:
|
||||||
Game seems unhappy with NVRAM, clears contents on each boot.
|
Game seems unhappy with NVRAM, clears contents on each boot.
|
||||||
rad_skat:
|
rad_skat:
|
||||||
Palette issues on the High Score screen.
|
Palette issues on the High Score screen.
|
||||||
vii:
|
vii:
|
||||||
When loading a cart from file manager, sometimes MAME will crash.
|
When loading a cart from file manager, sometimes MAME will crash.
|
||||||
The "MOTOR" option in the diagnostic menu does nothing when selected.
|
The "MOTOR" option in the diagnostic menu does nothing when selected.
|
||||||
The "SPEECH IC" option in the diagnostic menu does nothing when selected.
|
The "SPEECH IC" option in the diagnostic menu does nothing when selected.
|
||||||
On 'vii_vc1' & 'vii_vc2' cart, the left-right keys are transposed with the up-down keys.
|
On 'vii_vc1' & 'vii_vc2' cart, the left-right keys are transposed with the up-down keys.
|
||||||
- This is not a bug per se, as the games are played with the controller physically rotated 90 degrees.
|
- This is not a bug per se, as the games are played with the controller physically rotated 90 degrees.
|
||||||
When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
|
When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
|
||||||
zone60/wirels60:
|
zone60/wirels60:
|
||||||
When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
|
When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
|
||||||
|
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
|
@ -10,18 +10,18 @@
|
|||||||
|
|
||||||
To-Do:
|
To-Do:
|
||||||
|
|
||||||
Proper UART support (SPG2xx) for controller
|
Proper UART support (SPG2xx) for controller
|
||||||
|
|
||||||
Similar Systems: ( from http://en.wkikpedia.org/wiki/V.Smile )
|
Similar Systems: ( from http://en.wkikpedia.org/wiki/V.Smile )
|
||||||
|
|
||||||
V.Smile by VTech, a system designed for children under the age of 10
|
V.Smile by VTech, a system designed for children under the age of 10
|
||||||
V.Smile Pocket (2 versions)
|
V.Smile Pocket (2 versions)
|
||||||
V.Smile Cyber Pocket
|
V.Smile Cyber Pocket
|
||||||
V.Smile PC Pal
|
V.Smile PC Pal
|
||||||
V-Motion Active Learning System
|
V-Motion Active Learning System
|
||||||
Leapster
|
Leapster
|
||||||
V.Smile Baby Infant Development System
|
V.Smile Baby Infant Development System
|
||||||
V.Flash
|
V.Flash
|
||||||
|
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
|
@ -517,7 +517,7 @@ void mu100_state::mu100_map(address_map &map)
|
|||||||
|
|
||||||
u16 mu100_state::adc0_r()
|
u16 mu100_state::adc0_r()
|
||||||
{
|
{
|
||||||
// logerror("adc0_r\n");
|
// logerror("adc0_r\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -615,7 +615,7 @@ void mu100_state::p6_w(u16 data)
|
|||||||
|
|
||||||
u16 mu100_state::p6_r()
|
u16 mu100_state::p6_r()
|
||||||
{
|
{
|
||||||
// logerror("plug in detect read\n");
|
// logerror("plug in detect read\n");
|
||||||
return 0x00;
|
return 0x00;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -68,7 +68,7 @@ protected:
|
|||||||
int m_yoffset;
|
int m_yoffset;
|
||||||
int m_pri_masks[3];
|
int m_pri_masks[3];
|
||||||
uint16_t m_scroll[7];
|
uint16_t m_scroll[7];
|
||||||
int m_sprtranspen;
|
int m_sprtranspen;
|
||||||
|
|
||||||
/* misc */
|
/* misc */
|
||||||
uint16_t m_snd_command;
|
uint16_t m_snd_command;
|
||||||
|
@ -124,7 +124,7 @@ protected:
|
|||||||
optional_device<eeprom_serial_93cxx_device> m_eeprom;
|
optional_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||||
optional_device<intelfsh16_device> m_flash;
|
optional_device<intelfsh16_device> m_flash;
|
||||||
optional_device<ticket_dispenser_device> m_dispenser;
|
optional_device<ticket_dispenser_device> m_dispenser;
|
||||||
|
|
||||||
optional_memory_bank_array<8> m_x1_bank;
|
optional_memory_bank_array<8> m_x1_bank;
|
||||||
optional_shared_ptr<uint16_t> m_nvram;
|
optional_shared_ptr<uint16_t> m_nvram;
|
||||||
optional_shared_ptr<uint16_t> m_spriteram;
|
optional_shared_ptr<uint16_t> m_spriteram;
|
||||||
|
@ -100,4 +100,4 @@ private:
|
|||||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // MAME_INCLUDES_SPACEFB
|
#endif // MAME_INCLUDES_SPACEFB
|
||||||
|
@ -131,10 +131,10 @@
|
|||||||
|
|
||||||
|
|
||||||
<!-- to match the schematics, we consider Col.0-3 to be driven by P14-17. The value in "inputmask" is the one read as "p1 & 0x0F", i.e. P13-P10. -->
|
<!-- to match the schematics, we consider Col.0-3 to be driven by P14-17. The value in "inputmask" is the one read as "p1 & 0x0F", i.e. P13-P10. -->
|
||||||
<!-- col.0 : (nc)|shift|ACA|DCA
|
<!-- col.0 : (nc)|shift|ACA|DCA
|
||||||
col.1 : 4W|2W|ACV|DCV
|
col.1 : 4W|2W|ACV|DCV
|
||||||
col.2 : int|dn|up|auto
|
col.2 : int|dn|up|auto
|
||||||
col.3 : (nc)|loc|srq|sgl -->
|
col.3 : (nc)|loc|srq|sgl -->
|
||||||
<bezel element="hl" inputtag="COL.0" inputmask="0x01"><bounds x="65" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
|
<bezel element="hl" inputtag="COL.0" inputmask="0x01"><bounds x="65" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
|
||||||
<bezel element="hl" inputtag="COL.0" inputmask="0x02"><bounds x="80" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
|
<bezel element="hl" inputtag="COL.0" inputmask="0x02"><bounds x="80" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
|
||||||
<bezel element="hl" inputtag="COL.0" inputmask="0x04"><bounds x="95" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
|
<bezel element="hl" inputtag="COL.0" inputmask="0x04"><bounds x="95" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
|
||||||
|
@ -3,7 +3,7 @@
|
|||||||
|
|
||||||
<element name="DIGIT" defstate="0">
|
<element name="DIGIT" defstate="0">
|
||||||
<led7seg><color red="0.0" green="0.45" blue="0.45" /></led7seg>
|
<led7seg><color red="0.0" green="0.45" blue="0.45" /></led7seg>
|
||||||
</element>
|
</element>
|
||||||
<element name="BALL0">
|
<element name="BALL0">
|
||||||
<disk state = "0">
|
<disk state = "0">
|
||||||
<color red="0.0" green="0.3" blue="0" />
|
<color red="0.0" green="0.3" blue="0" />
|
||||||
@ -203,14 +203,14 @@
|
|||||||
<screen index="0">
|
<screen index="0">
|
||||||
<bounds left="100" top="0" right="832" bottom="1072" />
|
<bounds left="100" top="0" right="832" bottom="1072" />
|
||||||
</screen>
|
</screen>
|
||||||
|
|
||||||
<bezel name="lamp10" element="DIGIT"><bounds x="1140" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
<bezel name="lamp10" element="DIGIT"><bounds x="1140" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
||||||
<bezel name="lamp11" element="DIGIT"><bounds x="1160" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
<bezel name="lamp11" element="DIGIT"><bounds x="1160" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
||||||
<bezel name="lamp12" element="DIGIT"><bounds x="1180" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
<bezel name="lamp12" element="DIGIT"><bounds x="1180" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
||||||
<bezel name="lamp13" element="DIGIT"><bounds x="1200" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
<bezel name="lamp13" element="DIGIT"><bounds x="1200" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
||||||
<bezel name="lamp14" element="DIGIT"><bounds x="1220" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
<bezel name="lamp14" element="DIGIT"><bounds x="1220" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
||||||
<bezel name="lamp15" element="DIGIT"><bounds x="1240" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
<bezel name="lamp15" element="DIGIT"><bounds x="1240" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
|
||||||
|
|
||||||
<bezel element="BBET" inputtag="IN0" inputmask="0x04" >
|
<bezel element="BBET" inputtag="IN0" inputmask="0x04" >
|
||||||
<bounds x="270" y="50" width="42" height="42" />
|
<bounds x="270" y="50" width="42" height="42" />
|
||||||
</bezel>
|
</bezel>
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
// copyright-holders:Philip Bennett
|
// copyright-holders:Philip Bennett
|
||||||
/***************************************************************************
|
/***************************************************************************
|
||||||
|
|
||||||
3DO M2 Bulldog ASIC
|
3DO M2 Bulldog ASIC
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
@ -32,71 +32,71 @@ DEFINE_DEVICE_TYPE(M2_CDE, m2_cde_device, "m2cde", "3DO M2 CDE ASIC")
|
|||||||
// VDU REGISTER DEFINITIONS
|
// VDU REGISTER DEFINITIONS
|
||||||
//**************************************************************************
|
//**************************************************************************
|
||||||
|
|
||||||
#define VDU_VLOC 0x00
|
#define VDU_VLOC 0x00
|
||||||
#define VDU_VINT 0x04
|
#define VDU_VINT 0x04
|
||||||
#define VDU_VDC0 0x08
|
#define VDU_VDC0 0x08
|
||||||
#define VDU_VDC1 0x0c
|
#define VDU_VDC1 0x0c
|
||||||
#define VDU_FV0A 0x10
|
#define VDU_FV0A 0x10
|
||||||
#define VDU_FV1A 0x14
|
#define VDU_FV1A 0x14
|
||||||
#define VDU_AVDI 0x1c
|
#define VDU_AVDI 0x1c
|
||||||
#define VDU_VDLI 0x20
|
#define VDU_VDLI 0x20
|
||||||
#define VDU_VCFG 0x24
|
#define VDU_VCFG 0x24
|
||||||
#define VDU_DMT0 0x28
|
#define VDU_DMT0 0x28
|
||||||
#define VDU_DMT1 0x2c
|
#define VDU_DMT1 0x2c
|
||||||
#define VDU_LFSR 0x30
|
#define VDU_LFSR 0x30
|
||||||
#define VDU_VRST 0x34
|
#define VDU_VRST 0x34
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VLOC
|
// VLOC
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDU_VLOC_VCOUNT_MASK 0x00003FF8
|
#define VDU_VLOC_VCOUNT_MASK 0x00003FF8
|
||||||
#define VDU_VLOC_VCOUNT_SHIFT 3
|
#define VDU_VLOC_VCOUNT_SHIFT 3
|
||||||
#define VDU_VLOC_VIDEOFIELD 0x00004000
|
#define VDU_VLOC_VIDEOFIELD 0x00004000
|
||||||
#define VDU_VLOC_RESERVED 0xFFFF8007
|
#define VDU_VLOC_RESERVED 0xFFFF8007
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VINT
|
// VINT
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDU_VINT_VINT0 0x80000000
|
#define VDU_VINT_VINT0 0x80000000
|
||||||
#define VDU_VINT_VLINE0_MASK 0x7FF00000
|
#define VDU_VINT_VLINE0_MASK 0x7FF00000
|
||||||
#define VDU_VINT_VLINE0_SHIFT 20
|
#define VDU_VINT_VLINE0_SHIFT 20
|
||||||
#define VDU_VINT_VINT1 0x00008000
|
#define VDU_VINT_VINT1 0x00008000
|
||||||
#define VDU_VINT_VLINE1_MASK 0x00007FF0
|
#define VDU_VINT_VLINE1_MASK 0x00007FF0
|
||||||
#define VDU_VINT_VLINE1_SHIFT 4
|
#define VDU_VINT_VLINE1_SHIFT 4
|
||||||
#define VDU_VINT_RESERVED 0x000F000F
|
#define VDU_VINT_RESERVED 0x000F000F
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDC0/VDC1
|
// VDC0/VDC1
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDU_VDC_HINT 0x02000000
|
#define VDU_VDC_HINT 0x02000000
|
||||||
#define VDU_VDC_VINT 0x01000000
|
#define VDU_VDC_VINT 0x01000000
|
||||||
#define VDU_VDC_DITHER 0x00400000
|
#define VDU_VDC_DITHER 0x00400000
|
||||||
#define VDU_VDC_MTXBYP 0x00200000
|
#define VDU_VDC_MTXBYP 0x00200000
|
||||||
#define VDU_VDC_RESERVED 0xFC9FFFFF
|
#define VDU_VDC_RESERVED 0xFC9FFFFF
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// AVDI
|
// AVDI
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDU_AVDI_HSTART_MASK 0xFFE00000
|
#define VDU_AVDI_HSTART_MASK 0xFFE00000
|
||||||
#define VDU_AVDI_HWIDTH_MASK 0x0003FF80
|
#define VDU_AVDI_HWIDTH_MASK 0x0003FF80
|
||||||
#define VDU_AVDI_HDOUBLE 0x00000008
|
#define VDU_AVDI_HDOUBLE 0x00000008
|
||||||
#define VDU_AVDI_VDOUBLE 0x00000004
|
#define VDU_AVDI_VDOUBLE 0x00000004
|
||||||
#define VDU_AVDI_RESERVED 0x001C0073
|
#define VDU_AVDI_RESERVED 0x001C0073
|
||||||
#define VDU_AVDI_HSTART_SHIFT 21
|
#define VDU_AVDI_HSTART_SHIFT 21
|
||||||
#define VDU_AVDI_HWIDTH_SHIFT 7
|
#define VDU_AVDI_HWIDTH_SHIFT 7
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDLI
|
// VDLI
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDU_VDLI_BYPASSTYPE 0x10000000
|
#define VDU_VDLI_BYPASSTYPE 0x10000000
|
||||||
#define VDU_VDLI_FBFORMAT 0x04000000
|
#define VDU_VDLI_FBFORMAT 0x04000000
|
||||||
#define VDU_VDLI_ONEVINTDIS 0x00400000
|
#define VDU_VDLI_ONEVINTDIS 0x00400000
|
||||||
#define VDU_VDLI_RANDOMDITHER 0x00200000
|
#define VDU_VDLI_RANDOMDITHER 0x00200000
|
||||||
#define VDU_VDLI_RESERVED 0xEB9FFFFF
|
#define VDU_VDLI_RESERVED 0xEB9FFFFF
|
||||||
#define VDU_VDLI_BYPASSTYPE_MSB 0
|
#define VDU_VDLI_BYPASSTYPE_MSB 0
|
||||||
#define VDU_VDLI_BYPASSTYPE_LSB 0x10000000
|
#define VDU_VDLI_BYPASSTYPE_LSB 0x10000000
|
||||||
#define VDU_VDLI_FBFORMAT_16 0
|
#define VDU_VDLI_FBFORMAT_16 0
|
||||||
#define VDU_VDLI_FBFORMAT_32 0x04000000
|
#define VDU_VDLI_FBFORMAT_32 0x04000000
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VCFG
|
// VCFG
|
||||||
@ -105,82 +105,82 @@ DEFINE_DEVICE_TYPE(M2_CDE, m2_cde_device, "m2cde", "3DO M2 CDE ASIC")
|
|||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VRST
|
// VRST
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDU_VRST_DVERESET 0x00000002
|
#define VDU_VRST_DVERESET 0x00000002
|
||||||
#define VDU_VRST_VIDRESET 0x00000001
|
#define VDU_VRST_VIDRESET 0x00000001
|
||||||
#define VDU_VRST_RESERVED 0xFFFFFFFC
|
#define VDU_VRST_RESERVED 0xFFFFFFFC
|
||||||
|
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDL DMA CONTROL WORD
|
// VDL DMA CONTROL WORD
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDL_DMA_MOD_MASK 0xFF000000
|
#define VDL_DMA_MOD_MASK 0xFF000000
|
||||||
#define VDL_DMA_ENABLE 0x00200000
|
#define VDL_DMA_ENABLE 0x00200000
|
||||||
#define VDL_DMA_NOBUCKET 0x00020000
|
#define VDL_DMA_NOBUCKET 0x00020000
|
||||||
#define VDL_DMA_LDLOWER 0x00010000
|
#define VDL_DMA_LDLOWER 0x00010000
|
||||||
#define VDL_DMA_LDUPPER 0x00008000
|
#define VDL_DMA_LDUPPER 0x00008000
|
||||||
#define VDL_DMA_NWORDS_MASK 0x00007E00
|
#define VDL_DMA_NWORDS_MASK 0x00007E00
|
||||||
#define VDL_DMA_NLINES_MASK 0x000001FF
|
#define VDL_DMA_NLINES_MASK 0x000001FF
|
||||||
#define VDL_DMA_RESERVED 0x00DC0000
|
#define VDL_DMA_RESERVED 0x00DC0000
|
||||||
#define VDL_DMA_NWORDS_SHIFT 9
|
#define VDL_DMA_NWORDS_SHIFT 9
|
||||||
#define VDL_DMA_MOD_SHIFT 24
|
#define VDL_DMA_MOD_SHIFT 24
|
||||||
#define VDL_DMA_NLINES_SHIFT 0
|
#define VDL_DMA_NLINES_SHIFT 0
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDL DC CONTROL WORD
|
// VDL DC CONTROL WORD
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDL_DC 0x80000000
|
#define VDL_DC 0x80000000
|
||||||
#define VDL_DC_0 0x00000000
|
#define VDL_DC_0 0x00000000
|
||||||
#define VDL_DC_1 0x10000000
|
#define VDL_DC_1 0x10000000
|
||||||
#define VDL_DC_HINTCTL_MASK 0x00060000
|
#define VDL_DC_HINTCTL_MASK 0x00060000
|
||||||
#define VDL_DC_HINTCTL_SHIFT 17
|
#define VDL_DC_HINTCTL_SHIFT 17
|
||||||
#define VDL_DC_VINTCTL_MASK 0x00018000
|
#define VDL_DC_VINTCTL_MASK 0x00018000
|
||||||
#define VDL_DC_VINTCTL_SHIFT 15
|
#define VDL_DC_VINTCTL_SHIFT 15
|
||||||
#define VDL_DC_DITHERCTL_MASK 0x00001800
|
#define VDL_DC_DITHERCTL_MASK 0x00001800
|
||||||
#define VDL_DC_DITHERCTL_SHIFT 11
|
#define VDL_DC_DITHERCTL_SHIFT 11
|
||||||
#define VDL_DC_MTXBYPCTL_MASK 0x00000600
|
#define VDL_DC_MTXBYPCTL_MASK 0x00000600
|
||||||
#define VDL_DC_MTXBYPCTL_SHIFT 9
|
#define VDL_DC_MTXBYPCTL_SHIFT 9
|
||||||
#define VDL_DC_RESERVED 0x0FF861FF
|
#define VDL_DC_RESERVED 0x0FF861FF
|
||||||
#define VDL_CTL_DISABLE 0
|
#define VDL_CTL_DISABLE 0
|
||||||
#define VDL_CTL_ENABLE 1
|
#define VDL_CTL_ENABLE 1
|
||||||
#define VDL_CTL_NOP 2
|
#define VDL_CTL_NOP 2
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDL AV CONTROL WORD
|
// VDL AV CONTROL WORD
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDL_AV 0xA0000000
|
#define VDL_AV 0xA0000000
|
||||||
#define VDL_AV_HSTART_MASK 0x1FFC0000
|
#define VDL_AV_HSTART_MASK 0x1FFC0000
|
||||||
#define VDL_AV_HSTART_SHIFT 18
|
#define VDL_AV_HSTART_SHIFT 18
|
||||||
#define VDL_AV_LD_HSTART 0x00020000
|
#define VDL_AV_LD_HSTART 0x00020000
|
||||||
#define VDL_AV_HWIDTH_MASK 0x0001FFC0
|
#define VDL_AV_HWIDTH_MASK 0x0001FFC0
|
||||||
#define VDL_AV_HWIDTH_SHIFT 6
|
#define VDL_AV_HWIDTH_SHIFT 6
|
||||||
#define VDL_AV_LD_HWIDTH 0x00000020
|
#define VDL_AV_LD_HWIDTH 0x00000020
|
||||||
#define VDL_AV_HDOUBLE 0x00000010
|
#define VDL_AV_HDOUBLE 0x00000010
|
||||||
#define VDL_AV_VDOUBLE 0x00000008
|
#define VDL_AV_VDOUBLE 0x00000008
|
||||||
#define VDL_AV_LD_HDOUBLE 0x00000004
|
#define VDL_AV_LD_HDOUBLE 0x00000004
|
||||||
#define VDL_AV_LD_VDOUBLE 0x00000002
|
#define VDL_AV_LD_VDOUBLE 0x00000002
|
||||||
#define VDL_AV_RESERVED 0x00000001
|
#define VDL_AV_RESERVED 0x00000001
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDL LC CONTROL WORD
|
// VDL LC CONTROL WORD
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
#define VDL_LC 0xC0000000
|
#define VDL_LC 0xC0000000
|
||||||
#define VDL_LC_BYPASSTYPE 0x02000000
|
#define VDL_LC_BYPASSTYPE 0x02000000
|
||||||
#define VDL_LC_FBFORMAT 0x00800000
|
#define VDL_LC_FBFORMAT 0x00800000
|
||||||
#define VDL_LC_ONEVINTDIS 0x00080000
|
#define VDL_LC_ONEVINTDIS 0x00080000
|
||||||
#define VDL_LC_RANDOMDITHER 0x00040000
|
#define VDL_LC_RANDOMDITHER 0x00040000
|
||||||
#define VDL_LC_LD_BYPASSTYPE 0x00002000
|
#define VDL_LC_LD_BYPASSTYPE 0x00002000
|
||||||
#define VDL_LC_LD_FBFORMAT 0x00001000
|
#define VDL_LC_LD_FBFORMAT 0x00001000
|
||||||
#define VDL_LC_RESERVED 0x1D73CFFF
|
#define VDL_LC_RESERVED 0x1D73CFFF
|
||||||
#define VDL_LC_BYPASSTYPE_MSB 0x00000000
|
#define VDL_LC_BYPASSTYPE_MSB 0x00000000
|
||||||
#define VDL_LC_BYPASSTYPE_LSB 0x02000000
|
#define VDL_LC_BYPASSTYPE_LSB 0x02000000
|
||||||
#define VDL_LC_FBFORMAT_16 0x00000000
|
#define VDL_LC_FBFORMAT_16 0x00000000
|
||||||
#define VDL_LC_FBFORMAT_32 0x00800000
|
#define VDL_LC_FBFORMAT_32 0x00800000
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// VDL DMA CONTROL WORD
|
// VDL DMA CONTROL WORD
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
|
|
||||||
#define VDL_NOP 0xe1000000
|
#define VDL_NOP 0xe1000000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -192,9 +192,9 @@ static void write_m2_reg(uint32_t ®, uint32_t data, reg_wmode mode)
|
|||||||
{
|
{
|
||||||
switch (mode)
|
switch (mode)
|
||||||
{
|
{
|
||||||
case REG_WRITE: reg = data; break;
|
case REG_WRITE: reg = data; break;
|
||||||
case REG_SET: reg |= data; break;
|
case REG_SET: reg |= data; break;
|
||||||
case REG_CLEAR: reg &= ~data; break;
|
case REG_CLEAR: reg &= ~data; break;
|
||||||
default:
|
default:
|
||||||
assert_always(false, "Bad register write mode");
|
assert_always(false, "Bad register write mode");
|
||||||
}
|
}
|
||||||
@ -278,7 +278,7 @@ void m2_bda_device::device_post_load()
|
|||||||
|
|
||||||
|
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
// machine_config_fragment - declare sub-devices
|
// machine_config_fragment - declare sub-devices
|
||||||
//-------------------------------------------------
|
//-------------------------------------------------
|
||||||
|
|
||||||
void m2_bda_device::device_add_mconfig(machine_config &config)
|
void m2_bda_device::device_add_mconfig(machine_config &config)
|
||||||
@ -294,7 +294,7 @@ void m2_bda_device::device_add_mconfig(machine_config &config)
|
|||||||
M2_CTRLPORT(config, m_ctrlport, DERIVED_CLOCK(1, 1));
|
M2_CTRLPORT(config, m_ctrlport, DERIVED_CLOCK(1, 1));
|
||||||
|
|
||||||
M2_MPEG(config, m_mpeg, DERIVED_CLOCK(1, 1));
|
M2_MPEG(config, m_mpeg, DERIVED_CLOCK(1, 1));
|
||||||
// m_mpeg->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_MPEG_LINE>));
|
// m_mpeg->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_MPEG_LINE>));
|
||||||
|
|
||||||
DSPP(config, m_dspp, DERIVED_CLOCK(1, 1));
|
DSPP(config, m_dspp, DERIVED_CLOCK(1, 1));
|
||||||
m_dspp->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_DSP_LINE>));
|
m_dspp->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_DSP_LINE>));
|
||||||
@ -469,15 +469,15 @@ void m2_bda_device::configure_ppc_address_map(address_space &space)
|
|||||||
space.install_ram(TE_TRAM_BASE, TE_TRAM_BASE + TE_TRAM_MASK, m_te->tram_ptr());
|
space.install_ram(TE_TRAM_BASE, TE_TRAM_BASE + TE_TRAM_MASK, m_te->tram_ptr());
|
||||||
|
|
||||||
// Install BDA sub-devices
|
// Install BDA sub-devices
|
||||||
space.install_readwrite_handler(POWERBUS_BASE, POWERBUS_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_powerbus_device::read), &(*m_powerbus)), write32_delegate(FUNC(m2_powerbus_device::write), &(*m_powerbus)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(POWERBUS_BASE, POWERBUS_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_powerbus_device::read), &(*m_powerbus)), write32_delegate(FUNC(m2_powerbus_device::write), &(*m_powerbus)), 0xffffffffffffffffULL);
|
||||||
space.install_readwrite_handler(MEMCTL_BASE, MEMCTL_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_memctl_device::read), &(*m_memctl)), write32_delegate(FUNC(m2_memctl_device::write), &(*m_memctl)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(MEMCTL_BASE, MEMCTL_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_memctl_device::read), &(*m_memctl)), write32_delegate(FUNC(m2_memctl_device::write), &(*m_memctl)), 0xffffffffffffffffULL);
|
||||||
space.install_readwrite_handler(VDU_BASE, VDU_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_vdu_device::read), &(*m_vdu)), write32_delegate(FUNC(m2_vdu_device::write), &(*m_vdu)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(VDU_BASE, VDU_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_vdu_device::read), &(*m_vdu)), write32_delegate(FUNC(m2_vdu_device::write), &(*m_vdu)), 0xffffffffffffffffULL);
|
||||||
space.install_readwrite_handler(TE_BASE, TE_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_te_device::read), &(*m_te)), write32_delegate(FUNC(m2_te_device::write), &(*m_te)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(TE_BASE, TE_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_te_device::read), &(*m_te)), write32_delegate(FUNC(m2_te_device::write), &(*m_te)), 0xffffffffffffffffULL);
|
||||||
space.install_readwrite_handler(DSP_BASE, DSP_BASE + DEVICE_MASK, read32_delegate(FUNC(dspp_device::read), &(*m_dspp)), write32_delegate(FUNC(dspp_device::write), &(*m_dspp)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(DSP_BASE, DSP_BASE + DEVICE_MASK, read32_delegate(FUNC(dspp_device::read), &(*m_dspp)), write32_delegate(FUNC(dspp_device::write), &(*m_dspp)), 0xffffffffffffffffULL);
|
||||||
space.install_readwrite_handler(CTRLPORT_BASE, CTRLPORT_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_ctrlport_device::read), &(*m_ctrlport)), write32_delegate(FUNC(m2_ctrlport_device::write), &(*m_ctrlport)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(CTRLPORT_BASE, CTRLPORT_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_ctrlport_device::read), &(*m_ctrlport)), write32_delegate(FUNC(m2_ctrlport_device::write), &(*m_ctrlport)), 0xffffffffffffffffULL);
|
||||||
space.install_readwrite_handler(MPEG_BASE, MPEG_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_mpeg_device::read), &(*m_mpeg)), write32_delegate(FUNC(m2_mpeg_device::write), &(*m_mpeg)), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(MPEG_BASE, MPEG_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_mpeg_device::read), &(*m_mpeg)), write32_delegate(FUNC(m2_mpeg_device::write), &(*m_mpeg)), 0xffffffffffffffffULL);
|
||||||
|
|
||||||
space.install_readwrite_handler(CPUID_BASE, CPUID_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_bda_device::cpu_id_r), this), write32_delegate(FUNC(m2_bda_device::cpu_id_w), this), 0xffffffffffffffffULL);
|
space.install_readwrite_handler(CPUID_BASE, CPUID_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_bda_device::cpu_id_r), this), write32_delegate(FUNC(m2_bda_device::cpu_id_w), this), 0xffffffffffffffffULL);
|
||||||
|
|
||||||
|
|
||||||
// Find and install the CDE
|
// Find and install the CDE
|
||||||
@ -954,7 +954,7 @@ WRITE32_MEMBER( m2_vdu_device::write )
|
|||||||
uint32_t byte_offs = offset << 2;
|
uint32_t byte_offs = offset << 2;
|
||||||
reg_wmode wmode = byte_offs & 0x400 ? REG_CLEAR : REG_WRITE;
|
reg_wmode wmode = byte_offs & 0x400 ? REG_CLEAR : REG_WRITE;
|
||||||
|
|
||||||
// logerror("%s: VDU WRITE: %03x %08x %x\n", machine().describe_context(), byte_offs, data, mem_mask);
|
// logerror("%s: VDU WRITE: %03x %08x %x\n", machine().describe_context(), byte_offs, data, mem_mask);
|
||||||
byte_offs &= ~0x400;
|
byte_offs &= ~0x400;
|
||||||
switch (byte_offs)
|
switch (byte_offs)
|
||||||
{
|
{
|
||||||
@ -1132,8 +1132,8 @@ void m2_vdu_device::draw_scanline(uint32_t *dst, uint32_t srclower, uint32_t src
|
|||||||
uint32_t hw = (m_avdi & VDU_AVDI_HWIDTH_MASK) >> VDU_AVDI_HWIDTH_SHIFT;
|
uint32_t hw = (m_avdi & VDU_AVDI_HWIDTH_MASK) >> VDU_AVDI_HWIDTH_SHIFT;
|
||||||
|
|
||||||
bool is32bpp = m_vdli & VDU_VDLI_FBFORMAT_32 ? true : false;
|
bool is32bpp = m_vdli & VDU_VDLI_FBFORMAT_32 ? true : false;
|
||||||
// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
|
// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
|
||||||
// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
|
// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
|
||||||
|
|
||||||
uint32_t h = 0;
|
uint32_t h = 0;
|
||||||
|
|
||||||
@ -1188,8 +1188,8 @@ void m2_vdu_device::draw_scanline_double(uint32_t *dst, uint32_t srclower, uint3
|
|||||||
uint32_t hw = (m_avdi & VDU_AVDI_HWIDTH_MASK) >> VDU_AVDI_HWIDTH_SHIFT;
|
uint32_t hw = (m_avdi & VDU_AVDI_HWIDTH_MASK) >> VDU_AVDI_HWIDTH_SHIFT;
|
||||||
|
|
||||||
bool is32bpp = m_vdli & VDU_VDLI_FBFORMAT_32 ? true : false;
|
bool is32bpp = m_vdli & VDU_VDLI_FBFORMAT_32 ? true : false;
|
||||||
// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
|
// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
|
||||||
// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
|
// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
|
||||||
|
|
||||||
uint32_t h = 0;
|
uint32_t h = 0;
|
||||||
|
|
||||||
@ -1333,7 +1333,7 @@ uint32_t m2_vdu_device::screen_update(screen_device &screen, bitmap_rgb32 &bitma
|
|||||||
{
|
{
|
||||||
bool hdouble = m_avdi & VDU_AVDI_HDOUBLE ? true : false;
|
bool hdouble = m_avdi & VDU_AVDI_HDOUBLE ? true : false;
|
||||||
bool vdouble = m_avdi & VDU_AVDI_VDOUBLE ? true : false;
|
bool vdouble = m_avdi & VDU_AVDI_VDOUBLE ? true : false;
|
||||||
// bool onevintdis = m_vdli & VDU_VDLI_ONEVINTDIS ? true : false;
|
// bool onevintdis = m_vdli & VDU_VDLI_ONEVINTDIS ? true : false;
|
||||||
|
|
||||||
uint32_t srclower = lower;
|
uint32_t srclower = lower;
|
||||||
uint32_t srcupper = upper;
|
uint32_t srcupper = upper;
|
||||||
@ -1760,7 +1760,7 @@ WRITE32_MEMBER( m2_cde_device::write )
|
|||||||
{
|
{
|
||||||
case CDE_SDBG_CNTL:
|
case CDE_SDBG_CNTL:
|
||||||
{
|
{
|
||||||
// ........ ........ xxxxxxxx xxxx.... Clock scaler (written with 33MHz/38400 = 868)
|
// ........ ........ xxxxxxxx xxxx.... Clock scaler (written with 33MHz/38400 = 868)
|
||||||
write_m2_reg(m_sdbg_cntl, data, wm_cw);
|
write_m2_reg(m_sdbg_cntl, data, wm_cw);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -1844,7 +1844,7 @@ WRITE32_MEMBER( m2_cde_device::write )
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
// case CDE_SYSTEM_CONF:
|
// case CDE_SYSTEM_CONF:
|
||||||
case CDE_VISA_DIS:
|
case CDE_VISA_DIS:
|
||||||
{
|
{
|
||||||
write_m2_reg(m_visa_dis, data, wm_cw);
|
write_m2_reg(m_visa_dis, data, wm_cw);
|
||||||
@ -1941,7 +1941,7 @@ void m2_cde_device::start_dma(uint32_t ch)
|
|||||||
// TODO: DMA timing is probably inaccurate
|
// TODO: DMA timing is probably inaccurate
|
||||||
attotime delay = attotime::from_nsec(10);// * dma_ch.m_ccnt;
|
attotime delay = attotime::from_nsec(10);// * dma_ch.m_ccnt;
|
||||||
|
|
||||||
// attotime delay = clocks_to_attotime(4 * dma_ch.m_ccnt);
|
// attotime delay = clocks_to_attotime(4 * dma_ch.m_ccnt);
|
||||||
dma_ch.m_timer->adjust(delay);
|
dma_ch.m_timer->adjust(delay);
|
||||||
|
|
||||||
if (dma_ch.m_cntl & CDE_DMA_DIRECTION)
|
if (dma_ch.m_cntl & CDE_DMA_DIRECTION)
|
||||||
|
@ -2,9 +2,9 @@
|
|||||||
// copyright-holders:Philip Bennett
|
// copyright-holders:Philip Bennett
|
||||||
/***************************************************************************
|
/***************************************************************************
|
||||||
|
|
||||||
3DO M2
|
3DO M2
|
||||||
|
|
||||||
TODO: Move reg defines out of classes and into source
|
TODO: Move reg defines out of classes and into source
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
@ -18,7 +18,7 @@
|
|||||||
#include "cpu/powerpc/ppc.h"
|
#include "cpu/powerpc/ppc.h"
|
||||||
#include "screen.h"
|
#include "screen.h"
|
||||||
|
|
||||||
#define M2_BAD_TIMING 0 // HACK
|
#define M2_BAD_TIMING 0 // HACK
|
||||||
|
|
||||||
/***************************************************************************
|
/***************************************************************************
|
||||||
ENUMERATIONS
|
ENUMERATIONS
|
||||||
@ -26,55 +26,55 @@
|
|||||||
|
|
||||||
enum
|
enum
|
||||||
{
|
{
|
||||||
SYSCFG_VIDEO_NTSC = 0x00000000,
|
SYSCFG_VIDEO_NTSC = 0x00000000,
|
||||||
SYSCFG_VIDEO_PAL = 0x00000001,
|
SYSCFG_VIDEO_PAL = 0x00000001,
|
||||||
|
|
||||||
SYSCFG_VIDEO_ENCODER_MEIENC = 0x00000000, // NTSC by default
|
SYSCFG_VIDEO_ENCODER_MEIENC = 0x00000000, // NTSC by default
|
||||||
SYSCFG_VIDEO_ENCODER_VP536 = 0x00000004, // NTSC by default
|
SYSCFG_VIDEO_ENCODER_VP536 = 0x00000004, // NTSC by default
|
||||||
SYSCFG_VIDEO_ENCODER_BT9103 = 0x00000008, // PAL by default
|
SYSCFG_VIDEO_ENCODER_BT9103 = 0x00000008, // PAL by default
|
||||||
SYSCFG_VIDEO_ENCODER_DENC = 0x0000000C, // PAL by default
|
SYSCFG_VIDEO_ENCODER_DENC = 0x0000000C, // PAL by default
|
||||||
|
|
||||||
SYSCFG_REGION_UK = 0x00000800,
|
SYSCFG_REGION_UK = 0x00000800,
|
||||||
SYSCFG_REGION_JAPAN = 0x00001000,
|
SYSCFG_REGION_JAPAN = 0x00001000,
|
||||||
SYSCFG_REGION_US = 0x00001800,
|
SYSCFG_REGION_US = 0x00001800,
|
||||||
|
|
||||||
#if 0 // Console
|
#if 0 // Console
|
||||||
SYSCFG_AUDIO_CS4216 = 0xA0000000,
|
SYSCFG_AUDIO_CS4216 = 0xA0000000,
|
||||||
SYSCFG_AUDIO_ASASHI = 0xE0000000,
|
SYSCFG_AUDIO_ASASHI = 0xE0000000,
|
||||||
#else
|
#else
|
||||||
SYSCFG_AUDIO_CS4216 = 0x20000000,
|
SYSCFG_AUDIO_CS4216 = 0x20000000,
|
||||||
SYSCFG_AUDIO_ASASHI = 0x60000000,
|
SYSCFG_AUDIO_ASASHI = 0x60000000,
|
||||||
#endif
|
#endif
|
||||||
SYSCFG_BOARD_AC_DEVCARD = 0x00040000,
|
SYSCFG_BOARD_AC_DEVCARD = 0x00040000,
|
||||||
SYSCFG_BOARD_AC_COREBOARD = 0x00058000,
|
SYSCFG_BOARD_AC_COREBOARD = 0x00058000,
|
||||||
SYSCFG_BOARD_DEVCARD = 0x00060000,
|
SYSCFG_BOARD_DEVCARD = 0x00060000,
|
||||||
SYSCFG_BOARD_UPGRADE = 0x00070000,
|
SYSCFG_BOARD_UPGRADE = 0x00070000,
|
||||||
SYSCFG_BOARD_MULTIPLAYER = 0x00078000,
|
SYSCFG_BOARD_MULTIPLAYER = 0x00078000,
|
||||||
|
|
||||||
SYSCONFIG_ARCADE = 0x03600000 | SYSCFG_BOARD_AC_COREBOARD | SYSCFG_AUDIO_ASASHI | SYSCFG_REGION_JAPAN | SYSCFG_VIDEO_ENCODER_MEIENC | SYSCFG_VIDEO_NTSC,
|
SYSCONFIG_ARCADE = 0x03600000 | SYSCFG_BOARD_AC_COREBOARD | SYSCFG_AUDIO_ASASHI | SYSCFG_REGION_JAPAN | SYSCFG_VIDEO_ENCODER_MEIENC | SYSCFG_VIDEO_NTSC,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum bdaint_line
|
enum bdaint_line
|
||||||
{
|
{
|
||||||
BDAINT_EXTD4_LINE = 3,
|
BDAINT_EXTD4_LINE = 3,
|
||||||
BDAINT_EXTD3_LINE = 4,
|
BDAINT_EXTD3_LINE = 4,
|
||||||
BDAINT_EXTD2_LINE = 5,
|
BDAINT_EXTD2_LINE = 5,
|
||||||
BDAINT_EXTD1_LINE = 6,
|
BDAINT_EXTD1_LINE = 6,
|
||||||
BDAINT_PVIOL_LINE = 7,
|
BDAINT_PVIOL_LINE = 7,
|
||||||
BDAINT_WVIOL_LINE = 8,
|
BDAINT_WVIOL_LINE = 8,
|
||||||
BDAINT_TO_LINE = 9,
|
BDAINT_TO_LINE = 9,
|
||||||
|
|
||||||
BDAINT_CEL_LINE = 21,
|
BDAINT_CEL_LINE = 21,
|
||||||
BDAINT_MYSTERY_LINE = 22,
|
BDAINT_MYSTERY_LINE = 22,
|
||||||
BDAINT_VINT1_LINE = 23,
|
BDAINT_VINT1_LINE = 23,
|
||||||
BDAINT_VINT0_LINE = 24,
|
BDAINT_VINT0_LINE = 24,
|
||||||
BDAINT_DSP_LINE = 25,
|
BDAINT_DSP_LINE = 25,
|
||||||
BDAINT_MPEG_LINE = 26,
|
BDAINT_MPEG_LINE = 26,
|
||||||
BDAINT_TRIGEN_LINE = 27,
|
BDAINT_TRIGEN_LINE = 27,
|
||||||
BDAINT_TRIDFINST_LINE = 28,
|
BDAINT_TRIDFINST_LINE = 28,
|
||||||
BDAINT_TRIDMINST_LINE = 29,
|
BDAINT_TRIDMINST_LINE = 29,
|
||||||
BDAINT_TRILISTEND_LINE = 30,
|
BDAINT_TRILISTEND_LINE = 30,
|
||||||
BDAINT_TRIWINCLIP_LINE = 31,
|
BDAINT_TRIWINCLIP_LINE = 31,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum reg_wmode
|
enum reg_wmode
|
||||||
@ -111,10 +111,10 @@ class m2_bda_device : public device_t
|
|||||||
public:
|
public:
|
||||||
enum rambank_size // TODO: REMOVE ME
|
enum rambank_size // TODO: REMOVE ME
|
||||||
{
|
{
|
||||||
RAM_2MB = 2,
|
RAM_2MB = 2,
|
||||||
RAM_4MB = 4,
|
RAM_4MB = 4,
|
||||||
RAM_8MB = 8,
|
RAM_8MB = 8,
|
||||||
RAM_16MB = 16
|
RAM_16MB = 16
|
||||||
};
|
};
|
||||||
|
|
||||||
template <typename T, typename U>
|
template <typename T, typename U>
|
||||||
@ -163,7 +163,7 @@ public:
|
|||||||
|
|
||||||
void set_interrupt(uint32_t state);
|
void set_interrupt(uint32_t state);
|
||||||
|
|
||||||
// screen_device * get_screen() const { return m_screen; }
|
// screen_device * get_screen() const { return m_screen; }
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
// Device-level overrides
|
// Device-level overrides
|
||||||
@ -176,31 +176,31 @@ protected:
|
|||||||
private:
|
private:
|
||||||
enum base_addr
|
enum base_addr
|
||||||
{
|
{
|
||||||
POWERBUS_BASE = 0x00010000,
|
POWERBUS_BASE = 0x00010000,
|
||||||
MEMCTL_BASE = 0x00020000,
|
MEMCTL_BASE = 0x00020000,
|
||||||
VDU_BASE = 0x00030000,
|
VDU_BASE = 0x00030000,
|
||||||
TE_BASE = 0x00040000,
|
TE_BASE = 0x00040000,
|
||||||
DSP_BASE = 0x00060000,
|
DSP_BASE = 0x00060000,
|
||||||
CTRLPORT_BASE = 0x00070000,
|
CTRLPORT_BASE = 0x00070000,
|
||||||
MPEG_BASE = 0x00080000,
|
MPEG_BASE = 0x00080000,
|
||||||
TE_TRAM_BASE = 0x000c0000,
|
TE_TRAM_BASE = 0x000c0000,
|
||||||
SLOT1_BASE = 0x01000000,
|
SLOT1_BASE = 0x01000000,
|
||||||
SLOT2_BASE = 0x02000000,
|
SLOT2_BASE = 0x02000000,
|
||||||
SLOT3_BASE = 0x03000000,
|
SLOT3_BASE = 0x03000000,
|
||||||
SLOT4_BASE = 0x04000000,
|
SLOT4_BASE = 0x04000000,
|
||||||
SLOT5_BASE = 0x05000000,
|
SLOT5_BASE = 0x05000000,
|
||||||
SLOT6_BASE = 0x06000000,
|
SLOT6_BASE = 0x06000000,
|
||||||
SLOT7_BASE = 0x07000000,
|
SLOT7_BASE = 0x07000000,
|
||||||
SLOT8_BASE = 0x08000000,
|
SLOT8_BASE = 0x08000000,
|
||||||
CPUID_BASE = 0x10000000,
|
CPUID_BASE = 0x10000000,
|
||||||
RAM_BASE = 0x40000000,
|
RAM_BASE = 0x40000000,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum dev_mask
|
enum dev_mask
|
||||||
{
|
{
|
||||||
DEVICE_MASK = 0x0000ffff,
|
DEVICE_MASK = 0x0000ffff,
|
||||||
SLOT_MASK = 0x00ffffff,
|
SLOT_MASK = 0x00ffffff,
|
||||||
TE_TRAM_MASK = 0x00003fff,
|
TE_TRAM_MASK = 0x00003fff,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -209,24 +209,24 @@ private:
|
|||||||
public: // TODO: THIS SHOULD NOT BE PUBLIC
|
public: // TODO: THIS SHOULD NOT BE PUBLIC
|
||||||
required_device<ppc_device> m_cpu1;
|
required_device<ppc_device> m_cpu1;
|
||||||
required_device<ppc_device> m_cpu2;
|
required_device<ppc_device> m_cpu2;
|
||||||
devcb_read_line m_videores_in;
|
devcb_read_line m_videores_in;
|
||||||
|
|
||||||
// Sub-devices
|
// Sub-devices
|
||||||
required_device<m2_memctl_device> m_memctl;
|
required_device<m2_memctl_device> m_memctl;
|
||||||
required_device<m2_powerbus_device> m_powerbus;
|
required_device<m2_powerbus_device> m_powerbus;
|
||||||
required_device<m2_vdu_device> m_vdu;
|
required_device<m2_vdu_device> m_vdu;
|
||||||
required_device<m2_ctrlport_device> m_ctrlport;
|
required_device<m2_ctrlport_device> m_ctrlport;
|
||||||
required_device<dspp_device> m_dspp;
|
required_device<dspp_device> m_dspp;
|
||||||
required_device<m2_mpeg_device> m_mpeg;
|
required_device<m2_mpeg_device> m_mpeg;
|
||||||
required_device<m2_te_device> m_te;
|
required_device<m2_te_device> m_te;
|
||||||
|
|
||||||
// System RAM
|
// System RAM
|
||||||
uint32_t *m_ram;
|
uint32_t *m_ram;
|
||||||
uint32_t m_rambank_size[2];
|
uint32_t m_rambank_size[2];
|
||||||
uint32_t m_ram_mask;
|
uint32_t m_ram_mask;
|
||||||
|
|
||||||
devcb_write16 m_dac_l;
|
devcb_write16 m_dac_l;
|
||||||
devcb_write16 m_dac_r;
|
devcb_write16 m_dac_r;
|
||||||
|
|
||||||
emu_timer *m_dac_timer;
|
emu_timer *m_dac_timer;
|
||||||
|
|
||||||
@ -269,24 +269,24 @@ protected:
|
|||||||
private:
|
private:
|
||||||
enum reg_offs
|
enum reg_offs
|
||||||
{
|
{
|
||||||
BDAPCTL_DEVID = 0x00,
|
BDAPCTL_DEVID = 0x00,
|
||||||
BDAPCTL_PBCONTROL = 0x10,
|
BDAPCTL_PBCONTROL = 0x10,
|
||||||
BDAPCTL_PBINTENSET = 0x40,
|
BDAPCTL_PBINTENSET = 0x40,
|
||||||
BDAPCTL_PBINTSTAT = 0x50,
|
BDAPCTL_PBINTSTAT = 0x50,
|
||||||
BDAPCTL_ERRSTAT = 0x60,
|
BDAPCTL_ERRSTAT = 0x60,
|
||||||
BDAPCTL_ERRADDR = 0x70,
|
BDAPCTL_ERRADDR = 0x70,
|
||||||
};
|
};
|
||||||
|
|
||||||
void update_interrupts();
|
void update_interrupts();
|
||||||
|
|
||||||
devcb_write_line m_int_handler;
|
devcb_write_line m_int_handler;
|
||||||
|
|
||||||
// Registers
|
// Registers
|
||||||
uint32_t m_ctrl;
|
uint32_t m_ctrl;
|
||||||
uint32_t m_int_enable;
|
uint32_t m_int_enable;
|
||||||
uint32_t m_int_status;
|
uint32_t m_int_status;
|
||||||
uint32_t m_err_status;
|
uint32_t m_err_status;
|
||||||
uint32_t m_err_address;
|
uint32_t m_err_address;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -313,46 +313,46 @@ protected:
|
|||||||
private:
|
private:
|
||||||
enum reg_offs
|
enum reg_offs
|
||||||
{
|
{
|
||||||
MCTL_MCONFIG = 0x0,
|
MCTL_MCONFIG = 0x0,
|
||||||
MCTL_MREF = 0x4,
|
MCTL_MREF = 0x4,
|
||||||
MCTL_MCNTL = 0x8,
|
MCTL_MCNTL = 0x8,
|
||||||
MCTL_MRESET = 0xc,
|
MCTL_MRESET = 0xc,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum mcfg_reg
|
enum mcfg_reg
|
||||||
{
|
{
|
||||||
MCFG_LDIA_MASK = 0x07000000,
|
MCFG_LDIA_MASK = 0x07000000,
|
||||||
MCFG_LDIA_SHIFT = 24,
|
MCFG_LDIA_SHIFT = 24,
|
||||||
MCFG_LDOA_MASK = 0x00c00000,
|
MCFG_LDOA_MASK = 0x00c00000,
|
||||||
MCFG_LDOA_SHIFT = 22,
|
MCFG_LDOA_SHIFT = 22,
|
||||||
MCFG_RC_MASK = 0x003c0000,
|
MCFG_RC_MASK = 0x003c0000,
|
||||||
MCFG_RC_SHIFT = 18,
|
MCFG_RC_SHIFT = 18,
|
||||||
MCFG_RCD_MASK = 0x00030000,
|
MCFG_RCD_MASK = 0x00030000,
|
||||||
MCFG_RCD_SHIFT = 16,
|
MCFG_RCD_SHIFT = 16,
|
||||||
MCFG_SS1_MASK = 0x0000e000,
|
MCFG_SS1_MASK = 0x0000e000,
|
||||||
MCFG_SS1_SHIFT = 13,
|
MCFG_SS1_SHIFT = 13,
|
||||||
MCFG_SS0_MASK = 0x00001c00,
|
MCFG_SS0_MASK = 0x00001c00,
|
||||||
MCFG_SS0_SHIFT = 10,
|
MCFG_SS0_SHIFT = 10,
|
||||||
MCFG_CL_MASK = 0x00000030,
|
MCFG_CL_MASK = 0x00000030,
|
||||||
MCFG_CL_SHIFT = 4,
|
MCFG_CL_SHIFT = 4,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum mref_reg
|
enum mref_reg
|
||||||
{
|
{
|
||||||
MREF_DEBUGADDR = 0x7F000000, /* Selector if GPIOx_GP == 0 */
|
MREF_DEBUGADDR = 0x7F000000, /* Selector if GPIOx_GP == 0 */
|
||||||
MREF_GPIO3_GP = 0x00800000, /* General purpose or debug out */
|
MREF_GPIO3_GP = 0x00800000, /* General purpose or debug out */
|
||||||
MREF_GPIO3_OUT = 0x00400000, /* Output or input */
|
MREF_GPIO3_OUT = 0x00400000, /* Output or input */
|
||||||
MREF_GPIO3_VALUE = 0x00200000, /* Value if GPIOx_GP == 1 */
|
MREF_GPIO3_VALUE = 0x00200000, /* Value if GPIOx_GP == 1 */
|
||||||
MREF_GPIO2_GP = 0x00100000, /* General purpose or debug out */
|
MREF_GPIO2_GP = 0x00100000, /* General purpose or debug out */
|
||||||
MREF_GPIO2_OUT = 0x00080000, /* Output or input */
|
MREF_GPIO2_OUT = 0x00080000, /* Output or input */
|
||||||
MREF_GPIO2_VALUE = 0x00040000, /* Value if GPIOx_GP == 1 */
|
MREF_GPIO2_VALUE = 0x00040000, /* Value if GPIOx_GP == 1 */
|
||||||
MREF_GPIO1_GP = 0x00020000, /* General purpose or debug out */
|
MREF_GPIO1_GP = 0x00020000, /* General purpose or debug out */
|
||||||
MREF_GPIO1_OUT = 0x00010000, /* Output or input */
|
MREF_GPIO1_OUT = 0x00010000, /* Output or input */
|
||||||
MREF_GPIO1_VALUE = 0x00008000, /* Value if GPIOx_GP == 1 */
|
MREF_GPIO1_VALUE = 0x00008000, /* Value if GPIOx_GP == 1 */
|
||||||
MREF_GPIO0_GP = 0x00004000, /* General purpose or debug out */
|
MREF_GPIO0_GP = 0x00004000, /* General purpose or debug out */
|
||||||
MREF_GPIO0_OUT = 0x00002000, /* Output or input */
|
MREF_GPIO0_OUT = 0x00002000, /* Output or input */
|
||||||
MREF_GPIO0_VALUE = 0x00001000, /* Value if GPIOx_GP == 1 */
|
MREF_GPIO0_VALUE = 0x00001000, /* Value if GPIOx_GP == 1 */
|
||||||
MREF_REFRESH = 0x00000FFF, /* Memory refresh count */
|
MREF_REFRESH = 0x00000FFF, /* Memory refresh count */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -361,25 +361,25 @@ private:
|
|||||||
// 0:0MB 1:2MB 2:4MB 3:4MB 4:4MB 5:8MB 6:16MB 7:0MB
|
// 0:0MB 1:2MB 2:4MB 3:4MB 4:4MB 5:8MB 6:16MB 7:0MB
|
||||||
switch (size)
|
switch (size)
|
||||||
{
|
{
|
||||||
case 0: return 0;
|
case 0: return 0;
|
||||||
case 2: return 1;
|
case 2: return 1;
|
||||||
case 4: return 2;
|
case 4: return 2;
|
||||||
case 8: return 5;
|
case 8: return 5;
|
||||||
case 16: return 6;
|
case 16: return 6;
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
// GPIO
|
// GPIO
|
||||||
devcb_read_line m_gpio_in[4];
|
devcb_read_line m_gpio_in[4];
|
||||||
devcb_write_line m_gpio_out[4];
|
devcb_write_line m_gpio_out[4];
|
||||||
|
|
||||||
// Registers
|
// Registers
|
||||||
uint32_t m_mcfg;
|
uint32_t m_mcfg;
|
||||||
uint32_t m_mref;
|
uint32_t m_mref;
|
||||||
uint32_t m_mcntl;
|
uint32_t m_mcntl;
|
||||||
uint32_t m_reset;
|
uint32_t m_reset;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -425,29 +425,29 @@ private:
|
|||||||
|
|
||||||
// Internal stuff
|
// Internal stuff
|
||||||
required_device<screen_device> m_screen;
|
required_device<screen_device> m_screen;
|
||||||
emu_timer *m_vint0_timer;
|
emu_timer *m_vint0_timer;
|
||||||
emu_timer *m_vint1_timer;
|
emu_timer *m_vint1_timer;
|
||||||
devcb_write_line m_vint0_int_handler;
|
devcb_write_line m_vint0_int_handler;
|
||||||
devcb_write_line m_vint1_int_handler;
|
devcb_write_line m_vint1_int_handler;
|
||||||
|
|
||||||
// Registers
|
// Registers
|
||||||
uint32_t m_vint;
|
uint32_t m_vint;
|
||||||
uint32_t m_vdc0;
|
uint32_t m_vdc0;
|
||||||
uint32_t m_vdc1;
|
uint32_t m_vdc1;
|
||||||
uint32_t m_fv0a;
|
uint32_t m_fv0a;
|
||||||
uint32_t m_fv1a;
|
uint32_t m_fv1a;
|
||||||
uint32_t m_avdi;
|
uint32_t m_avdi;
|
||||||
uint32_t m_vdli;
|
uint32_t m_vdli;
|
||||||
uint32_t m_vcfg;
|
uint32_t m_vcfg;
|
||||||
uint32_t m_dmt0;
|
uint32_t m_dmt0;
|
||||||
uint32_t m_dmt1;
|
uint32_t m_dmt1;
|
||||||
uint32_t m_vrst;
|
uint32_t m_vrst;
|
||||||
|
|
||||||
// Screen parameters
|
// Screen parameters
|
||||||
uint32_t m_hstart;
|
uint32_t m_hstart;
|
||||||
uint32_t m_htotal;
|
uint32_t m_htotal;
|
||||||
uint32_t m_vstart;
|
uint32_t m_vstart;
|
||||||
uint32_t m_vtotal;
|
uint32_t m_vtotal;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -512,28 +512,28 @@ private:
|
|||||||
|
|
||||||
enum misc
|
enum misc
|
||||||
{
|
{
|
||||||
PIP_RAM_WORDS = 256,
|
PIP_RAM_WORDS = 256,
|
||||||
TEXTURE_RAM_WORDS = 4096,
|
TEXTURE_RAM_WORDS = 4096,
|
||||||
PIP_RAM_BYTEMASK = PIP_RAM_WORDS * 4 - 1,
|
PIP_RAM_BYTEMASK = PIP_RAM_WORDS * 4 - 1,
|
||||||
TEXTURE_RAM_BYTEMASK = TEXTURE_RAM_WORDS * 4 - 1,
|
TEXTURE_RAM_BYTEMASK = TEXTURE_RAM_WORDS * 4 - 1,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum inst_type
|
enum inst_type
|
||||||
{
|
{
|
||||||
INST_WRITE_REG = 0x10000000,
|
INST_WRITE_REG = 0x10000000,
|
||||||
INST_VTX_SHORT = 0x20000000,
|
INST_VTX_SHORT = 0x20000000,
|
||||||
INST_VTX_LONG = 0x30000000,
|
INST_VTX_LONG = 0x30000000,
|
||||||
INST_VTX_POINT = 0x40000000,
|
INST_VTX_POINT = 0x40000000,
|
||||||
INST_MASK = 0xf0000000,
|
INST_MASK = 0xf0000000,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum vtx_flag
|
enum vtx_flag
|
||||||
{
|
{
|
||||||
VTX_FLAG_SHAD = 0x00010000,
|
VTX_FLAG_SHAD = 0x00010000,
|
||||||
VTX_FLAG_TEXT = 0x00020000,
|
VTX_FLAG_TEXT = 0x00020000,
|
||||||
VTX_FLAG_PRSP = 0x00040000,
|
VTX_FLAG_PRSP = 0x00040000,
|
||||||
VTX_FLAG_NEW = 0x00080000,
|
VTX_FLAG_NEW = 0x00080000,
|
||||||
VTX_FLAG_RM = 0x00100000,
|
VTX_FLAG_RM = 0x00100000,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct se_vtx
|
struct se_vtx
|
||||||
@ -639,14 +639,14 @@ private:
|
|||||||
uint32_t readbits_from_ram(uint32_t & src_addr, uint32_t & bit_offs, uint32_t bits);
|
uint32_t readbits_from_ram(uint32_t & src_addr, uint32_t & bit_offs, uint32_t bits);
|
||||||
void load_texture();
|
void load_texture();
|
||||||
|
|
||||||
m2_bda_device *m_bda;
|
m2_bda_device *m_bda;
|
||||||
const address_space_config m_space_config; // TODO: Why is this still here?
|
const address_space_config m_space_config; // TODO: Why is this still here?
|
||||||
|
|
||||||
devcb_write_line m_general_int_handler;
|
devcb_write_line m_general_int_handler;
|
||||||
devcb_write_line m_dfinstr_int_handler;
|
devcb_write_line m_dfinstr_int_handler;
|
||||||
devcb_write_line m_iminstr_int_handler;
|
devcb_write_line m_iminstr_int_handler;
|
||||||
devcb_write_line m_listend_int_handler;
|
devcb_write_line m_listend_int_handler;
|
||||||
devcb_write_line m_winclip_int_handler;
|
devcb_write_line m_winclip_int_handler;
|
||||||
|
|
||||||
// Registers
|
// Registers
|
||||||
union
|
union
|
||||||
@ -672,9 +672,9 @@ private:
|
|||||||
{
|
{
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
se_vtx vertices[3];
|
se_vtx vertices[3];
|
||||||
uint32_t reserved[16];
|
uint32_t reserved[16];
|
||||||
uint32_t vertex_state;
|
uint32_t vertex_state;
|
||||||
};
|
};
|
||||||
uint32_t m_regs[65];
|
uint32_t m_regs[65];
|
||||||
} m_se;
|
} m_se;
|
||||||
@ -841,26 +841,26 @@ private:
|
|||||||
// Destination blender state
|
// Destination blender state
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t x;
|
uint32_t x;
|
||||||
uint32_t y;
|
uint32_t y;
|
||||||
uint32_t w;
|
uint32_t w;
|
||||||
|
|
||||||
rgba ti;
|
rgba ti;
|
||||||
uint8_t ssb;
|
uint8_t ssb;
|
||||||
|
|
||||||
rgba src;
|
rgba src;
|
||||||
uint8_t dsb;
|
uint8_t dsb;
|
||||||
|
|
||||||
rgba srcpath;
|
rgba srcpath;
|
||||||
rgba texpath;
|
rgba texpath;
|
||||||
rgba blend;
|
rgba blend;
|
||||||
rgba dst;
|
rgba dst;
|
||||||
} m_dbstate;
|
} m_dbstate;
|
||||||
|
|
||||||
te_state m_state;
|
te_state m_state;
|
||||||
|
|
||||||
uint32_t *m_pipram;
|
uint32_t *m_pipram;
|
||||||
uint32_t *m_tram;
|
uint32_t *m_tram;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -937,141 +937,141 @@ private:
|
|||||||
enum reg_offs
|
enum reg_offs
|
||||||
{
|
{
|
||||||
// Miscellaneous
|
// Miscellaneous
|
||||||
CDE_DEVICE_ID = 0x000,
|
CDE_DEVICE_ID = 0x000,
|
||||||
CDE_VERSION = 0x004,
|
CDE_VERSION = 0x004,
|
||||||
CDE_SDBG_CNTL = 0x00C, // Serial debug control register
|
CDE_SDBG_CNTL = 0x00C, // Serial debug control register
|
||||||
CDE_SDBG_RD = 0x010, // Serial debug read data
|
CDE_SDBG_RD = 0x010, // Serial debug read data
|
||||||
CDE_SDBG_WRT = 0x014, // Serial debug write data
|
CDE_SDBG_WRT = 0x014, // Serial debug write data
|
||||||
CDE_INT_STS = 0x018, // offset for status reg
|
CDE_INT_STS = 0x018, // offset for status reg
|
||||||
CDE_INT_ENABLE = 0x01C,
|
CDE_INT_ENABLE = 0x01C,
|
||||||
CDE_RESET_CNTL = 0x020,
|
CDE_RESET_CNTL = 0x020,
|
||||||
CDE_ROM_DISABLE = 0x024,
|
CDE_ROM_DISABLE = 0x024,
|
||||||
CDE_CD_CMD_WRT = 0x028,
|
CDE_CD_CMD_WRT = 0x028,
|
||||||
CDE_CD_STS_RD = 0x02C,
|
CDE_CD_STS_RD = 0x02C,
|
||||||
CDE_GPIO1 = 0x030, // GPIO1 control register (UART interrupt)
|
CDE_GPIO1 = 0x030, // GPIO1 control register (UART interrupt)
|
||||||
CDE_GPIO2 = 0x034, // GPIO1 control register
|
CDE_GPIO2 = 0x034, // GPIO1 control register
|
||||||
|
|
||||||
// BIO Bus
|
// BIO Bus
|
||||||
CDE_DEV_DETECT = 0x200,
|
CDE_DEV_DETECT = 0x200,
|
||||||
CDE_BBLOCK = 0x204,
|
CDE_BBLOCK = 0x204,
|
||||||
CDE_BBLOCK_EN = 0x208, // Blocking enable register
|
CDE_BBLOCK_EN = 0x208, // Blocking enable register
|
||||||
CDE_DEV5_CONF = 0x20C,
|
CDE_DEV5_CONF = 0x20C,
|
||||||
CDE_DEV_STATE = 0x210,
|
CDE_DEV_STATE = 0x210,
|
||||||
CDE_DEV6_CONF = 0x214,
|
CDE_DEV6_CONF = 0x214,
|
||||||
CDE_DEV5_VISA_CONF = 0x218,
|
CDE_DEV5_VISA_CONF = 0x218,
|
||||||
CDE_DEV6_VISA_CONF = 0x21C,
|
CDE_DEV6_VISA_CONF = 0x21C,
|
||||||
CDE_UNIQ_ID_CMD = 0x220,
|
CDE_UNIQ_ID_CMD = 0x220,
|
||||||
CDE_UNIQ_ID_RD = 0x224,
|
CDE_UNIQ_ID_RD = 0x224,
|
||||||
CDE_DEV_ERROR = 0x228,
|
CDE_DEV_ERROR = 0x228,
|
||||||
CDE_DEV7_CONF = 0x22C,
|
CDE_DEV7_CONF = 0x22C,
|
||||||
CDE_DEV7_VISA_CONF = 0x230,
|
CDE_DEV7_VISA_CONF = 0x230,
|
||||||
CDE_DEV0_SETUP = 0x240,
|
CDE_DEV0_SETUP = 0x240,
|
||||||
CDE_DEV0_CYCLE_TIME = 0x244,
|
CDE_DEV0_CYCLE_TIME = 0x244,
|
||||||
CDE_DEV1_SETUP = 0x248,
|
CDE_DEV1_SETUP = 0x248,
|
||||||
CDE_DEV1_CYCLE_TIME = 0x24C,
|
CDE_DEV1_CYCLE_TIME = 0x24C,
|
||||||
CDE_DEV2_SETUP = 0x250,
|
CDE_DEV2_SETUP = 0x250,
|
||||||
CDE_DEV2_CYCLE_TIME = 0x254,
|
CDE_DEV2_CYCLE_TIME = 0x254,
|
||||||
CDE_DEV3_SETUP = 0x258,
|
CDE_DEV3_SETUP = 0x258,
|
||||||
CDE_DEV3_CYCLE_TIME = 0x25C,
|
CDE_DEV3_CYCLE_TIME = 0x25C,
|
||||||
CDE_DEV4_SETUP = 0x260,
|
CDE_DEV4_SETUP = 0x260,
|
||||||
CDE_DEV4_CYCLE_TIME = 0x264,
|
CDE_DEV4_CYCLE_TIME = 0x264,
|
||||||
CDE_DEV5_SETUP = 0x268,
|
CDE_DEV5_SETUP = 0x268,
|
||||||
CDE_DEV5_CYCLE_TIME = 0x26C,
|
CDE_DEV5_CYCLE_TIME = 0x26C,
|
||||||
CDE_DEV6_SETUP = 0x270,
|
CDE_DEV6_SETUP = 0x270,
|
||||||
CDE_DEV6_CYCLE_TIME = 0x274,
|
CDE_DEV6_CYCLE_TIME = 0x274,
|
||||||
CDE_DEV7_SETUP = 0x278,
|
CDE_DEV7_SETUP = 0x278,
|
||||||
CDE_DEV7_CYCLE_TIME = 0x27C,
|
CDE_DEV7_CYCLE_TIME = 0x27C,
|
||||||
CDE_SYSTEM_CONF = 0x280,
|
CDE_SYSTEM_CONF = 0x280,
|
||||||
CDE_VISA_DIS = 0x284,
|
CDE_VISA_DIS = 0x284,
|
||||||
CDE_MICRO_RWS = 0x290,
|
CDE_MICRO_RWS = 0x290,
|
||||||
CDE_MICRO_WI = 0x294,
|
CDE_MICRO_WI = 0x294,
|
||||||
CDE_MICRO_WOB = 0x298,
|
CDE_MICRO_WOB = 0x298,
|
||||||
CDE_MICRO_WO = 0x29C,
|
CDE_MICRO_WO = 0x29C,
|
||||||
CDE_MICRO_STATUS = 0x2A0,
|
CDE_MICRO_STATUS = 0x2A0,
|
||||||
|
|
||||||
// CD DMA
|
// CD DMA
|
||||||
CDE_CD_DMA1_CNTL = 0x300,
|
CDE_CD_DMA1_CNTL = 0x300,
|
||||||
CDE_CD_DMA1_CPAD = 0x308,
|
CDE_CD_DMA1_CPAD = 0x308,
|
||||||
CDE_CD_DMA1_CCNT = 0x30C,
|
CDE_CD_DMA1_CCNT = 0x30C,
|
||||||
CDE_CD_DMA1_NPAD = 0x318,
|
CDE_CD_DMA1_NPAD = 0x318,
|
||||||
CDE_CD_DMA1_NCNT = 0x31C,
|
CDE_CD_DMA1_NCNT = 0x31C,
|
||||||
CDE_CD_DMA2_CNTL = 0x320,
|
CDE_CD_DMA2_CNTL = 0x320,
|
||||||
CDE_CD_DMA2_CPAD = 0x328,
|
CDE_CD_DMA2_CPAD = 0x328,
|
||||||
CDE_CD_DMA2_CCNT = 0x32C,
|
CDE_CD_DMA2_CCNT = 0x32C,
|
||||||
CDE_CD_DMA2_NPAD = 0x338,
|
CDE_CD_DMA2_NPAD = 0x338,
|
||||||
CDE_CD_DMA2_NCNT = 0x33C,
|
CDE_CD_DMA2_NCNT = 0x33C,
|
||||||
|
|
||||||
// BioBus DMA
|
// BioBus DMA
|
||||||
CDE_DMA1_CNTL = 0x1000,
|
CDE_DMA1_CNTL = 0x1000,
|
||||||
CDE_DMA1_CBAD = 0x1004,
|
CDE_DMA1_CBAD = 0x1004,
|
||||||
CDE_DMA1_CPAD = 0x1008,
|
CDE_DMA1_CPAD = 0x1008,
|
||||||
CDE_DMA1_CCNT = 0x100C,
|
CDE_DMA1_CCNT = 0x100C,
|
||||||
CDE_DMA1_NBAD = 0x1014,
|
CDE_DMA1_NBAD = 0x1014,
|
||||||
CDE_DMA1_NPAD = 0x1018,
|
CDE_DMA1_NPAD = 0x1018,
|
||||||
CDE_DMA1_NCNT = 0x101C,
|
CDE_DMA1_NCNT = 0x101C,
|
||||||
CDE_DMA2_CNTL = 0x1020,
|
CDE_DMA2_CNTL = 0x1020,
|
||||||
CDE_DMA2_CBAD = 0x1024,
|
CDE_DMA2_CBAD = 0x1024,
|
||||||
CDE_DMA2_CPAD = 0x1028,
|
CDE_DMA2_CPAD = 0x1028,
|
||||||
CDE_DMA2_CCNT = 0x102C,
|
CDE_DMA2_CCNT = 0x102C,
|
||||||
CDE_DMA2_NBAD = 0x1034,
|
CDE_DMA2_NBAD = 0x1034,
|
||||||
CDE_DMA2_NPAD = 0x1038,
|
CDE_DMA2_NPAD = 0x1038,
|
||||||
CDE_DMA2_NCNT = 0x103C,
|
CDE_DMA2_NCNT = 0x103C,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum cde_int
|
enum cde_int
|
||||||
{
|
{
|
||||||
CDE_INT_SENT = 0x80000000,
|
CDE_INT_SENT = 0x80000000,
|
||||||
CDE_SDBG_WRT_DONE = 0x10000000,
|
CDE_SDBG_WRT_DONE = 0x10000000,
|
||||||
CDE_SDBG_RD_DONE = 0x08000000,
|
CDE_SDBG_RD_DONE = 0x08000000,
|
||||||
CDE_DIPIR = 0x04000000,
|
CDE_DIPIR = 0x04000000,
|
||||||
CDE_ARM_BOUNDS = 0x01000000,
|
CDE_ARM_BOUNDS = 0x01000000,
|
||||||
CDE_DMA2_BLOCKED = 0x00400000,
|
CDE_DMA2_BLOCKED = 0x00400000,
|
||||||
CDE_DMA1_BLOCKED = 0x00200000,
|
CDE_DMA1_BLOCKED = 0x00200000,
|
||||||
CDE_ID_READY = 0x00100000,
|
CDE_ID_READY = 0x00100000,
|
||||||
CDE_ARM_FENCE = 0x00080000,
|
CDE_ARM_FENCE = 0x00080000,
|
||||||
CDE_EXT_INT = 0x00040000, // PJB: Used for SIO?
|
CDE_EXT_INT = 0x00040000, // PJB: Used for SIO?
|
||||||
CDE_3DO_CARD_INT = 0x00020000,
|
CDE_3DO_CARD_INT = 0x00020000,
|
||||||
CDE_ARM_INT = 0x00010000,
|
CDE_ARM_INT = 0x00010000,
|
||||||
CDE_CD_DMA2_OF = 0x00004000,
|
CDE_CD_DMA2_OF = 0x00004000,
|
||||||
CDE_CD_DMA1_OF = 0x00002000,
|
CDE_CD_DMA1_OF = 0x00002000,
|
||||||
CDE_ARM_ABORT = 0x00001000,
|
CDE_ARM_ABORT = 0x00001000,
|
||||||
CDE_CD_DMA2_DONE = 0x00000800,
|
CDE_CD_DMA2_DONE = 0x00000800,
|
||||||
CDE_CD_DMA1_DONE = 0x00000400,
|
CDE_CD_DMA1_DONE = 0x00000400,
|
||||||
CDE_DMA2_DONE = 0x00000100,
|
CDE_DMA2_DONE = 0x00000100,
|
||||||
CDE_DMA1_DONE = 0x00000080,
|
CDE_DMA1_DONE = 0x00000080,
|
||||||
CDE_PBUS_ERROR = 0x00000040,
|
CDE_PBUS_ERROR = 0x00000040,
|
||||||
CDE_CD_CMD_WRT_DONE = 0x00000020,
|
CDE_CD_CMD_WRT_DONE = 0x00000020,
|
||||||
CDE_CD_STS_RD_DONE = 0x00000010,
|
CDE_CD_STS_RD_DONE = 0x00000010,
|
||||||
CDE_CD_STS_FL_DONE = 0x00000008,
|
CDE_CD_STS_FL_DONE = 0x00000008,
|
||||||
CDE_GPIO1_INT = 0x00000004,
|
CDE_GPIO1_INT = 0x00000004,
|
||||||
CDE_GPIO2_INT = 0x00000002,
|
CDE_GPIO2_INT = 0x00000002,
|
||||||
CDE_BBUS_ERROR = 0x00000001,
|
CDE_BBUS_ERROR = 0x00000001,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum cde_dma_cntl
|
enum cde_dma_cntl
|
||||||
{
|
{
|
||||||
CDE_DMA_DIRECTION = 0x00000400, /* PowerBus to BioBus if set */
|
CDE_DMA_DIRECTION = 0x00000400, /* PowerBus to BioBus if set */
|
||||||
CDE_DMA_RESET = 0x00000200, /* Reset engine if set */
|
CDE_DMA_RESET = 0x00000200, /* Reset engine if set */
|
||||||
CDE_DMA_GLOBAL = 0x00000100, /* snoopable trans if set */
|
CDE_DMA_GLOBAL = 0x00000100, /* snoopable trans if set */
|
||||||
CDE_DMA_CURR_VALID = 0x00000080, /* current setup valid if set */
|
CDE_DMA_CURR_VALID = 0x00000080, /* current setup valid if set */
|
||||||
CDE_DMA_NEXT_VALID = 0x00000040, /* next setup valid if set */
|
CDE_DMA_NEXT_VALID = 0x00000040, /* next setup valid if set */
|
||||||
CDE_DMA_GO_FOREVER = 0x00000020, /* copy next to current if set*/
|
CDE_DMA_GO_FOREVER = 0x00000020, /* copy next to current if set*/
|
||||||
CDE_PB_CHANNEL_MASK = 0x0000001F, /* powerbus channel to use */
|
CDE_PB_CHANNEL_MASK = 0x0000001F, /* powerbus channel to use */
|
||||||
};
|
};
|
||||||
|
|
||||||
enum cde_dev_setup
|
enum cde_dev_setup
|
||||||
{
|
{
|
||||||
CDE_WRITEN_HOLD = 0x00000003,
|
CDE_WRITEN_HOLD = 0x00000003,
|
||||||
CDE_WRITEN_SETUP = 0x0000001C,
|
CDE_WRITEN_SETUP = 0x0000001C,
|
||||||
CDE_READ_HOLD = 0x00000060,
|
CDE_READ_HOLD = 0x00000060,
|
||||||
CDE_READ_SETUP = 0x00000380,
|
CDE_READ_SETUP = 0x00000380,
|
||||||
CDE_PAGEMODE = 0x00000400,
|
CDE_PAGEMODE = 0x00000400,
|
||||||
CDE_DATAWIDTH = 0x00001800,
|
CDE_DATAWIDTH = 0x00001800,
|
||||||
CDE_DATAWIDTH_8 = 0x00000000,
|
CDE_DATAWIDTH_8 = 0x00000000,
|
||||||
CDE_DATAWIDTH_16 = 0x00000800,
|
CDE_DATAWIDTH_16 = 0x00000800,
|
||||||
CDE_READ_SETUP_IO = 0x0000E000,
|
CDE_READ_SETUP_IO = 0x0000E000,
|
||||||
CDE_MODEA = 0x00010000,
|
CDE_MODEA = 0x00010000,
|
||||||
CDE_HIDEA = 0x00020000,
|
CDE_HIDEA = 0x00020000,
|
||||||
};
|
};
|
||||||
|
|
||||||
void write_reg(uint32_t ®, uint32_t data, bool clear);
|
void write_reg(uint32_t ®, uint32_t data, bool clear);
|
||||||
@ -1089,38 +1089,38 @@ private:
|
|||||||
}
|
}
|
||||||
|
|
||||||
required_device<ppc_device> m_cpu1;
|
required_device<ppc_device> m_cpu1;
|
||||||
m2_bda_device *m_bda; // todo
|
m2_bda_device *m_bda; // todo
|
||||||
|
|
||||||
devcb_write_line m_int_handler;
|
devcb_write_line m_int_handler;
|
||||||
devcb_write32 m_sdbg_out_handler;
|
devcb_write32 m_sdbg_out_handler;
|
||||||
|
|
||||||
|
|
||||||
// Registers
|
// Registers
|
||||||
uint32_t m_sdbg_in;
|
uint32_t m_sdbg_in;
|
||||||
uint32_t m_sdbg_out;
|
uint32_t m_sdbg_out;
|
||||||
uint32_t m_sdbg_cntl;
|
uint32_t m_sdbg_cntl;
|
||||||
uint32_t m_int_status;
|
uint32_t m_int_status;
|
||||||
uint32_t m_int_enable;
|
uint32_t m_int_enable;
|
||||||
uint32_t m_bblock_en;
|
uint32_t m_bblock_en;
|
||||||
uint32_t m_syscfg;
|
uint32_t m_syscfg;
|
||||||
uint32_t m_visa_dis;
|
uint32_t m_visa_dis;
|
||||||
|
|
||||||
struct biobus_device
|
struct biobus_device
|
||||||
{
|
{
|
||||||
uint32_t m_setup;
|
uint32_t m_setup;
|
||||||
uint32_t m_cycle_time;
|
uint32_t m_cycle_time;
|
||||||
} m_bio_device[8];
|
} m_bio_device[8];
|
||||||
|
|
||||||
struct dma_channel
|
struct dma_channel
|
||||||
{
|
{
|
||||||
uint32_t m_cntl;
|
uint32_t m_cntl;
|
||||||
uint32_t m_cbad;
|
uint32_t m_cbad;
|
||||||
uint32_t m_cpad;
|
uint32_t m_cpad;
|
||||||
uint32_t m_ccnt;
|
uint32_t m_ccnt;
|
||||||
uint32_t m_nbad;
|
uint32_t m_nbad;
|
||||||
uint32_t m_npad;
|
uint32_t m_npad;
|
||||||
uint32_t m_ncnt;
|
uint32_t m_ncnt;
|
||||||
emu_timer *m_timer;
|
emu_timer *m_timer;
|
||||||
} m_dma[2];
|
} m_dma[2];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -17,4 +17,4 @@ void genpin_class::genpin_audio(machine_config &config)
|
|||||||
m_samples->set_channels(6);
|
m_samples->set_channels(6);
|
||||||
m_samples->set_samples_names(genpin_sample_names);
|
m_samples->set_samples_names(genpin_sample_names);
|
||||||
m_samples->add_route(ALL_OUTPUTS, "mechvol", 1.0);
|
m_samples->add_route(ALL_OUTPUTS, "mechvol", 1.0);
|
||||||
}
|
}
|
||||||
|
@ -13,12 +13,12 @@
|
|||||||
#include "includes/midtunit.h"
|
#include "includes/midtunit.h"
|
||||||
#include "includes/midwunit.h"
|
#include "includes/midwunit.h"
|
||||||
|
|
||||||
#define LOG_UNKNOWN (1 << 0)
|
#define LOG_UNKNOWN (1 << 0)
|
||||||
#define LOG_CMOS (1 << 1)
|
#define LOG_CMOS (1 << 1)
|
||||||
#define LOG_IO (1 << 2)
|
#define LOG_IO (1 << 2)
|
||||||
#define LOG_SOUND (1 << 3)
|
#define LOG_SOUND (1 << 3)
|
||||||
|
|
||||||
#define VERBOSE (0)
|
#define VERBOSE (0)
|
||||||
#include "logmacro.h"
|
#include "logmacro.h"
|
||||||
|
|
||||||
/*************************************
|
/*************************************
|
||||||
|
@ -14,12 +14,12 @@
|
|||||||
#include "includes/midxunit.h"
|
#include "includes/midxunit.h"
|
||||||
#include "midwayic.h"
|
#include "midwayic.h"
|
||||||
|
|
||||||
#define LOG_IO (1 << 0)
|
#define LOG_IO (1 << 0)
|
||||||
#define LOG_UART (1 << 1)
|
#define LOG_UART (1 << 1)
|
||||||
#define LOG_UNKNOWN (1 << 2)
|
#define LOG_UNKNOWN (1 << 2)
|
||||||
#define LOG_SOUND (1 << 3)
|
#define LOG_SOUND (1 << 3)
|
||||||
|
|
||||||
#define VERBOSE (0)
|
#define VERBOSE (0)
|
||||||
#include "logmacro.h"
|
#include "logmacro.h"
|
||||||
|
|
||||||
/*************************************
|
/*************************************
|
||||||
|
@ -1368,12 +1368,12 @@ void galaxian_state::jumpbug_extend_sprite_info(const uint8_t *base, uint8_t *sx
|
|||||||
*
|
*
|
||||||
*************************************/
|
*************************************/
|
||||||
|
|
||||||
/* gfxbank[4] is used as a cpu bank number, and gfxbank[0] for graphics banking */
|
/* gfxbank[4] is used as a cpu bank number, and gfxbank[0] for graphics banking */
|
||||||
WRITE8_MEMBER( galaxian_state::fourplay_rombank_w )
|
WRITE8_MEMBER( galaxian_state::fourplay_rombank_w )
|
||||||
{
|
{
|
||||||
m_gfxbank[4] = (m_gfxbank[4] & (2 - offset)) | (data << offset);
|
m_gfxbank[4] = (m_gfxbank[4] & (2 - offset)) | (data << offset);
|
||||||
|
|
||||||
m_gfxbank[0] = (m_gfxbank[4] == 3); // 1 = true, 0 = false
|
m_gfxbank[0] = (m_gfxbank[4] == 3); // 1 = true, 0 = false
|
||||||
|
|
||||||
membank("bank1")->set_entry( m_gfxbank[4] );
|
membank("bank1")->set_entry( m_gfxbank[4] );
|
||||||
}
|
}
|
||||||
|
@ -41,7 +41,7 @@ public:
|
|||||||
|
|
||||||
template <typename... T> void set_tile_callback(T &&... args) { m_k056832_cb = k056832_cb_delegate(std::forward<T>(args)...); }
|
template <typename... T> void set_tile_callback(T &&... args) { m_k056832_cb = k056832_cb_delegate(std::forward<T>(args)...); }
|
||||||
|
|
||||||
template <typename T>
|
template <typename T>
|
||||||
void set_config(T &&gfx_reg, int bpp, int big, int djmain_hack)
|
void set_config(T &&gfx_reg, int bpp, int big, int djmain_hack)
|
||||||
{
|
{
|
||||||
m_rombase.set_tag(std::forward<T>(gfx_reg));
|
m_rombase.set_tag(std::forward<T>(gfx_reg));
|
||||||
|
@ -140,8 +140,8 @@ WRITE16_MEMBER(midtunit_video_device::midtunit_vram_w)
|
|||||||
offset *= 2;
|
offset *= 2;
|
||||||
if (m_videobank_select)
|
if (m_videobank_select)
|
||||||
{
|
{
|
||||||
if (ACCESSING_BITS_0_7)
|
if (ACCESSING_BITS_0_7)
|
||||||
m_local_videoram[offset] = (data & 0xff) | ((m_dma_register[DMA_PALETTE] & 0xff) << 8);
|
m_local_videoram[offset] = (data & 0xff) | ((m_dma_register[DMA_PALETTE] & 0xff) << 8);
|
||||||
if (ACCESSING_BITS_8_15)
|
if (ACCESSING_BITS_8_15)
|
||||||
m_local_videoram[offset + 1] = ((data >> 8) & 0xff) | (m_dma_register[DMA_PALETTE] & 0xff00);
|
m_local_videoram[offset + 1] = ((data >> 8) & 0xff) | (m_dma_register[DMA_PALETTE] & 0xff00);
|
||||||
}
|
}
|
||||||
|
@ -16,7 +16,7 @@
|
|||||||
#include "cpu/tms34010/tms34010.h"
|
#include "cpu/tms34010/tms34010.h"
|
||||||
#include "emupal.h"
|
#include "emupal.h"
|
||||||
|
|
||||||
#define DEBUG_MIDTUNIT_BLITTER (0)
|
#define DEBUG_MIDTUNIT_BLITTER (0)
|
||||||
|
|
||||||
class midtunit_video_device : public device_t
|
class midtunit_video_device : public device_t
|
||||||
{
|
{
|
||||||
@ -110,16 +110,16 @@ protected:
|
|||||||
};
|
};
|
||||||
|
|
||||||
/* graphics-related variables */
|
/* graphics-related variables */
|
||||||
uint16_t m_midtunit_control;
|
uint16_t m_midtunit_control;
|
||||||
bool m_gfx_rom_large;
|
bool m_gfx_rom_large;
|
||||||
|
|
||||||
/* videoram-related variables */
|
/* videoram-related variables */
|
||||||
uint32_t m_gfxbank_offset[2];
|
uint32_t m_gfxbank_offset[2];
|
||||||
std::unique_ptr<uint16_t[]> m_local_videoram;
|
std::unique_ptr<uint16_t[]> m_local_videoram;
|
||||||
uint8_t m_videobank_select;
|
uint8_t m_videobank_select;
|
||||||
|
|
||||||
/* DMA-related variables */
|
/* DMA-related variables */
|
||||||
uint16_t m_dma_register[18];
|
uint16_t m_dma_register[18];
|
||||||
struct dma_state
|
struct dma_state
|
||||||
{
|
{
|
||||||
uint8_t * gfxrom;
|
uint8_t * gfxrom;
|
||||||
@ -145,7 +145,7 @@ protected:
|
|||||||
uint16_t xstep; /* 8.8 fixed number scale x factor */
|
uint16_t xstep; /* 8.8 fixed number scale x factor */
|
||||||
uint16_t ystep; /* 8.8 fixed number scale y factor */
|
uint16_t ystep; /* 8.8 fixed number scale y factor */
|
||||||
};
|
};
|
||||||
dma_state m_dma_state;
|
dma_state m_dma_state;
|
||||||
|
|
||||||
#if DEBUG_MIDTUNIT_BLITTER
|
#if DEBUG_MIDTUNIT_BLITTER
|
||||||
virtual void device_reset() override;
|
virtual void device_reset() override;
|
||||||
@ -223,4 +223,4 @@ DECLARE_DEVICE_TYPE(MIDTUNIT_VIDEO, midtunit_video_device)
|
|||||||
DECLARE_DEVICE_TYPE(MIDWUNIT_VIDEO, midwunit_video_device)
|
DECLARE_DEVICE_TYPE(MIDWUNIT_VIDEO, midwunit_video_device)
|
||||||
DECLARE_DEVICE_TYPE(MIDXUNIT_VIDEO, midxunit_video_device)
|
DECLARE_DEVICE_TYPE(MIDXUNIT_VIDEO, midxunit_video_device)
|
||||||
|
|
||||||
#endif // MAME_VIDEO_MIDTUNIT_H
|
#endif // MAME_VIDEO_MIDTUNIT_H
|
||||||
|
@ -9,23 +9,23 @@
|
|||||||
**************************************************************************/
|
**************************************************************************/
|
||||||
|
|
||||||
#define INIT_TEMPLATED_DMA_DRAW(dest, i, xflip, skip, scale, zero, nonzero) \
|
#define INIT_TEMPLATED_DMA_DRAW(dest, i, xflip, skip, scale, zero, nonzero) \
|
||||||
dest[i+0] = &midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>; \
|
dest[i+0] = &midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+1] = &midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>; \
|
dest[i+1] = &midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+2] = &midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>; \
|
dest[i+2] = &midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+3] = &midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>; \
|
dest[i+3] = &midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+4] = &midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>; \
|
dest[i+4] = &midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+5] = &midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>; \
|
dest[i+5] = &midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+6] = &midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>; \
|
dest[i+6] = &midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>; \
|
||||||
dest[i+7] = &midtunit_video_device::dma_draw<7, xflip, skip, scale, zero, nonzero>;
|
dest[i+7] = &midtunit_video_device::dma_draw<7, xflip, skip, scale, zero, nonzero>;
|
||||||
|
|
||||||
#define TEMPLATED_DMA_DRAW_NONE(dest, i) \
|
#define TEMPLATED_DMA_DRAW_NONE(dest, i) \
|
||||||
dest[i+0] = &midtunit_video_device::dma_draw_none; \
|
dest[i+0] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+1] = &midtunit_video_device::dma_draw_none; \
|
dest[i+1] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+2] = &midtunit_video_device::dma_draw_none; \
|
dest[i+2] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+3] = &midtunit_video_device::dma_draw_none; \
|
dest[i+3] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+4] = &midtunit_video_device::dma_draw_none; \
|
dest[i+4] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+5] = &midtunit_video_device::dma_draw_none; \
|
dest[i+5] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+6] = &midtunit_video_device::dma_draw_none; \
|
dest[i+6] = &midtunit_video_device::dma_draw_none; \
|
||||||
dest[i+7] = &midtunit_video_device::dma_draw_none;
|
dest[i+7] = &midtunit_video_device::dma_draw_none;
|
||||||
|
|
||||||
#define TEMPLATED_DMA_DRAW_P0(dest, i, skip, scale) INIT_TEMPLATED_DMA_DRAW(dest, i, false, skip, scale, PIXEL_COPY, PIXEL_SKIP)
|
#define TEMPLATED_DMA_DRAW_P0(dest, i, skip, scale) INIT_TEMPLATED_DMA_DRAW(dest, i, false, skip, scale, PIXEL_COPY, PIXEL_SKIP)
|
||||||
@ -47,33 +47,33 @@
|
|||||||
#define TEMPLATED_DMA_DRAW_P0C1_XF(dest, i, skip, scale) INIT_TEMPLATED_DMA_DRAW(dest, i, true, skip, scale, PIXEL_COPY, PIXEL_COLOR)
|
#define TEMPLATED_DMA_DRAW_P0C1_XF(dest, i, skip, scale) INIT_TEMPLATED_DMA_DRAW(dest, i, true, skip, scale, PIXEL_COPY, PIXEL_COLOR)
|
||||||
|
|
||||||
#define INIT_TEMPLATED_DMA_DRAW_GROUP(dest, skip, scale) \
|
#define INIT_TEMPLATED_DMA_DRAW_GROUP(dest, skip, scale) \
|
||||||
TEMPLATED_DMA_DRAW_NONE(dest, 0); \
|
TEMPLATED_DMA_DRAW_NONE(dest, 0); \
|
||||||
TEMPLATED_DMA_DRAW_P0(dest, 8, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0(dest, 8, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P1(dest, 16, skip, scale); \
|
TEMPLATED_DMA_DRAW_P1(dest, 16, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P0P1(dest, 24, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0P1(dest, 24, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0(dest, 32, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0(dest, 32, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0(dest, 40, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0(dest, 40, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0P1(dest, 48, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0P1(dest, 48, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0P1(dest, 56, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0P1(dest, 56, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C1(dest, 64, skip, scale); \
|
TEMPLATED_DMA_DRAW_C1(dest, 64, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P0C1(dest, 72, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0C1(dest, 72, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C1(dest, 80, skip, scale); \
|
TEMPLATED_DMA_DRAW_C1(dest, 80, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P0C1(dest, 88, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0C1(dest, 88, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0C1(dest, 96, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0C1(dest, 96, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0C1(dest, 104, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0C1(dest, 104, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0C1(dest, 112, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0C1(dest, 112, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0C1(dest, 120, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0C1(dest, 120, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_NONE(dest, 128); \
|
TEMPLATED_DMA_DRAW_NONE(dest, 128); \
|
||||||
TEMPLATED_DMA_DRAW_P0_XF(dest, 136, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0_XF(dest, 136, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P1_XF(dest, 144, skip, scale); \
|
TEMPLATED_DMA_DRAW_P1_XF(dest, 144, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P0P1_XF(dest, 152, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0P1_XF(dest, 152, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0_XF(dest, 160, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0_XF(dest, 160, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0_XF(dest, 168, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0_XF(dest, 168, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0P1_XF(dest, 176, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0P1_XF(dest, 176, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0P1_XF(dest, 184, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0P1_XF(dest, 184, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C1_XF(dest, 192, skip, scale); \
|
TEMPLATED_DMA_DRAW_C1_XF(dest, 192, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P0C1_XF(dest, 200, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0C1_XF(dest, 200, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C1_XF(dest, 208, skip, scale); \
|
TEMPLATED_DMA_DRAW_C1_XF(dest, 208, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_P0C1_XF(dest, 216, skip, scale); \
|
TEMPLATED_DMA_DRAW_P0C1_XF(dest, 216, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 224, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 224, skip, scale); \
|
||||||
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 232, skip, scale); \
|
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 232, skip, scale); \
|
||||||
@ -81,13 +81,13 @@
|
|||||||
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 248, skip, scale);
|
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 248, skip, scale);
|
||||||
|
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW(xflip, skip, scale, zero, nonzero) \
|
#define DEFINE_TEMPLATED_DMA_DRAW(xflip, skip, scale, zero, nonzero) \
|
||||||
template void midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>(); \
|
template void midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>(); \
|
||||||
template void midtunit_video_device::dma_draw<7, xflip, skip, scale, zero, nonzero>();
|
template void midtunit_video_device::dma_draw<7, xflip, skip, scale, zero, nonzero>();
|
||||||
|
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_P0(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_P0(skip, scale) \
|
||||||
@ -107,21 +107,21 @@
|
|||||||
#define DEFINE_TEMPLATED_DMA_DRAW_P0C1(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_P0C1(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(false, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COLOR)
|
DEFINE_TEMPLATED_DMA_DRAW(false, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COLOR)
|
||||||
|
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_P0_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_P0_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_SKIP)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_SKIP)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_P1_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_P1_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_SKIP, midtunit_video_device::PIXEL_COPY)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_SKIP, midtunit_video_device::PIXEL_COPY)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_C0_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_C0_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_SKIP)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_SKIP)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_C1_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_C1_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_SKIP, midtunit_video_device::PIXEL_COLOR)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_SKIP, midtunit_video_device::PIXEL_COLOR)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_P0P1_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_P0P1_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COPY)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COPY)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_C0C1_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_C0C1_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_COLOR)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_COLOR)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_C0P1_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_C0P1_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_COPY)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_COPY)
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_P0C1_XF(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_P0C1_XF(skip, scale) \
|
||||||
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COLOR)
|
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COLOR)
|
||||||
|
|
||||||
#define DEFINE_TEMPLATED_DMA_DRAW_GROUP(skip, scale) \
|
#define DEFINE_TEMPLATED_DMA_DRAW_GROUP(skip, scale) \
|
||||||
|
@ -9,7 +9,7 @@
|
|||||||
|
|
||||||
#define LOG_LCD (1 << 0)
|
#define LOG_LCD (1 << 0)
|
||||||
|
|
||||||
#define VERBOSE (0)
|
#define VERBOSE (0)
|
||||||
#include "logmacro.h"
|
#include "logmacro.h"
|
||||||
|
|
||||||
const char *const pc1251_state::s_def[5] =
|
const char *const pc1251_state::s_def[5] =
|
||||||
|
@ -99,68 +99,68 @@
|
|||||||
1c Zoom Y? low bits
|
1c Zoom Y? low bits
|
||||||
1e Zoom Y? high bits *
|
1e Zoom Y? high bits *
|
||||||
|
|
||||||
24 1->0 in funcube3 and staraudi
|
24 1->0 in funcube3 and staraudi
|
||||||
26 1->0 during INT0, before writing sprites
|
26 1->0 during INT0, before writing sprites
|
||||||
(probably creates a custom format sprite list at 0x0000 by processing the list at 0x3000)
|
(probably creates a custom format sprite list at 0x0000 by processing the list at 0x3000)
|
||||||
|
|
||||||
30 fedc ba98 7654 321-
|
30 fedc ba98 7654 321-
|
||||||
---- ---- ---- ---0 Disable video
|
---- ---- ---- ---0 Disable video
|
||||||
|
|
||||||
32..3f ?
|
32..3f ?
|
||||||
|
|
||||||
Global X offset values based on penbros
|
Global X offset values based on penbros
|
||||||
|
|
||||||
0x1c0 - when zoom is smallest
|
0x1c0 - when zoom is smallest
|
||||||
counts up to 0x7ff
|
counts up to 0x7ff
|
||||||
then 0x00 when finished
|
then 0x00 when finished
|
||||||
|
|
||||||
counts up to 0x089 when zooming in
|
counts up to 0x089 when zooming in
|
||||||
|
|
||||||
Zoom values (both x and y) based on penbros and others (x flip/unflip logic is reverse of y logic)
|
Zoom values (both x and y) based on penbros and others (x flip/unflip logic is reverse of y logic)
|
||||||
|
|
||||||
(unflipped gfx)
|
(unflipped gfx)
|
||||||
0x7f5 00 = smallest
|
0x7f5 00 = smallest
|
||||||
0x7ff 00 = normal
|
0x7ff 00 = normal
|
||||||
0x7ff xx = larger
|
0x7ff xx = larger
|
||||||
|
|
||||||
(flipped gfx, negative zoom factor!, used instead of flipscreen bits in some cases)
|
(flipped gfx, negative zoom factor!, used instead of flipscreen bits in some cases)
|
||||||
0x00b 00 = smallest
|
0x00b 00 = smallest
|
||||||
0x001 00 = normal
|
0x001 00 = normal
|
||||||
0x001 xx = larger
|
0x001 xx = larger
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
/***************************************************************************
|
/***************************************************************************
|
||||||
|
|
||||||
NON-BUGS
|
NON-BUGS
|
||||||
|
|
||||||
grdians : After the fire rowscroll effect in the intro there is a small artifact
|
grdians : After the fire rowscroll effect in the intro there is a small artifact
|
||||||
left scrolling at the top of the screen when the next image is displayed
|
left scrolling at the top of the screen when the next image is displayed
|
||||||
See 4:24 in https://www.youtube.com/watch?v=cvHGFEsB_cM
|
See 4:24 in https://www.youtube.com/watch?v=cvHGFEsB_cM
|
||||||
|
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
WRITE16_MEMBER(seta2_state::vregs_w)
|
WRITE16_MEMBER(seta2_state::vregs_w)
|
||||||
{
|
{
|
||||||
/* 02/04 = horizontal display start/end
|
/* 02/04 = horizontal display start/end
|
||||||
mj4simai = 0065/01E5 (0180 visible area)
|
mj4simai = 0065/01E5 (0180 visible area)
|
||||||
myangel = 005D/01D5 (0178 visible area)
|
myangel = 005D/01D5 (0178 visible area)
|
||||||
pzlbowl = 0058/01D8 (0180 visible area)
|
pzlbowl = 0058/01D8 (0180 visible area)
|
||||||
penbros = 0065/01A5 (0140 visible area)
|
penbros = 0065/01A5 (0140 visible area)
|
||||||
grdians = 0059/0188 (012f visible area)
|
grdians = 0059/0188 (012f visible area)
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||||||
06 = horizontal total?
|
06 = horizontal total?
|
||||||
mj4simai = 0204
|
mj4simai = 0204
|
||||||
myangel = 0200
|
myangel = 0200
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||||||
pzlbowl = 0204
|
pzlbowl = 0204
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||||||
penbros = 01c0
|
penbros = 01c0
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||||||
grdians = 019a
|
grdians = 019a
|
||||||
*/
|
*/
|
||||||
|
|
||||||
uint16_t olddata = m_vregs[offset];
|
uint16_t olddata = m_vregs[offset];
|
||||||
|
|
||||||
COMBINE_DATA(&m_vregs[offset]);
|
COMBINE_DATA(&m_vregs[offset]);
|
||||||
|
|
||||||
// popmessage("%04x %04x", m_vregs[0x1e/2], m_vregs[0x1c/2]);
|
// popmessage("%04x %04x", m_vregs[0x1e/2], m_vregs[0x1c/2]);
|
||||||
|
|
||||||
if (m_vregs[offset] != olddata)
|
if (m_vregs[offset] != olddata)
|
||||||
logerror("CPU #0 PC %06X: Video Reg %02X <- %04X\n", m_maincpu->pc(), offset * 2, data);
|
logerror("CPU #0 PC %06X: Video Reg %02X <- %04X\n", m_maincpu->pc(), offset * 2, data);
|
||||||
@ -233,7 +233,7 @@ WRITE16_MEMBER(seta2_state::vregs_w)
|
|||||||
m_private_spriteram[i + 3] |= 0x4000;
|
m_private_spriteram[i + 3] |= 0x4000;
|
||||||
}
|
}
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -337,7 +337,7 @@ inline void seta2_state::drawgfx_line(bitmap_ind16 &bitmap, const rectangle &cli
|
|||||||
int pen_shift = 15 - shadow;
|
int pen_shift = 15 - shadow;
|
||||||
int pen_mask = (1 << pen_shift) - 1;
|
int pen_mask = (1 << pen_shift) - 1;
|
||||||
dest[sx] = ((dest[sx] & pen_mask) | (pen << pen_shift)) & 0x7fff;
|
dest[sx] = ((dest[sx] & pen_mask) | (pen << pen_shift)) & 0x7fff;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -362,7 +362,7 @@ inline void seta2_state::get_tile(uint16_t* spriteram, int is_16x16, int x, int
|
|||||||
if (is_16x16)
|
if (is_16x16)
|
||||||
{
|
{
|
||||||
code &= ~3;
|
code &= ~3;
|
||||||
|
|
||||||
if (!flipx)
|
if (!flipx)
|
||||||
{
|
{
|
||||||
if (x & 8)
|
if (x & 8)
|
||||||
@ -419,7 +419,7 @@ void seta2_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
|
|||||||
|
|
||||||
// HACK: this inverts the zoom on all sprites, thus flipping the screen and altering positions as the origin becomes the right hand side, not left, see star audition (by default) or deer hunting when you turn on horizontal flip
|
// HACK: this inverts the zoom on all sprites, thus flipping the screen and altering positions as the origin becomes the right hand side, not left, see star audition (by default) or deer hunting when you turn on horizontal flip
|
||||||
// TODO: properly render negative zoom sprites
|
// TODO: properly render negative zoom sprites
|
||||||
if (global_xzoom & 0x400)
|
if (global_xzoom & 0x400)
|
||||||
{
|
{
|
||||||
global_xoffset -= 0x14f;
|
global_xoffset -= 0x14f;
|
||||||
}
|
}
|
||||||
@ -454,7 +454,7 @@ void seta2_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
|
|||||||
if (special)
|
if (special)
|
||||||
{
|
{
|
||||||
use_shadow = 0;
|
use_shadow = 0;
|
||||||
// which_gfx = 4 << 8;
|
// which_gfx = 4 << 8;
|
||||||
global_yoffset = -0x90;
|
global_yoffset = -0x90;
|
||||||
global_xoffset = 0x80;
|
global_xoffset = 0x80;
|
||||||
}
|
}
|
||||||
@ -590,7 +590,7 @@ void seta2_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
|
|||||||
|
|
||||||
int realfirstline = firstline;
|
int realfirstline = firstline;
|
||||||
|
|
||||||
if (firstline < cliprect.min_y) realfirstline = cliprect.min_y;
|
if (firstline < cliprect.min_y) realfirstline = cliprect.min_y;
|
||||||
if (endline > cliprect.max_y) endline = cliprect.max_y;
|
if (endline > cliprect.max_y) endline = cliprect.max_y;
|
||||||
|
|
||||||
for (int realline = realfirstline; realline <= endline; realline++)
|
for (int realline = realfirstline; realline <= endline; realline++)
|
||||||
@ -627,7 +627,7 @@ TIMER_CALLBACK_MEMBER(seta2_state::raster_timer_done)
|
|||||||
{
|
{
|
||||||
m_tmp68301->external_interrupt_1();
|
m_tmp68301->external_interrupt_1();
|
||||||
logerror("external int (vpos is %d)\n", m_screen->vpos());
|
logerror("external int (vpos is %d)\n", m_screen->vpos());
|
||||||
m_screen->update_partial(m_screen->vpos() - 1);
|
m_screen->update_partial(m_screen->vpos() - 1);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -165,7 +165,7 @@ void ssv_state::drawgfx_line(bitmap_ind16 &bitmap, const rectangle &cliprect, in
|
|||||||
{ 0x0f,0 }, // 4: eagle shot 4bpp birdie text
|
{ 0x0f,0 }, // 4: eagle shot 4bpp birdie text
|
||||||
{ 0xf0,4 }, // 5: eagle shot 4bpp Japanese text
|
{ 0xf0,4 }, // 5: eagle shot 4bpp Japanese text
|
||||||
{ 0x3f,0 }, // 6: common 6bpp case + keithlcy (logo), drifto94 (wheels) masking
|
{ 0x3f,0 }, // 6: common 6bpp case + keithlcy (logo), drifto94 (wheels) masking
|
||||||
{ 0xff,0 } // 7: common 8bpp case
|
{ 0xff,0 } // 7: common 8bpp case
|
||||||
};
|
};
|
||||||
|
|
||||||
const uint8_t gfxbppmask = BPP_MASK_TABLE[gfx & 0x07].gfx_mask;
|
const uint8_t gfxbppmask = BPP_MASK_TABLE[gfx & 0x07].gfx_mask;
|
||||||
@ -829,12 +829,12 @@ void ssv_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
|
|||||||
{
|
{
|
||||||
// "Normal" Sprite
|
// "Normal" Sprite
|
||||||
/*
|
/*
|
||||||
hot spots:
|
hot spots:
|
||||||
"warning" in hypreac2 has mode & 0x0100 and is not 16x16
|
"warning" in hypreac2 has mode & 0x0100 and is not 16x16
|
||||||
keithlcy high scores has mode & 0x0100 and y & 0x0c00 can be 0x0c00
|
keithlcy high scores has mode & 0x0100 and y & 0x0c00 can be 0x0c00
|
||||||
drifto94 "you have proved yOur".. has mode & 0x0100 and x & 0x0c00 can be 0x0c00
|
drifto94 "you have proved yOur".. has mode & 0x0100 and x & 0x0c00 can be 0x0c00
|
||||||
ultrax (begin of lev1): 100010: 6b60 4280 0016 00a0
|
ultrax (begin of lev1): 100010: 6b60 4280 0016 00a0
|
||||||
121400: 51a0 0042 6800 0c00 needs to be a normal sprite
|
121400: 51a0 0042 6800 0c00 needs to be a normal sprite
|
||||||
*/
|
*/
|
||||||
|
|
||||||
int code = spritelist_local[0]; // code high bits
|
int code = spritelist_local[0]; // code high bits
|
||||||
|
Loading…
Reference in New Issue
Block a user