Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-05-05 13:54:42 +03:00
Code Issues Actions 4 Packages Projects Releases Wiki Activity

Carnival King now working

Browse Source
This commit is contained in:
Ted Green 2016-01-28 09:01:32 -07:00
parent 1319453a84
commit 664196e047
3 changed files with 36 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mame/drivers/iteagle.cpp
View File

@ -179,7 +179,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( gtfore01, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x01000401, 0x0b0b0b)
MCFG_ITEAGLE_FPGA_INIT(0x00000401, 0x0b0b0b)
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0401, 0x7)
MACHINE_CONFIG_END
@ -187,7 +187,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( gtfore02, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x01000402, 0x020201)
MCFG_DEVICE_MODIFY(":pci:0a.0")
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0402, 0x7)
MACHINE_CONFIG_END
@ -215,28 +215,28 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( gtfore06, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x01000406, 0x0c0b0d)
MCFG_DEVICE_MODIFY(":pci:0a.0")
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0406, 0x9);
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( carnking, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x01000603, 0x0c0b0d)
MCFG_ITEAGLE_FPGA_INIT(0x01000a01, 0x0e0a0a)
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x9)
MCFG_ITEAGLE_EEPROM_INIT(0x0a01, 0x9)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( bbhsc, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x01000600, 0x0c0a0a)
MCFG_ITEAGLE_FPGA_INIT(0x02000600, 0x0c0a0a)
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0600, 0x9)
MCFG_ITEAGLE_EEPROM_INIT(0x0000, 0x7)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( bbhcotw, iteagle )
MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
MCFG_ITEAGLE_FPGA_INIT(0x02000603, 0x080704)
MCFG_DEVICE_MODIFY(":pci:0a.0")
MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
MCFG_ITEAGLE_EEPROM_INIT(0x0603, 0x9)
MACHINE_CONFIG_END
@ -331,7 +331,7 @@ static INPUT_PORTS_START( virtpool )
INPUT_PORTS_END
static INPUT_PORTS_START( bbhcotw )
static INPUT_PORTS_START( bbh )
PORT_INCLUDE( iteagle )
PORT_MODIFY("IN1")
@ -557,7 +557,7 @@ ROM_END
GAME( 2000, iteagle, 0, iteagle, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", MACHINE_IS_BIOS_ROOT )
GAME( 1998, virtpool, iteagle, virtpool, virtpool, driver_device, 0, ROT0, "Incredible Technologies", "Virtual Pool", MACHINE_NOT_WORKING ) // random lockups on loading screens
GAME( 2002, carnking, iteagle, carnking, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", MACHINE_NOT_WORKING )
GAME( 2002, carnking, iteagle, carnking, bbh, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", 0 )
GAME( 2000, gtfore01, iteagle, gtfore01, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! (v1.00.25)", 0 )
GAME( 2001, gtfore02, iteagle, gtfore02, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.06)", 0 )
GAME( 2002, gtfore03, iteagle, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.10)", 0 )
@ -569,5 +569,5 @@ GAME( 2004, gtfore05a, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "I
GAME( 2004, gtfore05b, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.00)", 0 )
GAME( 2004, gtfore05c, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", 0 )
GAME( 2005, gtfore06, iteagle, gtfore06, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", 0 )
GAME( 2002, bbhsc, iteagle, bbhsc, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", MACHINE_NOT_WORKING ) // doesn't boot
GAME( 2006, bbhcotw, iteagle, bbhcotw, bbhcotw, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", MACHINE_NOT_WORKING ) // random lockups
GAME( 2002, bbhsc, iteagle, bbhsc, bbh, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", MACHINE_NOT_WORKING ) // doesn't boot
GAME( 2006, bbhcotw, iteagle, bbhcotw, bbh, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", MACHINE_NOT_WORKING ) // random lockups

43
src/mame/machine/iteagle_fpga.cpp
View File

@ -4,6 +4,7 @@
#include "coreutil.h"
#define LOG_FPGA (0)
#define LOG_SERIAL (0)
#define LOG_RTC (0)
#define LOG_RAM (0)
#define LOG_EEPROM (0)
@ -80,14 +81,14 @@ void iteagle_fpga_device::device_reset()
m_serial_str.clear();
m_serial_idx = 0;
m_serial_data = false;
memset(m_serial_com0, 0, sizeof(m_serial_com0));
memset(m_serial_com1, 0, sizeof(m_serial_com1));
memset(m_serial_com2, 0, sizeof(m_serial_com2));
memset(m_serial_com3, 0, sizeof(m_serial_com3));
memset(m_serial_com4, 0, sizeof(m_serial_com4));
m_serial_com0[0] = 0x2c;
m_serial_com1[0] = 0x2c;
m_serial_com2[0] = 0x2c;
m_serial_com3[0] = 0x2c;
m_serial_com4[0] = 0x2c;
}
void iteagle_fpga_device::update_sequence(UINT32 data)
@ -130,12 +131,10 @@ void iteagle_fpga_device::update_sequence_eg1(UINT32 data)
val1 = ((m_seq & 0x2)<<6) | ((m_seq & 0x4)<<4) | ((m_seq & 0x8)<<2) | ((m_seq & 0x10)<<0)
| ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4) | ((m_seq & 0x80)>>6) | ((m_seq & 0x100)>>8);
m_seq = (m_seq>>8) | ((feed&0xff)<<16);
//m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1)&0xFF);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
} else if (data & 0x2) {
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
//m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
} else {
@ -197,16 +196,16 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
break;
case 0x0c/4: // 1d = modem byte
result = (result & 0xFFFF0000) | ((m_serial_com2[m_serial_idx]&0xff)<<8) | (m_serial_com1[m_serial_idx]&0xff);
result = (result & 0xFFFF0000) | ((m_serial_com1[m_serial_idx]&0xff)<<8) | (m_serial_com0[m_serial_idx]&0xff);
if (ACCESSING_BITS_0_15) {
m_serial_data = false;
m_serial_idx = 0;
}
if (LOG_FPGA)
if (0 && LOG_FPGA)
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
break;
case 0x1c/4: // 1d = modem byte
result = (result & 0xFFFF0000) | ((m_serial_com4[m_serial_idx]&0xff)<<8) | (m_serial_com3[m_serial_idx]&0xff);
result = (result & 0xFFFF0000) | ((m_serial_com3[m_serial_idx]&0xff)<<8) | (m_serial_com2[m_serial_idx]&0xff);
if (ACCESSING_BITS_0_15) {
m_serial_data = false;
m_serial_idx = 0;
@ -233,8 +232,8 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
if ((m_version & 0xff00) == 0x0200)
update_sequence_eg1(data & 0xff);
else
// ATMEL Chip access. Returns version id's when bit 7 is set.
update_sequence(data & 0xff);
// ATMEL Chip access. Returns version id's when bit 7 is set.
update_sequence(data & 0xff);
if (0 && LOG_FPGA)
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
}
@ -242,7 +241,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
if (ACCESSING_BITS_24_31 && (data & 0x01000000)) {
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
// Not sure what value to use here, needed for lightgun
m_timer->adjust(attotime::from_hz(25));
m_timer->adjust(attotime::from_hz(59));
if (LOG_FPGA)
logerror("%s:fpga_w offset %04X = %08X & %08X Clearing interrupt(%i)\n", machine().describe_context(), offset*4, data, mem_mask, m_irq_num);
} else {
@ -269,7 +268,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
if (!m_serial_data) {
m_serial_idx = data&0xf;
} else {
m_serial_com1[m_serial_idx] = data&0xff;
m_serial_com0[m_serial_idx] = data&0xff;
m_serial_idx = 0;
}
m_serial_data = !m_serial_data;
@ -278,29 +277,31 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
if (!m_serial_data) {
m_serial_idx = (data&0x0f00)>>8;
} else {
m_serial_com2[m_serial_idx] = (data&0xff00)>>8;
m_serial_com1[m_serial_idx] = (data&0xff00)>>8;
}
m_serial_data = !m_serial_data;
}
if (ACCESSING_BITS_16_23) {
if (m_serial_str.size()==0)
m_serial_str = "com1: ";
m_serial_str = "com0: ";
m_serial_str += (data>>16)&0xff;
if (((data>>16)&0xff)==0xd) {
if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str());
osd_printf_debug("%s\n", m_serial_str.c_str());
m_serial_str.clear();
}
}
if (ACCESSING_BITS_24_31) {
if (m_serial_str.size()==0)
m_serial_str = "com2: ";
m_serial_str = "com1: ";
m_serial_str += (data>>24)&0xff;
if (1 || ((data>>24)&0xff)==0xd) {
if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str());
osd_printf_debug("%s\n", m_serial_str.c_str());
m_serial_str.clear();
}
}
if (LOG_FPGA)
if (0 && LOG_FPGA)
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
break;
case 0x1c/4:
@ -308,7 +309,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
if (!m_serial_data) {
m_serial_idx = data&0xf;
} else {
m_serial_com3[m_serial_idx] = data&0xff;
m_serial_com2[m_serial_idx] = data&0xff;
m_serial_idx = 0;
}
m_serial_data = !m_serial_data;
@ -317,24 +318,26 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
if (!m_serial_data) {
m_serial_idx = (data&0x0f00)>>8;
} else {
m_serial_com4[m_serial_idx] = (data&0xff00)>>8;
m_serial_com3[m_serial_idx] = (data&0xff00)>>8;
}
m_serial_data = !m_serial_data;
}
if (ACCESSING_BITS_16_23) {
if (m_serial_str.size()==0)
m_serial_str = "com3: ";
m_serial_str = "com2: ";
m_serial_str += (data>>16)&0xff;
if (1 || ((data>>16)&0xff)==0xd) {
if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str());
osd_printf_debug("%s\n", m_serial_str.c_str());
m_serial_str.clear();
}
}
if (ACCESSING_BITS_24_31) {
if (m_serial_str.size()==0)
m_serial_str = "com4: ";
m_serial_str = "com3: ";
m_serial_str += (data>>24)&0xff;
if (((data>>24)&0xff)==0xd) {
if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str());
osd_printf_debug("%s\n", m_serial_str.c_str());
m_serial_str.clear();
}
@ -649,7 +652,7 @@ void iteagle_ide_device::device_reset()
{
pci_device::device_reset();
memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3.
m_ctrl_regs[0x10/4] = 0x00070000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3. Bit 0 might be lan chip present.
memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
m_rtc_regs[0xa] = 0x20; // 32.768 MHz
m_rtc_regs[0xb] = 0x02; // 24-hour format

2
src/mame/machine/iteagle_fpga.h
View File

@ -63,10 +63,10 @@ private:
std::string m_serial_str;
UINT8 m_serial_idx;
bool m_serial_data;
UINT8 m_serial_com0[0x10];
UINT8 m_serial_com1[0x10];
UINT8 m_serial_com2[0x10];
UINT8 m_serial_com3[0x10];
UINT8 m_serial_com4[0x10];
UINT32 m_version;
UINT32 m_seq_init;