mirror of
https://github.com/holub/mame
synced 2025-04-24 01:11:11 +03:00
mb86235: some more progress (nw)
This commit is contained in:
Ville Linde
parent
e6155387a0
commit
667c8ea68e
@ -166,6 +166,7 @@ void mb86235_device::device_start()
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state_add(MB86235_MB6, "MB6", m_core->mb[6]).formatstr("%08X");
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state_add(MB86235_MB7, "MB7", m_core->mb[7]).formatstr("%08X");
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state_add(STATE_GENPC, "GENPC", m_core->pc ).noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_core->pc).noshow();
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m_icountptr = &m_core->icount;
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@ -261,7 +262,17 @@ bool mb86235_device::is_fifoin_full()
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uint64_t mb86235_device::fifoout0_r()
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{
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#if ENABLE_DRC
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fatalerror("fifoout0_r");
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if (m_core->fifoout0.num == 0)
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{
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fatalerror("fifoout0_r: reading from empty fifo");
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}
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uint64_t data = m_core->fifoout0.data[m_core->fifoout0.rpos];
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m_core->fifoout0.rpos++;
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m_core->fifoout0.rpos &= FIFOOUT0_SIZE - 1;
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m_core->fifoout0.num--;
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return data;
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#else
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return 0;
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#endif
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@ -45,7 +45,6 @@ public:
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void unimplemented_op();
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void unimplemented_alu();
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void unimplemented_control();
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void unimplemented_xfer1();
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void unimplemented_double_xfer1();
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void unimplemented_double_xfer2();
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void pcs_overflow();
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@ -115,12 +115,6 @@ static void cfunc_unimplemented_control(void *param)
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cpu->unimplemented_control();
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}
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static void cfunc_unimplemented_xfer1(void *param)
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{
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mb86235_device *cpu = (mb86235_device *)param;
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cpu->unimplemented_xfer1();
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}
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static void cfunc_unimplemented_double_xfer1(void *param)
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{
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mb86235_device *cpu = (mb86235_device *)param;
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@ -168,13 +162,6 @@ void mb86235_device::unimplemented_control()
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fatalerror("MB86235: PC=%08X: Unimplemented control %02X\n", m_core->pc, cop);
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}
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void mb86235_device::unimplemented_xfer1()
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{
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uint64_t op = m_core->arg64;
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printf("MB86235: PC=%08X: Unimplemented xfer1 %04X%08X\n", m_core->pc, (uint32_t)(op >> 32), (uint32_t)(op));
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fatalerror("MB86235: PC=%08X: Unimplemented xfer1 %04X%08X\n", m_core->pc, (uint32_t)(op >> 32), (uint32_t)(op));
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}
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void mb86235_device::unimplemented_double_xfer1()
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{
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uint64_t op = m_core->arg64;
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@ -452,6 +439,7 @@ void mb86235_device::static_generate_fifo()
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block->end();
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// read fifo in
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// I0 = return value
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block = m_drcuml->begin_block(32);
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alloc_handle(m_drcuml.get(), &m_read_fifo_in, "read_fifo_in");
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UML_HANDLE(block, *m_read_fifo_in);
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@ -466,10 +454,16 @@ void mb86235_device::static_generate_fifo()
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block->end();
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// write fifo out0
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// I0 = input value
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block = m_drcuml->begin_block(32);
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alloc_handle(m_drcuml.get(), &m_write_fifo_out0, "write_fifo_out0");
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UML_HANDLE(block, *m_write_fifo_out0);
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// TODO
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UML_MOV(block, I1, FIFOOUT0_WPOS);
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UML_STORE(block, m_core->fifoout0.data, I1, I0, SIZE_QWORD, SCALE_x8);
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UML_ADD(block, I1, I1, 1);
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UML_AND(block, I1, I1, FIFOOUT0_SIZE - 1);
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UML_MOV(block, FIFOOUT0_WPOS, I1);
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UML_ADD(block, FIFOOUT0_NUM, FIFOOUT0_NUM, 1);
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UML_RET(block);
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block->end();
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@ -637,6 +631,9 @@ void mb86235_device::generate_ea(drcuml_block *block, compiler_state *compiler,
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switch (md)
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{
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case 0x0: // @ARx
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UML_MOV(block, I0, AR(arx));
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break;
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case 0x1: // @ARx++
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UML_MOV(block, I0, AR(arx));
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UML_ADD(block, AR(arx), AR(arx), 1);
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@ -670,6 +667,11 @@ void mb86235_device::generate_reg_read(drcuml_block *block, compiler_state *comp
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UML_MOV(block, dst, AR(reg & 7));
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break;
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case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
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// AB0-7
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UML_MOV(block, dst, AB(reg & 7));
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break;
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case 0x30: // PR
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UML_LOAD(block, dst, m_core->pr, PRP, SIZE_DWORD, SCALE_x4);
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break;
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@ -731,6 +733,11 @@ void mb86235_device::generate_reg_write(drcuml_block *block, compiler_state *com
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UML_STORE(block, m_core->pr, PWP, src, SIZE_DWORD, SCALE_x4);
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break;
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case 0x32: // FO0
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UML_MOV(block, I0, src);
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UML_CALLH(block, *m_write_fifo_out0);
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break;
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case 0x34: // PDR
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UML_MOV(block, mem(&m_core->pdr), src);
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break;
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@ -845,13 +852,27 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
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// insert FIFO OUT0 check if needed
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if (fifoout0_check)
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{
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fatalerror("generate_opcode: fifoout0_check");
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code_label not_full = compiler->labelnum++;
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UML_CMP(block, FIFOOUT0_NUM, FIFOOUT0_SIZE - 1);
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UML_JMPc(block, COND_L, not_full);
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UML_MOV(block, mem(&m_core->icount), 0);
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UML_EXH(block, *m_out_of_cycles, desc->pc);
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UML_LABEL(block, not_full);
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}
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// insert FIFO OUT1 check if needed
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if (fifoout1_check)
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{
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fatalerror("generate_opcode: fifoout1_check");
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code_label not_full = compiler->labelnum++;
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UML_CMP(block, FIFOOUT1_NUM, FIFOOUT1_SIZE - 1);
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UML_JMPc(block, COND_L, not_full);
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UML_MOV(block, mem(&m_core->icount), 0);
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UML_EXH(block, *m_out_of_cycles, desc->pc);
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UML_LABEL(block, not_full);
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}
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@ -1256,6 +1277,20 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
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UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
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break;
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case 0x12: // SUB
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generate_alumul_input(block, compiler, desc, i2, I1, false, false);
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UML_SUB(block, I0, I1, get_alu1_input(i1));
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if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
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if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, FLAGS_AN);
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UML_CMP(block, I0, 0xff800000);
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UML_MOVc(block, COND_L, I0, 0xff800000);
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if (AV_CALC_REQUIRED) UML_MOVc(block, COND_L, FLAGS_AV, 1);
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UML_CMP(block, I0, 0x007fffff);
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UML_MOVc(block, COND_G, I0, 0x007fffff);
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if (AV_CALC_REQUIRED) UML_MOVc(block, COND_G, FLAGS_AV, 1);
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UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
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break;
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case 0x14: // CMP
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generate_alumul_input(block, compiler, desc, i2, I1, false, false);
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UML_SUB(block, I0, I1, get_alu1_input(i1));
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@ -1409,6 +1444,15 @@ void mb86235_device::generate_branch_target(drcuml_block *block, compiler_state
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UML_MOV(block, I0, AR(reg));
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break;
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}
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case 0x4: // Axx
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{
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int reg = (ef2 >> 6) & 7;
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if (ef2 & 0x400)
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UML_MOV(block, I0, AB(reg));
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else
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UML_MOV(block, I0, AA(reg));
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break;
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}
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default:
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fatalerror("generate_branch_target: type %02X at %08X", type, desc->pc);
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break;
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@ -1590,9 +1634,67 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
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void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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{
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UML_MOV(block, mem(&m_core->pc), desc->pc);
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UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]);
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UML_CALLC(block, cfunc_unimplemented_xfer1, this);
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uint64_t opcode = desc->opptr.q[0];
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int dr = (opcode >> 12) & 0x7f;
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int sr = (opcode >> 19) & 0x7f;
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int md = opcode & 0xf;
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int ary = (opcode >> 4) & 7;
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int disp5 = (opcode >> 7) & 0x1f;
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int trm = (opcode >> 26) & 1;
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// int dir = (opcode >> 25) & 1;
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if (trm == 0)
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{
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if (sr == 0x58)
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{
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// MOV1 #imm12, DR
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generate_reg_write(block, compiler, desc, dr & 0x3f, uml::parameter(opcode & 0xfff));
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}
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else
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{
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if ((sr & 0x40) == 0)
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{
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generate_reg_read(block, compiler, desc, sr & 0x3f, I1);
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}
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else
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{
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generate_ea(block, compiler, desc, md, sr & 7, ary, disp5);
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if (sr & 0x20) // RAM-B
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{
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UML_SHL(block, I0, I0, 2);
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UML_READ(block, I1, I0, SIZE_DWORD, SPACE_IO);
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}
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else // RAM-A
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{
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UML_CALLH(block, *m_read_abus);
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}
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}
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if ((dr & 0x40) == 0)
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{
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generate_reg_write(block, compiler, desc, dr & 0x3f, I1);
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}
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else
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{
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generate_ea(block, compiler, desc, md, dr & 7, ary, disp5);
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if (dr & 0x20) // RAM-B
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{
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UML_SHL(block, I0, I0, 2);
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UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_IO);
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}
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else // RAM-A
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{
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UML_CALLH(block, *m_write_abus);
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}
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}
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}
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}
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else
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{
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// external transfer
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fatalerror("generate_xfer1 MOV1 at %08X (%08X%08X)", desc->pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
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}
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}
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void mb86235_device::generate_double_xfer1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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@ -646,12 +646,61 @@ void mb86235_frontend::describe_ea(opcode_desc &desc, int md, int arx, int ary,
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void mb86235_frontend::describe_xfer1(opcode_desc &desc)
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{
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uint64_t opcode = desc.opptr.q[0];
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fatalerror("mb86235_frontend: describe_xfer1 at %08X (%08X%08X)", desc.pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
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int dr = (opcode >> 12) & 0x7f;
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int sr = (opcode >> 19) & 0x7f;
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int md = opcode & 0xf;
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int ary = (opcode >> 4) & 7;
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int disp5 = (opcode >> 7) & 0x1f;
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int trm = (opcode >> 26) & 1;
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int dir = (opcode >> 25) & 1;
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if (trm == 0)
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{
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if ((sr & 0x40) == 0)
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{
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describe_reg_read(desc, sr & 0x3f);
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}
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else if (sr == 0x58)
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{
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// MOV1 #imm12, DR
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}
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else
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{
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describe_ea(desc, md, sr & 7, ary, disp5);
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desc.flags |= OPFLAG_READS_MEMORY;
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}
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if ((dr & 0x40) == 0)
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{
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describe_reg_write(desc, dr & 0x3f);
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}
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else
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{
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describe_ea(desc, md, dr & 7, ary, disp5);
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desc.flags |= OPFLAG_WRITES_MEMORY;
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}
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}
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else
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{
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// external transfer
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if (dir == 0)
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{
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describe_reg_read(desc, dr & 0x3f);
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desc.flags |= OPFLAG_WRITES_MEMORY;
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}
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else
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{
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describe_reg_write(desc, dr & 0x3f);
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desc.flags |= OPFLAG_READS_MEMORY;
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}
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}
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}
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void mb86235_frontend::describe_double_xfer1(opcode_desc &desc)
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{
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uint64_t opcode = desc.opptr.q[0];
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fatalerror("mb86235_frontend: describe_double_xfer1 at %08X (%08X%08X)", desc.pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
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}
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@ -733,7 +782,7 @@ void mb86235_frontend::describe_xfer3(opcode_desc &desc)
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int ary = (opcode >> 4) & 7;
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int md = opcode & 0xf;
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switch (dr >> 4)
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switch (dr >> 5)
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{
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case 0:
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case 1: // reg
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@ -831,10 +831,18 @@ WRITE32_MEMBER(model2_state::copro_fifo_w)
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else if (m_dsp_type == DSP_TYPE_TGPX4)
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{
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if (m_tgpx4->is_fifoin_full())
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printf("trying to push to full fifo!\n");
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// printf("push %08X at %08X\n", data, space.device().safe_pc());
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m_tgpx4->fifoin_w(data);
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{
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/* Writing to full FIFO causes the i960 to enter wait state */
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downcast<i960_cpu_device &>(space.device()).i960_stall();
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/* spin the main cpu and let the TGP catch up */
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space.device().execute().spin_until_time(attotime::from_usec(100));
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printf("write stalled\n");
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}
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else
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{
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// printf("push %08X at %08X\n", data, space.device().safe_pc());
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m_tgpx4->fifoin_w(data);
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}
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}
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}
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}
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