From 6710f455f569673880c9b2bef16bc2d8be7aca05 Mon Sep 17 00:00:00 2001 From: hap Date: Thu, 30 May 2019 17:32:51 +0200 Subject: [PATCH] New working software list additions ----------------------------------- ibm5170: The ChessMachine (v3.1, The King v2.20) [hap, fhub] --- hash/ibm5170.xml | 38 +++++++++++++++++++++++++--------- src/devices/bus/isa/chessm.cpp | 8 ++++++- 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/hash/ibm5170.xml b/hash/ibm5170.xml index a514cd7c15a..29bd4cdcfdf 100644 --- a/hash/ibm5170.xml +++ b/hash/ibm5170.xml @@ -8544,11 +8544,26 @@ + + + The ChessMachine (v3.1, The King v2.20) + 1993 + Tasc + + + + + + + + + + - The ChessMachine (Installer v3.0) + + The ChessMachine (v2.3, Gideon v2.1) 1991 Tasc - @@ -8571,12 +8586,13 @@ - + - The ChessMachine (Installer v2.2) + + + The ChessMachine (v2.1, Gideon v2.1) 1991 Tasc - @@ -9611,8 +9627,9 @@ - The Final ChessCard (Installer v2.0/Program v1.9) - 1989 + + The Final ChessCard (v1.9) + 1990 Tasc @@ -9622,15 +9639,16 @@ - + - The Final ChessCard (Program v1.5) + + The Final ChessCard (v1.5) 1989 Tasc - + diff --git a/src/devices/bus/isa/chessm.cpp b/src/devices/bus/isa/chessm.cpp index 83033be95fe..9ed0f37eaf3 100644 --- a/src/devices/bus/isa/chessm.cpp +++ b/src/devices/bus/isa/chessm.cpp @@ -12,6 +12,12 @@ VLSI VY86C010-12QC (ARM2), seen with 30MHz XTAL, but XTAL label usually scratche It looks like Gideon 2.1 only sees up to 512KB RAM, The King up to 2MB RAM. Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare or prototype. +3 models exist: SR, DR, EC. SR and DR are ISA cards, EC is an external module (serial port). +It was also released for the Amiga. + +TODO: +- add model DR (missing bootstrap ROM dump?) + */ #include "emu.h" @@ -177,5 +183,5 @@ WRITE8_MEMBER(isa8_chessm_device::chessm_w) void isa8_chessm_device::chessm_mem(address_map &map) { - map(0x00380000, 0x00380000).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write)); + map(0x00380000, 0x00380000).mirror(0x00000008).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write)); }