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excellent/dblcrown.cpp: misc cleanups
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angelosa
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@ -1,43 +1,37 @@
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// license:BSD-3-Clause
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// copyright-holders: Angelo Salese, Roberto Fresca
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/***************************************************************************
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/**************************************************************************************************
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Double Crown (c) 1997 Cadence Technology / Dyna
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Double Crown (c) 1997 Cadence Technology / Dyna
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Driver by Angelo Salese
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Additional work by Roberto Fresca.
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TODO:
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- Bogus "Hole" in main screen display;
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- Is the background pen really black?
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- Lots of unmapped I/Os (game doesn't make much use of the HW);
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- video / irq timings;
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TODO:
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- Bogus "Hole" in main screen display;
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- Is the background pen really black?
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- Lots of unmapped I/Os (game doesn't make much use of the HW);
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- video / irq timings;
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Notes:
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- at POST the SW tries to write to the palette RAM in a banking fashion. HW left-over?
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- there are various $0030-$0033 ROM checks across the SW, changing these values to non-zero
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effectively changes game functionality (cfr. matrix mode at POST), ROM overlay?
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Notes:
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- at POST the SW tries to write to the palette RAM in a banking fashion.
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I think it's just an HW left-over.
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- there are various bogus checks to ROM region throughout the whole SW
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(0x0030-0x0033? O.o), trying to change the values of these ones changes
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the functionality of the game, almost like that the DSWs are tied to
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these ...
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===================================================================================================
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============================================================================
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Excellent System
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boardlabel: ES-9411B
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Excellent System
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boardlabel: ES-9411B
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28.6363 xtal
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ES-9409 QFP is 208 pins.. for graphics only?
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Z0840006PSC Zilog z80, is rated 6.17 MHz
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OKI M82C55A-2
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65764H-5 .. 64kbit ram CMOS
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2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8)
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4 * dipsw 8pos
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YMZ284-D (ay8910, but without i/o ports)
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MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog
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and for nvram functions.
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28.6363 xtal
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ES-9409 QFP is 208 pins.. for graphics only?
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Z0840006PSC Zilog z80, is rated 6.17 MHz
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OKI M82C55A-2
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65764H-5 .. 64kbit ram CMOS
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2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8)
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4 * dipsw 8pos
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YMZ284-D (ay8910, but without i/o ports)
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MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog
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and for nvram functions.
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***************************************************************************/
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**************************************************************************************************/
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#define MAIN_CLOCK XTAL(28'636'363)
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@ -60,6 +54,7 @@
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namespace {
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// TODO: remove me, crashes in screen_update at first RAM-based char drawn ...
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#define DEBUG_VRAM
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class dblcrown_state : public driver_device
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@ -96,18 +91,17 @@ private:
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void vram_w(offs_t offset, uint8_t data);
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uint8_t vram_bank_r(offs_t offset);
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void vram_bank_w(offs_t offset, uint8_t data);
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void mux_w(uint8_t data);
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uint8_t in_mux_r();
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uint8_t in_mux_type_r();
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void key_select_w(uint8_t data);
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uint8_t key_matrix_r();
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uint8_t key_pending_r();
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void output_w(uint8_t data);
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void lamps_w(uint8_t data);
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void watchdog_w(uint8_t data);
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TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_irq_scanline);
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void dblcrown_palette(palette_device &palette) const;
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void dblcrown_io(address_map &map);
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void dblcrown_map(address_map &map);
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void main_map(address_map &map);
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void main_io(address_map &map);
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// devices
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required_device<cpu_device> m_maincpu;
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@ -122,7 +116,7 @@ private:
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std::unique_ptr<uint8_t[]> m_pal_ram;
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std::unique_ptr<uint8_t[]> m_vram;
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uint8_t m_vram_bank[2]{};
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uint8_t m_mux_data = 0;
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uint8_t m_key_select = 0;
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};
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void dblcrown_state::video_start()
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@ -161,7 +155,7 @@ uint32_t dblcrown_state::screen_update( screen_device &screen, bitmap_ind16 &bit
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{
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for (x = 0; x < 64; x++)
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{
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uint16_t tile = ((m_vram[count]) | (m_vram[count + 1] << 8)) & 0xfff;
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uint16_t tile = ((m_vram[count]) | (m_vram[count + 1] << 8)) & 0x7ff;
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uint8_t col = (m_vram[count + 1] >> 4); // ok?
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gfx->transpen(bitmap, cliprect, tile, col, 0, 0, x * 8, y * 8, 0);
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@ -252,28 +246,28 @@ void dblcrown_state::vram_bank_w(offs_t offset, uint8_t data)
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m_vram_bank[offset] = data & 0xf;
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if(data & 0xf0)
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printf("vram bank = %02x\n",data);
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logerror("Upper vram bank write = %02x\n",data);
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}
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void dblcrown_state::mux_w(uint8_t data)
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void dblcrown_state::key_select_w(uint8_t data)
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{
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m_mux_data = data;
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m_key_select = data;
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}
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uint8_t dblcrown_state::in_mux_r()
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uint8_t dblcrown_state::key_matrix_r()
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{
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uint8_t res = 0;
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for(int i = 0; i < 4; i++)
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{
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if(m_mux_data & 1 << i)
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if(m_key_select & 1 << i)
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res |= m_inputs[i]->read();
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}
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return res;
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}
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uint8_t dblcrown_state::in_mux_type_r()
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uint8_t dblcrown_state::key_pending_r()
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{
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uint8_t res = 0xff;
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@ -286,47 +280,42 @@ uint8_t dblcrown_state::in_mux_type_r()
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return res;
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}
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/* bits
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* 7654 3210
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* ---- -x-- unknown (active after deal)
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* ---- x--- Payout counter pulse
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* ---x ---- Coin In counter pulse
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* -x-- ---- unknown (active after deal)
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* x-x- --xx unknown
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*/
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void dblcrown_state::output_w(uint8_t data)
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{
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/* bits
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7654 3210
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---- -x-- unknown (active after deal)
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---- x--- Payout counter pulse
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---x ---- Coin In counter pulse
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-x-- ---- unknown (active after deal)
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x-x- --xx unknown
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*/
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machine().bookkeeping().coin_counter_w(0, data & 0x10); /* Coin In counter pulse */
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machine().bookkeeping().coin_counter_w(1 ,data & 0x08); /* Payout counter pulse */
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// popmessage("out: %02x", data);
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machine().bookkeeping().coin_counter_w(0, BIT(data, 4)); /* Coin In counter pulse */
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// TODO: should be hopper motor_w
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machine().bookkeeping().coin_counter_w(1, BIT(data, 3)); /* Payout counter pulse */
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}
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/* bits
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* 7654 3210
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* ---- ---x Deal
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* ---- --x- Bet
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* ---- -x-- Cancel
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* ---- x--- Hold 5
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* ---x ---- Hold 4
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* --x- ---- Hold 3
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* -x-- ---- Hold 2
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* x--- ---- Hold 1
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*/
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void dblcrown_state::lamps_w(uint8_t data)
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{
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/* bits
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7654 3210
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---- ---x Deal
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---- --x- Bet
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---- -x-- Cancel
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---- x--- Hold 5
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---x ---- Hold 4
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--x- ---- Hold 3
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-x-- ---- Hold 2
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x--- ---- Hold 1
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*/
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for (int n = 0; n < 8; n++)
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m_lamps[n] = BIT(data, n);
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}
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void dblcrown_state::watchdog_w(uint8_t data)
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/*
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Always 0x01...
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*/
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{
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if (data & 0x01) /* check for refresh value (0x01) */
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// check for refresh value (0x01)
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if (data & 0x01)
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{
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m_watchdog->watchdog_reset();
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}
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@ -337,7 +326,7 @@ void dblcrown_state::watchdog_w(uint8_t data)
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}
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void dblcrown_state::dblcrown_map(address_map &map)
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void dblcrown_state::main_map(address_map &map)
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{
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map.unmap_value_high();
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map(0x0000, 0x7fff).rom();
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@ -353,7 +342,7 @@ void dblcrown_state::dblcrown_map(address_map &map)
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}
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void dblcrown_state::dblcrown_io(address_map &map)
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void dblcrown_state::main_io(address_map &map)
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{
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map.global_mask(0xff);
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map.unmap_value_high();
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@ -361,8 +350,8 @@ void dblcrown_state::dblcrown_io(address_map &map)
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map(0x01, 0x01).portr("DSWB");
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map(0x02, 0x02).portr("DSWC");
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map(0x03, 0x03).portr("DSWD");
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map(0x04, 0x04).r(FUNC(dblcrown_state::in_mux_r));
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map(0x05, 0x05).r(FUNC(dblcrown_state::in_mux_type_r));
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map(0x04, 0x04).r(FUNC(dblcrown_state::key_matrix_r));
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map(0x05, 0x05).r(FUNC(dblcrown_state::key_pending_r));
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map(0x10, 0x13).rw("ppi", FUNC(i8255_device::read), FUNC(i8255_device::write));
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map(0x20, 0x21).w("ymz", FUNC(ymz284_device::address_data_w));
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map(0x30, 0x30).w(FUNC(dblcrown_state::watchdog_w));
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@ -539,10 +528,6 @@ void dblcrown_state::machine_reset()
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}
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void dblcrown_state::dblcrown_palette(palette_device &palette) const
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{
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}
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TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_state::dblcrown_irq_scanline)
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{
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int scanline = param;
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@ -590,8 +575,8 @@ void dblcrown_state::dblcrown(machine_config &config)
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{
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/* basic machine hardware */
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Z80(config, m_maincpu, CPU_CLOCK);
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m_maincpu->set_addrmap(AS_PROGRAM, &dblcrown_state::dblcrown_map);
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m_maincpu->set_addrmap(AS_IO, &dblcrown_state::dblcrown_io);
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m_maincpu->set_addrmap(AS_PROGRAM, &dblcrown_state::main_map);
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m_maincpu->set_addrmap(AS_IO, &dblcrown_state::main_io);
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TIMER(config, "scantimer").configure_scanline(FUNC(dblcrown_state::dblcrown_irq_scanline), "screen", 0, 1);
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WATCHDOG_TIMER(config, m_watchdog).set_time(attotime::from_msec(1000)); /* 1000 ms. (minimal of MAX693A watchdog long timeout period with internal oscillator) */
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@ -607,14 +592,14 @@ void dblcrown_state::dblcrown(machine_config &config)
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GFXDECODE(config, m_gfxdecode, m_palette, gfx_dblcrown);
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PALETTE(config, m_palette, FUNC(dblcrown_state::dblcrown_palette), 0x100);
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PALETTE(config, m_palette).set_entries(0x100);
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NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
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i8255_device &ppi(I8255(config, "ppi"));
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ppi.out_pa_callback().set(FUNC(dblcrown_state::lamps_w));
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ppi.out_pb_callback().set(FUNC(dblcrown_state::bank_w));
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ppi.out_pc_callback().set(FUNC(dblcrown_state::mux_w));
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ppi.out_pc_callback().set(FUNC(dblcrown_state::key_select_w));
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/* sound hardware */
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SPEAKER(config, "mono").front_center();
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@ -647,5 +632,4 @@ ROM_END
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} // anonymous namespace
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/* YEAR NAME PARENT MACHINE INPUT CLASS INIT ROT COMPANY FULLNAME FLAGS LAYOUT */
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GAMEL( 1997, dblcrown, 0, dblcrown, dblcrown, dblcrown_state, empty_init, ROT0, "Cadence Technology", "Double Crown (v1.0.3)", MACHINE_IMPERFECT_GRAPHICS, layout_dblcrown ) // 1997 DYNA copyright in tile GFX
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@ -9,6 +9,9 @@
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Preliminary driver by Angelo Salese
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Improvements by Ryan Holtz
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References:
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- https://gist.github.com/evadot/66cfdb8891544b41b4c9
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- https://upload.wikimedia.org/wikipedia/commons/0/0b/Super-Acan-Motherboard-01.jpg
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*******************************************************************************
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