ncr5380: bug fixes

* clear ACK upon exit from DMA mode
* assert DRQ at start of DMA initiator send cycle
This commit is contained in:
Patrick Mackinlay 2020-10-29 17:17:42 +07:00
parent c44f6a05ce
commit 6778308df6
2 changed files with 26 additions and 19 deletions

View File

@ -286,6 +286,9 @@ void ncr5380n_device::mode_w(u8 data)
m_tcmd &= ~TC_LBS;
set_drq(false);
// clear ACK
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
}
// start/stop arbitration
@ -366,7 +369,7 @@ void ncr5380n_device::sds_w(u8 data)
if (m_mode & MODE_DMA)
{
m_state = DMA_OUT_REQ;
m_state = DMA_OUT_DRQ;
m_state_timer->adjust(attotime::zero);
}
}
@ -502,26 +505,27 @@ int ncr5380n_device::state_step()
}
break;
case DMA_OUT_DRQ:
m_state = DMA_OUT_REQ;
set_drq(true);
delay = -1;
break;
case DMA_OUT_REQ:
if (ctrl & S_REQ)
{
if ((ctrl & S_PHASE_MASK) == (m_tcmd & TC_PHASE))
{
m_state = DMA_OUT_DRQ;
set_drq(true);
LOGMASKED(LOG_DMA, "dma out: 0x%02x\n", m_odata);
m_state = DMA_OUT_ACK;
// assert data and ACK
scsi_bus->data_w(scsi_refid, m_odata);
scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
}
delay = -1;
}
break;
case DMA_OUT_DRQ:
LOGMASKED(LOG_DMA, "dma out: 0x%02x\n", m_odata);
m_state = DMA_OUT_ACK;
// assert data and ACK
scsi_bus->data_w(scsi_refid, m_odata);
scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
break;
case DMA_OUT_ACK:
if (!(ctrl & S_REQ))
{
@ -533,7 +537,7 @@ int ncr5380n_device::state_step()
m_tcmd |= TC_LBS;
}
else
m_state = DMA_OUT_REQ;
m_state = DMA_OUT_DRQ;
// clear data and ACK
scsi_bus->data_w(scsi_refid, 0);

View File

@ -143,12 +143,15 @@ void dmac_0266_device::dma_check(void *ptr, s32 param)
* adapter waits for more data that the DMAC is not ready to supply.
* It's not clear how the real hardware works - for now this hack
* continues to read and discard data from the device, or write
* arbitrary zero bytes to it until it deasserts the request line.
* arbitrary zero bytes to it until it asserts EOP (driven by IRQ).
*/
if (m_control & DIRECTION)
m_dma_r();
else
m_dma_w(0);
if (!(m_status & INTERRUPT))
{
if (m_control & DIRECTION)
m_dma_r();
else
m_dma_w(0);
}
return;
}