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https://github.com/holub/mame
synced 2025-04-21 16:01:56 +03:00
ncr5380: bug fixes
* clear ACK upon exit from DMA mode * assert DRQ at start of DMA initiator send cycle
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@ -286,6 +286,9 @@ void ncr5380n_device::mode_w(u8 data)
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m_tcmd &= ~TC_LBS;
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set_drq(false);
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// clear ACK
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scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
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}
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// start/stop arbitration
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@ -366,7 +369,7 @@ void ncr5380n_device::sds_w(u8 data)
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if (m_mode & MODE_DMA)
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{
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m_state = DMA_OUT_REQ;
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m_state = DMA_OUT_DRQ;
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m_state_timer->adjust(attotime::zero);
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}
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}
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@ -502,26 +505,27 @@ int ncr5380n_device::state_step()
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}
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break;
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case DMA_OUT_DRQ:
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m_state = DMA_OUT_REQ;
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set_drq(true);
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delay = -1;
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break;
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case DMA_OUT_REQ:
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if (ctrl & S_REQ)
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{
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if ((ctrl & S_PHASE_MASK) == (m_tcmd & TC_PHASE))
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{
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m_state = DMA_OUT_DRQ;
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set_drq(true);
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LOGMASKED(LOG_DMA, "dma out: 0x%02x\n", m_odata);
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m_state = DMA_OUT_ACK;
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// assert data and ACK
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scsi_bus->data_w(scsi_refid, m_odata);
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scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
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}
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delay = -1;
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}
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break;
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case DMA_OUT_DRQ:
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LOGMASKED(LOG_DMA, "dma out: 0x%02x\n", m_odata);
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m_state = DMA_OUT_ACK;
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// assert data and ACK
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scsi_bus->data_w(scsi_refid, m_odata);
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scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
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break;
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case DMA_OUT_ACK:
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if (!(ctrl & S_REQ))
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{
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@ -533,7 +537,7 @@ int ncr5380n_device::state_step()
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m_tcmd |= TC_LBS;
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}
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else
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m_state = DMA_OUT_REQ;
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m_state = DMA_OUT_DRQ;
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// clear data and ACK
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scsi_bus->data_w(scsi_refid, 0);
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@ -143,12 +143,15 @@ void dmac_0266_device::dma_check(void *ptr, s32 param)
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* adapter waits for more data that the DMAC is not ready to supply.
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* It's not clear how the real hardware works - for now this hack
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* continues to read and discard data from the device, or write
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* arbitrary zero bytes to it until it deasserts the request line.
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* arbitrary zero bytes to it until it asserts EOP (driven by IRQ).
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*/
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if (m_control & DIRECTION)
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m_dma_r();
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else
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m_dma_w(0);
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if (!(m_status & INTERRUPT))
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{
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if (m_control & DIRECTION)
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m_dma_r();
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else
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m_dma_w(0);
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}
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return;
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}
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