Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-22 08:22:15 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

(mess) pc9801: make ide almost work (nw)

Browse Source 
---
This one will actually try to boot with the changes noted in the source (the tvram change may work for sasi too along with the sasi rom in 2hdif.rom) but there appear to be pio timing issues so when it branches in the bootloader it lands on the wrong instruction.  The ide rom has a few 386 instructions in it so it won't work with the ux.
This commit is contained in:
cracyc 2014-10-05 21:21:36 +00:00
parent d99fd52d67
commit 677beaab07
1 changed files with 9 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
src/mess/drivers/pc9801.c
View File

@ -649,13 +649,6 @@ public:
DECLARE_READ8_MEMBER(pic_r);
DECLARE_WRITE8_MEMBER(pic_w);
DECLARE_READ8_MEMBER(pc9801rs_ide_io_0_r);
DECLARE_READ16_MEMBER(pc9801rs_ide_io_1_r);
DECLARE_READ16_MEMBER(pc9801rs_ide_io_2_r);
DECLARE_WRITE8_MEMBER(pc9801rs_ide_io_0_w);
DECLARE_WRITE16_MEMBER(pc9801rs_ide_io_1_w);
DECLARE_WRITE16_MEMBER(pc9801rs_ide_io_2_w);
DECLARE_READ8_MEMBER(sdip_0_r);
DECLARE_READ8_MEMBER(sdip_1_r);
DECLARE_READ8_MEMBER(sdip_2_r);
@ -2054,6 +2047,7 @@ READ8_MEMBER(pc9801_state::pc9801rs_memory_r)
else if(offset >= 0x000b8000 && offset <= 0x000bffff) { return m_pc9801rs_grcg_r(offset & 0x7fff,3); }
else if(offset >= 0x000cc000 && offset <= 0x000cffff) { return pc9801rs_soundrom_r(space,offset & 0x3fff);}
else if(offset >= 0x000d8000 && offset <= 0x000d9fff) { return pc9801rs_ide_r(space,offset & 0x1fff); }
else if(offset >= 0x000da000 && offset <= 0x000dbfff) { return pc9821_ideram_r(space,offset & 0x1fff); }
else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { return m_pc9801rs_grcg_r(offset & 0x7fff,0); }
else if(offset >= 0x000e0000 && offset <= 0x000fffff) { return pc9801rs_ipl_r(space,offset & 0x1ffff); }
else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
@ -2075,6 +2069,7 @@ WRITE8_MEMBER(pc9801_state::pc9801rs_memory_w)
else if(offset >= 0x000a8000 && offset <= 0x000affff) { m_pc9801rs_grcg_w(offset & 0x7fff,1,data); }
else if(offset >= 0x000b0000 && offset <= 0x000b7fff) { m_pc9801rs_grcg_w(offset & 0x7fff,2,data); }
else if(offset >= 0x000b8000 && offset <= 0x000bffff) { m_pc9801rs_grcg_w(offset & 0x7fff,3,data); }
else if(offset >= 0x000da000 && offset <= 0x000dbfff) { pc9821_ideram_w(space,offset & 0x1fff,data); }
else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { m_pc9801rs_grcg_w(offset & 0x7fff,0,data); }
else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data); }
//else
@ -2308,55 +2303,6 @@ WRITE8_MEMBER(pc9801_state::pc9801rs_pit_mirror_w)
}
}
READ8_MEMBER(pc9801_state::pc9801rs_ide_io_0_r)
{
printf("IDE r %02x\n",offset);
return m_ide_bank[offset];
}
WRITE8_MEMBER(pc9801_state::pc9801rs_ide_io_0_w)
{
/*
[0x430]
[Read/write]
bit 7-0: unknown
00 h = IDE Bank # 1
01 h = IDE Bank # 2
[0x432]
bit 7-0: Bank select
80 h = readout for dummy (only [WRITE])
00 h = IDE Bank # 1 choice
01 h = IDE Bank # 2 selection
*/
printf("IDE w %02x %02x\n",offset,data);
if ((data & 0x80) == 0x00)
m_ide_bank[offset] = data & 0x7f;
}
/* TODO: is mapping correct? */
READ16_MEMBER(pc9801_state::pc9801rs_ide_io_1_r)
{
return m_ide->read_cs0(space, offset, mem_mask);
}
WRITE16_MEMBER(pc9801_state::pc9801rs_ide_io_1_w)
{
m_ide->write_cs0(space, offset, data, mem_mask);
}
READ16_MEMBER(pc9801_state::pc9801rs_ide_io_2_r)
{
return m_ide->read_cs1(space, offset + 6, mem_mask);
}
WRITE16_MEMBER(pc9801_state::pc9801rs_ide_io_2_w)
{
m_ide->write_cs1(space, offset + 6, data, mem_mask);
}
static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state )
AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff)
ADDRESS_MAP_END
@ -2381,13 +2327,12 @@ static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 32, pc9801_state )
// AM_RANGE(0x00ec, 0x00ef) PC-9801-86 sound board
AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r, pc9801rs_f0_w, 0xffffffff)
// AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r, pc9801_opn_w, 0xffffffff) //ym2203 opn / <undefined>
AM_RANGE(0x0430, 0x0433) AM_READWRITE8(pc9801rs_ide_io_0_r, pc9801rs_ide_io_0_w,0x00ff00ff)
AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff)
AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank
AM_RANGE(0x0640, 0x064f) AM_READWRITE16(pc9801rs_ide_io_1_r, pc9801rs_ide_io_1_w,0xffffffff)
AM_RANGE(0x074c, 0x074f) AM_READWRITE16(pc9801rs_ide_io_2_r, pc9801rs_ide_io_2_w,0xffffffff)
AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r, pc9801rs_pit_mirror_w, 0xffffffff) // <undefined> / pit mirror ports
AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r, pc9801_mouse_w, 0xffffffff) // <undefined> / mouse ppi8255 ports
@ -2751,15 +2696,14 @@ static ADDRESS_MAP_START( pc9821_io, AS_IO, 32, pc9801_state )
AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r, pc9801rs_f0_w, 0xffffffff)
// AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r, pc9801_opn_w, 0xffffffff) //ym2203 opn / <undefined>
// AM_RANGE(0x018c, 0x018f) YM2203 OPN extended ports / <undefined>
AM_RANGE(0x0430, 0x0433) AM_READWRITE8(pc9801rs_ide_io_0_r, pc9801rs_ide_io_0_w,0x00ff00ff) // IDE bank register
AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff)
// AM_RANGE(0x043d, 0x043d) ROM/RAM bank (NEC)
AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank (EPSON)
AM_RANGE(0x0460, 0x0463) AM_READWRITE8(pc9821_window_bank_r,pc9821_window_bank_w, 0xffffffff)
// AM_RANGE(0x04a0, 0x04af) EGC
// AM_RANGE(0x04be, 0x04be) FDC "RPM" register
AM_RANGE(0x0640, 0x064f) AM_READWRITE16(pc9801rs_ide_io_1_r, pc9801rs_ide_io_1_w,0xffffffff) // IDE registers / <undefined>
AM_RANGE(0x074c, 0x074f) AM_READWRITE16(pc9801rs_ide_io_2_r, pc9801rs_ide_io_2_w,0xffffffff) // IDE status (r) - IDE control registers (w) / <undefined>
AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
// AM_RANGE(0x08e0, 0x08ea) <undefined> / EMM SIO registers
AM_RANGE(0x09a0, 0x09a3) AM_READWRITE8(pc9821_ext2_video_ff_r, pc9821_ext2_video_ff_w, 0xffffffff) // GDC extended register r/w
// AM_RANGE(0x09a8, 0x09a8) GDC 31KHz register r/w
@ -3393,7 +3337,9 @@ MACHINE_START_MEMBER(pc9801_state,pc9801rs)
}
m_ide_rom = memregion("ide")->base();
m_ide_ram = auto_alloc_array(machine(), UINT8, 0x2000);
m_sys_type = 0x80 >> 6;
save_pointer(NAME(m_ide_ram), 0x2000);
}
MACHINE_START_MEMBER(pc9801_state,pc9801bx2)
@ -3408,11 +3354,9 @@ MACHINE_START_MEMBER(pc9801_state,pc9821)
{
MACHINE_START_CALL_MEMBER(pc9801rs);
m_ide_ram = auto_alloc_array(machine(), UINT8, 0x2000);
m_ext_gvram = auto_alloc_array(machine(), UINT8, 0xa0000);
save_pointer(NAME(m_sdip), 24);
save_pointer(NAME(m_ide_ram), 0x2000);
save_pointer(NAME(m_ext_gvram), 0xa0000);
}
@ -3431,6 +3375,7 @@ MACHINE_RESET_MEMBER(pc9801_state,pc9801_common)
int i;
static const UINT8 default_memsw_data[0x10] =
{
// set high nibble of byte 9 to 0xa and comment ROM_FILL below to boot from hdd
0xe1, 0x48, 0xe1, 0x05, 0xe1, 0x04, 0xe1, 0x00, 0xe1, 0x01, 0xe1, 0x00, 0xe1, 0x00, 0xe1, 0x6e
// 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff
};