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https://github.com/holub/mame
synced 2025-04-19 23:12:11 +03:00
iteagle -- Organize bios for iteagle 1 boards (virtual pool).
voodoo_pci -- Fixed voodoo_1 pci initialization.
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4587bb0369
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67a7c86c94
@ -51,6 +51,11 @@ machine_config_constructor voodoo_pci_device::device_mconfig_additions() const
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const device_type VOODOO_PCI = &device_creator<voodoo_pci_device>;
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DEVICE_ADDRESS_MAP_START(config_map, 32, voodoo_pci_device)
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AM_RANGE(0x40, 0x4f) AM_READWRITE (pcictrl_r, pcictrl_w)
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AM_INHERIT_FROM(pci_device::config_map)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(voodoo_reg_map, 32, voodoo_pci_device)
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AM_RANGE(0x0, 0x00ffffff) AM_DEVREADWRITE("voodoo", voodoo_device, voodoo_r, voodoo_w)
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ADDRESS_MAP_END
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@ -83,11 +88,12 @@ void voodoo_pci_device::device_start()
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voodoo_device::static_set_fbmem(m_voodoo, m_fbmem);
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voodoo_device::static_set_tmumem(m_voodoo, m_tmumem0, m_tmumem1);
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switch (m_type) {
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//void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subsystem_id);
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case TYPE_VOODOO_1:
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set_ids(0x121a0001, 0x02, 0x000003, 0x000000);
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set_ids(0x121a0001, 0x02, 0x000000, 0x000000);
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break;
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case TYPE_VOODOO_2:
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set_ids(0x121a0002, 0x02, 0x000003, 0x000000);
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set_ids(0x121a0002, 0x02, 0x040000, 0x000000);
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break;
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case TYPE_VOODOO_BANSHEE:
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set_ids(0x121a0003, 0x02, 0x000003, 0x000000);
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@ -109,6 +115,7 @@ void voodoo_pci_device::device_start()
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void voodoo_pci_device::device_reset()
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{
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memset(m_pcictrl_reg, 0, sizeof(m_pcictrl_reg));
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pci_device::device_reset();
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}
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@ -148,3 +155,26 @@ UINT32 voodoo_pci_device::screen_update(screen_device &screen, bitmap_rgb32 &bit
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{
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return voodoo_update(m_voodoo, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
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}
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// PCI bus control
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READ32_MEMBER (voodoo_pci_device::pcictrl_r)
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{
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UINT32 result = m_pcictrl_reg[offset];
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if (1)
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logerror("%06X:voodoo_pci_device pcictrl_r from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask);
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return result;
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}
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WRITE32_MEMBER (voodoo_pci_device::pcictrl_w)
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{
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COMBINE_DATA(&m_pcictrl_reg[offset]);
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switch (offset) {
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case 0x0/4: // The address map starts at 0x40
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// HW initEnable
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voodoo_set_init_enable(m_voodoo, data);
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logerror("%06X:voodoo_pci_device pcictrl_w to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
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break;
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default:
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logerror("%06X:voodoo_pci_device pcictrl_w to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
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break;
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}
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}
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@ -27,12 +27,16 @@ public:
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// optional information overrides
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virtual machine_config_constructor device_mconfig_additions() const;
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UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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virtual DECLARE_ADDRESS_MAP(config_map, 32);
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void set_cpu_tag(const char *tag);
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static void set_type(const int type) {m_type = type;}
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void set_fbmem(const int fbmem) {m_fbmem = fbmem;}
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void set_tmumem(const int tmumem0, const int tmumem1) {m_tmumem0 = tmumem0; m_tmumem1 = tmumem1;}
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DECLARE_READ32_MEMBER( pcictrl_r);
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DECLARE_WRITE32_MEMBER( pcictrl_w);
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protected:
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virtual void device_start();
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virtual void device_reset();
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@ -43,6 +47,7 @@ private:
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int m_fbmem, m_tmumem0, m_tmumem1;
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const char *m_cpu_tag;
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UINT32 m_pcictrl_reg[0x10];
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DECLARE_ADDRESS_MAP(voodoo_reg_map, 32);
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DECLARE_ADDRESS_MAP(banshee_reg_map, 32);
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DECLARE_ADDRESS_MAP(lfb_map, 32);
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@ -34,19 +34,23 @@
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* Creative/Ensoniq AudioPCI ES1373 audio
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* Atmel 90S2313 AVR-based microcontroller for protection
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* STM48T02 NVRAM
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* AMD AM85C30 Enhanced Serial Communications Controller
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* Conexant CX88168 modem
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Eagle 1 Notes:
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* Cypress CY82C693 Peripheral Controller
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* 3DFX Voodoo 1 video
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TODO:
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* Add support for Eagle 1 (Virtual Pool) PCBs
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* Add support for later RED boards
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* Add support for later RED boards
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Notes:
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Sound volume may be muted, it can be adjusted through the service menu or with volume up/down buttons (+/-)
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Notes:
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Sound volume may be muted, it can be adjusted through the service menu or with volume up/down buttons (+/-)
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The PCB for Virtual Pool is considered "Eagle 1" while the boards
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that were production runs for later games are considered Eagle 2.
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IE: GT Fore! & BBH, both security chips are "E2-" as are various
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preprogrammed PALs: E2-CARD1 & E2-RES3
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The PCB for Virtual Pool is considered "Eagle 1" while the boards
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that were production runs for later games are considered Eagle 2.
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IE: GT Fore! & BBH, both security chips are "E2-" as are various
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preprogrammed PALs: E2-CARD1 & E2-RES3
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***************************************************************************/
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@ -339,8 +343,6 @@ INPUT_PORTS_END
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ROMX_LOAD( "eagle102.u15", 0x000000, 0x100000, CRC(1fd39e73) SHA1(d1ac758f94defc5c55c62594b3999a406dd9ef1f), ROM_BIOS(10) ) \
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ROM_SYSTEM_BIOS( 10, "101", "bootrom 1.01" ) \
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ROMX_LOAD( "eagle101.u15", 0x000000, 0x100000, CRC(2600bc2b) SHA1(c4b89e69c51e4a3bb1874407c4d30b6caed4f396), ROM_BIOS(11) ) \
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ROM_SYSTEM_BIOS( 11, "pool", "Virtual Pool bootrom" ) \
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ROMX_LOAD( "eagle1_bootrom_v1p01", 0x000000, 0x080000, CRC(6c8c1593) SHA1(707d5633388f8dd4e9252f4d8d6f27c98c2cb35a), ROM_BIOS(12) ) \
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ROM_REGION( 0x30000, "fpga", 0 ) \
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ROM_LOAD( "17s20lpc_sb4.u26", 0x000000, 0x008000, CRC(62c4af8a) SHA1(6eca277b9c66a401990599e98fdca64a9e38cc9a) ) \
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ROM_LOAD( "17s20lpc_sb5.u26", 0x008000, 0x008000, CRC(c88b9d42) SHA1(b912d0fc50ecdc6a198c626f6e1644e8405fac6e) ) \
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@ -358,7 +360,9 @@ ROM_START( iteagle )
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ROM_END
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ROM_START( virtpool ) /* On earlier Eagle 1 PCB, possibly a prototype version - later boards are known as Eagle 2 */
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EAGLE_BIOS
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ROM_REGION( 0x100000, ":pci:00.0", 0 ) /* MIPS code */
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ROM_SYSTEM_BIOS( 0, "pool", "Virtual Pool bootrom" )
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ROMX_LOAD( "eagle1_bootrom_v1p01", 0x000000, 0x080000, CRC(6c8c1593) SHA1(707d5633388f8dd4e9252f4d8d6f27c98c2cb35a), ROM_BIOS(1) )
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ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
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ROM_LOAD( "itvp-1.u53", 0x0000, 0x0880, NO_DUMP )
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@ -131,11 +131,11 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
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if (LOG_FPGA && m_prev_reg!=offset)
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logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
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break;
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case 0x0c/4: // 1d = modem byte
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result = (result & 0xFFFF0000) | 0x2c2c;
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if (LOG_FPGA)
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logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
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break;
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// case 0x0c/4: // 1d = modem byte
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// result = (result & 0xFFFF0000) | 0x2c2c;
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// if (LOG_FPGA)
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// logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
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// break;
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case 0x14/4: // Interrupt & 0x4==0x00080000
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result = 0x00000000;
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if (LOG_FPGA)
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@ -146,6 +146,7 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
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if (LOG_FPGA)
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logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
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break;
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case 0x0c/4: // 1d = modem byte
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case 0x1c/4: // 1d = modem byte
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result = (result & 0xFFFF0000) | ((m_serial_reg1d[m_serial_idx]&0xff)<<8) | (m_serial_reg1c[m_serial_idx]&0xff);
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if (ACCESSING_BITS_0_15) {
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@ -200,6 +201,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
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if (LOG_FPGA)
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logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
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break;
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case 0x0c/4:
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case 0x1c/4:
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if (ACCESSING_BITS_0_7) {
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if (!m_serial_data) {
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@ -23,6 +23,7 @@
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#define MCFG_ITEAGLE_EEPROM_INIT(_sw_version, _hw_version) \
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downcast<iteagle_eeprom_device *>(device)->set_info(_sw_version, _hw_version);
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// Mimic Cypress CY82C693 Peripheral Controller
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#define MCFG_ITEAGLE_IDE_ADD(_tag) \
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MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x1080C693, 0x00, 0x060100, 0x00)
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