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fix regression with partial revert of d3196bd991 (nw)

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This commit is contained in:
smf- 2020-05-09 13:39:12 +01:00
parent 2f0ce57217
commit 67e22e2477
4 changed files with 7 additions and 7 deletions
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2
src/mame/drivers/aa310.cpp
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@ -426,7 +426,7 @@ void aa310_state::aa310(machine_config &config)
m_kart->out_tx_callback().set(FUNC(archimedes_state::a310_kart_tx_w));
m_kart->out_rx_callback().set(FUNC(archimedes_state::a310_kart_rx_w));
PCF8583(config, "i2cmem", 0);
I2C_24C02(config, "i2cmem", 0); // TODO: PCF8583
SCREEN(config, "screen", SCREEN_TYPE_RASTER);

2
src/mame/drivers/ertictac.cpp
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@ -224,7 +224,7 @@ void ertictac_state::ertictac(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &ertictac_state::ertictac_map);
m_maincpu->set_periodic_int(FUNC(ertictac_state::ertictac_podule_irq), attotime::from_hz(60)); // FIXME: timing of this
PCF8583(config, "i2cmem", 0); // TODO: Are we sure that this HW have I2C device?
I2C_24C02(config, "i2cmem", 0); // TODO: PCF8583 // TODO: Are we sure that this HW have I2C device?
// AAKART(config, m_kart, 24_MHz_XTAL/3); // TODO: frequency

4
src/mame/includes/archimds.h
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@ -12,7 +12,7 @@
#include "cpu/arm/arm.h"
#include "imagedev/floppy.h"
#include "machine/aakart.h"
#include "machine/pcf8583.h"
#include "machine/i2cmem.h"
#include "machine/wd_fdc.h"
#include "machine/acorn_vidc.h"
@ -90,7 +90,7 @@ public:
protected:
required_device<arm_cpu_device> m_maincpu;
optional_device<pcf8583_device> m_i2cmem;
optional_device<i2cmem_device> m_i2cmem;
required_device<acorn_vidc10_device> m_vidc;
optional_device<wd1772_device> m_fdc;
optional_device<floppy_connector> m_floppy0;

6
src/mame/machine/archimds.cpp
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@ -462,7 +462,7 @@ READ32_MEMBER( archimedes_state::ioc_ctrl_r )
if ( m_i2cmem )
{
i2c_data = (m_i2cmem->sda_r() & 1);
i2c_data = (m_i2cmem->read_sda() & 1);
}
floppy_ready_state = check_floppy_ready();
@ -532,8 +532,8 @@ WRITE32_MEMBER( archimedes_state::ioc_ctrl_w )
//logerror("IOC I2C: CLK %d DAT %d\n", (data>>1)&1, data&1);
if ( m_i2cmem )
{
m_i2cmem->sda_w(data & 0x01);
m_i2cmem->scl_w((data & 0x02) >> 1);
m_i2cmem->write_sda(data & 0x01);
m_i2cmem->write_scl((data & 0x02) >> 1);
}
m_i2c_clk = (data & 2) >> 1;
//TODO: does writing bit 2 here causes a fdc force ready?