mirror of
https://github.com/holub/mame
synced 2025-07-17 07:19:48 +03:00
*fixed the build : zaurus.cpp
This commit is contained in:
Robbbert
parent
96bc593eaa
commit
68dfea282b
@ -1420,27 +1420,19 @@ class zaurus_state : public driver_device
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public:
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zaurus_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_pxa_periphs(*this, "pxa_periphs")
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, m_maincpu(*this, "maincpu")
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, m_ram(*this, "ram")
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{ }
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// devices
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required_device<pxa255_periphs_device> m_pxa_periphs;
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required_device<cpu_device> m_maincpu;
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required_shared_ptr<uint32_t> m_ram;
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uint8_t m_rtc_tick;
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DECLARE_READ32_MEMBER(pxa255_ostimer_r);
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DECLARE_WRITE32_MEMBER(pxa255_ostimer_w);
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DECLARE_READ32_MEMBER(pxa255_rtc_r);
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DECLARE_WRITE32_MEMBER(pxa255_rtc_w);
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DECLARE_READ32_MEMBER(pxa255_intc_r);
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DECLARE_WRITE32_MEMBER(pxa255_intc_w);
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PXA255_OSTMR_Regs m_ostimer_regs;
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PXA255_INTC_Regs m_intc_regs;
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void pxa255_ostimer_irq_check();
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void pxa255_update_interrupts();
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void pxa255_set_irq_line(uint32_t line, int irq_state);
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TIMER_DEVICE_CALLBACK_MEMBER(rtc_irq_callback);
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// screen updates
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@ -1482,223 +1474,6 @@ uint32_t zaurus_state::screen_update( screen_device &screen, bitmap_rgb32 &bitma
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return 0;
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}
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void zaurus_state::pxa255_update_interrupts()
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{
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PXA255_INTC_Regs *intc_regs = &m_intc_regs;
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intc_regs->icfp = (intc_regs->icpr & intc_regs->icmr) & intc_regs->iclr;
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intc_regs->icip = (intc_regs->icpr & intc_regs->icmr) & (~intc_regs->iclr);
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m_maincpu->set_input_line(ARM7_FIRQ_LINE, intc_regs->icfp ? ASSERT_LINE : CLEAR_LINE);
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m_maincpu->set_input_line(ARM7_IRQ_LINE, intc_regs->icip ? ASSERT_LINE : CLEAR_LINE);
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}
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void zaurus_state::pxa255_set_irq_line(uint32_t line, int irq_state)
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{
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PXA255_INTC_Regs *intc_regs = &m_intc_regs;
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intc_regs->icpr &= ~line;
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intc_regs->icpr |= irq_state ? line : 0;
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//printf( "Setting IRQ line %08x to %d\n", line, irq_state );
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pxa255_update_interrupts();
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}
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void zaurus_state::pxa255_ostimer_irq_check()
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{
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PXA255_OSTMR_Regs *ostimer_regs = &m_ostimer_regs;
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// logerror("%08x OStimer irq check\n",ostimer_regs->oier);
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pxa255_set_irq_line(PXA255_INT_OSTIMER0, (ostimer_regs->oier & PXA255_OIER_E0) ? ((ostimer_regs->ossr & PXA255_OSSR_M0) ? 1 : 0) : 0);
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//pxa255_set_irq_line(PXA255_INT_OSTIMER1, (ostimer_regs->oier & PXA255_OIER_E1) ? ((ostimer_regs->ossr & PXA255_OSSR_M1) ? 1 : 0) : 0);
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//pxa255_set_irq_line(PXA255_INT_OSTIMER2, (ostimer_regs->oier & PXA255_OIER_E2) ? ((ostimer_regs->ossr & PXA255_OSSR_M2) ? 1 : 0) : 0);
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//pxa255_set_irq_line(PXA255_INT_OSTIMER3, (ostimer_regs->oier & PXA255_OIER_E3) ? ((ostimer_regs->ossr & PXA255_OSSR_M3) ? 1 : 0) : 0);
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}
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READ32_MEMBER(zaurus_state::pxa255_ostimer_r)
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{
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PXA255_OSTMR_Regs *ostimer_regs = &m_ostimer_regs;
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switch(PXA255_OSTMR_BASE_ADDR | (offset << 2))
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{
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case PXA255_OSMR0:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs->osmr[0], mem_mask );
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return ostimer_regs->osmr[0];
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case PXA255_OSMR1:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs->osmr[1], mem_mask );
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return ostimer_regs->osmr[1];
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case PXA255_OSMR2:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs->osmr[2], mem_mask );
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return ostimer_regs->osmr[2];
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case PXA255_OSMR3:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs->osmr[3], mem_mask );
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return ostimer_regs->osmr[3];
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case PXA255_OSCR:
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if (0) verboselog(*this, 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs->oscr, mem_mask );
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// free-running 3.something MHz counter. this is a complete hack.
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ostimer_regs->oscr += 0x300;
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return ostimer_regs->oscr;
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case PXA255_OSSR:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs->ossr, mem_mask );
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return ostimer_regs->ossr;
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case PXA255_OWER:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs->ower, mem_mask );
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return ostimer_regs->ower;
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case PXA255_OIER:
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if (0) verboselog(*this, 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs->oier, mem_mask );
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return ostimer_regs->oier;
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default:
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if (0) verboselog(*this, 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2));
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break;
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}
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return 0;
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}
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WRITE32_MEMBER(zaurus_state::pxa255_ostimer_w)
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{
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PXA255_OSTMR_Regs *ostimer_regs = &m_ostimer_regs;
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switch(PXA255_OSTMR_BASE_ADDR | (offset << 2))
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{
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case PXA255_OSMR0:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask );
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ostimer_regs->osmr[0] = data;
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if(ostimer_regs->oier & PXA255_OIER_E0)
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{
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attotime period = attotime::from_hz(3846400) * (ostimer_regs->osmr[0] - ostimer_regs->oscr);
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//printf( "Adjusting one-shot timer to 200MHz * %08x\n", ostimer_regs->osmr[0]);
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ostimer_regs->timer[0]->adjust(period);
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}
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break;
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case PXA255_OSMR1:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask );
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ostimer_regs->osmr[1] = data;
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if(ostimer_regs->oier & PXA255_OIER_E1)
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{
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attotime period = attotime::from_hz(3846400) * (ostimer_regs->osmr[1] - ostimer_regs->oscr);
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ostimer_regs->timer[1]->adjust(period, 1);
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}
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break;
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case PXA255_OSMR2:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask );
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ostimer_regs->osmr[2] = data;
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if(ostimer_regs->oier & PXA255_OIER_E2)
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{
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attotime period = attotime::from_hz(3846400) * (ostimer_regs->osmr[2] - ostimer_regs->oscr);
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ostimer_regs->timer[2]->adjust(period, 2);
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}
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break;
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case PXA255_OSMR3:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask );
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ostimer_regs->osmr[3] = data;
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if(ostimer_regs->oier & PXA255_OIER_E3)
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{
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//attotime period = attotime::from_hz(3846400) * (ostimer_regs->osmr[3] - ostimer_regs->oscr);
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//ostimer_regs->timer[3]->adjust(period, 3);
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}
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break;
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case PXA255_OSCR:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs->oscr = data;
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break;
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case PXA255_OSSR:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs->ossr &= ~data;
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pxa255_ostimer_irq_check();
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break;
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case PXA255_OWER:
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs->ower = data & 0x00000001;
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break;
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case PXA255_OIER:
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{
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int index = 0;
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if (0) verboselog(*this, 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs->oier = data & 0x0000000f;
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for(index = 0; index < 4; index++)
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{
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if(ostimer_regs->oier & (1 << index))
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{
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//attotime period = attotime::from_hz(200000000) * ostimer_regs->osmr[index];
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//ostimer_regs->timer[index]->adjust(period, index);
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}
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}
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break;
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}
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default:
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verboselog(*this, 0, "pxa255_ostimer_w: Unknown address: %08x = %08x & %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2), data, mem_mask);
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break;
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}
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}
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READ32_MEMBER(zaurus_state::pxa255_intc_r)
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{
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PXA255_INTC_Regs *intc_regs = &m_intc_regs;
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switch(PXA255_INTC_BASE_ADDR | (offset << 2))
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{
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case PXA255_ICIP:
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if (0) verboselog(*this, 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs->icip, mem_mask );
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return intc_regs->icip;
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case PXA255_ICMR:
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if (0) verboselog(*this, 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs->icmr, mem_mask );
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return intc_regs->icmr;
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case PXA255_ICLR:
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if (0) verboselog(*this, 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs->iclr, mem_mask );
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return intc_regs->iclr;
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case PXA255_ICFP:
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if (0) verboselog(*this, 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs->icfp, mem_mask );
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return intc_regs->icfp;
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case PXA255_ICPR:
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if (0) verboselog(*this, 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs->icpr, mem_mask );
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return intc_regs->icpr;
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case PXA255_ICCR:
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if (0) verboselog(*this, 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs->iccr, mem_mask );
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return intc_regs->iccr;
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default:
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verboselog(*this, 0, "pxa255_intc_r: Unknown address: %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2));
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break;
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}
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return 0;
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}
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WRITE32_MEMBER(zaurus_state::pxa255_intc_w)
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{
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PXA255_INTC_Regs *intc_regs = &m_intc_regs;
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switch(PXA255_INTC_BASE_ADDR | (offset << 2))
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{
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case PXA255_ICIP:
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verboselog(*this, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller IRQ Pending Register: %08x & %08x\n", data, mem_mask );
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break;
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case PXA255_ICMR:
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if (0) verboselog(*this, 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask );
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intc_regs->icmr = data & 0xfffe7f00;
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break;
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case PXA255_ICLR:
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if (0) verboselog(*this, 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask );
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intc_regs->iclr = data & 0xfffe7f00;
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break;
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case PXA255_ICFP:
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if (0) verboselog(*this, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask );
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break;
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case PXA255_ICPR:
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if (0) verboselog(*this, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask );
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break;
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case PXA255_ICCR:
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if (0) verboselog(*this, 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask );
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intc_regs->iccr = data & 0x00000001;
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break;
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default:
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verboselog(*this, 0, "pxa255_intc_w: Unknown address: %08x = %08x & %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2), data, mem_mask);
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break;
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}
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}
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READ32_MEMBER(zaurus_state::pxa255_rtc_r)
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{
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@ -1717,8 +1492,12 @@ void zaurus_state::zaurus_map(address_map &map)
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{
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map(0x00000000, 0x001fffff).ram().region("firmware", 0);
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map(0x40900000, 0x4090000f).rw(FUNC(zaurus_state::pxa255_rtc_r), FUNC(zaurus_state::pxa255_rtc_w));
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map(0x40a00000, 0x40a0001f).rw(FUNC(zaurus_state::pxa255_ostimer_r), FUNC(zaurus_state::pxa255_ostimer_w));
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map(0x40d00000, 0x40d00017).rw(FUNC(zaurus_state::pxa255_intc_r), FUNC(zaurus_state::pxa255_intc_w));
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map(0x40000000, 0x400002ff).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::pxa255_dma_r), FUNC(pxa255_periphs_device::pxa255_dma_w));
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map(0x40400000, 0x40400083).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::pxa255_i2s_r), FUNC(pxa255_periphs_device::pxa255_i2s_w));
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map(0x40a00000, 0x40a0001f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::pxa255_ostimer_r), FUNC(pxa255_periphs_device::pxa255_ostimer_w));
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map(0x40d00000, 0x40d00017).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::pxa255_intc_r), FUNC(pxa255_periphs_device::pxa255_intc_w));
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map(0x40e00000, 0x40e0006b).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::pxa255_gpio_r), FUNC(pxa255_periphs_device::pxa255_gpio_w));
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map(0x44000000, 0x4400021f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::pxa255_lcd_r), FUNC(pxa255_periphs_device::pxa255_lcd_w));
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map(0xa0000000, 0xa07fffff).ram().share("ram");
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}
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@ -1774,6 +1553,8 @@ MACHINE_CONFIG_START(zaurus_state::zaurus)
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SPEAKER(config, "mono").front_center();
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// MCFG_DEVICE_ADD("aysnd", AY8910, MAIN_CLOCK/4)
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// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
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MCFG_DEVICE_ADD("pxa_periphs", PXA255_PERIPHERALS, MAIN_CLOCK, "maincpu")
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MACHINE_CONFIG_END
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