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(MESS) Emulated the SSE HardBox, a Corvus interface for PET [Mike Naberezny]
This commit is contained in:
Curt Coder
parent
08dbb3ccfb
commit
68e33427df
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -7422,6 +7422,8 @@ src/mess/machine/gba_rom.h svneol=native#text/plain
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src/mess/machine/gba_slot.c svneol=native#text/plain
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src/mess/machine/gba_slot.h svneol=native#text/plain
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src/mess/machine/genpc.c svneol=native#text/plain
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src/mess/machine/hardbox.c svneol=native#text/plain
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src/mess/machine/hardbox.h svneol=native#text/plain
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src/mess/machine/hd63450.c svneol=native#text/plain
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src/mess/machine/hd63450.h svneol=native#text/plain
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src/mess/machine/hd64610.c svneol=native#text/plain
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@ -289,6 +289,24 @@
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</part>
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</software>
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<software name="hardbox">
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<description>HardBox Utilities</description>
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<year>1981</year>
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<publisher>Small Systems Engineering"</publisher>
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<part name="flop1" interface="floppy_5_25">
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<dataarea name="flop" size="533248">
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<rom name="hardbox-utils.d80" size="533248" crc="13e90ead" sha1="99449d79c6bca9f291afb672a67025419cbd1199" offset="0" />
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</dataarea>
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</part>
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<part name="flop2" interface="floppy_5_25">
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<dataarea name="flop" size="174848">
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<rom name="hardbox-utils.d64" size="174848" crc="4e1880e3" sha1="0e6bb17f7361be3be5f05ba55fb307a89cfc1897" offset="0" />
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</dataarea>
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</part>
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</software>
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<software name="assorted">
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<!-- assorted.d80-d82 from zimmers.net, needs cleaning and splitting up -->
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<description>Assorted PET software</description>
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@ -1091,6 +1091,7 @@ SLOT_INTERFACE_START( cbm_ieee488_devices )
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SLOT_INTERFACE("d9060", D9060)
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SLOT_INTERFACE("d9090", D9090)
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SLOT_INTERFACE("softbox", SOFTBOX)
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SLOT_INTERFACE("hardbox", HARDBOX)
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SLOT_INTERFACE("shark", SHARK)
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SLOT_INTERFACE_END
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@ -89,6 +89,7 @@
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#include "machine/diag264_lb_tape.h"
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#include "machine/diag264_lb_user.h"
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#include "machine/fd2000.h"
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#include "machine/hardbox.h"
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#include "machine/interpod.h"
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#include "machine/pet_64k.h"
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#include "machine/plus4_sid.h"
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401
src/mess/machine/hardbox.c
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401
src/mess/machine/hardbox.c
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@ -0,0 +1,401 @@
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/****************************************************************************
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SSE HardBox emulation
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Copyright MESS Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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****************************************************************************/
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/*
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http://mikenaberezny.com/hardware/pet-cbm/sse-hardbox-corvus-interface/
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The HardBox provides a CBM DOS interface for a Corvus hard disk. Before
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it can be used, a hard disk image must first be created and formatted.
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Use the CHDMAN utility to create a 20MB image:
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$ chdman createhd -o /path/to/corvus20mb.chd -chs 388,5,20 -ss 512
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Start the pet8032 emulator with the HardBox attached as device 9,
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with the new CHD and the utilities floppy mounted:
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$ mess pet8032 -ieee9 hardbox \
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-hard1 /path/to/corvus20mb.chd \
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-flop1 /path/to/hardbox-utils.d80
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Load and run the "configure" program from the floppy. When prompted
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for the HardBox device number, enter "9".
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Select "q" for quick configure at the menu. It will present a default
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drive size and ask if you want to alter it. If the size is not 20,
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change it to 20.
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After accepting the drive size, it will prompt if you want to perform
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a format check. This requires uploading code into the Corvus, which
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the high level emulation of the Corvus does not support. Enter "n"
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to skip the format check.
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Enter "y" to proceed with the format. After it has completed, the
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program will exit back to BASIC. The drive should now be usable.
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*/
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#include "hardbox.h"
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//**************************************************************************
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// MACROS / CONSTANTS
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//**************************************************************************
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#define Z80_TAG "z80"
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#define I8255_0_TAG "ic17"
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#define I8255_1_TAG "ic16"
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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const device_type HARDBOX = &device_creator<hardbox_device>;
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//-------------------------------------------------
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// ROM( hardbox )
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//-------------------------------------------------
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ROM_START( hardbox )
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ROM_REGION( 0x2000, Z80_TAG, 0 )
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ROM_DEFAULT_BIOS("v3.1")
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ROM_SYSTEM_BIOS( 0, "v2.3", "Version 2.3" )
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ROMX_LOAD( "295-2.3.ic3", 0x0000, 0x1000, CRC(a3eb5fc2) SHA1(39941b45b0696db928615c41c7eae18d951d9ada), ROM_BIOS(1) )
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ROMX_LOAD( "296-2.3.ic4", 0x1000, 0x1000, CRC(fb55b058) SHA1(8f9ec313ec6beaf7b513edf39d9628e6abcc7bc3), ROM_BIOS(1) )
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ROM_SYSTEM_BIOS( 1, "v2.4", "Version 2.4" )
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ROMX_LOAD( "289.ic3", 0x0000, 0x1000, CRC(c39e058f) SHA1(45b390d7125a40f84c7b411a479218baff079746), ROM_BIOS(2) )
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ROMX_LOAD( "290.ic4", 0x1000, 0x1000, CRC(62f51405) SHA1(fdfa0d7b7e8d0182f2df0aa8163c790506104dcf), ROM_BIOS(2) )
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ROM_SYSTEM_BIOS( 2, "v3.1", "Version 3.1" )
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ROMX_LOAD( "295-3.1.ic3", 0x0000, 0x1000, CRC(654a5db1) SHA1(c40859526921e3d8bfd58fc28cc9cc64e59ec638), ROM_BIOS(3) )
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ROMX_LOAD( "296-3.1.ic4", 0x1000, 0x1000, CRC(4c62ddc0) SHA1(151f99dc554d3762b805fc8383cf1b3e1455784f), ROM_BIOS(3) )
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/* Note: Two sets of EPROMs were found marked only "295" and "296" but they have different contents.
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The version numbers listed are the ROM version reported by the HardBox diagnostics program. */
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ROM_END
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//-------------------------------------------------
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// rom_region - device-specific ROM region
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//-------------------------------------------------
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const rom_entry *hardbox_device::device_rom_region() const
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{
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return ROM_NAME( hardbox );
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}
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//-------------------------------------------------
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// ADDRESS_MAP( hardbox_mem )
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//-------------------------------------------------
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static ADDRESS_MAP_START( hardbox_mem, AS_PROGRAM, 8, hardbox_device )
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AM_RANGE(0x0000, 0xdfff) AM_RAM
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AM_RANGE(0xe000, 0xffff) AM_ROM AM_REGION(Z80_TAG, 0)
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ADDRESS_MAP_END
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//-------------------------------------------------
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// ADDRESS_MAP( hardbox_io )
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//-------------------------------------------------
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static ADDRESS_MAP_START( hardbox_io, AS_IO, 8, hardbox_device )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x10, 0x13) AM_DEVREADWRITE(I8255_0_TAG, i8255_device, read, write)
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AM_RANGE(0x14, 0x17) AM_DEVREADWRITE(I8255_1_TAG, i8255_device, read, write)
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AM_RANGE(0x18, 0x18) AM_READWRITE_LEGACY(corvus_hdc_data_r, corvus_hdc_data_w)
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ADDRESS_MAP_END
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//-------------------------------------------------
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// I8255A_INTERFACE( ppi0_intf )
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//-------------------------------------------------
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READ8_MEMBER( hardbox_device::ppi0_pa_r )
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{
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return m_bus->dio_r() ^ 0xff;
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}
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WRITE8_MEMBER( hardbox_device::ppi0_pb_w )
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{
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m_bus->dio_w(this, data ^ 0xff);
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}
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READ8_MEMBER( hardbox_device::ppi0_pc_r )
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{
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UINT8 data = ioport("SW1")->read();
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/* DIP switches on PC1,PC2,PC3 configure the IEEE-488 primary address.
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We get the address from m_address instead. */
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data |= ((m_address - 8) << 1) ^ 0xff;
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return data;
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}
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static I8255A_INTERFACE( ppi0_intf )
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{
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi0_pa_r),
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DEVCB_NULL, // Port A write
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DEVCB_NULL, // Port B read
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi0_pb_w),
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi0_pc_r),
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DEVCB_NULL // Port C write
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};
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//-------------------------------------------------
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// I8255A_INTERFACE( ppi1_intf )
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//-------------------------------------------------
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READ8_MEMBER( hardbox_device::ppi1_pa_r )
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{
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/*
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bit description
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PA0 ATN
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PA1 DAV
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PA2 NDAC
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PA3 NRFD
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PA4 EOI
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PA5 SRQ
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PA6 REN
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PA7 IFC
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*/
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UINT8 data = 0;
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data |= !m_bus->atn_r();
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data |= !m_bus->dav_r() << 1;
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data |= !m_bus->ndac_r() << 2;
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data |= !m_bus->nrfd_r() << 3;
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data |= !m_bus->eoi_r() << 4;
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data |= !m_bus->srq_r() << 5;
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data |= !m_bus->ren_r() << 6;
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data |= !m_bus->ifc_r() << 7;
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return data;
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}
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WRITE8_MEMBER( hardbox_device::ppi1_pb_w )
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{
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/*
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bit description
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PB0 ATN
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PB1 DAV
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PB2 NDAC
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PB3 NRFD
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PB4 EOI
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PB5 SRQ
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PB6 REN
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PB7 IFC
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Note: When the PCB is configured as a HardBox instead of a SoftBox,
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IFC is read only. Do not connect IFC for output here.
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*/
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m_bus->atn_w(this, !BIT(data, 0));
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m_bus->dav_w(this, !BIT(data, 1));
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m_bus->ndac_w(this, !BIT(data, 2));
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m_bus->nrfd_w(this, !BIT(data, 3));
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m_bus->eoi_w(this, !BIT(data, 4));
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m_bus->srq_w(this, !BIT(data, 5));
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m_bus->ren_w(this, !BIT(data, 6));
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}
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READ8_MEMBER( hardbox_device::ppi1_pc_r )
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{
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/*
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bit description
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PC0
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PC1
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PC2
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PC3
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PC4 Corvus READY
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PC5 Corvus DIRC
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PC6
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PC7
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*/
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UINT8 status = corvus_hdc_status_r(space, 0);
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UINT8 data = 0;
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data |= (status & CONTROLLER_BUSY) ? 0 : 0x10;
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data |= (status & CONTROLLER_DIRECTION) ? 0 : 0x20;
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return data;
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}
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WRITE8_MEMBER( hardbox_device::ppi1_pc_w )
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{
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/*
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bit description
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PC0 LED "A"
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PC1 LED "B"
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PC2 LED "READY"
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PC3
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PC4
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PC5
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PC6
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PC7
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*/
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output_set_led_value(LED_A, !BIT(data, 0));
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output_set_led_value(LED_B, !BIT(data, 1));
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output_set_led_value(LED_READY, !BIT(data, 2));
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}
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static I8255A_INTERFACE( ppi1_intf )
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{
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi1_pa_r),
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DEVCB_NULL, // Port A write
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DEVCB_NULL, // Port B read
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi1_pb_w),
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi1_pc_r),
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DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, hardbox_device, ppi1_pc_w)
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};
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//-------------------------------------------------
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// MACHINE_CONFIG_FRAGMENT( hardbox )
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//-------------------------------------------------
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static MACHINE_CONFIG_FRAGMENT( hardbox )
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// basic machine hardware
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MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_8MHz/2)
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MCFG_CPU_PROGRAM_MAP(hardbox_mem)
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MCFG_CPU_IO_MAP(hardbox_io)
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// devices
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MCFG_I8255A_ADD(I8255_0_TAG, ppi0_intf)
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MCFG_I8255A_ADD(I8255_1_TAG, ppi1_intf)
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MCFG_HARDDISK_ADD("harddisk1")
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MCFG_HARDDISK_ADD("harddisk2")
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MCFG_HARDDISK_ADD("harddisk3")
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MCFG_HARDDISK_ADD("harddisk4")
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MACHINE_CONFIG_END
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//-------------------------------------------------
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// machine_config_additions - device-specific
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// machine configurations
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//-------------------------------------------------
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machine_config_constructor hardbox_device::device_mconfig_additions() const
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{
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return MACHINE_CONFIG_NAME( hardbox );
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}
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//-------------------------------------------------
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// INPUT_PORTS( hardbox )
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//-------------------------------------------------
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INPUT_PORTS_START( hardbox )
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PORT_START("SW1")
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PORT_DIPUNKNOWN_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW1:1" )
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/* SW1:2,3,4 are missing intentionally. These switches would control
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IEEE-488 primary address. See the note in hardbox_device::ppi0_pc_r. */
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PORT_DIPUNKNOWN_DIPLOC( 0x10, IP_ACTIVE_LOW, "SW1:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x20, IP_ACTIVE_LOW, "SW1:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x40, IP_ACTIVE_LOW, "SW1:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW1:8" )
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INPUT_PORTS_END
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//-------------------------------------------------
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// input_ports - device-specific input ports
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//-------------------------------------------------
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ioport_constructor hardbox_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME( hardbox );
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// hardbox_device - constructor
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//-------------------------------------------------
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hardbox_device::hardbox_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, HARDBOX, "HardBox", tag, owner, clock, "hardbox", __FILE__),
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device_ieee488_interface(mconfig, *this),
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m_maincpu(*this, Z80_TAG)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void hardbox_device::device_start()
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{
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corvus_hdc_init(this);
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}
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//-------------------------------------------------
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// device_reset_after_children - device-specific
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// reset that must happen after child devices
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// have performed their resets
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//-------------------------------------------------
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void hardbox_device::device_reset_after_children()
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{
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/* The Z80 starts at address 0x0000 but the HardBox has RAM there and
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needs to start from the BIOS at 0xe000. The PCB has logic and a
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74S287 PROM that temporarily changes the memory map so that the
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IC3 EPROM at 0xe000 is mapped to 0x0000 for the first instruction
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fetch only. The instruction normally at 0xe000 is an absolute jump
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into the ROM. On reset, the Z80 will fetch it from 0x0000 and set
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its PC, then the normal map will be restored before the next
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instruction fetch. Here we just set the PC to 0xe000 after the Z80
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resets, which has the same effect. */
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m_maincpu->set_state_int(Z80_PC, 0xe000);
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}
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//-------------------------------------------------
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// ieee488_ifc - interface clear (reset)
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//-------------------------------------------------
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void hardbox_device::ieee488_ifc(int state)
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{
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if (!m_ifc && state)
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{
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device_reset();
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}
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m_ifc = state;
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}
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79
src/mess/machine/hardbox.h
Normal file
79
src/mess/machine/hardbox.h
Normal file
@ -0,0 +1,79 @@
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/**********************************************************************
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SSE HardBox emulation
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Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __PET_HARDBOX__
|
||||
#define __PET_HARDBOX__
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "imagedev/harddriv.h"
|
||||
#include "includes/corvushd.h"
|
||||
#include "machine/cbmipt.h"
|
||||
#include "machine/i8255.h"
|
||||
#include "machine/ieee488.h"
|
||||
#include "machine/serial.h"
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> hardbox_device
|
||||
|
||||
class hardbox_device : public device_t,
|
||||
public device_ieee488_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
hardbox_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// optional information overrides
|
||||
virtual const rom_entry *device_rom_region() const;
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual ioport_constructor device_input_ports() const;
|
||||
|
||||
DECLARE_READ8_MEMBER( ppi0_pa_r );
|
||||
DECLARE_WRITE8_MEMBER( ppi0_pb_w );
|
||||
DECLARE_READ8_MEMBER( ppi0_pc_r );
|
||||
|
||||
DECLARE_READ8_MEMBER( ppi1_pa_r );
|
||||
DECLARE_WRITE8_MEMBER( ppi1_pb_w );
|
||||
DECLARE_READ8_MEMBER( ppi1_pc_r );
|
||||
DECLARE_WRITE8_MEMBER( ppi1_pc_w );
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset_after_children();
|
||||
|
||||
// device_ieee488_interface overrides
|
||||
virtual void ieee488_ifc(int state);
|
||||
|
||||
private:
|
||||
enum
|
||||
{
|
||||
LED_A,
|
||||
LED_B,
|
||||
LED_READY
|
||||
};
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
|
||||
int m_ifc; // Tracks previous state of IEEE-488 IFC line
|
||||
};
|
||||
|
||||
// device type definition
|
||||
extern const device_type HARDBOX;
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@ -1184,6 +1184,7 @@ $(MESSOBJ)/cbm.a: \
|
||||
$(MESS_MACHINE)/d9060hd.o \
|
||||
$(MESS_MACHINE)/serialbox.o \
|
||||
$(MESS_MACHINE)/softbox.o \
|
||||
$(MESS_MACHINE)/hardbox.o \
|
||||
$(MESS_MACHINE)/cmdhd.o \
|
||||
$(MESS_MACHINE)/fd2000.o \
|
||||
$(MESS_DRIVERS)/clcd.o \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user