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-midzeus: Moved some Zeus2-specific members into the appropriate subclass, and added more state registration. [Ryan Holtz]

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-tsb12lv01a: Added a skeleton device for the TI TSB12LV01A IEEE 1394 link-layer controller. [Ryan Holtz]

-ibm21s850: Added a skeleton device for the iBM 21S850 IEEE 1394 PHY controller. [Ryan Holtz]
This commit is contained in:
Ryan Holtz 2020-07-11 21:20:46 +02:00
parent 902b0da8f5
commit 68f6988509
10 changed files with 868 additions and 192 deletions
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24
scripts/src/machine.lua
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@ -1536,6 +1536,18 @@ if (MACHINES["ICM7170"]~=null) then
}
end
---------------------------------------------------
--
--@src/devices/machine/ibm21s850.h,MACHINES["IBM21S850"] = true
---------------------------------------------------
if (MACHINES["IBM21S850"]~=null) then
files {
MAME_DIR .. "src/devices/machine/ibm21s850.cpp",
MAME_DIR .. "src/devices/machine/ibm21s850.h",
}
end
---------------------------------------------------
--
--@src/devices/machine/idectrl.h,MACHINES["IDECTRL"] = true
@ -3184,6 +3196,18 @@ if (MACHINES["TMS9914"]~=null) then
}
end
---------------------------------------------------
--
--@src/devices/machine/tsb12lv01a.h,MACHINES["TSB12LV01A"] = true
---------------------------------------------------
if (MACHINES["TSB12LV01A"]~=null) then
files {
MAME_DIR .. "src/devices/machine/tsb12lv01a.cpp",
MAME_DIR .. "src/devices/machine/tsb12lv01a.h",
}
end
---------------------------------------------------
--
--@src/devices/machine/tube.h,MACHINES["TUBE"] = true

2
scripts/target/mame/arcade.lua
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@ -495,6 +495,7 @@ MACHINES["I8255"] = true
--MACHINES["I8271"] = true
MACHINES["I8279"] = true
MACHINES["I8355"] = true
MACHINES["IBM21S850"] = true
MACHINES["IDECTRL"] = true
MACHINES["IE15"] = true
MACHINES["IM6402"] = true
@ -638,6 +639,7 @@ MACHINES["TMS6100"] = true
MACHINES["TMS9901"] = true
MACHINES["TMS9902"] = true
--MACHINES["TPI6525"] = true
MACHINES["TSB12LV01A"] = true
--MACHINES["TTL74123"] = true
--MACHINES["TTL74145"] = true
--MACHINES["TTL74148"] = true

2
scripts/target/mame/mess.lua
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@ -523,6 +523,7 @@ MACHINES["I8271"] = true
MACHINES["I8279"] = true
MACHINES["I8291A"] = true
MACHINES["I8355"] = true
--MACHINES["IBM21S850"] = true
MACHINES["ICM7170"] = true
MACHINES["IDECTRL"] = true
MACHINES["IE15"] = true
@ -673,6 +674,7 @@ MACHINES["TMS9914"] = true
MACHINES["TPI6525"] = true
MACHINES["TTL7400"] = true
MACHINES["TTL7404"] = true
--MACHINES["TSB12LV01A"] = true
MACHINES["TTL74123"] = true
MACHINES["TTL74145"] = true
MACHINES["TTL74148"] = true

90
src/devices/machine/ibm21s850.cpp Normal file
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@ -0,0 +1,90 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*************************************************************
IBM 21S850 IEEE 1394 400Mb/s Physical Layer
Transceiver (PHY)
Skeleton device
**************************************************************/
#include "emu.h"
#include "ibm21s850.h"
#define LOG_READS (1 << 1)
#define LOG_WRITES (1 << 2)
#define LOG_UNKNOWNS (1 << 3)
#define LOG_ALL (LOG_READS | LOG_WRITES | LOG_UNKNOWNS)
#define VERBOSE (0)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(IBM21S850, ibm21s850_device, "ibm21s850", "IBM 21S850 IEEE 1394 PHY")
ibm21s850_device::ibm21s850_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, IBM21S850, tag, owner, clock)
{
}
void ibm21s850_device::device_start()
{
save_item(NAME(m_regs));
}
void ibm21s850_device::device_reset()
{
}
uint8_t ibm21s850_device::read(offs_t offset)
{
if (offset < 0x10)
{
LOGMASKED(LOG_READS, "%s: Register %02x read: %02x\n", machine().describe_context(), offset, m_regs[offset]);
return m_regs[offset];
}
LOGMASKED(LOG_READS | LOG_UNKNOWNS, "%s: Unknown Register (%02x) read\n", machine().describe_context(), offset);
return 0;
}
void ibm21s850_device::write(offs_t offset, uint8_t data)
{
switch (offset)
{
default:
LOGMASKED(LOG_WRITES, "%s: Register %02x write (ignored): %02x\n", machine().describe_context(), offset, data);
break;
case 0x01:
LOGMASKED(LOG_WRITES, "%s: Register 01 write: %02x\n", machine().describe_context(), data);
LOGMASKED(LOG_WRITES, "%s: Root Hold-off: %d\n", machine().describe_context(), (data & ROOT_HOLD_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Initiate Bus Reset: %d\n", machine().describe_context(), (data & BUS_RESET_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Gap Offset: %02x\n", machine().describe_context(), data & GAP_COUNT_MASK);
m_regs[offset] = data;
break;
case 0x0d:
LOGMASKED(LOG_WRITES, "%s: Register 0d write: %02x\n", machine().describe_context(), data);
LOGMASKED(LOG_WRITES, "%s: Enable L-P Selftest: %d\n", machine().describe_context(), (data & LP_TEST_EN_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Enable Ack Accel Arbitration: %d\n", machine().describe_context(), (data & ACK_ACCEL_EN_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Enable Multi-Speed Concat: %d\n", machine().describe_context(), (data & MULTISP_CONCAT_EN_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Mask LPS Bit: %d\n", machine().describe_context(), (data & MASK_LPS_MASK) ? 1 : 0);
m_regs[offset] = data;
break;
case 0x0e:
LOGMASKED(LOG_WRITES, "%s: Register 0e write: %02x\n", machine().describe_context(), data);
LOGMASKED(LOG_WRITES, "%s: Enable Tx/Rx Timeout: %d\n", machine().describe_context(), (data & EN_TIMEOUT_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Ignore Unplug: %d\n", machine().describe_context(), (data & IGNORE_UNPLUG_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Override CMC: %d\n", machine().describe_context(), (data & OVERRIDE_CMC_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Software CMC: %d\n", machine().describe_context(), (data & SOFT_CMC_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Disable Port 1: %d\n", machine().describe_context(), (data & DISABLE_P1_MASK) ? 1 : 0);
m_regs[offset] = data;
break;
case 0x0f:
LOGMASKED(LOG_WRITES, "%s: Register 0f write: %02x\n", machine().describe_context(), data);
LOGMASKED(LOG_WRITES, "%s: Soft POR: %d\n", machine().describe_context(), (data & SOFT_POR_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Send PHY-Link Diag (SID) Packet: %d\n", machine().describe_context(), (data & SEND_PL_DIAG_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Degate Ack_Acc_Arb: %d\n", machine().describe_context(), (data & ACK_ACCEL_SYNC_MASK) ? 1 : 0);
LOGMASKED(LOG_WRITES, "%s: Initiate Short Bus Reset: %d\n", machine().describe_context(), (data & ISBR_MASK) ? 1 : 0);
m_regs[offset] = data;
break;
}
}

135
src/devices/machine/ibm21s850.h Normal file
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@ -0,0 +1,135 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*************************************************************
IBM 21S850 IEEE 1394 400Mb/s Physical Layer
Transceiver (PHY)
Skeleton device
**************************************************************/
#ifndef MAME_MACHINE_IBM21S850_H
#define MAME_MACHINE_IBM21S850_H
#pragma once
class ibm21s850_device : public device_t
{
public:
ibm21s850_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
uint8_t read(offs_t offset);
void write(offs_t offset, uint8_t data);
static constexpr feature_type unemulated_features() { return feature::COMMS; }
private:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
enum
{
PHYSICAL_ID_OFFS = 0,
PHYSICAL_ID_SHIFT = 2,
PHYSICAL_ID_MASK = 0xfc,
ROOT_OFFS = 0,
ROOT_MASK = 0x02,
CABLE_PWR_OFFS = 0,
CABLE_PWR_MASK = 0x01,
ROOT_HOLD_OFFS = 1,
ROOT_HOLD_MASK = 0x80,
BUS_RESET_OFFS = 1,
BUS_RESET_MASK = 0x40,
GAP_COUNT_OFFS = 1,
GAP_COUNT_MASK = 0x3f,
SPEED_OFFS = 2,
SPEED_SHIFT = 6,
SPEED_MASK = 0xc0,
ENHANCED_REGS_OFFS = 2,
ENHANCED_REGS_MASK = 0x20,
NUM_PORTS_OFFS = 2,
NUM_PORTS_MASK = 0x1f,
ASTAT1_OFFS = 3,
ASTAT1_SHIFT = 6,
ASTAT1_MASK = 0xc0,
BSTAT1_OFFS = 3,
BSTAT1_SHIFT = 4,
BSTAT1_MASK = 0x30,
CHILD1_OFFS = 3,
CHILD1_MASK = 0x08,
CONNECTION1_OFFS = 3,
CONNECTION1_MASK = 0x04,
PEER_SPEED1_OFFS = 3,
PEER_SPEED1_MASK = 0x03,
ENV_OFFS = 4,
ENV_SHIFT = 6,
ENV_MASK = 0xc0,
REG_COUNT_OFFS = 4,
REG_COUNT_MASK = 0x3f,
LPS_OFFS = 11,
LPS_MASK = 0x80,
PHY_DELAY_OFFS = 11,
PHY_DELAY_SHIFT = 5,
PHY_DELAY_MASK = 0x60,
CONFIG_MGR_CAP_OFFS = 11,
CONFIG_MGR_CAP_MASK = 0x10,
POWER_CLASS_OFFS = 11,
POWER_CLASS_SHIFT = 1,
POWER_CLASS_MASK = 0x0e,
CMC_PIN_OFFS = 12,
CMC_PIN_MASK = 0x80,
CPS_INT_OFFS = 12,
CPS_INT_MASK = 0x40,
LP_TEST_ERR_OFFS = 12,
LP_TEST_ERR_MASK = 0x20,
ARB_PHASE_OFFS = 12,
ARB_PHASE_SHIFT = 3,
ARB_PHASE_MASK = 0x18,
ARB_STATE_OFFS = 12,
ARB_STATE_MASK = 0x07,
LP_TEST_EN_OFFS = 13,
LP_TEST_EN_MASK = 0x40,
ACK_ACCEL_EN_OFFS = 13,
ACK_ACCEL_EN_MASK = 0x08,
MULTISP_CONCAT_EN_OFFS = 13,
MULTISP_CONCAT_EN_MASK = 0x02,
MASK_LPS_OFFS = 13,
MASK_LPS_MASK = 0x01,
EN_TIMEOUT_OFFS = 14,
EN_TIMEOUT_MASK = 0x80,
IGNORE_UNPLUG_OFFS = 14,
IGNORE_UNPLUG_MASK = 0x40,
OVERRIDE_CMC_OFFS = 14,
OVERRIDE_CMC_MASK = 0x20,
SOFT_CMC_OFFS = 14,
SOFT_CMC_MASK = 0x10,
DISABLE_P1_OFFS = 14,
DISABLE_P1_MASK = 0x04,
SOFT_POR_OFFS = 15,
SOFT_POR_MASK = 0x80,
SEND_PL_DIAG_OFFS = 15,
SEND_PL_DIAG_MASK = 0x20,
ACK_ACCEL_SYNC_OFFS = 15,
ACK_ACCEL_SYNC_MASK = 0x10,
ISBR_OFFS = 15,
ISBR_MASK = 0x08
};
uint8_t m_regs[16];
};
//device type definition
DECLARE_DEVICE_TYPE(IBM21S850, ibm21s850_device)
#endif // MAME_MACHINE_IBM21S850_H

259
src/devices/machine/tsb12lv01a.cpp Normal file
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@ -0,0 +1,259 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*************************************************************
Texas Instruments TSB12LV01A/TSB12LV01AI IEEE 1394-1995
High-Speed Serial-Bus Link-Layer Controller
Skeleton device
**************************************************************/
#include "emu.h"
#include "tsb12lv01a.h"
#define LOG_READS (1 << 1)
#define LOG_WRITES (1 << 2)
#define LOG_UNKNOWNS (1 << 3)
#define LOG_ALL (LOG_READS | LOG_WRITES | LOG_UNKNOWNS)
#define VERBOSE (0)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(TSB12LV01A, tsb12lv01a_device, "tsb12lv01a", "TSB12LV01A IEEE 1394 Link Controller")
tsb12lv01a_device::tsb12lv01a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, TSB12LV01A, tag, owner, clock)
, m_int_cb(*this)
, m_phy_read_cb(*this)
, m_phy_write_cb(*this)
{
}
void tsb12lv01a_device::device_start()
{
save_item(NAME(m_version));
save_item(NAME(m_node_address));
save_item(NAME(m_ctrl));
save_item(NAME(m_int_status));
save_item(NAME(m_int_mask));
save_item(NAME(m_cycle_timer));
save_item(NAME(m_isoch_port_num));
save_item(NAME(m_fifo_ctrl));
save_item(NAME(m_diag_ctrl));
save_item(NAME(m_phy_access));
save_item(NAME(m_atf_status));
save_item(NAME(m_itf_status));
save_item(NAME(m_grf_status));
m_int_cb.resolve_safe();
m_phy_read_cb.resolve_safe(0x00);
m_phy_write_cb.resolve_safe();
}
void tsb12lv01a_device::device_reset()
{
m_version = 0x30313042;
m_node_address = 0xffff0000;
m_ctrl = 0x00000000;
m_int_status = 0x10000000;
m_int_mask = 0x00000000;
m_cycle_timer = 0x00000000;
m_isoch_port_num = 0x00000000;
m_fifo_ctrl = 0x00000000;
m_diag_ctrl = 0x00000000;
m_phy_access = 0x00000000;
m_atf_status = 0x00000000;
m_itf_status = 0x00000000;
m_grf_status = 0x00000000;
}
void tsb12lv01a_device::set_interrupt(uint32_t bit)
{
m_int_status |= bit;
check_interrupts();
}
void tsb12lv01a_device::check_interrupts()
{
if (m_int_status & 0x7fffffff)
{
m_int_status |= INT_INT;
}
const uint32_t active_bits = m_int_status & m_int_mask;
m_int_cb((active_bits & INT_INT) ? 1 : 0);
}
void tsb12lv01a_device::reset_tx()
{
// TODO
set_interrupt(INT_TXRDY);
}
void tsb12lv01a_device::reset_rx()
{
}
void tsb12lv01a_device::clear_atf()
{
const uint32_t atf_size = (m_fifo_ctrl & FIFO_CTRL_ATF_SIZE_MASK) >> FIFO_CTRL_ATF_SIZE_SHIFT;
m_atf_status &= ~(ATF_STATUS_FULL | ATF_STATUS_CONERR | ATF_STATUS_ADRCOUNTER_MASK | ATF_STATUS_ATFSPACE_MASK);
m_atf_status |= ATF_STATUS_EMPTY;
m_atf_status |= (atf_size << ATF_STATUS_ATFSPACE_SHIFT);
}
void tsb12lv01a_device::clear_itf()
{
const uint32_t itf_size = (m_fifo_ctrl & FIFO_CTRL_ITF_SIZE_MASK) >> FIFO_CTRL_ITF_SIZE_SHIFT;
m_itf_status &= ~(ITF_STATUS_FULL | ITF_STATUS_ITFSPACE_MASK);
m_itf_status |= ITF_STATUS_EMPTY;
m_itf_status |= (itf_size << ITF_STATUS_ITFSPACE_SHIFT);
}
void tsb12lv01a_device::clear_grf()
{
const uint32_t atf_size = (m_fifo_ctrl & FIFO_CTRL_ATF_SIZE_MASK) >> FIFO_CTRL_ATF_SIZE_SHIFT;
const uint32_t itf_size = (m_fifo_ctrl & FIFO_CTRL_ITF_SIZE_MASK) >> FIFO_CTRL_ITF_SIZE_SHIFT;
const uint32_t grf_size = 0x200 - (atf_size + itf_size);
m_grf_status &= ~(GRF_STATUS_CD | GRF_STATUS_PACCOM | GRF_STATUS_GRFTOTAL_MASK | GRF_STATUS_WRITECOUNT_MASK);
m_grf_status |= GRF_STATUS_EMPTY;
m_grf_status |= grf_size << GRF_STATUS_GRFSIZE_SHIFT;
}
uint32_t tsb12lv01a_device::read(offs_t offset)
{
switch (offset)
{
case 0x00:
LOGMASKED(LOG_READS, "%s: TSB12 Version register read: %08x\n", machine().describe_context(), m_version);
return m_version;
case 0x04:
LOGMASKED(LOG_READS, "%s: TSB12 Node Address register read: %08x\n", machine().describe_context(), m_node_address);
return m_node_address;
case 0x08:
LOGMASKED(LOG_READS, "%s: TSB12 Control register read: %08x\n", machine().describe_context(), m_ctrl);
return m_ctrl;
case 0x0c:
LOGMASKED(LOG_READS, "%s: TSB12 Interrupt Status register read: %08x\n", machine().describe_context(), m_int_status);
return m_int_status;
case 0x10:
LOGMASKED(LOG_READS, "%s: TSB12 Interrupt Mask register read: %08x\n", machine().describe_context(), m_int_mask);
return m_int_mask;
case 0x14:
LOGMASKED(LOG_READS, "%s: TSB12 Cycle Timer register read: %08x\n", machine().describe_context(), m_cycle_timer);
return m_cycle_timer;
case 0x18:
LOGMASKED(LOG_READS, "%s: TSB12 Isochronous Receive-Port Number register read: %08x\n", machine().describe_context(), m_isoch_port_num);
return m_isoch_port_num;
case 0x1c:
LOGMASKED(LOG_READS, "%s: TSB12 FIFO Control register read: %08x\n", machine().describe_context(), m_fifo_ctrl);
return m_fifo_ctrl;
case 0x20:
LOGMASKED(LOG_READS, "%s: TSB12 Diagnostic Control register read: %08x\n", machine().describe_context(), m_diag_ctrl);
return m_diag_ctrl;
case 0x24:
LOGMASKED(LOG_READS, "%s: TSB12 Phy-Chip Access register read: %08x\n", machine().describe_context(), m_phy_access);
return m_phy_access;
case 0x30:
LOGMASKED(LOG_READS, "%s: TSB12 Asynchronous Transmit-FIFO (ATF) register read: %08x\n", machine().describe_context(), m_atf_status);
return m_atf_status;
case 0x34:
LOGMASKED(LOG_READS, "%s: TSB12 Isochronous Transmit-FIFO (ITF) register read: %08x\n", machine().describe_context(), m_itf_status);
return m_itf_status;
case 0x3c:
LOGMASKED(LOG_READS, "%s: TSB12 General Receive-FIFO (GRF) register read: %08x\n", machine().describe_context(), m_grf_status);
return m_grf_status;
default:
LOGMASKED(LOG_READS | LOG_UNKNOWNS, "%s: TSB12 Unknown read: %08x\n", machine().describe_context(), offset << 2);
return 0;
}
}
void tsb12lv01a_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset)
{
case 0x00:
LOGMASKED(LOG_WRITES, "%s: TSB12 Version register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x04:
LOGMASKED(LOG_WRITES, "%s: TSB12 Node Address register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x08:
LOGMASKED(LOG_WRITES, "%s: TSB12 Control register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
if (data & CTRL_RSTTX)
{
data &= ~CTRL_RSTTX;
reset_tx();
}
if (data & CTRL_RSTRX)
{
data &= ~CTRL_RSTRX;
reset_rx();
}
COMBINE_DATA(&m_ctrl);
break;
case 0x0c:
LOGMASKED(LOG_WRITES, "%s: TSB12 Interrupt Status register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_int_status &= ~m_int_status;
check_interrupts();
break;
case 0x10:
LOGMASKED(LOG_WRITES, "%s: TSB12 Interrupt Mask register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x14:
LOGMASKED(LOG_WRITES, "%s: TSB12 Cycle Timer register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x18:
LOGMASKED(LOG_WRITES, "%s: TSB12 Isochronous Receive-Port Number register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x1c:
LOGMASKED(LOG_WRITES, "%s: TSB12 FIFO Control register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_fifo_ctrl &= ~FIFO_CTRL_RW_BITS;
m_fifo_ctrl |= data & FIFO_CTRL_RW_BITS;
if (data & FIFO_CTRL_CLRATF)
clear_atf();
if (data & FIFO_CTRL_CLRITF)
clear_itf();
if (data & FIFO_CTRL_CLRGRF)
clear_grf();
break;
case 0x20:
LOGMASKED(LOG_WRITES, "%s: TSB12 Diagnostic Control register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x24:
LOGMASKED(LOG_WRITES, "%s: TSB12 Phy-Chip Access register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
if (data & PHY_WRPHY)
{
const uint8_t phy_addr = (data & PHY_PHYRGAD_MASK) >> PHY_PHYRGAD_SHIFT;
const uint8_t phy_data = (data & PHY_PHYRGDATA_MASK) >> PHY_PHYRGDATA_SHIFT;
m_phy_write_cb(phy_addr, phy_data);
}
if (data & PHY_RDPHY)
{
const uint8_t phy_addr = (data & PHY_PHYRGAD_MASK) >> PHY_PHYRGAD_SHIFT;
m_phy_access &= ~PHY_PHYRXAD_MASK;
m_phy_access |= phy_addr << PHY_PHYRXAD_SHIFT;
m_phy_access &= ~PHY_PHYRXDATA_MASK;
m_phy_access |= m_phy_read_cb(phy_addr);
m_int_status |= INT_PHYRRX;
check_interrupts();
}
m_phy_access &= ~(PHY_PHYRXDATA_MASK | PHY_PHYRXAD_MASK);
m_phy_access |= data & (PHY_PHYRGAD_MASK | PHY_PHYRGDATA_MASK);
break;
case 0x30:
LOGMASKED(LOG_WRITES, "%s: TSB12 Asynchronous Transmit-FIFO (ATF) register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x34:
LOGMASKED(LOG_WRITES, "%s: TSB12 Isochronous Transmit-FIFO (ITF) register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x3c:
LOGMASKED(LOG_WRITES, "%s: TSB12 General Receive-FIFO (GRF) register write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
default:
LOGMASKED(LOG_WRITES | LOG_UNKNOWNS, "%s: TSB12 Unknown write: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
break;
}
}

193
src/devices/machine/tsb12lv01a.h Normal file
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@ -0,0 +1,193 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*************************************************************
Texas Instruments TSB12LV01A/TSB12LV01AI IEEE 1394-1995
High-Speed Serial-Bus Link-Layer Controller
Skeleton device
**************************************************************/
#ifndef MAME_MACHINE_TSB12LV01A_H
#define MAME_MACHINE_TSB12LV01A_H
#pragma once
class tsb12lv01a_device : public device_t
{
public:
tsb12lv01a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
uint32_t read(offs_t offset);
void write(offs_t offset, uint32_t data, uint32_t mem_mask);
auto int_cb() { return m_int_cb.bind(); }
auto phy_read() { return m_phy_read_cb.bind(); }
auto phy_write() { return m_phy_write_cb.bind(); }
private:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
void set_interrupt(uint32_t bit);
void check_interrupts();
void reset_tx();
void reset_rx();
void clear_atf();
void clear_itf();
void clear_grf();
enum
{
NODE_ADDR_BUSNUM_SHIFT = 22,
NODE_ADDR_BUSNUM_MASK = 0xffc00000,
NODE_ADDR_NODENUM_SHIFT = 16,
NODE_ADDR_NODENUM_MASK = 0x003f0000,
NODE_ADDR_ROOT = 0x8000,
NODE_ADDR_ATACK_SHIFT = 4,
NODE_ADDR_ATACK_MASK = 0x000001f0,
NODE_ADDR_ACKV = 0x00000001,
CTRL_IDVAL = 0x80000000,
CTRL_RXSID = 0x40000000,
CTRL_BSYCTRL = 0x20000000,
CTRL_RAI = 0x10000000,
CTRL_RCVCYST = 0x08000000,
CTRL_TXAEN = 0x04000000,
CTRL_RXAEN = 0x02000000,
CTRL_TXIEN = 0x01000000,
CTRL_RXIEN = 0x00800000,
CTRL_ACKCEN = 0x00400000,
CTRL_RSTTX = 0x00200000,
CTRL_RSTRX = 0x00100000,
CTRL_CYMAS = 0x00000800,
CTRL_CYSRC = 0x00000400,
CTRL_CYTEN = 0x00000200,
CTRL_TRGEN = 0x00000100,
CTRL_IRP1EN = 0x00000080,
CTRL_IRP2EN = 0x00000040,
CTRL_FHBAD = 0x00000001,
CTRL_RW_BITS = CTRL_IDVAL | CTRL_RXSID | CTRL_BSYCTRL | CTRL_RAI | CTRL_RCVCYST |
CTRL_TXAEN | CTRL_RXAEN | CTRL_TXIEN | CTRL_RXIEN | CTRL_ACKCEN |
CTRL_CYMAS | CTRL_CYSRC | CTRL_CYTEN | CTRL_TRGEN | CTRL_IRP1EN |
CTRL_IRP2EN | CTRL_FHBAD,
INT_INT = 0x80000000,
INT_PHINT = 0x40000000,
INT_PHYRRX = 0x20000000,
INT_PHRST = 0x10000000,
INT_SIDCOMP = 0x08000000,
INT_TXRDY = 0x04000000,
INT_RXDTA = 0x02000000,
INT_CMDRST = 0x01000000,
INT_ACKRCV = 0x00800000,
INT_ITBADF = 0x00100000,
INT_ATBADF = 0x00080000,
INT_SNTRJ = 0x00020000,
INT_HDRDR = 0x00010000,
INT_TCERR = 0x00008000,
INT_CYTMOUT = 0x00001000,
INT_CYSEC = 0x00000800,
INT_CYST = 0x00000400,
INT_CYDNE = 0x00000200,
INT_CYPND = 0x00000100,
INT_CYLST = 0x00000080,
INT_CARBFL = 0x00000040,
INT_ARBGP = 0x00000004,
INT_FRGP = 0x00000002,
INT_IARBFL = 0x00000001,
CYTMR_SEC_COUNT_SHIFT = 25,
CYTMR_SEC_COUNT_MASK = 0xfe000000,
CYTMR_CYC_COUNT_SHIFT = 12,
CYTMR_CYC_COUNT_MASK = 0x01fff000,
CYTMR_CYC_OFFSET_SHIFT = 0,
CYTMR_CYC_OFFSET_MASK = 0x00000fff,
ISOCH_PORT_TAG_SHIFT = 30,
ISOCH_PORT_TAG_MASK = 0xc0000000,
ISOCH_PORT_IRPORT1_SHIFT = 24,
ISOCH_PORT_IRPORT1_MASK = 0x3f000000,
ISOCH_PORT_TAG2_SHIFT = 22,
ISOCH_PORT_TAG2_MASK = 0x00c00000,
ISOCH_PORT_IRPORT2_SHIFT = 16,
ISOCH_PORT_IRPORT2_MASK = 0x003f0000,
ISOCH_PORT_MON_TAG = 0x00000001,
FIFO_CTRL_CLRATF = 0x80000000,
FIFO_CTRL_CLRITF = 0x40000000,
FIFO_CTRL_CLRGRF = 0x20000000,
FIFO_CTRL_TRIG_SIZE_SHIFT = 18,
FIFO_CTRL_TRIG_SIZE_MASK = 0x07fc0000,
FIFO_CTRL_ATF_SIZE_SHIFT = 9,
FIFO_CTRL_ATF_SIZE_MASK = 0x0003fe00,
FIFO_CTRL_ITF_SIZE_SHIFT = 0,
FIFO_CTRL_ITF_SIZE_MASK = 0x000001ff,
FIFO_CTRL_RW_BITS = (FIFO_CTRL_TRIG_SIZE_MASK | FIFO_CTRL_ATF_SIZE_MASK | FIFO_CTRL_ITF_SIZE_MASK),
PHY_RDPHY = 0x80000000,
PHY_WRPHY = 0x40000000,
PHY_PHYRGAD_SHIFT = 24,
PHY_PHYRGAD_MASK = 0x0f000000,
PHY_PHYRGDATA_SHIFT = 16,
PHY_PHYRGDATA_MASK = 0x00ff0000,
PHY_PHYRXAD_SHIFT = 8,
PHY_PHYRXAD_MASK = 0x00000f00,
PHY_PHYRXDATA_SHIFT = 0,
PHY_PHYRXDATA_MASK = 0x000000ff,
PHY_RW_BITS = 0x0fff0fff,
ATF_STATUS_FULL = 0x80000000,
ATF_STATUS_EMPTY = 0x40000000,
ATF_STATUS_CONERR = 0x20000000,
ATF_STATUS_ADRCLR = 0x10000000,
ATF_STATUS_CONTROL = 0x08000000,
ATF_STATUS_RAMTEST = 0x04000000,
ATF_STATUS_ADRCOUNTER_SHIFT = 17,
ATF_STATUS_ADRCOUNTER_MASK = 0x03fe0000,
ATF_STATUS_ATFSPACE_SHIFT = 0,
ATF_STATUS_ATFSPACE_MASK = 0x000001ff,
ITF_STATUS_FULL = 0x80000000,
ITF_STATUS_EMPTY = 0x40000000,
ITF_STATUS_ITFSPACE_SHIFT = 0,
ITF_STATUS_ITFSPACE_MASK = 0x000001ff,
GRF_STATUS_EMPTY = 0x80000000,
GRF_STATUS_CD = 0x40000000,
GRF_STATUS_PACCOM = 0x20000000,
GRF_STATUS_GRFTOTAL_SHIFT = 19,
GRF_STATUS_GRFTOTAL_MASK = 0x1ff80000,
GRF_STATUS_GRFSIZE_SHIFT = 9,
GRF_STATUS_GRFSIZE_MASK = 0x0007fe00,
GRF_STATUS_WRITECOUNT_SHIFT = 0,
GRF_STATUS_WRITECOUNT_MASK = 0x000001ff
};
uint32_t m_version;
uint32_t m_node_address;
uint32_t m_ctrl;
uint32_t m_int_status;
uint32_t m_int_mask;
uint32_t m_cycle_timer;
uint32_t m_isoch_port_num;
uint32_t m_fifo_ctrl;
uint32_t m_diag_ctrl;
uint32_t m_phy_access;
uint32_t m_atf_status;
uint32_t m_itf_status;
uint32_t m_grf_status;
devcb_write_line m_int_cb;
devcb_read8 m_phy_read_cb;
devcb_write8 m_phy_write_cb;
};
//device type definition
DECLARE_DEVICE_TYPE(TSB12LV01A, tsb12lv01a_device)
#endif // MAME_MACHINE_TSB12LV01A_H

266
src/mame/drivers/midzeus.cpp
View File

@ -27,17 +27,21 @@ The Grid v1.2 10/18/2000
**************************************************************************/
#include "emu.h"
#include "audio/dcs.h"
#include "cpu/tms32031/tms32031.h"
#include "cpu/adsp2100/adsp2100.h"
#include "cpu/pic16c5x/pic16c5x.h"
#include "includes/midzeus.h"
#include "audio/dcs.h"
#include "machine/ibm21s850.h"
#include "machine/nvram.h"
#include "machine/tsb12lv01a.h"
#include "crusnexo.lh"
#define LOG_FW (0)
#define LOG_FW (0)
#define CPU_CLOCK XTAL(60'000'000)
@ -52,6 +56,8 @@ public:
midzeus2_state(const machine_config &mconfig, device_type type, const char *tag)
: midzeus_state(mconfig, type, tag)
, m_zeus(*this, "zeus2")
, m_fw_link(*this, "fw_link")
, m_fw_phy(*this, "fw_phy")
, m_leds(*this, "led%u", 0U)
, m_lamps(*this, "lamp%u", 0U)
{ }
@ -64,21 +70,49 @@ public:
void init_thegrid();
private:
virtual void machine_start() override
{
midzeus_state::machine_start();
m_leds.resolve();
m_lamps.resolve();
save_item(NAME(m_disk_asic));
save_item(NAME(m_fw_int_enable));
save_item(NAME(m_fw_int));
}
virtual void machine_reset() override
{
midzeus_state::machine_reset();
memset(m_disk_asic, 0x0, 0x10 * 4);
m_fw_int_enable = 0;
m_fw_int = 0;
}
virtual void video_start() override {}
void zeus2_map(address_map &map);
uint32_t disk_asic_r(offs_t offset);
void disk_asic_w(offs_t offset, uint32_t data);
DECLARE_WRITE_LINE_MEMBER(firewire_irq);
DECLARE_WRITE_LINE_MEMBER(zeus_irq);
uint32_t zeus2_timekeeper_r(offs_t offset);
void zeus2_timekeeper_w(offs_t offset, uint32_t data);
uint32_t crusnexo_leds_r(offs_t offset);
void crusnexo_leds_w(offs_t offset, uint32_t data);
void zeus2_map(address_map &map);
virtual void machine_start() override
{
MACHINE_START_CALL_MEMBER(midzeus);
m_leds.resolve();
m_lamps.resolve();
}
uint32_t m_disk_asic[0x10];
int m_fw_int_enable;
int m_fw_int;
required_device<zeus2_device> m_zeus;
required_device<tsb12lv01a_device> m_fw_link;
required_device<ibm21s850_device> m_fw_phy;
output_finder<32> m_leds;
output_finder<8> m_lamps;
};
@ -91,37 +125,38 @@ private:
*
*************************************/
MACHINE_START_MEMBER(midzeus_state,midzeus)
void midzeus_state::machine_start()
{
m_digits.resolve();
timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate());
timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate());
m_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate());
m_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate());
gun_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(midzeus_state::invasn_gun_callback), this));
gun_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(midzeus_state::invasn_gun_callback), this));
m_gun_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(midzeus_state::invasn_gun_callback), this));
m_gun_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(midzeus_state::invasn_gun_callback), this));
m_display_irq_off_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(midzeus_state::display_irq_off), this));
save_item(NAME(gun_control));
save_item(NAME(gun_irq_state));
save_item(NAME(gun_x));
save_item(NAME(gun_y));
save_item(NAME(crusnexo_leds_select));
save_item(NAME(keypad_select));
save_item(NAME(m_crusnexo_leds_select));
save_item(NAME(m_disk_asic_jr));
save_item(NAME(m_cmos_protected));
save_item(NAME(m_gun_control));
save_item(NAME(m_gun_irq_state));
save_item(NAME(m_gun_x));
save_item(NAME(m_gun_y));
save_item(NAME(m_keypad_select));
}
MACHINE_RESET_MEMBER(midzeus_state,midzeus)
void midzeus_state::machine_reset()
{
memcpy(m_ram_base, memregion("user1")->base(), 0x40000*4);
*m_ram_base <<= 1;
m_maincpu->reset();
cmos_protected = true;
memset(disk_asic_jr, 0x0, 0x10 * 4);
disk_asic_jr[6] = 0xa0; // Rev3 Athens
memset(disk_asic, 0x0, 0x10 * 4);
m_cmos_protected = true;
memset(m_disk_asic_jr, 0x0, 0x10 * 4);
m_disk_asic_jr[6] = 0xa0; // Rev3 Athens
}
@ -134,18 +169,18 @@ MACHINE_RESET_MEMBER(midzeus_state,midzeus)
TIMER_CALLBACK_MEMBER(midzeus_state::display_irq_off)
{
m_maincpu->set_input_line(0, CLEAR_LINE);
m_maincpu->set_input_line(TMS3203X_IRQ0, CLEAR_LINE);
}
INTERRUPT_GEN_MEMBER(midzeus_state::display_irq)
{
device.execute().set_input_line(0, ASSERT_LINE);
m_maincpu->set_input_line(TMS3203X_IRQ0, ASSERT_LINE);
m_display_irq_off_timer->adjust(attotime::from_hz(30000000));
}
WRITE_LINE_MEMBER(midzeus2_state::zeus_irq)
{
m_maincpu->set_input_line(2, ASSERT_LINE);
m_maincpu->set_input_line(TMS3203X_IRQ2, ASSERT_LINE);
}
@ -157,11 +192,11 @@ WRITE_LINE_MEMBER(midzeus2_state::zeus_irq)
void midzeus_state::cmos_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (disk_asic_jr[2] && !cmos_protected)
if (m_disk_asic_jr[2] && !m_cmos_protected)
COMBINE_DATA(&m_nvram[offset]);
else
logerror("%06X:timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", m_maincpu->pc(), disk_asic_jr[2], cmos_protected);
cmos_protected = true;
logerror("%06X:timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", m_maincpu->pc(), m_disk_asic_jr[2], m_cmos_protected);
m_cmos_protected = true;
}
@ -173,7 +208,7 @@ uint32_t midzeus_state::cmos_r(offs_t offset)
void midzeus_state::cmos_protect_w(uint32_t data)
{
cmos_protected = false;
m_cmos_protected = false;
}
@ -192,11 +227,11 @@ uint32_t midzeus2_state::zeus2_timekeeper_r(offs_t offset)
void midzeus2_state::zeus2_timekeeper_w(offs_t offset, uint32_t data)
{
if (disk_asic_jr[2] && !cmos_protected)
if (m_disk_asic_jr[2] && !m_cmos_protected)
m_m48t35->write(offset, data);
else
logerror("%s:zeus2_timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", machine().describe_context(), disk_asic_jr[2], cmos_protected);
cmos_protected = true;
logerror("%s:zeus2_timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", machine().describe_context(), m_disk_asic_jr[2], m_cmos_protected);
m_cmos_protected = true;
}
@ -208,10 +243,10 @@ uint32_t midzeus_state::zpram_r(offs_t offset)
void midzeus_state::zpram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (disk_asic_jr[2])
if (m_disk_asic_jr[2])
COMBINE_DATA(&m_nvram[offset]);
else
logerror("%06X:zpram_w with disk_asic_jr[2] = %d\n", m_maincpu->pc(), disk_asic_jr[2]);
logerror("%06X:zpram_w with disk_asic_jr[2] = %d\n", m_maincpu->pc(), m_disk_asic_jr[2]);
}
@ -221,9 +256,10 @@ void midzeus_state::zpram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
* Disk ASIC registers
*
*************************************/
uint32_t midzeus_state::disk_asic_r(offs_t offset)
uint32_t midzeus2_state::disk_asic_r(offs_t offset)
{
uint32_t retVal = disk_asic[offset];
uint32_t retVal = m_disk_asic[offset];
switch (offset)
{
// Sys Control
@ -237,7 +273,7 @@ uint32_t midzeus_state::disk_asic_r(offs_t offset)
// 0x004: IFIFO Interrupt
// 0x200: Firewire
case 1:
retVal = 0x0;
retVal = (m_fw_int << 9);
break;
// Test
case 2:
@ -260,9 +296,9 @@ uint32_t midzeus_state::disk_asic_r(offs_t offset)
}
void midzeus_state::disk_asic_w(offs_t offset, uint32_t data)
void midzeus2_state::disk_asic_w(offs_t offset, uint32_t data)
{
disk_asic[offset] = data;
m_disk_asic[offset] = data;
switch (offset)
{
@ -275,6 +311,7 @@ void midzeus_state::disk_asic_w(offs_t offset, uint32_t data)
// 0x004: IFIFO Interrupt
// 0x200: Enable Firewire interrupt
case 1:
m_fw_int_enable = BIT(data, 9);
break;
// Test
case 2:
@ -302,7 +339,7 @@ void midzeus_state::disk_asic_w(offs_t offset, uint32_t data)
*************************************/
uint32_t midzeus_state::disk_asic_jr_r(offs_t offset)
{
uint32_t retVal = disk_asic_jr[offset];
uint32_t retVal = m_disk_asic_jr[offset];
switch (offset)
{
// miscellaneous hw wait states
@ -311,16 +348,16 @@ uint32_t midzeus_state::disk_asic_jr_r(offs_t offset)
/* CMOS/ZPRAM write enable; only low bit is used */
case 2:
break;
// return disk_asic_jr[offset] | ~1;
// return m_disk_asic_jr[offset] | ~1;
/* reset status; bit 0 is watchdog reset; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */
case 3:
break;
// return disk_asic_jr[offset] | ~1;
// return m_disk_asic_jr[offset] | ~1;
/* ROM bank selection on Zeus 2; two bits are used */
case 5:
// return disk_asic_jr[offset] | ~3;
// return m_disk_asic_jr[offset] | ~3;
/* disk asic jr id; crusnexo reads at startup: if (val & 0xf0) == 0xa0 it affects */
/* how the Zeus is used (reg 0x5d is set to 0x54580006) */
@ -343,8 +380,8 @@ uint32_t midzeus_state::disk_asic_jr_r(offs_t offset)
void midzeus_state::disk_asic_jr_w(offs_t offset, uint32_t data)
{
//uint32_t oldval = disk_asic_jr[offset];
disk_asic_jr[offset] = data;
//uint32_t oldval = m_disk_asic_jr[offset];
m_disk_asic_jr[offset] = data;
switch (offset)
{
@ -376,7 +413,7 @@ void midzeus_state::disk_asic_jr_w(offs_t offset, uint32_t data)
/* ROM bank selection on Zeus 2 */
case 5:
membank("bank1")->set_entry(disk_asic_jr[offset] & 3);
membank("bank1")->set_entry(m_disk_asic_jr[offset] & 3);
break;
/* zeus2 ws; 0=zeus access 1 wait state, 2=unlock ROMs; crusnexo/thegrid write 1 at startup */
@ -436,18 +473,18 @@ void midzeus2_state::crusnexo_leds_w(offs_t offset, uint32_t data)
/* selection bits 4-6 select the 3 7-segment LEDs */
for (bit = 4; bit < 7; bit++)
if ((crusnexo_leds_select & (1 << bit)) == 0)
if ((m_crusnexo_leds_select & (1 << bit)) == 0)
m_digits[bit] = ~data & 0xff;
/* selection bits 0-2 select the tachometer LEDs */
for (bit = 0; bit < 3; bit++)
if ((crusnexo_leds_select & (1 << bit)) == 0)
if ((m_crusnexo_leds_select & (1 << bit)) == 0)
for (led = 0; led < 8; led++)
m_leds[bit * 8 + led] = BIT(~data, led);
break;
case 3: /* selects which set of LEDs we are addressing */
crusnexo_leds_select = data;
m_crusnexo_leds_select = data;
break;
}
}
@ -462,76 +499,12 @@ void midzeus2_state::crusnexo_leds_w(offs_t offset, uint32_t data)
*
*************************************/
uint32_t midzeus_state::firewire_r(offs_t offset)
WRITE_LINE_MEMBER(midzeus2_state::firewire_irq)
{
uint32_t retVal = 0;
if (offset < 0x40)
retVal = m_firewire[offset / 4];
switch (offset) {
case 0:
// Version
retVal = 0x30313042;
break;
case 0x0c:
// Interrupt
retVal = 0xf4000000;// &m_firewire[0x10 / 4];
break;
case 0x30:
// Asynchronous Transmit FIFO Status
// 8:0 space available
retVal = 0x1ff;
break;
case 0x3c:
// General Rx FIFO Status
// 0x80000000 = Empty
// 0x40000000 = Control Data
// 0x20000000 = Packet Complete
retVal = 0x80000000;
break;
case 0xc0:
// General Rx FIFO
retVal = 0x0;
break;
}
if LOG_FW logerror("%06X:firewire_r(%02X)=%08X\n", m_maincpu->pc(), offset, retVal);
return retVal;
m_fw_int = state;
m_maincpu->set_input_line(TMS3203X_IRQ1, (m_fw_int_enable && m_fw_int) ? ASSERT_LINE : CLEAR_LINE);
}
void midzeus_state::firewire_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// 0x08 // Control
// Bit 0: Flush bad packets from Rx FIFO
// Bit 6: IRP2En
// Bit 7: IRP1En
// Bit 8: TrgEn
// Bit 20: Reset Rx
// Bit 21: Reset Tx
// Bit 22: Enable Acknowledge
// Bit 23: Iso Rx Enable
// Bit 24: Iso Rx Enable
// Bit 25: Async Rx Enable
// Bit 26: Async Tx Enable
// Bit 30: Rx Self ID packets
// Bit 31: Rx Packets addressed to phy
// 0x00200000 Reset Tx
// 0x00100000 Reset Rx
// 0x1c // FIFO Control
// Bit 0:8: ITF Size
// Bit 9:17: ATF Size
// Bit 18:26 Trigger Size
// Bit 29: Clear GRF
// Bit 32: Clear ATF
// 0x20 // Diagnostics
// Bit 31: Enable Snooping
if (offset < 0x40)
COMBINE_DATA(&m_firewire[offset / 4]);
if LOG_FW logerror("%06X:firewire_w(%02X) = %08X\n", m_maincpu->pc(), offset, data);
}
/*************************************
*
* TMS32031 I/O accesses
@ -545,7 +518,7 @@ uint32_t midzeus_state::tms32031_control_r(offs_t offset)
{
/* timer is clocked at 100ns */
int which = (offset >> 4) & 1;
int32_t result = (timer[which]->elapsed() * 10000000).as_double();
int32_t result = (m_timer[which]->elapsed() * 10000000).as_double();
return result;
}
@ -570,7 +543,7 @@ void midzeus_state::tms32031_control_w(offs_t offset, uint32_t data, uint32_t me
{
int which = (offset >> 4) & 1;
if (data & 0x40)
timer[which]->adjust(attotime::never);
m_timer[which]->adjust(attotime::never);
}
else
logerror("%06X:tms32031_control_w(%02X) = %08X\n", m_maincpu->pc(), offset, data);
@ -594,14 +567,14 @@ CUSTOM_INPUT_MEMBER(midzeus_state::custom_49way_r)
void midzeus_state::keypad_select_w(offs_t offset, uint32_t data)
{
if (offset == 1)
keypad_select = data;
m_keypad_select = data;
}
CUSTOM_INPUT_MEMBER(midzeus_state::keypad_r)
{
uint32_t bits = m_io_keypad->read();
uint8_t select = keypad_select;
uint8_t select = m_keypad_select;
while ((select & 1) != 0)
{
select >>= 1;
@ -656,10 +629,10 @@ void midzeus_state::analog_w(uint32_t data)
void midzeus_state::update_gun_irq()
{
/* low 2 bits of gun_control seem to enable IRQs */
if (gun_irq_state & gun_control & 0x03)
m_maincpu->set_input_line(3, ASSERT_LINE);
if (m_gun_irq_state & m_gun_control & 0x03)
m_maincpu->set_input_line(TMS3203X_IRQ3, ASSERT_LINE);
else
m_maincpu->set_input_line(3, CLEAR_LINE);
m_maincpu->set_input_line(TMS3203X_IRQ3, CLEAR_LINE);
}
@ -669,37 +642,37 @@ TIMER_CALLBACK_MEMBER(midzeus_state::invasn_gun_callback)
int beamy = m_screen->vpos();
/* set the appropriate IRQ in the internal gun control and update */
gun_irq_state |= 0x01 << player;
m_gun_irq_state |= 0x01 << player;
update_gun_irq();
/* generate another interrupt on the next scanline while we are within the BEAM_DY */
beamy++;
if (beamy <= m_screen->visible_area().max_y && beamy <= gun_y[player] + BEAM_DY)
gun_timer[player]->adjust(m_screen->time_until_pos(beamy, std::max(0, gun_x[player] - BEAM_DX)), player);
if (beamy <= m_screen->visible_area().max_y && beamy <= m_gun_y[player] + BEAM_DY)
m_gun_timer[player]->adjust(m_screen->time_until_pos(beamy, std::max(0, m_gun_x[player] - BEAM_DX)), player);
}
void midzeus_state::invasn_gun_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t old_control = gun_control;
uint32_t old_control = m_gun_control;
int player;
COMBINE_DATA(&gun_control);
COMBINE_DATA(&m_gun_control);
/* bits 0-1 enable IRQs (?) */
/* bits 2-3 reset IRQ states */
gun_irq_state &= ~((gun_control >> 2) & 3);
m_gun_irq_state &= ~((m_gun_control >> 2) & 3);
update_gun_irq();
for (player = 0; player < 2; player++)
{
uint8_t pmask = 0x04 << player;
if (((old_control ^ gun_control) & pmask) != 0 && (gun_control & pmask) == 0)
if (((old_control ^ m_gun_control) & pmask) != 0 && (m_gun_control & pmask) == 0)
{
const rectangle &visarea = m_screen->visible_area();
gun_x[player] = m_io_gun_x[player]->read() * visarea.width() / 255 + visarea.min_x + BEAM_XOFFS;
gun_y[player] = m_io_gun_y[player]->read() * visarea.height() / 255 + visarea.min_y;
gun_timer[player]->adjust(m_screen->time_until_pos(std::max(0, gun_y[player] - BEAM_DY), std::max(0, gun_x[player] - BEAM_DX)), player);
m_gun_x[player] = m_io_gun_x[player]->read() * visarea.width() / 255 + visarea.min_x + BEAM_XOFFS;
m_gun_y[player] = m_io_gun_y[player]->read() * visarea.height() / 255 + visarea.min_y;
m_gun_timer[player]->adjust(m_screen->time_until_pos(std::max(0, m_gun_y[player] - BEAM_DY), std::max(0, m_gun_x[player] - BEAM_DX)), player);
}
}
}
@ -714,8 +687,8 @@ uint32_t midzeus_state::invasn_gun_r()
for (player = 0; player < 2; player++)
{
int diffx = beamx - gun_x[player];
int diffy = beamy - gun_y[player];
int diffx = beamx - m_gun_x[player];
int diffy = beamy - m_gun_y[player];
if (diffx >= -BEAM_DX && diffx <= BEAM_DX && diffy >= -BEAM_DY && diffy <= BEAM_DY)
result ^= 0x1000 << player;
}
@ -753,7 +726,7 @@ void midzeus2_state::zeus2_map(address_map &map)
map(0x400000, 0x43ffff).ram();
map(0x808000, 0x80807f).rw(FUNC(midzeus2_state::tms32031_control_r), FUNC(midzeus2_state::tms32031_control_w)).share("tms32031_ctl");
map(0x880000, 0x88007f).rw(m_zeus, FUNC(zeus2_device::zeus2_r), FUNC(zeus2_device::zeus2_w));
map(0x8a0000, 0x8a00cf).rw(FUNC(midzeus2_state::firewire_r), FUNC(midzeus2_state::firewire_w)).share("firewire");
map(0x8a0000, 0x8a00cf).rw(m_fw_link, FUNC(tsb12lv01a_device::read), FUNC(tsb12lv01a_device::write));
map(0x8d0000, 0x8d0009).rw(FUNC(midzeus2_state::disk_asic_jr_r), FUNC(midzeus2_state::disk_asic_jr_w));
map(0x900000, 0x91ffff).rw(FUNC(midzeus2_state::zpram_r), FUNC(midzeus2_state::zpram_w)).share("nvram").mirror(0x020000);
map(0x990000, 0x99000f).rw("ioasic", FUNC(midway_ioasic_device::read), FUNC(midway_ioasic_device::write));
@ -1266,8 +1239,6 @@ void midzeus_state::midzeus(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &midzeus_state::zeus_map);
m_maincpu->set_vblank_int("screen", FUNC(midzeus_state::display_irq));
MCFG_MACHINE_START_OVERRIDE(midzeus_state,midzeus)
MCFG_MACHINE_RESET_OVERRIDE(midzeus_state,midzeus)
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_1);
/* video hardware */
@ -1275,11 +1246,9 @@ void midzeus_state::midzeus(machine_config &config)
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(MIDZEUS_VIDEO_CLOCK / 8, 529, 0, 400, 278, 0, 256);
m_screen->set_screen_update(FUNC(midzeus_state::screen_update_midzeus));
m_screen->set_screen_update(FUNC(midzeus_state::screen_update));
m_screen->set_palette("palette");
MCFG_VIDEO_START_OVERRIDE(midzeus_state,midzeus)
/* sound hardware */
DCS2_AUDIO_2104(config, "dcs", 0);
@ -1309,7 +1278,6 @@ void midzeus2_state::midzeus2(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &midzeus2_state::zeus2_map);
m_maincpu->set_vblank_int("screen", FUNC(midzeus2_state::display_irq));
MCFG_MACHINE_RESET_OVERRIDE(midzeus2_state,midzeus)
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_1);
/* video hardware */
@ -1325,10 +1293,18 @@ void midzeus2_state::midzeus2(machine_config &config)
M48T35(config, m_m48t35, 0);
/* I/O hardware */
MIDWAY_IOASIC(config, m_ioasic, 0);
m_ioasic->set_shuffle(MIDWAY_IOASIC_STANDARD);
m_ioasic->set_yearoffs(99);
m_ioasic->set_upper(474);
IBM21S850(config, m_fw_phy, 0);
TSB12LV01A(config, m_fw_link, 0);
m_fw_link->int_cb().set(FUNC(midzeus2_state::firewire_irq));
m_fw_link->phy_read().set(m_fw_phy, FUNC(ibm21s850_device::read));
m_fw_link->phy_write().set(m_fw_phy, FUNC(ibm21s850_device::write));
}
void midzeus2_state::crusnexo(machine_config &config)

71
src/mame/includes/midzeus.h
View File

@ -69,7 +69,6 @@ public:
: driver_device(mconfig, type, tag),
m_nvram(*this, "nvram"),
m_ram_base(*this, "ram_base"),
m_firewire(*this, "firewire"),
m_tms32031_control(*this, "tms32031_ctl"),
m_zeusbase(*this, "zeusbase"),
m_m48t35(*this, "m48t35"),
@ -95,7 +94,6 @@ public:
required_shared_ptr<uint32_t> m_nvram;
required_shared_ptr<uint32_t> m_ram_base;
optional_shared_ptr<uint32_t> m_firewire;
required_shared_ptr<uint32_t> m_tms32031_control;
optional_shared_ptr<uint32_t> m_zeusbase;
@ -104,12 +102,8 @@ public:
void cmos_protect_w(uint32_t data);
uint32_t zpram_r(offs_t offset);
void zpram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t disk_asic_r(offs_t offset);
void disk_asic_w(offs_t offset, uint32_t data);
uint32_t disk_asic_jr_r(offs_t offset);
void disk_asic_jr_w(offs_t offset, uint32_t data);
uint32_t firewire_r(offs_t offset);
void firewire_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t tms32031_control_r(offs_t offset);
void tms32031_control_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
void keypad_select_w(offs_t offset, uint32_t data);
@ -125,10 +119,8 @@ public:
uint32_t trackball_r(offs_t offset);
void init_invasn();
void init_mk4();
DECLARE_MACHINE_START(midzeus);
DECLARE_MACHINE_RESET(midzeus);
DECLARE_VIDEO_START(midzeus);
uint32_t screen_update_midzeus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
INTERRUPT_GEN_MEMBER(display_irq);
TIMER_CALLBACK_MEMBER(display_irq_off);
TIMER_CALLBACK_MEMBER(invasn_gun_callback);
@ -136,7 +128,12 @@ public:
void invasn(machine_config &config);
void mk4(machine_config &config);
void zeus_map(address_map &map);
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
optional_device<timekeeper_device> m_m48t35;
required_device<cpu_device> m_maincpu;
required_device<screen_device> m_screen;
@ -151,20 +148,22 @@ protected:
optional_ioport m_io_49way_y;
optional_ioport m_io_keypad;
output_finder<7> m_digits;
emu_timer *m_display_irq_off_timer;
uint8_t crusnexo_leds_select;
uint32_t disk_asic[0x10];
uint32_t disk_asic_jr[0x10];
uint8_t cmos_protected;
emu_timer * m_display_irq_off_timer;
uint8_t m_crusnexo_leds_select;
uint32_t m_disk_asic_jr[0x10];
uint8_t m_cmos_protected;
emu_timer * m_timer[2];
emu_timer *timer[2];
private:
uint32_t gun_control;
uint8_t gun_irq_state;
emu_timer * gun_timer[2];
int32_t gun_x[2], gun_y[2];
uint8_t keypad_select;
uint32_t m_gun_control;
uint8_t m_gun_irq_state;
emu_timer * m_gun_timer[2];
int32_t m_gun_x[2], m_gun_y[2];
uint8_t m_keypad_select;
void exit_handler();
void zeus_pointer_w(uint32_t which, uint32_t data, bool logit);
void zeus_register16_w(offs_t offset, uint16_t data, bool logit);
@ -187,22 +186,22 @@ private:
void waveram_plot_check_depth_nowrite(int y, int x, uint16_t color, uint16_t depth);
std::unique_ptr<midzeus_renderer> m_poly;
uint8_t m_log_fifo;
uint8_t m_log_fifo;
uint32_t m_zeus_fifo[20];
uint8_t m_zeus_fifo_words;
int16_t m_zeus_matrix[3][3];
int32_t m_zeus_point[3];
int16_t m_zeus_light[3];
void *m_zeus_renderbase;
uint32_t m_zeus_palbase;
uint32_t m_zeus_unkbase;
int m_zeus_enable_logging;
uint32_t m_zeus_objdata;
rectangle m_zeus_cliprect;
uint32_t m_zeus_fifo[20];
uint8_t m_zeus_fifo_words;
int16_t m_zeus_matrix[3][3];
int32_t m_zeus_point[3];
int16_t m_zeus_light[3];
void * m_zeus_renderbase;
uint32_t m_zeus_palbase;
uint32_t m_zeus_unkbase;
int m_zeus_enable_logging;
uint32_t m_zeus_objdata;
rectangle m_zeus_cliprect;
std::unique_ptr<uint32_t[]> m_waveram[2];
int m_yoffs;
int m_texel_width;
int m_is_mk4b;
int m_yoffs;
int m_texel_width;
int m_is_mk4b;
};

18
src/mame/video/midzeus.cpp
View File

@ -204,16 +204,14 @@ midzeus_renderer::midzeus_renderer(midzeus_state &state)
m_state(state)
{}
VIDEO_START_MEMBER(midzeus_state,midzeus)
void midzeus_state::video_start()
{
int i;
/* allocate memory for "wave" RAM */
m_waveram[0] = std::make_unique<uint32_t[]>(WAVERAM0_WIDTH * WAVERAM0_HEIGHT * 8/4);
m_waveram[1] = std::make_unique<uint32_t[]>(WAVERAM1_WIDTH * WAVERAM1_HEIGHT * 8/4);
/* initialize a 5-5-5 palette */
for (i = 0; i < 32768; i++)
for (int i = 0; i < 32768; i++)
m_palette->set_pen_color(i, pal5bit(i >> 10), pal5bit(i >> 5), pal5bit(i >> 0));
/* initialize polygon engine */
@ -272,10 +270,8 @@ void midzeus_state::exit_handler()
*
*************************************/
uint32_t midzeus_state::screen_update_midzeus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
uint32_t midzeus_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
int x, y;
m_poly->wait("VIDEO_UPDATE");
/* normal update case */
@ -283,10 +279,10 @@ uint32_t midzeus_state::screen_update_midzeus(screen_device &screen, bitmap_ind1
{
const void *base = waveram1_ptr_from_expanded_addr(m_zeusbase[0xcc]);
int xoffs = screen.visible_area().min_x;
for (y = cliprect.min_y; y <= cliprect.max_y; y++)
for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
{
uint16_t *dest = &bitmap.pix16(y);
for (x = cliprect.min_x; x <= cliprect.max_x; x++)
for (int x = cliprect.min_x; x <= cliprect.max_x; x++)
dest[x] = WAVERAM_READPIX(base, y, x - xoffs) & 0x7fff;
}
}
@ -304,10 +300,10 @@ uint32_t midzeus_state::screen_update_midzeus(screen_device &screen, bitmap_ind1
if (m_yoffs < 0) m_yoffs = 0;
base = waveram0_ptr_from_block_addr(m_yoffs << 12);
for (y = cliprect.min_y; y <= cliprect.max_y; y++)
for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
{
uint16_t *dest = &bitmap.pix16(y);
for (x = cliprect.min_x; x <= cliprect.max_x; x++)
for (int x = cliprect.min_x; x <= cliprect.max_x; x++)
{
uint8_t tex = get_texel_8bit(base, y, x, m_texel_width);
dest[x] = (tex << 8) | tex;