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bus/a2bus: Added Apple II 3.5" Disk Controller Card. (#9215)
Apple II 3.5" Disk Controller Card, Apple P/N A0076LL/A, Announced July 1991, Released March 1992. $149.95 MSRP
This commit is contained in:
ksherlock
GitHub
parent
b6addc3d06
commit
69271581e6
@ -2529,6 +2529,8 @@ if (BUSES["A2BUS"]~=null) then
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MAME_DIR .. "src/devices/bus/a2bus/a2softcard.h",
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MAME_DIR .. "src/devices/bus/a2bus/a2ssc.cpp",
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MAME_DIR .. "src/devices/bus/a2bus/a2ssc.h",
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MAME_DIR .. "src/devices/bus/a2bus/a2superdrive.cpp",
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MAME_DIR .. "src/devices/bus/a2bus/a2superdrive.h",
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MAME_DIR .. "src/devices/bus/a2bus/a2swyft.cpp",
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MAME_DIR .. "src/devices/bus/a2bus/a2swyft.h",
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MAME_DIR .. "src/devices/bus/a2bus/a2themill.cpp",
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348
src/devices/bus/a2bus/a2superdrive.cpp
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348
src/devices/bus/a2bus/a2superdrive.cpp
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@ -0,0 +1,348 @@
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// license:BSD-3-Clause
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// copyright-holders:Kelvin Sherlock
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/*********************************************************************
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a2superdrive.cpp
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Apple II 3.5" Disk Controller Card (Apple, 1991)
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aka SuperDrive Card, aka NuMustang (development codename)
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32k ram
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32k eprom
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15.6672Mhz crystal
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SWIM 1 Chip (1987)
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65c02 processor (~2mhz)
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uc:
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$0000-$7fff is ram
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$8000-$ffff is rom
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$0a00-$0aff is i/o
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apple 2 bus:
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$c0n0-$c0nf - memory latch. selects a 1k window for $c800-$cbff
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$cn00-$cnff - uc ram ($7b00-$7bff)
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$c800-$cbff - uc ram ($0000-$3cff, based on memory latch)
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$cc00-$cfff - uc ram ($7c00-$7fff)
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spamming Control-D while booting will invoke the built-in
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diagnostics. An alternative entry is Cx0DG from the monitor.
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*********************************************************************/
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#include "emu.h"
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#include "a2superdrive.h"
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#include "cpu/m6502/w65c02s.h"
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#include "machine/applefdintf.h"
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#include "machine/swim1.h"
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#include "imagedev/floppy.h"
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#define C16M (15.6672_MHz_XTAL)
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namespace {
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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class a2bus_superdrive_device:
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public device_t,
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public device_a2bus_card_interface
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{
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public:
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// construction/destruction
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a2bus_superdrive_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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a2bus_superdrive_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual const tiny_rom_entry *device_rom_region() const override;
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// overrides of standard a2bus slot functions
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virtual uint8_t read_c0nx(uint8_t offset) override;
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virtual void write_c0nx(uint8_t offset, uint8_t data) override;
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virtual uint8_t read_cnxx(uint8_t offset) override;
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virtual void write_cnxx(uint8_t offset, uint8_t data) override;
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virtual uint8_t read_c800(uint16_t offset) override;
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virtual void write_c800(uint16_t offset, uint8_t data) override;
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private:
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void m65c02_mem(address_map &map);
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void m65c02_w(offs_t offset, uint8_t value);
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uint8_t m65c02_r(offs_t offset);
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void phases_w(uint8_t phases);
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void sel35_w(int sel35);
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void devsel_w(uint8_t devsel);
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void hdsel_w(int hdsel);
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required_device<cpu_device> m_65c02;
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required_region_ptr<u8> m_rom;
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required_shared_ptr<u8> m_ram;
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required_device<applefdintf_device> m_fdc;
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uint8_t m_bank_select;
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uint8_t m_side;
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};
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#define SUPERDRIVE_ROM_REGION "superdrive_rom"
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ROM_START( superdrive )
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ROM_REGION(0x8000, SUPERDRIVE_ROM_REGION, 0)
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ROM_LOAD( "341-0438-a.bin", 0x0000, 0x08000, CRC(c73ff25b) SHA1(440c3f84176c7b9f542da0b6ddf4fb13ec326c46) )
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ROM_END
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const tiny_rom_entry *a2bus_superdrive_device::device_rom_region() const
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{
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return ROM_NAME( superdrive );
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}
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void a2bus_superdrive_device::m65c02_mem(address_map &map)
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{
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map(0x0000, 0x7fff).ram().share(m_ram);
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map(0x0a00, 0x0aff).rw(FUNC(a2bus_superdrive_device::m65c02_r), FUNC(a2bus_superdrive_device::m65c02_w));
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map(0x8000, 0xffff).rom().region(SUPERDRIVE_ROM_REGION, 0x0000);
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}
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void a2bus_superdrive_device::device_add_mconfig(machine_config &config)
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{
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W65C02S(config, m_65c02, DERIVED_CLOCK(2, 7)); /* ~ 2.046 MHz */
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m_65c02->set_addrmap(AS_PROGRAM, &a2bus_superdrive_device::m65c02_mem);
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SWIM1(config, m_fdc, C16M);
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applefdintf_device::add_35_hd(config, "fdc:0");
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applefdintf_device::add_35_hd(config, "fdc:1");
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m_fdc->devsel_cb().set(FUNC(a2bus_superdrive_device::devsel_w));
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m_fdc->hdsel_cb().set(FUNC(a2bus_superdrive_device::hdsel_w));
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m_fdc->phases_cb().set(FUNC(a2bus_superdrive_device::phases_w));
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m_fdc->sel35_cb().set(FUNC(a2bus_superdrive_device::sel35_w));
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}
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a2bus_superdrive_device::a2bus_superdrive_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, type, tag, owner, clock),
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device_a2bus_card_interface(mconfig, *this),
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m_65c02(*this, "superdrive_65c02"),
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m_rom(*this, SUPERDRIVE_ROM_REGION),
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m_ram(*this, "superdrive_ram"),
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m_fdc(*this, "fdc"),
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m_bank_select(0),
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m_side(0)
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{ }
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a2bus_superdrive_device::a2bus_superdrive_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock):
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a2bus_superdrive_device(mconfig, A2BUS_SUPERDRIVE, tag, owner, clock)
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{ }
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void a2bus_superdrive_device::device_start()
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{
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save_item(NAME(m_bank_select));
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save_item(NAME(m_side));
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}
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void a2bus_superdrive_device::device_reset()
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{
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m_bank_select = 0;
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m_side = 0;
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}
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// overrides of standard a2bus slot functions
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uint8_t a2bus_superdrive_device::read_c0nx(uint8_t offset)
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{
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if (machine().side_effects_disabled()) return 0;
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m_bank_select = offset & 0x0f;
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return 0;
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}
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void a2bus_superdrive_device::write_c0nx(uint8_t offset, uint8_t data)
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{
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m_bank_select = offset & 0x0f;
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}
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uint8_t a2bus_superdrive_device::read_cnxx(uint8_t offset)
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{
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return m_ram[0x7b00 + offset];
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}
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void a2bus_superdrive_device::write_cnxx(uint8_t offset, uint8_t data)
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{
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//m_ram[0x7b00 + offset] = data;
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}
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/*
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* $c800 - $cbff is uc RAM, controlled via c0nx
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* $cc00 - $cfff is uc RAM, hardcoded to $7c00 - $7fff
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*/
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uint8_t a2bus_superdrive_device::read_c800(uint16_t offset)
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{
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unsigned address;
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if (offset < 0x400)
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address = (m_bank_select << 10) + offset;
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else
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address = 0x7c00 + offset - 0x400;
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return m_ram[address];
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}
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void a2bus_superdrive_device::write_c800(uint16_t offset, uint8_t data)
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{
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unsigned address;
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if (offset < 0x400)
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address = (m_bank_select << 10) + offset;
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else
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address = 0x7c00 + offset - 0x400;
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m_ram[address] = data;
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}
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/* uc 65c02 i/o at $0a00 */
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void a2bus_superdrive_device::m65c02_w(offs_t offset, uint8_t value)
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{
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// $00-$0f = swim registers
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// $40 = head sel low
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// $41 = head sel high
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// $80 = diagnostic led on
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// $81 = diagnostic led off
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floppy_image_device *floppy = nullptr;
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if (offset < 16)
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{
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m_fdc->write(offset, value);
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return;
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}
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switch (offset)
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{
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case 0x40:
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m_side = 0;
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floppy = m_fdc->get_floppy();
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if (floppy) floppy->ss_w(m_side);
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break;
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case 0x41:
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m_side = 1;
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floppy = m_fdc->get_floppy();
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if (floppy) floppy->ss_w(m_side);
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break;
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case 0x80:
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logerror("LED on\n");
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break;
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case 0x81:
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logerror("LED off\n");
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break;
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default:
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logerror("write($0a%02x,%02x)\n", offset, value);
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break;
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}
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}
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uint8_t a2bus_superdrive_device::m65c02_r(offs_t offset)
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{
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floppy_image_device *floppy = nullptr;
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if (offset < 16)
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return m_fdc->read(offset);
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if (machine().side_effects_disabled()) return 0;
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switch (offset)
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{
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case 0x40:
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m_side = 0;
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floppy = m_fdc->get_floppy();
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if (floppy) floppy->ss_w(m_side);
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break;
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case 0x41:
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m_side = 1;
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floppy = m_fdc->get_floppy();
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if (floppy) floppy->ss_w(m_side);
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break;
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case 0x80:
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logerror("LED on\n");
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break;
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case 0x81:
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logerror("LED off\n");
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break;
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default:
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logerror("read($0a%02x)\n", offset);
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break;
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}
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return 0;
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}
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void a2bus_superdrive_device::devsel_w(uint8_t devsel)
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{
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floppy_image_device *floppy = nullptr;
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switch (devsel)
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{
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case 1:
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floppy = m_fdc->subdevice<floppy_connector>("0")->get_device();
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break;
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case 2:
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floppy = m_fdc->subdevice<floppy_connector>("1")->get_device();
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break;
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}
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m_fdc->set_floppy(floppy);
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}
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void a2bus_superdrive_device::phases_w(uint8_t phases)
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{
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floppy_image_device *floppy = m_fdc->get_floppy();
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if (floppy)
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floppy->seek_phase_w(phases);
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}
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void a2bus_superdrive_device::sel35_w(int sel35)
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{
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}
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void a2bus_superdrive_device::hdsel_w(int hdsel)
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{
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/* Q3/HDSEL pin (ISM MODE register bit 5) is used to control the clock speed */
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/* MFM runs at 15.6672, GCR at 15.6672/2 */
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m_fdc->set_clock_scale( hdsel ? 1.0 : 0.5);
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}
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} // anonymous namespace
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DEFINE_DEVICE_TYPE_PRIVATE(A2BUS_SUPERDRIVE, device_a2bus_card_interface, a2bus_superdrive_device, "a2superdrive", "Apple II 3.5\" Disk Controller Card")
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22
src/devices/bus/a2bus/a2superdrive.h
Normal file
22
src/devices/bus/a2bus/a2superdrive.h
Normal file
@ -0,0 +1,22 @@
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// license:BSD-3-Clause
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// copyright-holders:Kelvin Sherlock
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/*********************************************************************
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a2superdrive.h
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Implementation of the Apple II 3.5 Disk Controller Card
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*********************************************************************/
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#ifndef MAME_BUS_A2BUS_SUPERDRIVE_H
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#define MAME_BUS_A2BUS_SUPERDRIVE_H
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#pragma once
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#include "a2bus.h"
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// device type definition
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DECLARE_DEVICE_TYPE(A2BUS_SUPERDRIVE, device_a2bus_card_interface)
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#endif // MAME_BUS_A2BUS_SUPERDRIVE_H
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@ -33,6 +33,7 @@
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#include "bus/a2bus/a2scsi.h"
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#include "bus/a2bus/a2softcard.h"
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#include "bus/a2bus/a2ssc.h"
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#include "bus/a2bus/a2superdrive.h"
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#include "bus/a2bus/a2swyft.h"
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#include "bus/a2bus/a2themill.h"
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#include "bus/a2bus/a2thunderclock.h"
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@ -69,6 +70,7 @@
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#include "bus/a2bus/titan3plus2.h"
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#include "bus/a2bus/softcard3.h"
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void apple2_slot0_cards(device_slot_interface &device)
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{
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device.option_add("lang", A2BUS_RAMCARD16K); // Apple II RAM Language Card
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@ -217,6 +219,7 @@ void apple2e_cards(device_slot_interface &device)
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device.option_add("a2sd", A2BUS_A2SD); // Florian Reitz AppleIISD
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device.option_add("grafex", A2BUS_GRAFEX); // Grafex card (uPD7220 graphics)
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device.option_add("pdromdrive", A2BUS_PRODOSROMDRIVE); // ProDOS ROM Drive
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device.option_add("superdrive", A2BUS_SUPERDRIVE); // Apple II 3.5" Disk Controller
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}
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void apple2gs_cards(device_slot_interface &device)
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@ -288,6 +291,7 @@ void apple2gs_cards(device_slot_interface &device)
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device.option_add("q68plus", A2BUS_Q68PLUS); // Stellation Q68 Plus 68000 card
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device.option_add("grafex", A2BUS_GRAFEX); // Grafex card (uPD7220 graphics)
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device.option_add("pdromdrive", A2BUS_PRODOSROMDRIVE); // ProDOS ROM Drive
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device.option_add("superdrive", A2BUS_SUPERDRIVE); // Apple II 3.5" Disk Controller
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}
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void apple3_cards(device_slot_interface &device)
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@ -9,8 +9,6 @@
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#include "emu.h"
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#include "swim1.h"
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#include "cpu/m68000/m68000.h"
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DEFINE_DEVICE_TYPE(SWIM1, swim1_device, "swim1", "Apple SWIM1 (Sander/Wozniak Integrated Machine) version 1 floppy controller")
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swim1_device::swim1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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@ -459,6 +459,7 @@ private:
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bool m_ramrd, m_ramwrt;
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bool m_lcram, m_lcram2, m_lcprewrite, m_lcwriteenable;
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bool m_ioudis;
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bool m_rombank;
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u8 m_shadow, m_speed, m_textcol;
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u8 m_motors_active, m_slotromsel, m_intflag, m_vgcint, m_inten, m_newvideo;
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@ -1393,6 +1394,7 @@ void apple2gs_state::machine_start()
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save_item(NAME(m_an2));
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save_item(NAME(m_an3));
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save_item(NAME(m_intcxrom));
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save_item(NAME(m_rombank));
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save_item(NAME(m_80store));
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save_item(NAME(m_slotc3rom));
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save_item(NAME(m_altzp));
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@ -1494,6 +1496,7 @@ void apple2gs_state::machine_reset()
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m_slotc3rom = false;
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m_irqmask = 0;
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m_intcxrom = false;
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m_rombank = false;
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m_80store = false;
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m_video->m_80store = false;
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m_altzp = false;
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@ -2611,6 +2614,7 @@ u8 apple2gs_state::c000_r(offs_t offset)
|
||||
(m_ramwrt ? 0x10 : 0x00) |
|
||||
(m_lcram ? 0x00 : 0x08) |
|
||||
(m_lcram2 ? 0x04 : 0x00) |
|
||||
(m_rombank ? 0x02 : 0x00) |
|
||||
(m_intcxrom ? 0x01 : 0x00);
|
||||
|
||||
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
|
||||
@ -3065,6 +3069,7 @@ void apple2gs_state::c000_w(offs_t offset, u8 data)
|
||||
m_ramwrt = (data & 0x10);
|
||||
m_lcram = (data & 0x08) ? false : true;
|
||||
m_lcram2 = (data & 0x04);
|
||||
m_rombank = (data & 0x02);
|
||||
m_intcxrom = (data & 0x01);
|
||||
|
||||
// update the aux state
|
||||
|
||||
Loading…
Reference in New Issue
Block a user