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https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
ngen: added basic display, and other little bits of WIP.
This commit is contained in:
mahlemiut
parent
2729c3ec67
commit
6933bb3947
@ -14,6 +14,7 @@
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#include "machine/am9517a.h"
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#include "machine/pic8259.h"
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#include "machine/pit8253.h"
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#include "machine/z80dart.h"
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class ngen_state : public driver_device
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{
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@ -23,9 +24,12 @@ public:
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m_maincpu(*this,"maincpu"),
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m_crtc(*this,"crtc"),
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m_viduart(*this,"videouart"),
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m_iouart(*this,"iouart"),
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m_dmac(*this,"dmac"),
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m_pic(*this,"pic"),
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m_pit(*this,"pit")
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m_pit(*this,"pit"),
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m_vram(*this,"vram"),
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m_fontram(*this,"fontram")
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{}
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DECLARE_WRITE_LINE_MEMBER(pit_out0_w);
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@ -43,27 +47,34 @@ private:
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required_device<cpu_device> m_maincpu;
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required_device<mc6845_device> m_crtc;
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required_device<i8251_device> m_viduart;
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required_device<upd7201_device> m_iouart;
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required_device<am9517a_device> m_dmac;
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required_device<pic8259_device> m_pic;
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required_device<pit8254_device> m_pit;
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required_shared_ptr<UINT16> m_vram;
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required_shared_ptr<UINT16> m_fontram;
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UINT16 m_peripheral;
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UINT16 m_upper;
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UINT16 m_middle;
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UINT16 m_port00;
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UINT16 m_periph141;
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};
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WRITE_LINE_MEMBER(ngen_state::pit_out0_w)
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{
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m_pic->ir0_w(state);
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//m_pic->ir0_w(state);
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logerror("80186 Timer 1 state %i\n",state);
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}
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WRITE_LINE_MEMBER(ngen_state::pit_out1_w)
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{
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logerror("PIT Timer 1 state %i\n",state);
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}
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WRITE_LINE_MEMBER(ngen_state::pit_out2_w)
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{
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logerror("PIT Timer 2 state %i\n",state);
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}
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WRITE16_MEMBER(ngen_state::cpu_peripheral_cb)
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@ -97,10 +108,15 @@ WRITE16_MEMBER(ngen_state::cpu_peripheral_cb)
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}
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// 80186 peripheral space
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// Largely guesswork at this stage
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WRITE16_MEMBER(ngen_state::peripheral_w)
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{
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switch(offset)
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{
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case 0x141:
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// bit 1 enables speaker?
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COMBINE_DATA(&m_periph141);
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break;
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case 0x144:
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if(mem_mask & 0x00ff)
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m_crtc->address_w(space,0,data & 0xff);
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@ -111,21 +127,27 @@ WRITE16_MEMBER(ngen_state::peripheral_w)
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break;
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case 0x146:
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if(mem_mask & 0x00ff)
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m_pic->write(space,0,data & 0xff);
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m_iouart->ba_cd_w(space,0,data & 0xff);
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logerror("Video write offset 0x146 data %04x mask %04x\n",data,mem_mask);
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break;
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case 0x147:
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if(mem_mask & 0x00ff)
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m_pic->write(space,1,data & 0xff);
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m_iouart->ba_cd_w(space,1,data & 0xff);
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logerror("Video write offset 0x147 data %04x mask %04x\n",data,mem_mask);
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break;
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default:
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logerror("(PC=%06x) Unknown 80186 peripheral write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
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}
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logerror("Peripheral write offset %04x data %04x mask %04x\n",offset,data,mem_mask);
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}
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READ16_MEMBER(ngen_state::peripheral_r)
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{
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UINT16 ret = 0xff;
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UINT16 ret = 0xffff;
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switch(offset)
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{
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case 0x141:
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ret = m_periph141;
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break;
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case 0x144:
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if(mem_mask & 0x00ff)
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ret = m_crtc->status_r(space,0);
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@ -136,14 +158,17 @@ READ16_MEMBER(ngen_state::peripheral_r)
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break;
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case 0x146:
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if(mem_mask & 0x00ff)
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ret = m_pic->read(space,0);
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ret = m_iouart->ba_cd_r(space,0);
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break;
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case 0x147:
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case 0x147: // definitely video related, likely UART sending data to the video board
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if(mem_mask & 0x00ff)
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ret = m_pic->read(space,1);
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ret = m_iouart->ba_cd_r(space,1);
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// expects bit 0 to be set (Video ready signal?)
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ret |= 1;
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break;
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default:
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logerror("(PC=%06x) Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret);
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}
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logerror("Peripheral read offset %04x mask %04x\n",offset,mem_mask);
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return ret;
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}
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@ -165,10 +190,25 @@ READ16_MEMBER(ngen_state::port00_r)
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MC6845_UPDATE_ROW( ngen_state::crtc_update_row )
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{
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UINT16 addr = ma;
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for(int x=0;x<bitmap.width();x+=9)
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{
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UINT8 ch = m_vram[addr++];
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for(int z=0;z<9;z++)
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{
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if(BIT(m_fontram[ch*16+ra],8-z))
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bitmap.pix32(y,x+z) = rgb_t(0,0xff,0);
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else
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bitmap.pix32(y,x+z) = rgb_t(0,0,0);
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}
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}
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}
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static ADDRESS_MAP_START( ngen_mem, AS_PROGRAM, 16, ngen_state )
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AM_RANGE(0x00000, 0xfdfff) AM_RAM
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AM_RANGE(0x00000, 0xf7fff) AM_RAM
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AM_RANGE(0xf8000, 0xf9fff) AM_RAM AM_SHARE("vram")
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AM_RANGE(0xfa000, 0xfbfff) AM_RAM AM_SHARE("fontram")
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AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("bios",0)
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ADDRESS_MAP_END
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@ -215,6 +255,9 @@ static MACHINE_CONFIG_START( ngen, ngen_state )
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MCFG_DEVICE_ADD("dmac", AM9517A, XTAL_14_7456MHz / 3) // NEC D8237A, divisor unknown
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// I/O board
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MCFG_UPD7201_ADD("iouart",XTAL_14_7456MHz / 3, 0,0,0,0) // no clock visible on I/O board, guessing for now
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// video board
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_SIZE(720,348)
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