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https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
vertigo: Use ADC0808 device
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@ -41,7 +41,7 @@ void vertigo_state::vertigo_map(address_map &map)
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map(0x000008, 0x001fff).ram().mirror(0x010000);
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map(0x002000, 0x003fff).ram().share("vectorram");
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map(0x004000, 0x00400f).r(this, FUNC(vertigo_state::vertigo_io_convert)).mirror(0x001000);
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map(0x004010, 0x00401f).r(this, FUNC(vertigo_state::vertigo_io_adc)).mirror(0x001000);
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map(0x004010, 0x00401f).r(m_adc, FUNC(adc0808_device::data_r)).mirror(0x001000);
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map(0x004020, 0x00402f).r(this, FUNC(vertigo_state::vertigo_coin_r)).mirror(0x001000);
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map(0x004030, 0x00403f).portr("GIO").mirror(0x001000);
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map(0x004040, 0x00404f).r(this, FUNC(vertigo_state::vertigo_sio_r)).mirror(0x001000);
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@ -131,6 +131,12 @@ MACHINE_CONFIG_START(vertigo_state::vertigo)
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MCFG_CPU_PROGRAM_MAP(vertigo_map)
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MCFG_CPU_PERIODIC_INT_DRIVER(vertigo_state, vertigo_interrupt, 60)
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MCFG_DEVICE_ADD("adc", ADC0808, 500000) // unknown clock
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MCFG_ADC0808_EOC_FF_CB(WRITELINE(vertigo_state, adc_eoc_w))
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MCFG_ADC0808_IN0_CB(IOPORT("P1X"))
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MCFG_ADC0808_IN1_CB(IOPORT("P1Y"))
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MCFG_ADC0808_IN2_CB(IOPORT("PADDLE"))
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exidy440_audio(config);
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MCFG_DEVICE_ADD("pit", PIT8254, 0)
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@ -12,6 +12,7 @@
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#include "audio/exidy440.h"
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#include "machine/74148.h"
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#include "machine/adc0808.h"
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#include "video/vector.h"
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/*************************************
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@ -33,14 +34,15 @@ public:
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m_custom(*this, "custom"),
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m_ttl74148(*this, "74148"),
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m_vector(*this, "vector"),
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m_adc(*this, "adc"),
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m_vectorram(*this, "vectorram")
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{ }
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void vertigo(machine_config &config);
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protected:
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DECLARE_WRITE_LINE_MEMBER(adc_eoc_w);
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DECLARE_READ16_MEMBER(vertigo_io_convert);
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DECLARE_READ16_MEMBER(vertigo_io_adc);
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DECLARE_READ16_MEMBER(vertigo_coin_r);
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DECLARE_WRITE16_MEMBER(vertigo_wsot_w);
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DECLARE_WRITE16_MEMBER(vertigo_audio_w);
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@ -134,10 +136,10 @@ private:
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required_device<exidy440_sound_device> m_custom;
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required_device<ttl74148_device> m_ttl74148;
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required_device<vector_device> m_vector;
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required_device<adc0808_device> m_adc;
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required_shared_ptr<uint16_t> m_vectorram;
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attotime m_irq4_time;
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uint8_t m_irq_state;
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uint8_t m_adc_result;
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vproc m_vs;
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am2901 m_bsp;
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vector_generator m_vgen;
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@ -10,19 +10,6 @@
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#include "includes/vertigo.h"
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/*************************************
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*
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* Statics
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*
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*************************************/
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/* Timestamp of last INTL4 change. The vector CPU runs for
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the delta between this and now.
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*/
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/* State of the priority encoder output */
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/* Result of the last ADC channel sampled */
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/*************************************
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*
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@ -75,24 +62,16 @@ WRITE_LINE_MEMBER(vertigo_state::v_irq3_w)
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*
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*************************************/
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READ16_MEMBER(vertigo_state::vertigo_io_convert)
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WRITE_LINE_MEMBER( vertigo_state::adc_eoc_w )
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{
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static const char *const adcnames[] = { "P1X", "P1Y", "PADDLE" };
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if (offset > 2)
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m_adc_result = 0;
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else
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m_adc_result = ioport(adcnames[offset])->read();
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update_irq_encoder(INPUT_LINE_IRQ2, ASSERT_LINE);
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return 0;
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update_irq_encoder(INPUT_LINE_IRQ2, state ? ASSERT_LINE : CLEAR_LINE);
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}
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READ16_MEMBER(vertigo_state::vertigo_io_adc)
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READ16_MEMBER(vertigo_state::vertigo_io_convert)
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{
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update_irq_encoder(INPUT_LINE_IRQ2, CLEAR_LINE);
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return m_adc_result;
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m_adc->address_offset_start_w(space, offset, 0);
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return 0;
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}
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@ -163,7 +142,6 @@ READ16_MEMBER(vertigo_state::vertigo_sio_r)
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void vertigo_state::machine_start()
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{
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save_item(NAME(m_irq_state));
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save_item(NAME(m_adc_result));
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save_item(NAME(m_irq4_time));
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vertigo_vproc_init();
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