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https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
Missed a file, nw.
This commit is contained in:
mooglyguy
parent
4e74f8c28f
commit
69e58bfbfe
@ -580,9 +580,6 @@ private:
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DECLARE_READ32_MEMBER( ram_r );
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DECLARE_WRITE32_MEMBER( ram_w );
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DECLARE_READ32_MEMBER( ss1_sl0_id );
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DECLARE_READ32_MEMBER( ss1_sl1_id );
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DECLARE_READ32_MEMBER( ss1_sl2_id );
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DECLARE_READ32_MEMBER( ss1_sl3_id );
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DECLARE_READ32_MEMBER( timer_r );
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DECLARE_WRITE32_MEMBER( timer_w );
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DECLARE_READ8_MEMBER( irq_r );
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@ -620,7 +617,7 @@ private:
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required_device<mb86901_device> m_maincpu;
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required_device<mk48t12_device> m_timekpr;
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required_device<m48t02_device> m_timekpr;
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required_device<z80scc_device> m_scc1;
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required_device<z80scc_device> m_scc2;
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@ -720,7 +717,7 @@ uint32_t sun4_state::read_insn_data_4c(uint8_t asi, address_space &space, uint32
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{
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if (!machine().side_effects_disabled())
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{
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//printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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m_maincpu->set_mae();
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m_buserr[0] |= 0x80; // invalid PTE
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m_buserr[0] &= ~0x8000; // read
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@ -780,7 +777,7 @@ void sun4_state::write_insn_data_4c(uint8_t asi, address_space &space, uint32_t
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m_type1space->write32(space, tmp, data, mem_mask);
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return;
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default:
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//printf("sun4c: access to memory type not defined\n");
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printf("sun4c: access to memory type not defined\n");
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m_maincpu->set_mae();
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m_buserr[0] = 0x8020;
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m_buserr[1] = offset << 2;
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@ -789,7 +786,7 @@ void sun4_state::write_insn_data_4c(uint8_t asi, address_space &space, uint32_t
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}
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else
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{
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//printf("sun4c: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry, m_pagemap[entry], data, offset <<2, m_maincpu->pc());
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printf("sun4c: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry, m_pagemap[entry], data, offset <<2, m_maincpu->pc());
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m_maincpu->set_mae();
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m_buserr[0] |= 0x8080; // write cycle, invalid PTE
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m_buserr[1] = offset<<2;
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@ -1049,7 +1046,7 @@ uint32_t sun4_state::read_insn_data(uint8_t asi, address_space &space, uint32_t
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{
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if (!machine().side_effects_disabled())
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{
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//printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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m_maincpu->set_mae();
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m_buserr[0] |= 0x80; // invalid PTE
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m_buserr[0] &= ~0x8000; // read
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@ -1589,7 +1586,7 @@ READ8_MEMBER( sun4_state::irq_r )
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WRITE8_MEMBER( sun4_state::irq_w )
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{
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//printf("%02x to IRQ\n", data);
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printf("%02x to IRQ\n", data);
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m_irq_reg = data;
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@ -1600,6 +1597,7 @@ WRITE8_MEMBER( sun4_state::irq_w )
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WRITE_LINE_MEMBER( sun4_state::scc1_int )
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{
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logerror("scc1\n");
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m_scc1_int = state;
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m_maincpu->set_input_line(SPARC_IRQ12, ((m_scc1_int || m_scc2_int) && (m_irq_reg & 0x01)) ? ASSERT_LINE : CLEAR_LINE);
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@ -1607,6 +1605,7 @@ WRITE_LINE_MEMBER( sun4_state::scc1_int )
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WRITE_LINE_MEMBER( sun4_state::scc2_int )
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{
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logerror("scc2\n");
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m_scc2_int = state;
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m_maincpu->set_input_line(SPARC_IRQ12, ((m_scc1_int || m_scc2_int) && (m_irq_reg & 0x01)) ? ASSERT_LINE : CLEAR_LINE);
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@ -1624,6 +1623,7 @@ void sun4_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
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start_timer(0);
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if ((m_irq_reg & 0x21) == 0x21)
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{
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logerror("t0\n");
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m_maincpu->set_input_line(SPARC_IRQ10, ASSERT_LINE);
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//printf("Taking INT10\n");
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}
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@ -1637,6 +1637,7 @@ void sun4_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
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//m_c1_timer->adjust(attotime::never);
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if ((m_irq_reg & 0x81) == 0x81)
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{
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logerror("t1\n");
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m_maincpu->set_input_line(SPARC_IRQ14, ASSERT_LINE);
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//printf("Taking INT14\n");
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}
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@ -1664,6 +1665,7 @@ READ32_MEMBER( sun4_state::timer_r )
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//printf("Read timer limit 0 (%08x) @ %x, mask %08x\n", ret, m_maincpu->pc(), mem_mask);
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m_counter[0] &= ~0x80000000;
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m_counter[1] &= ~0x80000000;
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logerror("tc0\n");
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m_maincpu->set_input_line(SPARC_IRQ10, CLEAR_LINE);
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}
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@ -1676,6 +1678,7 @@ READ32_MEMBER( sun4_state::timer_r )
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//printf("Read timer limit 1 (%08x) @ %x, mask %08x\n", ret, m_maincpu->pc(), mem_mask);
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m_counter[2] &= ~0x80000000;
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m_counter[3] &= ~0x80000000;
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logerror("tc1\n");
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m_maincpu->set_input_line(SPARC_IRQ14, CLEAR_LINE);
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}
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return ret;
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@ -1744,6 +1747,7 @@ void sun4_state::dma_check_interrupts()
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if (old_irq != m_dma_irq)
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{
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//logerror("m_dma_irq %d because irq_or_err_pending:%d and irq_enabled:%d\n", m_dma_irq ? 1 : 0, irq_or_err_pending, irq_enabled);
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logerror("dma\n");
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m_maincpu->set_input_line(SPARC_IRQ3, m_dma_irq ? ASSERT_LINE : CLEAR_LINE);
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}
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}
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@ -1970,32 +1974,6 @@ READ32_MEMBER( sun4_state::ss1_sl0_id )
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return 0xfe810101;
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}
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// indicate 4/60 color video card exists
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READ32_MEMBER( sun4_state::ss1_sl3_id )
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{
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return 0xfe010101;
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}
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// indicate no card exists
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READ32_MEMBER( sun4_state::ss1_sl1_id )
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{
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m_maincpu->set_mae();
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m_buserr[0] |= 0x20; // timeout
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m_buserr[0] &= ~0x8000; // read
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m_buserr[1] = 0xffa00000;
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return 0;
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}
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// indicate no card exists
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READ32_MEMBER( sun4_state::ss1_sl2_id )
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{
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m_maincpu->set_mae();
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m_buserr[0] |= 0x20; // timeout
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m_buserr[0] &= ~0x8000; // read
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m_buserr[1] = 0xffc00000;
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return 0;
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}
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FLOPPY_FORMATS_MEMBER( sun4_state::floppy_formats )
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FLOPPY_PC_FORMAT
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FLOPPY_FORMATS_END
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@ -2035,7 +2013,7 @@ MACHINE_CONFIG_START(sun4_state::sun4)
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RAM(config, RAM_TAG).set_default_size("16M").set_default_value(0x00);
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MCFG_DEVICE_ADD(TIMEKEEPER_TAG, MK48T12, 0)
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M48T02(config, TIMEKEEPER_TAG, 0);
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MCFG_N82077AA_ADD(FDC_TAG, n82077aa_device::MODE_PS2)
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MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun4_state::floppy_formats)
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@ -2095,7 +2073,7 @@ MACHINE_CONFIG_START(sun4_state::sun4c)
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RAM(config, RAM_TAG).set_default_size("16M").set_default_value(0x00);
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MCFG_DEVICE_ADD(TIMEKEEPER_TAG, MK48T12, 0)
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M48T02(config, TIMEKEEPER_TAG, 0);
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MCFG_N82077AA_ADD(FDC_TAG, n82077aa_device::MODE_PS2)
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MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun4_state::floppy_formats)
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