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trs80.cpp: Derive almost all clocks from actual XTALs, including screen raw parameters

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- UART modernization (nw)
This commit is contained in:
AJR 2018-03-05 23:02:07 -05:00
parent 365b55e915
commit 69ea9be761
4 changed files with 78 additions and 90 deletions
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3
src/emu/xtal.cpp
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@ -138,6 +138,7 @@ const double XTAL::known_xtals[] = {
10'380'000, /* 10.38_MHz_XTAL Fairlight Q219 Lightpen/Graphics Card */
10'500'000, /* 10.5_MHz_XTAL Agat-7 */
10'595'000, /* 10.595_MHz_XTAL Mad Alien */
10'644'500, /* 10.6445_MHz_XTAL TRS-80 Model I */
10'687'500, /* 10.6875_MHz_XTAL BBC Bridge Companion */
10'694'250, /* 10.69425_MHz_XTAL Xerox 820 */
10'717'200, /* 10.7172_MHz_XTAL Eltec EurocomII */
@ -163,6 +164,7 @@ const double XTAL::known_xtals[] = {
12'472'500, /* 12.4725_MHz_XTAL Bonanza's Mini Boy 7 */
12'480'000, /* 12.48_MHz_XTAL TRS-80 Model II */
12'500'000, /* 12.5_MHz_XTAL Red Alert audio board */
12'672'000, /* 12.672_MHz_XTAL TRS-80 Model 4 80*24 video */
12'800'000, /* 12.8_MHz_XTAL Cave CV1000 */
12'854'400, /* 12.8544_MHz_XTAL Alphatronic P3 */
12'979'200, /* 12.9792_MHz_XTAL Exidy 440 */
@ -224,6 +226,7 @@ const double XTAL::known_xtals[] = {
19'968'000, /* 19.968_MHz_XTAL Used mostly by some Taito games */
20'000'000, /* 20_MHz_XTAL - */
20'160'000, /* 20.16_MHz_XTAL Nintendo 8080 */
20'275'200, /* 20.2752_MHz_XTAL TRS-80 Model III */
20'625'000, /* 20.625_MHz_XTAL SM 7238 */
20'790'000, /* 20.79_MHz_XTAL Blockade-hardware Gremlin games */
21'000'000, /* 21_MHz_XTAL Lock-On pixel clock */

99
src/mame/drivers/trs80.cpp
View File

@ -161,7 +161,7 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(trs80_state::model1_map)
AM_RANGE(0x0000, 0x377f) AM_ROM // sys80,ht1080 needs up to 375F
AM_RANGE(0x37de, 0x37de) AM_READWRITE(sys80_f9_r, sys80_f8_w)
AM_RANGE(0x37df, 0x37df) AM_READWRITE(trs80m4_eb_r, trs80m4_eb_w)
AM_RANGE(0x37df, 0x37df) AM_DEVREADWRITE("uart", ay31015_device, receive, transmit)
AM_RANGE(0x37e0, 0x37e3) AM_READWRITE(trs80_irq_status_r, trs80_motor_w)
AM_RANGE(0x37e4, 0x37e7) AM_WRITE(trs80_cassunit_w)
AM_RANGE(0x37e8, 0x37eb) AM_READWRITE(trs80_printer_r, trs80_printer_w)
@ -184,8 +184,8 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(trs80_state::sys80_io)
ADDRESS_MAP_GLOBAL_MASK(0xff)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0xf8, 0xf8) AM_READWRITE(trs80m4_eb_r, sys80_f8_w)
AM_RANGE(0xf9, 0xf9) AM_READWRITE(sys80_f9_r, trs80m4_eb_w)
AM_RANGE(0xf8, 0xf8) AM_DEVREAD("uart", ay31015_device, receive) AM_WRITE(sys80_f8_w)
AM_RANGE(0xf9, 0xf9) AM_READ(sys80_f9_r) AM_DEVWRITE("uart", ay31015_device, transmit)
AM_RANGE(0xfd, 0xfd) AM_READWRITE(trs80_printer_r, trs80_printer_w)
AM_RANGE(0xfe, 0xfe) AM_WRITE(sys80_fe_w)
AM_RANGE(0xff, 0xff) AM_READWRITE(trs80_ff_r, trs80_ff_w)
@ -201,7 +201,7 @@ ADDRESS_MAP_START(trs80_state::lnw80_io)
AM_RANGE(0xe8, 0xe8) AM_READWRITE(trs80m4_e8_r, trs80m4_e8_w)
AM_RANGE(0xe9, 0xe9) AM_READ_PORT("E9")
AM_RANGE(0xea, 0xea) AM_READWRITE(trs80m4_ea_r, trs80m4_ea_w)
AM_RANGE(0xeb, 0xeb) AM_READWRITE(trs80m4_eb_r, trs80m4_eb_w)
AM_RANGE(0xeb, 0xeb) AM_DEVREADWRITE("uart", ay31015_device, receive, transmit)
AM_RANGE(0xfe, 0xfe) AM_READWRITE(lnw80_fe_r, lnw80_fe_w)
AM_RANGE(0xff, 0xff) AM_READWRITE(trs80_ff_r, trs80_ff_w)
ADDRESS_MAP_END
@ -217,7 +217,7 @@ ADDRESS_MAP_START(trs80_state::model3_io)
AM_RANGE(0xe8, 0xe8) AM_READWRITE(trs80m4_e8_r, trs80m4_e8_w)
AM_RANGE(0xe9, 0xe9) AM_READ_PORT("E9") AM_WRITE(trs80m4_e9_w)
AM_RANGE(0xea, 0xea) AM_READWRITE(trs80m4_ea_r, trs80m4_ea_w)
AM_RANGE(0xeb, 0xeb) AM_READWRITE(trs80m4_eb_r, trs80m4_eb_w)
AM_RANGE(0xeb, 0xeb) AM_DEVREADWRITE("uart", ay31015_device, receive, transmit)
AM_RANGE(0xec, 0xef) AM_READWRITE(trs80m4_ec_r, trs80m4_ec_w)
AM_RANGE(0xf0, 0xf0) AM_READ(trs80_wd179x_r)
AM_RANGE(0xf0, 0xf0) AM_DEVWRITE("fdc", fd1793_device, cmd_w)
@ -240,7 +240,7 @@ ADDRESS_MAP_START(trs80_state::model4_io)
AM_RANGE(0xe8, 0xe8) AM_READWRITE(trs80m4_e8_r, trs80m4_e8_w)
AM_RANGE(0xe9, 0xe9) AM_READ_PORT("E9") AM_WRITE(trs80m4_e9_w)
AM_RANGE(0xea, 0xea) AM_READWRITE(trs80m4_ea_r, trs80m4_ea_w)
AM_RANGE(0xeb, 0xeb) AM_READWRITE(trs80m4_eb_r, trs80m4_eb_w)
AM_RANGE(0xeb, 0xeb) AM_DEVREADWRITE("uart", ay31015_device, receive, transmit)
AM_RANGE(0xec, 0xef) AM_READWRITE(trs80m4_ec_r, trs80m4_ec_w)
AM_RANGE(0xf0, 0xf0) AM_READ(trs80_wd179x_r)
AM_RANGE(0xf0, 0xf0) AM_DEVWRITE("fdc", fd1793_device, cmd_w)
@ -264,7 +264,7 @@ ADDRESS_MAP_START(trs80_state::model4p_io)
AM_RANGE(0xe8, 0xe8) AM_READWRITE(trs80m4_e8_r, trs80m4_e8_w)
AM_RANGE(0xe9, 0xe9) AM_READ_PORT("E9") AM_WRITE(trs80m4_e9_w)
AM_RANGE(0xea, 0xea) AM_READWRITE(trs80m4_ea_r, trs80m4_ea_w)
AM_RANGE(0xeb, 0xeb) AM_READWRITE(trs80m4_eb_r, trs80m4_eb_w)
AM_RANGE(0xeb, 0xeb) AM_DEVREADWRITE("uart", ay31015_device, receive, transmit)
AM_RANGE(0xec, 0xef) AM_READWRITE(trs80m4_ec_r, trs80m4_ec_w)
AM_RANGE(0xf0, 0xf0) AM_READ(trs80_wd179x_r)
AM_RANGE(0xf0, 0xf0) AM_DEVWRITE("fdc", fd1793_device, cmd_w)
@ -310,7 +310,7 @@ ADDRESS_MAP_START(trs80_state::cp500_io)
AM_RANGE(0xe8, 0xe8) AM_READWRITE(trs80m4_e8_r, trs80m4_e8_w)
AM_RANGE(0xe9, 0xe9) AM_READ_PORT("E9") AM_WRITE(trs80m4_e9_w)
AM_RANGE(0xea, 0xea) AM_READWRITE(trs80m4_ea_r, trs80m4_ea_w)
AM_RANGE(0xeb, 0xeb) AM_READWRITE(trs80m4_eb_r, trs80m4_eb_w)
AM_RANGE(0xeb, 0xeb) AM_DEVREADWRITE("uart", ay31015_device, receive, transmit)
AM_RANGE(0xec, 0xef) AM_READWRITE(trs80m4_ec_r, trs80m4_ec_w)
AM_RANGE(0xf0, 0xf0) AM_READ(trs80_wd179x_r)
AM_RANGE(0xf0, 0xf0) AM_DEVWRITE("fdc", fd1793_device, cmd_w)
@ -593,17 +593,13 @@ SLOT_INTERFACE_END
MACHINE_CONFIG_START(trs80_state::trs80) // the original model I, level I, with no extras
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", Z80, 1796000) /* 1.796 MHz */
MCFG_CPU_ADD("maincpu", Z80, 10.6445_MHz_XTAL / 6) // "a little over 1.744 MHz"
MCFG_CPU_PROGRAM_MAP(trs80_map)
MCFG_CPU_IO_MAP(trs80_io)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MCFG_SCREEN_SIZE(64*6, 16*12)
MCFG_SCREEN_VISIBLE_AREA(0,64*6-1,0,16*12-1)
MCFG_SCREEN_RAW_PARAMS(10.6445_MHz_XTAL, 672, 0, 384, 264, 0, 192)
MCFG_SCREEN_UPDATE_DRIVER(trs80_state, screen_update_trs80)
MCFG_SCREEN_PALETTE("palette")
@ -618,24 +614,24 @@ MACHINE_CONFIG_START(trs80_state::trs80) // the original model I, level I,
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.05)
/* devices */
MCFG_CASSETTE_ADD( "cassette" )
MCFG_CASSETTE_ADD("cassette")
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::model1) // model I, level II
trs80(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_PROGRAM_MAP( model1_map)
MCFG_CPU_IO_MAP( model1_io)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(model1_map)
MCFG_CPU_IO_MAP(model1_io)
MCFG_CPU_PERIODIC_INT_DRIVER(trs80_state, trs80_rtc_interrupt, 40)
/* devices */
MCFG_CASSETTE_MODIFY( "cassette" )
MCFG_CASSETTE_MODIFY("cassette")
MCFG_CASSETTE_FORMATS(trs80l2_cassette_formats)
MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_PLAY)
MCFG_QUICKLOAD_ADD("quickload", trs80_state, trs80_cmd, "cmd", 0.5)
MCFG_FD1793_ADD("fdc", XTAL(1'000'000)) // todo: should be fd1771
MCFG_FD1793_ADD("fdc", 4_MHz_XTAL / 4) // todo: should be fd1771
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(trs80_state,trs80_fdc_intrq_w))
MCFG_FLOPPY_DRIVE_ADD("fdc:0", trs80_floppies, "sssd", trs80_state::floppy_formats)
@ -655,44 +651,45 @@ MACHINE_CONFIG_START(trs80_state::model1) // model I, level II
MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
MCFG_DEVICE_ADD( "tr1602", AY31015, 0 )
MCFG_DEVICE_ADD("uart", AY31015, 0)
MCFG_AY31015_RX_CLOCK(0.0)
MCFG_AY31015_TX_CLOCK(0.0)
MCFG_AY31015_AUTO_RDAV(true)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::model3)
model1(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_PROGRAM_MAP( model3_map)
MCFG_CPU_IO_MAP( model3_io)
MCFG_CPU_PERIODIC_INT_DRIVER(trs80_state, trs80_rtc_interrupt, 30)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CLOCK(20.2752_MHz_XTAL / 10)
MCFG_CPU_PROGRAM_MAP(model3_map)
MCFG_CPU_IO_MAP(model3_io)
MCFG_CPU_PERIODIC_INT_DRIVER(trs80_state, trs80_rtc_interrupt, 20.2752_MHz_XTAL / 10 / 67584)
MCFG_MACHINE_RESET_OVERRIDE(trs80_state, trs80m4 )
MCFG_MACHINE_RESET_OVERRIDE(trs80_state, trs80m4)
MCFG_GFXDECODE_MODIFY("gfxdecode",trs80m4)
MCFG_GFXDECODE_MODIFY("gfxdecode", trs80m4)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(trs80_state, screen_update_trs80m4)
MCFG_SCREEN_SIZE(80*8, 240)
MCFG_SCREEN_VISIBLE_AREA(0,80*8-1,0,239)
MCFG_SCREEN_RAW_PARAMS(12.672_MHz_XTAL, 800, 0, 640, 264, 0, 240)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::model4)
model3(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_IO_MAP( model4_io)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_IO_MAP(model4_io)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::model4p)
model3(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_IO_MAP( model4p_io)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_IO_MAP(model4p_io)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::sys80)
model1(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_IO_MAP( sys80_io)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_IO_MAP(sys80_io)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::ht1080z)
@ -704,10 +701,11 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::lnw80)
model1(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_PROGRAM_MAP( lnw80_map)
MCFG_CPU_IO_MAP( lnw80_io)
MCFG_MACHINE_RESET_OVERRIDE(trs80_state, lnw80 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CLOCK(16_MHz_XTAL / 4) // or 16MHz / 9
MCFG_CPU_PROGRAM_MAP(lnw80_map)
MCFG_CPU_IO_MAP(lnw80_io)
MCFG_MACHINE_RESET_OVERRIDE(trs80_state, lnw80)
MCFG_GFXDECODE_MODIFY("gfxdecode",lnw80)
@ -715,25 +713,28 @@ MACHINE_CONFIG_START(trs80_state::lnw80)
MCFG_PALETTE_ENTRIES(8)
MCFG_PALETTE_INIT_OWNER(trs80_state,lnw80)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_SIZE(80*6, 16*12)
MCFG_SCREEN_VISIBLE_AREA(0,80*6-1,0,16*12-1)
MCFG_SCREEN_RAW_PARAMS(3.579545_MHz_XTAL * 3, 682, 0, 480, 264, 0, 192)
// LNW80 Theory of Operations gives H and V periods as 15.750kHz and 59.66Hz, which don't seem exactly divisible
MCFG_SCREEN_UPDATE_DRIVER(trs80_state, screen_update_lnw80)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::radionic)
model1(config);
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CLOCK(12_MHz_XTAL / 6) // or 3.579MHz / 2
MCFG_CPU_PERIODIC_INT_DRIVER(trs80_state, nmi_line_pulse, 12_MHz_XTAL / 12 / 16384)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_SIZE(64*8, 16*16)
MCFG_SCREEN_VISIBLE_AREA(0,64*8-1,0,16*16-1)
MCFG_SCREEN_RAW_PARAMS(12_MHz_XTAL, 768, 0, 512, 312, 0, 256)
MCFG_SCREEN_UPDATE_DRIVER(trs80_state, screen_update_radionic)
MCFG_GFXDECODE_MODIFY("gfxdecode", radionic)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::meritum)
sys80(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_PROGRAM_MAP( meritum_map)
MCFG_CPU_IO_MAP( meritum_io)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(meritum_map)
MCFG_CPU_IO_MAP(meritum_io)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(trs80_state, screen_update_meritum)
MCFG_GFXDECODE_MODIFY("gfxdecode", meritum)
@ -741,10 +742,10 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(trs80_state::cp500)
model3(config);
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_IO_MAP( cp500_io)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_IO_MAP(cp500_io)
MCFG_MACHINE_RESET_OVERRIDE(trs80_state, cp500 )
MCFG_MACHINE_RESET_OVERRIDE(trs80_state, cp500)
MACHINE_CONFIG_END
/***************************************************************************

6
src/mame/includes/trs80.h
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@ -37,7 +37,7 @@ public:
, m_centronics(*this, "centronics")
, m_cent_data_out(*this, "cent_data_out")
, m_cent_status_in(*this, "cent_status_in")
, m_ay31015(*this, "tr1602")
, m_uart(*this, "uart")
, m_fdc(*this, "fdc")
, m_floppy0(*this, "fdc:0")
, m_floppy1(*this, "fdc:1")
@ -75,7 +75,6 @@ public:
DECLARE_WRITE8_MEMBER ( trs80m4_ff_w );
DECLARE_WRITE8_MEMBER ( trs80m4_f4_w );
DECLARE_WRITE8_MEMBER ( trs80m4_ec_w );
DECLARE_WRITE8_MEMBER ( trs80m4_eb_w );
DECLARE_WRITE8_MEMBER ( trs80m4_ea_w );
DECLARE_WRITE8_MEMBER ( trs80m4_e9_w );
DECLARE_WRITE8_MEMBER ( trs80m4_e8_w );
@ -89,7 +88,6 @@ public:
DECLARE_READ8_MEMBER ( sys80_f9_r );
DECLARE_READ8_MEMBER ( trs80m4_ff_r );
DECLARE_READ8_MEMBER ( trs80m4_ec_r );
DECLARE_READ8_MEMBER ( trs80m4_eb_r );
DECLARE_READ8_MEMBER ( trs80m4_ea_r );
DECLARE_READ8_MEMBER ( trs80m4_e8_r );
DECLARE_READ8_MEMBER ( trs80m4_e4_r );
@ -189,7 +187,7 @@ private:
optional_device<centronics_device> m_centronics;
optional_device<output_latch_device> m_cent_data_out;
optional_device<input_buffer_device> m_cent_status_in;
optional_device<ay31015_device> m_ay31015;
optional_device<ay31015_device> m_uart;
optional_device<fd1793_device> m_fdc;
optional_device<floppy_connector> m_floppy0;
optional_device<floppy_connector> m_floppy1;

60
src/mame/machine/trs80.cpp
View File

@ -126,26 +126,17 @@ READ8_MEMBER( trs80_state::trs80m4_ea_r )
d2..d0 Not used */
uint8_t data=7;
m_ay31015->write_swe(0);
data |= m_ay31015->tbmt_r() ? 0x40 : 0;
data |= m_ay31015->dav_r( ) ? 0x80 : 0;
data |= m_ay31015->or_r( ) ? 0x20 : 0;
data |= m_ay31015->fe_r( ) ? 0x10 : 0;
data |= m_ay31015->pe_r( ) ? 0x08 : 0;
m_ay31015->write_swe(1);
m_uart->write_swe(0);
data |= m_uart->tbmt_r() ? 0x40 : 0;
data |= m_uart->dav_r( ) ? 0x80 : 0;
data |= m_uart->or_r( ) ? 0x20 : 0;
data |= m_uart->fe_r( ) ? 0x10 : 0;
data |= m_uart->pe_r( ) ? 0x08 : 0;
m_uart->write_swe(1);
return data;
}
READ8_MEMBER( trs80_state::trs80m4_eb_r )
{
/* UART received data */
uint8_t data = m_ay31015->get_received_data();
m_ay31015->write_rdav(0);
m_ay31015->write_rdav(1);
return data;
}
READ8_MEMBER( trs80_state::trs80m4_ec_r )
{
/* Reset the RTC interrupt */
@ -166,13 +157,13 @@ READ8_MEMBER( trs80_state::sys80_f9_r )
d0 Data Available */
uint8_t data = 70;
m_ay31015->write_swe(0);
data |= m_ay31015->tbmt_r() ? 0 : 0x80;
data |= m_ay31015->dav_r( ) ? 0x01 : 0;
data |= m_ay31015->or_r( ) ? 0x02 : 0;
data |= m_ay31015->fe_r( ) ? 0x04 : 0;
data |= m_ay31015->pe_r( ) ? 0x08 : 0;
m_ay31015->write_swe(1);
m_uart->write_swe(0);
data |= m_uart->tbmt_r() ? 0 : 0x80;
data |= m_uart->dav_r( ) ? 0x01 : 0;
data |= m_uart->or_r( ) ? 0x02 : 0;
data |= m_uart->fe_r( ) ? 0x04 : 0;
data |= m_uart->pe_r( ) ? 0x08 : 0;
m_uart->write_swe(1);
return data;
}
@ -443,8 +434,8 @@ Note: this may be a COM5016 dual baud rate generator, or may be an equivalent ci
*/
static const int baud_clock[]={ 800, 1200, 1760, 2152, 2400, 4800, 9600, 19200, 28800, 32000, 38400, 57600, 76800, 115200, 153600, 307200 };
m_ay31015->set_receiver_clock(baud_clock[data & 0x0f]);
m_ay31015->set_transmitter_clock(baud_clock[data >> 4]);
m_uart->set_receiver_clock(baud_clock[data & 0x0f]);
m_uart->set_transmitter_clock(baud_clock[data >> 4]);
}
WRITE8_MEMBER( trs80_state::trs80m4_ea_w )
@ -464,13 +455,13 @@ WRITE8_MEMBER( trs80_state::trs80m4_ea_w )
d0 Data-Terminal-Ready (DTR), pin 20 */
{
m_ay31015->write_cs(0);
m_ay31015->write_nb1(BIT(data, 6));
m_ay31015->write_nb2(BIT(data, 5));
m_ay31015->write_tsb(BIT(data, 4));
m_ay31015->write_eps(BIT(data, 7));
m_ay31015->write_np(BIT(data, 3));
m_ay31015->write_cs(1);
m_uart->write_cs(0);
m_uart->write_nb1(BIT(data, 6));
m_uart->write_nb2(BIT(data, 5));
m_uart->write_tsb(BIT(data, 4));
m_uart->write_eps(BIT(data, 7));
m_uart->write_np(BIT(data, 3));
m_uart->write_cs(1);
}
else
{
@ -486,11 +477,6 @@ WRITE8_MEMBER( trs80_state::trs80m4_ea_w )
}
}
WRITE8_MEMBER( trs80_state::trs80m4_eb_w )
{
m_ay31015->set_transmit_data(data);
}
WRITE8_MEMBER( trs80_state::trs80m4_ec_w )
{
/* Hardware settings - d5..d4 not emulated