mirror of
https://github.com/holub/mame
synced 2025-07-03 00:56:03 +03:00
-dpb_storeaddr: Finished implementation, not yet tested, nw
This commit is contained in:
MooglyGuy
parent
a16e78a78b
commit
69fe70f815
@ -41,6 +41,8 @@ dpb7000_storeaddr_card_device::dpb7000_storeaddr_card_device(const machine_confi
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, m_bd_out(0)
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, m_protx(false)
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, m_proty(false)
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, m_delay_timer(nullptr)
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, m_delay_step(0)
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, m_df_out(0)
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, m_ee_out(0)
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, m_addr(0)
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@ -80,6 +82,12 @@ dpb7000_storeaddr_card_device::dpb7000_storeaddr_card_device(const machine_confi
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, m_cread(false)
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, m_prot_a(false)
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, m_prot_b(false)
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, m_preread(false)
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, m_rreq_pending(false)
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, m_rreq_active(false)
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, m_creq_pending(false)
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, m_creq_active(false)
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, m_store_busy(false)
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, m_rvl(false)
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, m_rhr(false)
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, m_plt(false)
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@ -88,7 +96,15 @@ dpb7000_storeaddr_card_device::dpb7000_storeaddr_card_device(const machine_confi
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, m_rb(false)
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, m_pflag(false)
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, m_mxr(false)
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, m_rc_sel(false)
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, m_ras(false)
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, m_cas(false)
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, m_laac(false)
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, m_t6(false)
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, m_clrw(false)
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, m_opstr(false)
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, m_cck_clear(false)
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, m_creq_sel(false)
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, m_write_active(false)
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, m_window_enable(false)
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, m_b26(false)
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, m_blank_d(false)
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@ -101,12 +117,27 @@ dpb7000_storeaddr_card_device::dpb7000_storeaddr_card_device(const machine_confi
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, m_rck(false)
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, m_ra(0)
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, m_opra(false)
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, m_opwa(false)
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, m_opwb(false)
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, m_cck(false)
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, m_csel(false)
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, m_ipsel_out(*this)
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, m_rck_out(*this)
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, m_ra_out(*this)
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, m_opra_out(*this)
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, m_oprb_out(*this)
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, m_blk_out(*this)
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, m_addr_out(*this)
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, m_r_busy_out(*this)
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, m_ras_out(*this)
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, m_cas_out(*this)
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, m_opwb_out(*this)
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, m_opstr_out(*this)
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, m_w_out(*this)
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, m_opwa_out(*this)
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, m_csel_out(*this)
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, m_cck_out(*this)
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, m_cbusy_out(*this)
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, m_x_prom(*this, "x_prom")
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, m_protx_prom(*this, "protx_prom")
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, m_proty_prom(*this, "proty_prom")
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@ -143,6 +174,8 @@ void dpb7000_storeaddr_card_device::device_start()
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save_item(NAME(m_protx));
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save_item(NAME(m_proty));
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save_item(NAME(m_delay_step));
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save_item(NAME(m_df_in));
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save_item(NAME(m_df_out));
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save_item(NAME(m_ee_in));
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@ -200,6 +233,13 @@ void dpb7000_storeaddr_card_device::device_start()
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save_item(NAME(m_prot_a));
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save_item(NAME(m_prot_b));
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save_item(NAME(m_preread));
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save_item(NAME(m_rreq_pending));
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save_item(NAME(m_rreq_active));
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save_item(NAME(m_creq_pending));
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save_item(NAME(m_creq_active));
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save_item(NAME(m_store_busy));
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save_item(NAME(m_rvl));
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save_item(NAME(m_rhr));
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save_item(NAME(m_plt));
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@ -209,7 +249,18 @@ void dpb7000_storeaddr_card_device::device_start()
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save_item(NAME(m_pflag));
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save_item(NAME(m_mxr));
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save_item(NAME(m_rc_sel));
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save_item(NAME(m_ras));
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save_item(NAME(m_cas));
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save_item(NAME(m_store_busy));
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save_item(NAME(m_laac));
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save_item(NAME(m_t6));
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save_item(NAME(m_clrw));
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save_item(NAME(m_opstr));
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save_item(NAME(m_cck_clear));
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save_item(NAME(m_creq_sel));
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save_item(NAME(m_write_active));
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save_item(NAME(m_window_enable));
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save_item(NAME(m_b26));
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@ -226,13 +277,32 @@ void dpb7000_storeaddr_card_device::device_start()
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save_item(NAME(m_rck));
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save_item(NAME(m_ra));
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save_item(NAME(m_opra));
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save_item(NAME(m_opwa));
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save_item(NAME(m_opwb));
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save_item(NAME(m_clrw));
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save_item(NAME(m_cck));
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save_item(NAME(m_csel));
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m_ipsel_out.resolve_safe();
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m_rck_out.resolve_safe();
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m_ra_out.resolve_safe();
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m_opra_out.resolve_safe();
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m_oprb_out.resolve_safe();
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m_blk_out.resolve_safe();
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m_addr_out.resolve_safe();
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m_r_busy_out.resolve_safe();
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m_ras_out.resolve_safe();
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m_cas_out.resolve_safe();
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m_opwb_out.resolve_safe();
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m_opstr_out.resolve_safe();
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m_w_out.resolve_safe();
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m_opwa_out.resolve_safe();
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m_csel_out.resolve_safe();
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m_cck_out.resolve_safe();
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m_cbusy_out.resolve_safe();
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m_delay_timer = timer_alloc(DELAY_TIMER);
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m_delay_timer->adjust(attotime::never);
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}
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void dpb7000_storeaddr_card_device::device_reset()
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@ -243,6 +313,9 @@ void dpb7000_storeaddr_card_device::device_reset()
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m_protx = false;
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m_proty = false;
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m_delay_timer->adjust(attotime::never);
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m_delay_step = 0;
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memset(m_df_in, 0, 2);
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m_df_in[1] = 0xc;
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m_df_out = 0;
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@ -304,6 +377,13 @@ void dpb7000_storeaddr_card_device::device_reset()
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m_prot_a = false;
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m_prot_b = false;
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m_preread = false;
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m_rreq_pending = false;
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m_rreq_active = false;
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m_creq_pending = false;
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m_creq_active = false;
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m_store_busy = false;
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m_rvl = false;
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m_rhr = false;
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m_plt = false;
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@ -313,7 +393,18 @@ void dpb7000_storeaddr_card_device::device_reset()
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m_pflag = false;
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m_mxr = false;
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m_rc_sel = false;
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m_ras = false;
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m_cas = false;
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m_store_busy = false;
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m_laac = false;
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m_t6 = false;
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m_clrw = false;
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m_opstr = false;
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m_cck_clear = false;
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m_creq_sel = false;
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m_write_active = false;
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m_window_enable = false;
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m_b26 = false;
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@ -330,6 +421,11 @@ void dpb7000_storeaddr_card_device::device_reset()
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m_rck = false;
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m_ra = 0;
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m_opra = false;
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m_opwa = false;
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m_opwb = false;
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m_clrw = false;
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m_cck = false;
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m_csel = false;
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m_bb_base = m_x_prom->base() + 0x000;
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m_bc_base = m_x_prom->base() + 0x400;
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@ -339,6 +435,202 @@ void dpb7000_storeaddr_card_device::device_reset()
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m_blanking_base = m_blanking_pal->base();
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}
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void dpb7000_storeaddr_card_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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if (id == DELAY_TIMER)
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{
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tick_delay_step();
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}
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}
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void dpb7000_storeaddr_card_device::tick_delay_step()
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{
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m_delay_step++;
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switch (m_delay_step & 15)
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{
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case 1:
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ras_w(true);
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break;
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case 3:
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mxr_w(false);
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break;
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case 5:
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cas_w(true);
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break;
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case 6:
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t6_w(true);
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break;
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case 10:
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t6_w(false);
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laac_w(true);
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break;
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case 11:
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ras_w(false);
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break;
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case 12:
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cas_w(false);
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laac_w(false);
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break;
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case 13:
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clrw_w(true);
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break;
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case 14:
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clrw_w(false);
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break;
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case 15:
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default:
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// Do nothing
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break;
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}
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}
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void dpb7000_storeaddr_card_device::mxr_w(bool state)
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{
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m_mxr = state;
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update_addr_select_outputs();
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}
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void dpb7000_storeaddr_card_device::opwb_w(bool state)
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{
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const bool old = m_opwb;
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m_opwb = state;
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if (old != m_opwb)
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{
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m_opwb_out(!m_opwb);
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update_r_busy(m_ras);
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m_opwa_out(!(m_opwb || BIT(m_rhscr_stripe_num, 0)));
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}
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}
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void dpb7000_storeaddr_card_device::update_opwa()
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{
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const bool old = m_opwa;
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m_opwa = !(m_opwb || BIT(m_rhscr_stripe_num, 0));
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if (old != m_opwa)
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{
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m_opwa_out(m_opwa);
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update_req_clears();
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}
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}
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void dpb7000_storeaddr_card_device::update_req_clears()
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{
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if (m_laac)
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{
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if (m_opwa)
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{
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m_creq_pending = false;
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m_creq_active = false;
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}
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else
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{
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m_rreq_pending = false;
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m_rreq_active = false;
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}
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}
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}
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void dpb7000_storeaddr_card_device::update_opstr()
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{
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const bool old = m_opstr;
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m_opstr = !(m_t6 && !m_write_active);
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if (old != m_opstr)
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{
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m_opstr_out(m_opstr);
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}
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}
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void dpb7000_storeaddr_card_device::update_cck()
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{
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const bool old_clear = m_cck_clear;
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m_cck_clear = !(m_opwb && m_t6);
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if (old_clear != m_cck_clear)
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{
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const bool old_csel = m_csel;
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m_csel = BIT(m_cx_stripe_addr, 0);
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if (old_csel != m_csel)
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{
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m_csel_out(m_csel);
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}
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}
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const bool old = m_cck;
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m_cck = !m_cck_clear;
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if (old != m_cck)
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{
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m_cck_out(m_cck);
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}
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}
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void dpb7000_storeaddr_card_device::ras_w(bool state)
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{
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const bool old_ras = m_ras;
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m_ras = state;
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if (old_ras != m_ras)
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{
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m_ras_out(!m_ras);
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update_r_busy(old_ras);
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}
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}
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void dpb7000_storeaddr_card_device::update_r_busy(bool old_ras)
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{
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const bool old_r_busy = m_opwb || !old_ras;
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const bool r_busy = m_opwb || !m_ras;
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if (old_r_busy != r_busy)
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{
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m_r_busy_out(r_busy);
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}
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}
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void dpb7000_storeaddr_card_device::cas_w(bool state)
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{
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const bool old_cas = m_cas;
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m_cas = state;
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if (old_cas != m_cas)
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{
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m_cas_out(!m_cas);
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}
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}
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void dpb7000_storeaddr_card_device::laac_w(bool state)
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{
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const bool old_laac = m_laac;
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m_laac = state;
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if (old_laac != m_laac)
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{
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update_req_clears();
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}
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}
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void dpb7000_storeaddr_card_device::t6_w(bool state)
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{
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const bool old = m_t6;
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m_t6 = state;
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if (old != m_t6)
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{
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update_opstr();
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update_cck();
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}
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}
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void dpb7000_storeaddr_card_device::clrw_w(bool state)
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{
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const bool old = m_clrw;
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m_clrw = state;
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if (old != m_clrw)
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{
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if (m_clrw)
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{
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opwb_w(false);
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m_write_active = false;
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update_opstr();
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}
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}
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}
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void dpb7000_storeaddr_card_device::reg_w(uint16_t data)
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{
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switch ((data >> 12) & 7)
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@ -595,17 +887,33 @@ void dpb7000_storeaddr_card_device::cyoen_w(int state)
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void dpb7000_storeaddr_card_device::clrc_w(int state)
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{
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const bool old = m_clrc;
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m_clrc = (bool)state;
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if (old != m_clrc && !m_clrc)
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{
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m_creq_pending = false;
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m_creq_active = true;
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}
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}
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void dpb7000_storeaddr_card_device::selvideo_w(int state)
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{
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const bool old = m_selvideo;
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m_selvideo = (bool)state;
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if (!old && m_selvideo && BIT(m_cx_stripe_addr, 3))
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{
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request_c_read();
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}
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}
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void dpb7000_storeaddr_card_device::creq_w(int state)
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{
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const bool old = m_creq;
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m_creq = (bool)state;
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if (!old && m_creq)
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{
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request_c_read();
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}
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}
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void dpb7000_storeaddr_card_device::cr_w(int state)
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@ -613,6 +921,55 @@ void dpb7000_storeaddr_card_device::cr_w(int state)
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m_cread = (bool)state;
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}
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void dpb7000_storeaddr_card_device::request_r_read()
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{
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m_rreq_pending = true;
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check_r_read();
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}
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void dpb7000_storeaddr_card_device::check_r_read()
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{
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if (m_rreq_pending && !m_creq_active)
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{
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m_rreq_active = true;
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m_creq_sel = false;
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update_addr_select_outputs();
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check_cycle_start();
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}
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}
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void dpb7000_storeaddr_card_device::request_c_read()
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{
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const bool old = m_creq_pending;
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m_creq_pending = true;
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if (!old && m_creq_pending)
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{
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m_cbusy_out(!m_creq_pending);
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}
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check_c_read();
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}
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void dpb7000_storeaddr_card_device::check_c_read()
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{
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if (m_creq_pending && !m_rreq_active)
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{
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m_creq_active = true;
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m_creq_sel = true;
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update_addr_select_outputs();
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check_cycle_start();
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const bool old_write = m_write_active;
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m_write_active = !(m_protx || m_proty || m_cread || BIT(m_cy_addr, 10));
|
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if (old_write != m_write_active)
|
||||
{
|
||||
update_opstr();
|
||||
m_w_out(m_write_active);
|
||||
}
|
||||
|
||||
opwb_w(true);
|
||||
}
|
||||
}
|
||||
|
||||
void dpb7000_storeaddr_card_device::prot_a_w(int state)
|
||||
{
|
||||
const bool old = m_prot_a;
|
||||
@ -629,6 +986,26 @@ void dpb7000_storeaddr_card_device::prot_b_w(int state)
|
||||
update_prot_proms();
|
||||
}
|
||||
|
||||
void dpb7000_storeaddr_card_device::preread_w(int state)
|
||||
{
|
||||
const bool old = m_preread;
|
||||
m_preread = (bool)state;
|
||||
if (!old && m_preread)
|
||||
{
|
||||
request_r_read();
|
||||
}
|
||||
}
|
||||
|
||||
void dpb7000_storeaddr_card_device::check_cycle_start()
|
||||
{
|
||||
if ((m_creq_active || m_rreq_active) && !m_store_busy)
|
||||
{
|
||||
m_store_busy = true;
|
||||
mxr_w(true);
|
||||
m_delay_timer->adjust(attotime::from_nsec(25), 0, attotime::from_nsec(25));
|
||||
}
|
||||
}
|
||||
|
||||
void dpb7000_storeaddr_card_device::update_prot_proms()
|
||||
{
|
||||
const uint16_t m_x_addr = ((uint8_t)m_cx_stripe_num) | (m_prot_a ? 0x000 : 0x100) | (m_prot_b ? 0x000 : 0x200);
|
||||
@ -648,6 +1025,12 @@ void dpb7000_storeaddr_card_device::rhr_w(int state)
|
||||
m_rhr = (bool)state;
|
||||
if (old && !m_rhr)
|
||||
{
|
||||
if (!m_rhr)
|
||||
{
|
||||
m_rreq_pending = false;
|
||||
m_rreq_active = false;
|
||||
}
|
||||
|
||||
if (!m_plt && !m_rhr)
|
||||
{
|
||||
m_rvscr_counter = 0;
|
||||
@ -735,6 +1118,7 @@ void dpb7000_storeaddr_card_device::rppck_w(int state)
|
||||
|
||||
const uint8_t old_stripe_num = m_rhscr_stripe_num;
|
||||
m_rhscr_stripe_num++;
|
||||
update_opwa();
|
||||
update_blanking_pal();
|
||||
if ((old_stripe_num & 1) != (m_rhscr_stripe_num & 1) && m_rck)
|
||||
{
|
||||
@ -809,6 +1193,11 @@ void dpb7000_storeaddr_card_device::update_rck()
|
||||
if (old_rck != m_rck)
|
||||
{
|
||||
m_rck_out(m_rck);
|
||||
m_oprb_out(m_rck);
|
||||
if (!old_rck && m_rck)
|
||||
{
|
||||
update_cck();
|
||||
}
|
||||
|
||||
const uint8_t old_ra = m_ra;
|
||||
const bool old_opra = m_opra;
|
||||
@ -897,7 +1286,7 @@ void dpb7000_storeaddr_card_device::update_addr_select_inputs()
|
||||
|
||||
void dpb7000_storeaddr_card_device::update_addr_select_outputs()
|
||||
{
|
||||
const uint8_t sel = (m_mxr ? 1 : 0) | (m_rc_sel ? 2 : 0);
|
||||
const uint8_t sel = (m_mxr ? 1 : 0) | (m_creq_sel ? 2 : 0);
|
||||
const uint8_t old = m_addr;
|
||||
m_addr = BIT(m_dg_in[0], sel);
|
||||
m_addr |= BIT(m_dg_in[1], sel) << 1;
|
||||
|
||||
@ -51,6 +51,8 @@ public:
|
||||
void prot_a_w(int state);
|
||||
void prot_b_w(int state);
|
||||
|
||||
void preread_w(int state);
|
||||
|
||||
void rvl_w(int state);
|
||||
void rhr_w(int state);
|
||||
void plt_w(int state);
|
||||
@ -70,22 +72,49 @@ protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
|
||||
static constexpr device_timer_id DELAY_TIMER = 0;
|
||||
|
||||
void set_cxpos(uint16_t data);
|
||||
|
||||
void tick_cxck();
|
||||
void tick_cyck();
|
||||
|
||||
void update_r_busy(bool old_ras);
|
||||
|
||||
void update_blanking_pal();
|
||||
void update_prot_proms();
|
||||
void update_rck();
|
||||
void update_v0();
|
||||
void update_opwa();
|
||||
void update_opstr();
|
||||
void update_req_clears();
|
||||
void update_cck();
|
||||
|
||||
void update_addr_mux_inputs();
|
||||
void update_addr_mux_outputs();
|
||||
void update_addr_select_inputs();
|
||||
void update_addr_select_outputs();
|
||||
|
||||
void check_cycle_start();
|
||||
void tick_delay_step();
|
||||
|
||||
void request_r_read();
|
||||
void check_r_read();
|
||||
void request_c_read();
|
||||
void check_c_read();
|
||||
|
||||
void opwb_w(bool state);
|
||||
|
||||
// Timed control signals
|
||||
void mxr_w(bool state);
|
||||
void ras_w(bool state);
|
||||
void cas_w(bool state);
|
||||
void laac_w(bool state);
|
||||
void t6_w(bool state);
|
||||
void clrw_w(bool state);
|
||||
|
||||
uint8_t *m_bb_base;
|
||||
uint8_t *m_bc_base;
|
||||
uint8_t *m_bd_base;
|
||||
@ -99,6 +128,9 @@ protected:
|
||||
bool m_protx;
|
||||
bool m_proty;
|
||||
|
||||
emu_timer *m_delay_timer;
|
||||
uint8_t m_delay_step;
|
||||
|
||||
uint8_t m_df_in[2];
|
||||
uint8_t m_df_out;
|
||||
uint8_t m_ee_in[2];
|
||||
@ -157,6 +189,13 @@ protected:
|
||||
bool m_prot_a;
|
||||
bool m_prot_b;
|
||||
|
||||
bool m_preread;
|
||||
bool m_rreq_pending;
|
||||
bool m_rreq_active;
|
||||
bool m_creq_pending;
|
||||
bool m_creq_active;
|
||||
bool m_store_busy;
|
||||
|
||||
bool m_rvl;
|
||||
bool m_rhr;
|
||||
bool m_plt;
|
||||
@ -166,7 +205,17 @@ protected:
|
||||
bool m_pflag;
|
||||
|
||||
bool m_mxr;
|
||||
bool m_rc_sel;
|
||||
bool m_ras;
|
||||
bool m_cas;
|
||||
bool m_laac;
|
||||
bool m_t6;
|
||||
bool m_clrw;
|
||||
bool m_opstr;
|
||||
bool m_cck_clear;
|
||||
|
||||
bool m_creq_sel;
|
||||
|
||||
bool m_write_active;
|
||||
|
||||
bool m_window_enable;
|
||||
bool m_b26;
|
||||
@ -184,14 +233,29 @@ protected:
|
||||
bool m_rck;
|
||||
uint8_t m_ra;
|
||||
bool m_opra;
|
||||
bool m_opwa;
|
||||
bool m_opwb;
|
||||
bool m_cck;
|
||||
bool m_csel;
|
||||
|
||||
// Output Handlers
|
||||
devcb_write_line m_ipsel_out;
|
||||
devcb_write_line m_rck_out;
|
||||
devcb_write8 m_ra_out;
|
||||
devcb_write_line m_opra_out;
|
||||
devcb_write_line m_oprb_out;
|
||||
devcb_write_line m_blk_out;
|
||||
devcb_write8 m_addr_out;
|
||||
devcb_write_line m_r_busy_out;
|
||||
devcb_write_line m_ras_out;
|
||||
devcb_write_line m_cas_out;
|
||||
devcb_write_line m_opwb_out;
|
||||
devcb_write_line m_opstr_out;
|
||||
devcb_write_line m_w_out;
|
||||
devcb_write_line m_opwa_out;
|
||||
devcb_write_line m_csel_out;
|
||||
devcb_write_line m_cck_out;
|
||||
devcb_write_line m_cbusy_out;
|
||||
|
||||
// Devices
|
||||
required_memory_region m_x_prom;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user