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Cleaned up NES PPU interface and struct [Fabio Priuli]

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Fixed multigam & multigmb [Robert Bohms]
This commit is contained in:
Fabio Priuli 2009-08-01 12:08:52 +00:00
parent 3f4b8a9c42
commit 6ab50fc436
6 changed files with 29 additions and 41 deletions
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5
src/mame/drivers/cham24.c
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@ -265,7 +265,6 @@ static void ppu_irq( const device_config *device, int *ppu_regs )
/* our ppu interface */
static const ppu2c0x_interface ppu_interface =
{
"gfx1", /* vrom gfx region */
0, /* gfxlayout num */
0, /* color base */
PPU_MIRROR_NONE, /* mirroring */
@ -291,6 +290,10 @@ static DRIVER_INIT( cham24 )
/* need nametable ram, though. I doubt this uses more than 2k, but it starts up configured for 4 */
nt_ram = auto_alloc_array(machine, UINT8, 0x1000);
nt_page[0] = nt_ram;
nt_page[1] = nt_ram + 0x400;
nt_page[2] = nt_ram + 0x800;
nt_page[3] = nt_ram + 0xc00;
/* and read/write handlers */
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x2000, 0x3eff, 0, 0, nt_r, nt_w);

21
src/mame/drivers/multigam.c
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@ -50,6 +50,7 @@
PPU external bus interface
*******************************************************/
static UINT8* nt_ram;
static UINT8* nt_page[4];
@ -84,11 +85,14 @@ void set_mirroring(int mirroring)
break;
}
}
static WRITE8_HANDLER (multigam_nt_w)
{
int page = ((offset & 0xc00) >> 10);
nt_page[page][offset & 0x3ff] = data;
}
static READ8_HANDLER (multigam_nt_r)
{
int page = ((offset & 0xc00) >> 10);
@ -101,7 +105,7 @@ void set_videorom_bank(running_machine* machine, int start, int count, int bank,
int offset = bank * (bank_size_in_kb * 0x400);
/* bank_size_in_kb is used to determine how large the "bank" parameter is */
/* count determines the size of the area mapped in KB */
for (i = 0; i < count; i++)
for (i = 0; i < count; i++, offset += 0x400)
{
j = i + start + 1;
memory_set_bankptr(machine, j, memory_region(machine, "gfx1") + offset);
@ -214,7 +218,7 @@ static WRITE8_HANDLER(multigam_switch_prg_rom)
static WRITE8_HANDLER(multigam_switch_gfx_rom)
{
memory_set_bankptr(space->machine, 1, memory_region(space->machine, "gfx1") + (0x2000 * data));
memory_set_bankptr(space->machine, 1, memory_region(space->machine, "gfx1") + (0x2000 * (data & 0x3f)));
set_mirroring(data & 0x40 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
multigam_game_gfx_bank = data;
};
@ -601,7 +605,6 @@ static void ppu_irq( const device_config *device, int *ppu_regs )
/* our ppu interface */
static const ppu2c0x_interface ppu_interface =
{
"gfx1", /* vrom gfx region */
0, /* gfxlayout num */
0, /* color base */
PPU_MIRROR_NONE, /* mirroring */
@ -643,6 +646,11 @@ static MACHINE_RESET( multigm3 )
static MACHINE_START( multigam )
{
nt_ram = auto_alloc_array(machine, UINT8, 0x1000);
nt_page[0] = nt_ram;
nt_page[1] = nt_ram + 0x400;
nt_page[2] = nt_ram + 0x800;
nt_page[3] = nt_ram + 0xc00;
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x2000, 0x3eff, 0, 0, multigam_nt_r, multigam_nt_w);
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x0000, 0x1fff, 0, 0, SMH_BANK(1), 0);
memory_set_bankptr(machine, 1, memory_region(machine, "gfx1"));
@ -651,6 +659,11 @@ static MACHINE_START( multigam )
static MACHINE_START( multigm3 )
{
nt_ram = auto_alloc_array(machine, UINT8, 0x1000);
nt_page[0] = nt_ram;
nt_page[1] = nt_ram + 0x400;
nt_page[2] = nt_ram + 0x800;
nt_page[3] = nt_ram + 0xc00;
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x2000, 0x3eff, 0, 0, multigam_nt_r, multigam_nt_w);
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x0000, 0x03ff, 0, 0, SMH_BANK(1), 0);
@ -661,6 +674,8 @@ static MACHINE_START( multigm3 )
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x1400, 0x17ff, 0, 0, SMH_BANK(6), 0);
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x1800, 0x1bff, 0, 0, SMH_BANK(7), 0);
memory_install_readwrite8_handler(cpu_get_address_space(cputag_get_cpu(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x1c00, 0x1fff, 0, 0, SMH_BANK(8), 0);
set_videorom_bank(machine, 0, 8, 0, 8);
};
static MACHINE_DRIVER_START( multigam )

8
src/mame/video/playch10.c
View File

@ -69,22 +69,18 @@ static void ppu_irq( const device_config *device, int *ppu_regs )
const ppu2c0x_interface playch10_ppu_interface =
{
"gfx2", /* vrom gfx region */
1, /* gfxlayout num */
256, /* color base */
PPU_MIRROR_NONE, /* mirroring */
ppu_irq, /* irq */
0 /* vram */
ppu_irq /* irq */
};
const ppu2c0x_interface playch10_ppu_interface_hboard =
{
"gfx2", /* vrom gfx region */
1, /* gfxlayout num */
256, /* color base */
PPU_MIRROR_NONE, /* mirroring */
ppu_irq, /* irq */
1 /* vram */
ppu_irq /* irq */
};
static TILE_GET_INFO( get_bg_tile_info )

24
src/mame/video/ppu2c0x.c
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@ -80,8 +80,6 @@ static const pen_t default_colortable[] =
typedef struct
{
bitmap_t *bitmap; /* target bitmap */
UINT8 *videomem; /* video mem */
UINT8 *videoram; /* video ram */
UINT8 *spriteram; /* sprite ram */
pen_t *colortable; /* color table modified at run time */
pen_t *colortable_mono; /* monochromatic color table modified at run time */
@ -92,10 +90,6 @@ typedef struct
ppu2c0x_scanline_cb scanline_callback_proc; /* optional scanline callback */
ppu2c0x_hblank_cb hblank_callback_proc; /* optional hblank callback */
ppu2c0x_vidaccess_cb vidaccess_callback_proc;/* optional video access callback */
int has_videorom; /* whether we access a video rom or not */
int videorom_banks; /* number of banks in the videorom (if available) */
int has_videoram;
int videoram_banks_indices[0x2000/VIDEOMEM_PAGE_SIZE];
int regs[PPU_MAX_REG]; /* registers */
int refresh_data; /* refresh-related */
int refresh_latch; /* refresh-related */
@ -109,7 +103,6 @@ typedef struct
int tile_page; /* current tile page */
int sprite_page; /* current sprite page */
int back_color; /* background color */
UINT8 *ppu_page[4]; /* ppu pages */
int nes_vram[8]; /* keep track of 8 .5k vram pages to speed things up */
UINT8 palette_ram[0x20]; /* shouldn't be in main memory! */
int scan_scale; /* scan scale */
@ -179,7 +172,7 @@ INLINE const ppu2c0x_interface *get_interface( const device_config *device )
/* default address map */
// make this INTERNAL, default should just be enough to avoid compile errors, print error messages!
static ADDRESS_MAP_START( ppu2c0x, 0, 8 )
AM_RANGE(0x3f00, 0x3fff) AM_READWRITE (ppu2c0x_palette_read, ppu2c0x_palette_write)
AM_RANGE(0x3f00, 0x3fff) AM_READWRITE(ppu2c0x_palette_read, ppu2c0x_palette_write)
ADDRESS_MAP_END
void ppu2c0x_init_palette( running_machine *machine, int first_entry )
@ -318,7 +311,6 @@ static const gfx_layout ppu_charlayout =
static DEVICE_START( ppu2c0x )
{
ppu2c0x_chip *chip = get_token(device);
// const ppu2c0x_interface *intf = get_interface(device);
memset(chip, 0, sizeof(*chip));
chip->scanlines_per_frame = (int) device_get_info_int(device, PPU2C0XINFO_INT_SCANLINES_PER_FRAME);
@ -527,7 +519,6 @@ static void draw_background( const device_config *device, UINT8 *line_priority )
static void draw_sprites( const device_config *device, UINT8 *line_priority )
{
// const ppu2c0x_interface *intf = get_interface(device);
ppu2c0x_chip *this_ppu = get_token(device);
/* cache some values locally */
@ -1017,9 +1008,6 @@ static DEVICE_RESET( ppu2c0x )
/* set the vram bank-switch values to the default */
for (i = 0; i < 8; i++)
this_ppu->nes_vram[i] = i * 64;
// if (this_ppu->has_videorom)
// ppu2c0x_set_videorom_bank(device, 0, 8, 0, 512);
}
/*************************************
@ -1265,15 +1253,6 @@ WRITE8_DEVICE_HANDLER( ppu2c0x_w )
/* see if it's on the chargen portion */
if (tempAddr < 0x2000)
{
/* if we have a videorom mapped there, dont write and log the problem */
if (this_ppu->has_videorom && !this_ppu->has_videoram)
{
/* if there is a vidaccess callback, assume it coped with it */
if (this_ppu->vidaccess_callback_proc == NULL)
logerror("PPU: Attempting to write to the chargen when there's a ROM there!\n");
}
else
{
/* store the data */
memory_write_byte(device->space[0], tempAddr, data);
@ -1281,7 +1260,6 @@ WRITE8_DEVICE_HANDLER( ppu2c0x_w )
/* mark the char dirty */
// gfx_element_mark_dirty(device->machine->gfx[intf->gfx_layout_number], tempAddr >> 4);
}
}
else
{

2
src/mame/video/ppu2c0x.h
View File

@ -87,12 +87,10 @@ typedef int (*ppu2c0x_vidaccess_cb)( const device_config *device, int address,
typedef struct _ppu2c0x_interface ppu2c0x_interface;
struct _ppu2c0x_interface
{
const char * vrom_region; /* region id of gfx vrom (or REGION_INVALID if none) */
int gfx_layout_number; /* gfx layout number used by each chip */
int color_base; /* color base to use per ppu */
int mirroring; /* mirroring options (PPU_MIRROR_* flag) */
ppu2c0x_nmi_cb nmi_handler; /* NMI handler */
int vram_enabled; /* PPU uses vram together with vrom */
};

2
src/mame/video/vsnes.c
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@ -27,7 +27,6 @@ static void ppu_irq_2( const device_config *device, int *ppu_regs )
/* our ppu interface */
const ppu2c0x_interface vsnes_ppu_interface_1 =
{
"gfx1", /* vrom gfx region */
0, /* gfxlayout num */
0, /* color base */
PPU_MIRROR_NONE, /* mirroring */
@ -37,7 +36,6 @@ const ppu2c0x_interface vsnes_ppu_interface_1 =
/* our ppu interface for dual games */
const ppu2c0x_interface vsnes_ppu_interface_2 =
{
"gfx2", /* vrom gfx region */
1, /* gfxlayout num */
64, /* color base */
PPU_MIRROR_NONE, /* mirroring */