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Sega/Williams compile and crash fixes.

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This commit is contained in:
Aaron Giles 2008-11-15 07:43:42 +00:00
parent 70d25997ad
commit 6ace92f89a
13 changed files with 252 additions and 211 deletions
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20
src/emu/cpuexec.c
View File

@ -46,8 +46,8 @@ enum
***************************************************************************/
/* internal information about the state of inputs */
typedef struct _cpuinput_data cpuinput_data;
struct _cpuinput_data
typedef struct _cpu_input_data cpu_input_data;
struct _cpu_input_data
{
INT32 vector; /* most recently written vector */
INT32 curvector; /* most recently processed vector */
@ -69,7 +69,7 @@ struct _cpu_class_data
/* input states and IRQ callbacks */
cpu_irq_callback driver_irq; /* driver-specific IRQ callback */
cpuinput_data input[MAX_INPUT_LINES]; /* data about inputs */
cpu_input_data input[MAX_INPUT_LINES]; /* data about inputs */
/* suspend states */
UINT8 suspend; /* suspend reason mask (0 = not suspended) */
@ -230,7 +230,7 @@ void cpuexec_init(running_machine *machine)
/* fill in the input states and IRQ callback information */
for (line = 0; line < ARRAY_LENGTH(classdata->input); line++)
{
cpuinput_data *inputline = &classdata->input[line];
cpu_input_data *inputline = &classdata->input[line];
/* vector and curvector are initialized later */
inputline->curstate = CLEAR_LINE;
inputline->qindex = 0;
@ -261,7 +261,7 @@ void cpuexec_init(running_machine *machine)
classdata->icount = cpu_get_icount_ptr(device);
for (line = 0; line < ARRAY_LENGTH(classdata->input); line++)
{
cpuinput_data *inputline = &classdata->input[line];
cpu_input_data *inputline = &classdata->input[line];
inputline->vector = cpu_get_default_irq_vector(device);
inputline->curvector = inputline->vector;
}
@ -320,7 +320,7 @@ static void cpuexec_reset(running_machine *machine)
/* reset the interrupt vectors and queues */
for (line = 0; line < ARRAY_LENGTH(classdata->input); line++)
{
cpuinput_data *inputline = &classdata->input[line];
cpu_input_data *inputline = &classdata->input[line];
inputline->vector = cpu_get_default_irq_vector(device);
inputline->qindex = 0;
}
@ -930,7 +930,7 @@ void cpu_set_input_line_and_vector(const device_config *device, int line, int st
if (line >= 0 && line < MAX_INPUT_LINES)
{
cpuinput_data *inputline = &classdata->input[line];
cpu_input_data *inputline = &classdata->input[line];
INT32 input_event = (state & 0xff) | (vector << 8);
int event_index = inputline->qindex++;
@ -1244,7 +1244,7 @@ static TIMER_CALLBACK( empty_event_queue )
{
const device_config *device = ptr;
cpu_class_data *classdata = device->classtoken;
cpuinput_data *inputline = &classdata->input[param];
cpu_input_data *inputline = &classdata->input[param];
int curevent;
/* swap to the CPU's context */
@ -1341,7 +1341,7 @@ static TIMER_CALLBACK( empty_event_queue )
static IRQ_CALLBACK( standard_irq_callback )
{
cpu_class_data *classdata = device->classtoken;
cpuinput_data *inputline = &classdata->input[irqline];
cpu_input_data *inputline = &classdata->input[irqline];
int vector = inputline->curvector;
LOG(("standard_irq_callback('%s', %d) $%04x\n", device->tag, irqline, vector));
@ -1392,7 +1392,7 @@ static void register_save_states(const device_config *device)
for (line = 0; line < ARRAY_LENGTH(classdata->input); line++)
{
cpuinput_data *inputline = &classdata->input[line];
cpu_input_data *inputline = &classdata->input[line];
int index = classdata->header.index * ARRAY_LENGTH(classdata->input) + line;
state_save_register_item("cpu", index, inputline->vector);
state_save_register_item("cpu", index, inputline->curvector);

8
src/emu/cpuintrf.c
View File

@ -1138,15 +1138,19 @@ int cpu_get_index_slow(const device_config *cpu)
void cpu_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
{
cpu_class_header *classheader = get_safe_classheader(device);
memory_set_context(device->machine, index);
device->machine->activecpu = device;
classheader->index = index;
cpu_push_context(device);
classheader->space[ADDRESS_SPACE_PROGRAM] = active_address_space[ADDRESS_SPACE_PROGRAM];
classheader->space[ADDRESS_SPACE_DATA] = active_address_space[ADDRESS_SPACE_DATA];
classheader->space[ADDRESS_SPACE_IO] = active_address_space[ADDRESS_SPACE_IO];
(*classheader->init)(device, index, clock, irqcallback);
(*classheader->get_context)(device->token);
cpu_pop_context();
device->machine->activecpu = NULL;
}

140
src/mame/audio/dcs.c
View File

@ -285,7 +285,7 @@ struct _dsio_denver_state
typedef struct _dcs_state dcs_state;
struct _dcs_state
{
UINT8 cpunum;
const device_config *cpu;
UINT8 rev;
/* sound output */
@ -761,7 +761,7 @@ static void dcs_boot(void)
/* rev 3/4: HALT the ADSP-2181 until program is downloaded via IDMA */
case 3:
case 4:
cpu_set_input_line(Machine->cpu[dcs.cpunum], INPUT_LINE_HALT, ASSERT_LINE);
cpu_set_input_line(dcs.cpu, INPUT_LINE_HALT, ASSERT_LINE);
dsio.start_on_next_write = 0;
break;
}
@ -814,9 +814,9 @@ static TIMER_CALLBACK( dcs_reset )
memset(dcs.control_regs, 0, sizeof(dcs.control_regs));
/* clear all interrupts */
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2105_IRQ0, CLEAR_LINE);
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2105_IRQ1, CLEAR_LINE);
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2105_IRQ2, CLEAR_LINE);
cpu_set_input_line(dcs.cpu, ADSP2105_IRQ0, CLEAR_LINE);
cpu_set_input_line(dcs.cpu, ADSP2105_IRQ1, CLEAR_LINE);
cpu_set_input_line(dcs.cpu, ADSP2105_IRQ2, CLEAR_LINE);
/* initialize the comm bits */
SET_INPUT_EMPTY();
@ -910,13 +910,13 @@ void dcs_init(running_machine *machine)
dcs_sram = NULL;
/* find the DCS CPU and the sound ROMs */
dcs.cpunum = mame_find_cpu_index(Machine, "dcs");
dcs.cpu = cputag_get_cpu(machine, "dcs");
dcs.rev = 1;
dcs.channels = 1;
/* initialize the ADSP Tx and timer callbacks */
cpu_set_info_fct(machine->cpu[dcs.cpunum], CPUINFO_PTR_ADSP2100_TX_HANDLER, (genf *)sound_tx_callback);
cpu_set_info_fct(machine->cpu[dcs.cpunum], CPUINFO_PTR_ADSP2100_TIMER_HANDLER, (genf *)timer_enable_callback);
cpu_set_info_fct(dcs.cpu, CPUINFO_PTR_ADSP2100_TX_HANDLER, (genf *)sound_tx_callback);
cpu_set_info_fct(dcs.cpu, CPUINFO_PTR_ADSP2100_TIMER_HANDLER, (genf *)timer_enable_callback);
/* configure boot and sound ROMs */
dcs.bootrom = (UINT16 *)memory_region(Machine, "dcs");
@ -948,26 +948,26 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset)
memset(&dcs, 0, sizeof(dcs));
/* find the DCS CPU and the sound ROMs */
dcs.cpunum = mame_find_cpu_index(machine, "dcs2");
dcs.cpu = cputag_get_cpu(machine, "dcs2");
dcs.rev = 2;
soundbank_words = 0x1000;
if ((INT8)dcs.cpunum == -1)
if (dcs.cpu == NULL)
{
dcs.cpunum = mame_find_cpu_index(machine, "dsio");
dcs.cpu = cputag_get_cpu(machine, "dsio");
dcs.rev = 3;
soundbank_words = 0x400;
}
if ((INT8)dcs.cpunum == -1)
if (dcs.cpu == NULL)
{
dcs.cpunum = mame_find_cpu_index(machine, "denver");
dcs.cpu = cputag_get_cpu(machine, "denver");
dcs.rev = 4;
soundbank_words = 0x800;
}
dcs.channels = 2;
/* initialize the ADSP Tx and timer callbacks */
cpu_set_info_fct(machine->cpu[dcs.cpunum], CPUINFO_PTR_ADSP2100_TX_HANDLER, (genf *)sound_tx_callback);
cpu_set_info_fct(machine->cpu[dcs.cpunum], CPUINFO_PTR_ADSP2100_TIMER_HANDLER, (genf *)timer_enable_callback);
cpu_set_info_fct(dcs.cpu, CPUINFO_PTR_ADSP2100_TX_HANDLER, (genf *)sound_tx_callback);
cpu_set_info_fct(dcs.cpu, CPUINFO_PTR_ADSP2100_TIMER_HANDLER, (genf *)timer_enable_callback);
/* always boot from the base of "dcs" */
dcs.bootrom = (UINT16 *)memory_region(machine, "dcs");
@ -1001,7 +1001,7 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset)
/* install the speedup handler */
if (polling_offset)
dcs_polling_base = memory_install_read16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, polling_offset, polling_offset, 0, 0, dcs_polling_r);
dcs_polling_base = memory_install_read16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, polling_offset, polling_offset, 0, 0, dcs_polling_r);
/* allocate a watchdog timer for HLE transfers */
transfer.hle_enabled = (ENABLE_HLE_TRANSFERS && dram_in_mb != 0);
@ -1092,24 +1092,24 @@ static void sdrc_remap_memory(running_machine *machine)
/* if SRAM disabled, clean it out */
if (SDRC_SM_EN == 0)
{
memory_install_readwrite32_handler(machine, dcs.cpunum, ADDRESS_SPACE_PROGRAM, 0x0800, 0x3fff, 0, 0, SMH_UNMAP, SMH_UNMAP);
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x0800, 0x37ff, 0, 0, SMH_UNMAP, SMH_UNMAP);
memory_install_readwrite32_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_PROGRAM, 0x0800, 0x3fff, 0, 0, SMH_UNMAP, SMH_UNMAP);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x0800, 0x37ff, 0, 0, SMH_UNMAP, SMH_UNMAP);
}
/* otherwise, map the SRAM */
else
{
/* first start with a clean program map */
memory_install_readwrite32_handler(machine, dcs.cpunum, ADDRESS_SPACE_PROGRAM, 0x0800, 0x3fff, 0, 0, SMH_BANK21, SMH_BANK21);
memory_install_readwrite32_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_PROGRAM, 0x0800, 0x3fff, 0, 0, SMH_BANK21, SMH_BANK21);
memory_set_bankptr(21, dcs_sram + 0x4800);
/* set up the data map based on the SRAM banking */
/* map 0: ram from 0800-37ff */
if (SDRC_SM_BK == 0)
{
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x0800, 0x17ff, 0, 0, SMH_BANK22, SMH_BANK22);
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x1800, 0x27ff, 0, 0, SMH_BANK23, SMH_BANK23);
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x2800, 0x37ff, 0, 0, SMH_BANK24, SMH_BANK24);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x0800, 0x17ff, 0, 0, SMH_BANK22, SMH_BANK22);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x1800, 0x27ff, 0, 0, SMH_BANK23, SMH_BANK23);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x2800, 0x37ff, 0, 0, SMH_BANK24, SMH_BANK24);
memory_set_bankptr(22, dcs_sram + 0x0000);
memory_set_bankptr(23, dcs_sram + 0x1000);
memory_set_bankptr(24, dcs_sram + 0x2000);
@ -1118,9 +1118,9 @@ static void sdrc_remap_memory(running_machine *machine)
/* map 1: nothing from 0800-17ff, alternate RAM at 1800-27ff, same RAM at 2800-37ff */
else
{
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x0800, 0x17ff, 0, 0, SMH_UNMAP, SMH_UNMAP);
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x1800, 0x27ff, 0, 0, SMH_BANK23, SMH_BANK23);
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, 0x2800, 0x37ff, 0, 0, SMH_BANK24, SMH_BANK24);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x0800, 0x17ff, 0, 0, SMH_UNMAP, SMH_UNMAP);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x1800, 0x27ff, 0, 0, SMH_BANK23, SMH_BANK23);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, 0x2800, 0x37ff, 0, 0, SMH_BANK24, SMH_BANK24);
memory_set_bankptr(23, dcs_sram + 0x3000);
memory_set_bankptr(24, dcs_sram + 0x2000);
}
@ -1131,14 +1131,14 @@ static void sdrc_remap_memory(running_machine *machine)
{
int baseaddr = (SDRC_ROM_ST == 0) ? 0x0000 : (SDRC_ROM_ST == 1) ? 0x3000 : 0x3400;
int pagesize = (SDRC_ROM_SZ == 0 && SDRC_ROM_ST != 0) ? 4096 : 1024;
memory_install_read16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, baseaddr, baseaddr + pagesize - 1, 0, 0, SMH_BANK25);
memory_install_read16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, baseaddr, baseaddr + pagesize - 1, 0, 0, SMH_BANK25);
}
/* map the DRAM page as bank 26 */
if (SDRC_DM_ST != 0)
{
int baseaddr = (SDRC_DM_ST == 1) ? 0x0000 : (SDRC_DM_ST == 2) ? 0x3000 : 0x3400;
memory_install_readwrite16_handler(machine, dcs.cpunum, ADDRESS_SPACE_DATA, baseaddr, baseaddr + 0x3ff, 0, 0, SMH_BANK26, SMH_BANK26);
memory_install_readwrite16_handler(machine, cpu_get_index(dcs.cpu), ADDRESS_SPACE_DATA, baseaddr, baseaddr + 0x3ff, 0, 0, SMH_BANK26, SMH_BANK26);
}
/* update the bank pointers */
@ -1408,8 +1408,8 @@ WRITE32_HANDLER( dsio_idma_addr_w )
{
if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_addr = %04X\n", cpu_get_pc(space->cpu), data);
cpu_push_context(space->machine->cpu[dcs.cpunum]);
adsp2181_idma_addr_w(space->machine->cpu[dcs.cpunum], data);
cpu_push_context(dcs.cpu);
adsp2181_idma_addr_w(dcs.cpu, data);
if (data == 0)
dsio.start_on_next_write = 2;
cpu_pop_context();
@ -1419,24 +1419,24 @@ WRITE32_HANDLER( dsio_idma_addr_w )
WRITE32_HANDLER( dsio_idma_data_w )
{
UINT32 pc = cpu_get_pc(space->cpu);
cpu_push_context(space->machine->cpu[dcs.cpunum]);
cpu_push_context(dcs.cpu);
if (ACCESSING_BITS_0_15)
{
if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, adsp2181_idma_addr_r(space->machine->cpu[dcs.cpunum]), data & 0xffff);
adsp2181_idma_data_w(space->machine->cpu[dcs.cpunum], data & 0xffff);
logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, adsp2181_idma_addr_r(dcs.cpu), data & 0xffff);
adsp2181_idma_data_w(dcs.cpu, data & 0xffff);
}
if (ACCESSING_BITS_16_31)
{
if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, adsp2181_idma_addr_r(space->machine->cpu[dcs.cpunum]), data >> 16);
adsp2181_idma_data_w(space->machine->cpu[dcs.cpunum], data >> 16);
logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, adsp2181_idma_addr_r(dcs.cpu), data >> 16);
adsp2181_idma_data_w(dcs.cpu, data >> 16);
}
cpu_pop_context();
if (dsio.start_on_next_write && --dsio.start_on_next_write == 0)
{
logerror("Starting DSIO CPU\n");
cpu_set_input_line(space->machine->cpu[dcs.cpunum], INPUT_LINE_HALT, CLEAR_LINE);
cpu_set_input_line(dcs.cpu, INPUT_LINE_HALT, CLEAR_LINE);
}
}
@ -1444,11 +1444,11 @@ WRITE32_HANDLER( dsio_idma_data_w )
READ32_HANDLER( dsio_idma_data_r )
{
UINT32 result;
cpu_push_context(space->machine->cpu[dcs.cpunum]);
result = adsp2181_idma_data_r(space->machine->cpu[dcs.cpunum]);
cpu_push_context(dcs.cpu);
result = adsp2181_idma_data_r(dcs.cpu);
cpu_pop_context();
if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_data_r(%04X) = %04X\n", cpu_get_pc(space->cpu), adsp2181_idma_addr_r(space->machine->cpu[dcs.cpunum]), result);
logerror("%08X:IDMA_data_r(%04X) = %04X\n", cpu_get_pc(space->cpu), adsp2181_idma_addr_r(dcs.cpu), result);
return result;
}
@ -1490,12 +1490,12 @@ void dcs_reset_w(int state)
/* just run through the init code again */
timer_call_after_resynch(NULL, 0, dcs_reset);
cpu_set_input_line(Machine->cpu[dcs.cpunum], INPUT_LINE_RESET, ASSERT_LINE);
cpu_set_input_line(dcs.cpu, INPUT_LINE_RESET, ASSERT_LINE);
}
/* going low resets and reactivates the CPU */
else
cpu_set_input_line(Machine->cpu[dcs.cpunum], INPUT_LINE_RESET, CLEAR_LINE);
cpu_set_input_line(dcs.cpu, INPUT_LINE_RESET, CLEAR_LINE);
}
@ -1537,7 +1537,7 @@ static void dcs_delayed_data_w(running_machine *machine, int data)
cpuexec_boost_interleave(machine, ATTOTIME_IN_NSEC(500), ATTOTIME_IN_USEC(5));
/* set the IRQ line on the ADSP */
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2105_IRQ2, ASSERT_LINE);
cpu_set_input_line(dcs.cpu, ADSP2105_IRQ2, ASSERT_LINE);
/* indicate we are no longer empty */
if (dcs.last_input_empty && dcs.input_empty_cb)
@ -1574,7 +1574,7 @@ static WRITE16_HANDLER( input_latch_ack_w )
if (!dcs.last_input_empty && dcs.input_empty_cb)
(*dcs.input_empty_cb)(dcs.last_input_empty = 1);
SET_INPUT_EMPTY();
cpu_set_input_line(space->machine->cpu[dcs.cpunum], ADSP2105_IRQ2, CLEAR_LINE);
cpu_set_input_line(dcs.cpu, ADSP2105_IRQ2, CLEAR_LINE);
}
@ -1695,7 +1695,7 @@ static void update_timer_count(running_machine *machine)
return;
/* count cycles */
elapsed_cycles = cpu_get_total_cycles(machine->cpu[dcs.cpunum]) - dcs.timer_start_cycles;
elapsed_cycles = cpu_get_total_cycles(dcs.cpu) - dcs.timer_start_cycles;
elapsed_clocks = elapsed_cycles / dcs.timer_scale;
/* if we haven't counted past the initial count yet, just do that */
@ -1721,12 +1721,12 @@ static TIMER_CALLBACK( internal_timer_callback )
/* we do this to avoid drifting */
dcs.timers_fired++;
target_cycles = dcs.timer_start_cycles + dcs.timer_scale * (dcs.timer_start_count + 1 + dcs.timers_fired * (dcs.timer_period + 1));
target_cycles -= cpu_get_total_cycles(machine->cpu[dcs.cpunum]);
target_cycles -= cpu_get_total_cycles(dcs.cpu);
/* set the next timer, but only if it's for a reasonable number */
if (!dcs.timer_ignore && (dcs.timer_period > 10 || dcs.timer_scale > 1))
timer_adjust_oneshot(dcs.internal_timer, ATTOTIME_IN_CYCLES(target_cycles, dcs.cpunum), 0);
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2105_TIMER, PULSE_LINE);
timer_adjust_oneshot(dcs.internal_timer, ATTOTIME_IN_CYCLES(target_cycles, cpu_get_index(dcs.cpu)), 0);
cpu_set_input_line(dcs.cpu, ADSP2105_TIMER, PULSE_LINE);
}
@ -1737,7 +1737,7 @@ static void reset_timer(running_machine *machine)
return;
/* compute the time until the first firing */
dcs.timer_start_cycles = cpu_get_total_cycles(machine->cpu[dcs.cpunum]);
dcs.timer_start_cycles = cpu_get_total_cycles(dcs.cpu);
dcs.timers_fired = 0;
/* if this is the first timer, check the IRQ routine for the DRAM refresh stub */
@ -1746,7 +1746,7 @@ static void reset_timer(running_machine *machine)
{
/* Road Burners: @ 28: JMP $0032 18032F, same code at $32 */
cpu_push_context(Machine->cpu[dcs.cpunum]);
cpu_push_context(dcs.cpu);
if (program_read_dword(0x18*4) == 0x0c0030 && /* ENA SEC_REG */
program_read_dword(0x19*4) == 0x804828 && /* SI = DM($0482) */
program_read_dword(0x1a*4) == 0x904828 && /* DM($0482) = SI */
@ -1760,7 +1760,7 @@ static void reset_timer(running_machine *machine)
/* adjust the timer if not optimized */
if (!dcs.timer_ignore)
timer_adjust_oneshot(dcs.internal_timer, ATTOTIME_IN_CYCLES(dcs.timer_scale * (dcs.timer_start_count + 1), dcs.cpunum), 0);
timer_adjust_oneshot(dcs.internal_timer, ATTOTIME_IN_CYCLES(dcs.timer_scale * (dcs.timer_start_count + 1), cpu_get_index(dcs.cpu)), 0);
}
@ -1770,7 +1770,7 @@ static void timer_enable_callback(int enable)
dcs.timer_ignore = 0;
if (enable)
{
// mame_printf_debug("Timer enabled @ %d cycles/int, or %f Hz\n", dcs.timer_scale * (dcs.timer_period + 1), 1.0 / ATTOTIME_IN_CYCLES(dcs.timer_scale * (dcs.timer_period + 1), dcs.cpunum));
// mame_printf_debug("Timer enabled @ %d cycles/int, or %f Hz\n", dcs.timer_scale * (dcs.timer_period + 1), 1.0 / ATTOTIME_IN_CYCLES(dcs.timer_scale * (dcs.timer_period + 1), cpu_get_index(dcs.cpu)));
reset_timer(Machine);
}
else
@ -1818,7 +1818,7 @@ static READ16_HANDLER( adsp_control_r )
break;
case IDMA_CONTROL_REG:
result = adsp2181_idma_addr_r(space->machine->cpu[dcs.cpunum]);
result = adsp2181_idma_addr_r(dcs.cpu);
break;
case TIMER_COUNT_REG:
@ -1845,7 +1845,7 @@ static WRITE16_HANDLER( adsp_control_w )
if (data & 0x0200)
{
logerror("%04X:Rebooting DCS due to SYSCONTROL write\n", cpu_get_pc(space->cpu));
cpu_set_input_line(space->machine->cpu[dcs.cpunum], INPUT_LINE_RESET, PULSE_LINE);
cpu_set_input_line(dcs.cpu, INPUT_LINE_RESET, PULSE_LINE);
dcs_boot();
dcs.control_regs[SYSCONTROL_REG] = 0;
}
@ -1899,7 +1899,7 @@ static WRITE16_HANDLER( adsp_control_w )
break;
case IDMA_CONTROL_REG:
adsp2181_idma_addr_w(space->machine->cpu[dcs.cpunum], data);
adsp2181_idma_addr_w(dcs.cpu, data);
break;
}
}
@ -1912,7 +1912,7 @@ static WRITE16_HANDLER( adsp_control_w )
static TIMER_CALLBACK( dcs_irq )
{
/* get the index register */
int reg = cpu_get_reg(machine->cpu[dcs.cpunum], ADSP2100_I0 + dcs.ireg);
int reg = cpu_get_reg(dcs.cpu, ADSP2100_I0 + dcs.ireg);
/* copy the current data into the buffer */
{
@ -1920,7 +1920,7 @@ static TIMER_CALLBACK( dcs_irq )
INT16 buffer[0x400];
int i;
cpu_push_context(machine->cpu[dcs.cpunum]);
cpu_push_context(dcs.cpu);
for (i = 0; i < count; i++)
{
buffer[i] = data_read_word_16le(reg * 2);
@ -1939,11 +1939,11 @@ static TIMER_CALLBACK( dcs_irq )
reg = dcs.ireg_base;
/* generate the (internal, thats why the pulse) irq */
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2105_IRQ1, PULSE_LINE);
cpu_set_input_line(dcs.cpu, ADSP2105_IRQ1, PULSE_LINE);
}
/* store it */
cpu_set_reg(machine->cpu[dcs.cpunum], ADSP2100_I0 + dcs.ireg, reg);
cpu_set_reg(dcs.cpu, ADSP2100_I0 + dcs.ireg, reg);
}
@ -1953,8 +1953,8 @@ static TIMER_CALLBACK( sport0_irq )
/* note that there is non-interrupt code that reads/modifies/writes the output_control */
/* register; if we don't interlock it, we will eventually lose sound (see CarnEvil) */
/* so we skip the SPORT interrupt if we read with output_control within the last 5 cycles */
if ((cpu_get_total_cycles(machine->cpu[dcs.cpunum]) - dcs.output_control_cycles) > 5)
cpu_set_input_line(machine->cpu[dcs.cpunum], ADSP2115_SPORT0_RX, PULSE_LINE);
if ((cpu_get_total_cycles(dcs.cpu) - dcs.output_control_cycles) > 5)
cpu_set_input_line(dcs.cpu, ADSP2115_SPORT0_RX, PULSE_LINE);
}
@ -1963,7 +1963,7 @@ static void recompute_sample_rate(running_machine *machine)
/* calculate how long until we generate an interrupt */
/* frequency the time per each bit sent */
attotime sample_period = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->cpu[dcs.cpunum])), 2 * (dcs.control_regs[S1_SCLKDIV_REG] + 1));
attotime sample_period = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(dcs.cpu)), 2 * (dcs.control_regs[S1_SCLKDIV_REG] + 1));
/* now put it down to samples, so we know what the channel frequency has to be */
sample_period = attotime_mul(sample_period, 16 * dcs.channels);
@ -2002,15 +2002,15 @@ static void sound_tx_callback(int port, INT32 data)
/* now get the register contents in a more legible format */
/* we depend on register indexes to be continuous (wich is the case in our core) */
source = cpu_get_reg(Machine->cpu[dcs.cpunum], ADSP2100_I0 + dcs.ireg);
dcs.incs = cpu_get_reg(Machine->cpu[dcs.cpunum], ADSP2100_M0 + mreg);
dcs.size = cpu_get_reg(Machine->cpu[dcs.cpunum], ADSP2100_L0 + lreg);
source = cpu_get_reg(dcs.cpu, ADSP2100_I0 + dcs.ireg);
dcs.incs = cpu_get_reg(dcs.cpu, ADSP2100_M0 + mreg);
dcs.size = cpu_get_reg(dcs.cpu, ADSP2100_L0 + lreg);
/* get the base value, since we need to keep it around for wrapping */
source -= dcs.incs;
/* make it go back one so we dont lose the first sample */
cpu_set_reg(Machine->cpu[dcs.cpunum], ADSP2100_I0 + dcs.ireg, source);
cpu_set_reg(dcs.cpu, ADSP2100_I0 + dcs.ireg, source);
/* save it as it is now */
dcs.ireg_base = source;
@ -2088,7 +2088,7 @@ static TIMER_CALLBACK( s1_ack_callback2 )
timer_set(ATTOTIME_IN_USEC(1), NULL, param, s1_ack_callback2);
return;
}
output_latch_w(machine, 0, 0x000a, 0xffff);
output_latch_w(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_PROGRAM), 0, 0x000a, 0xffff);
}
@ -2100,7 +2100,7 @@ static TIMER_CALLBACK( s1_ack_callback1 )
timer_set(ATTOTIME_IN_USEC(1), NULL, param, s1_ack_callback1);
return;
}
output_latch_w(machine, 0, param, 0xffff);
output_latch_w(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_PROGRAM), 0, param, 0xffff);
/* chain to the next word we need to write back */
timer_set(ATTOTIME_IN_USEC(1), NULL, 0, s1_ack_callback2);
@ -2207,7 +2207,7 @@ static int preprocess_stage_1(running_machine *machine, UINT16 data)
if (transfer.hle_enabled)
{
/* write the new data to memory */
cpu_push_context(machine->cpu[dcs.cpunum]);
cpu_push_context(dcs.cpu);
if (transfer.type == 0)
{
if (transfer.writes_left & 1)
@ -2232,14 +2232,16 @@ static int preprocess_stage_1(running_machine *machine, UINT16 data)
static TIMER_CALLBACK( s2_ack_callback )
{
const address_space *space = cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_PROGRAM);
/* if the output is full, stall for a usec */
if (IS_OUTPUT_FULL())
{
timer_set(ATTOTIME_IN_USEC(1), NULL, param, s2_ack_callback);
return;
}
output_latch_w(machine, 0, param, 0xffff);
output_control_w(machine, 0, (dcs.output_control & ~0xff00) | 0x0300, 0xffff);
output_latch_w(space, 0, param, 0xffff);
output_control_w(space, 0, (dcs.output_control & ~0xff00) | 0x0300, 0xffff);
}

95
src/mame/audio/williams.c
View File

@ -53,8 +53,8 @@ static UINT8 williams_sound_int_state;
static UINT8 audio_talkback;
static UINT8 audio_sync;
static INT8 sound_cpunum;
static INT8 soundalt_cpunum;
static const device_config *sound_cpu;
static const device_config *soundalt_cpu;
static UINT8 williams_pianum;
@ -265,8 +265,8 @@ void williams_cvsd_init(int pianum)
int bank;
/* configure the CPU */
sound_cpunum = mame_find_cpu_index(Machine, "cvsd");
soundalt_cpunum = -1;
sound_cpu = cputag_get_cpu(Machine, "cvsd");
soundalt_cpu = NULL;
/* configure the PIA */
williams_pianum = pianum;
@ -301,8 +301,8 @@ void williams_narc_init(void)
int bank;
/* configure the CPU */
sound_cpunum = mame_find_cpu_index(Machine, "narc1");
soundalt_cpunum = mame_find_cpu_index(Machine, "narc2");
sound_cpu = cputag_get_cpu(Machine, "narc1");
soundalt_cpu = cputag_get_cpu(Machine, "narc2");
/* configure master CPU banks */
ROM = memory_region(Machine, "narc1");
@ -344,8 +344,8 @@ void williams_adpcm_init(void)
UINT8 *ROM;
/* configure the CPU */
sound_cpunum = mame_find_cpu_index(Machine, "adpcm");
soundalt_cpunum = -1;
sound_cpu = cputag_get_cpu(Machine, "adpcm");
soundalt_cpu = NULL;
/* configure banks */
ROM = memory_region(Machine, "adpcm");
@ -384,17 +384,17 @@ static void init_audio_state(running_machine *machine)
/* clear all the interrupts */
williams_sound_int_state = 0;
if (sound_cpunum != -1)
if (sound_cpu != NULL)
{
cpu_set_input_line(machine->cpu[sound_cpunum], M6809_FIRQ_LINE, CLEAR_LINE);
cpu_set_input_line(machine->cpu[sound_cpunum], M6809_IRQ_LINE, CLEAR_LINE);
cpu_set_input_line(machine->cpu[sound_cpunum], INPUT_LINE_NMI, CLEAR_LINE);
cpu_set_input_line(sound_cpu, M6809_FIRQ_LINE, CLEAR_LINE);
cpu_set_input_line(sound_cpu, M6809_IRQ_LINE, CLEAR_LINE);
cpu_set_input_line(sound_cpu, INPUT_LINE_NMI, CLEAR_LINE);
}
if (soundalt_cpunum != -1)
if (soundalt_cpu != NULL)
{
cpu_set_input_line(machine->cpu[soundalt_cpunum], M6809_FIRQ_LINE, CLEAR_LINE);
cpu_set_input_line(machine->cpu[soundalt_cpunum], M6809_IRQ_LINE, CLEAR_LINE);
cpu_set_input_line(machine->cpu[soundalt_cpunum], INPUT_LINE_NMI, CLEAR_LINE);
cpu_set_input_line(soundalt_cpu, M6809_FIRQ_LINE, CLEAR_LINE);
cpu_set_input_line(soundalt_cpu, M6809_IRQ_LINE, CLEAR_LINE);
cpu_set_input_line(soundalt_cpu, INPUT_LINE_NMI, CLEAR_LINE);
}
}
@ -412,13 +412,13 @@ static void cvsd_ym2151_irq(running_machine *machine, int state)
static void cvsd_irqa(running_machine *machine, int state)
{
cpu_set_input_line(machine->cpu[sound_cpunum], M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
cpu_set_input_line(sound_cpu, M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
}
static void cvsd_irqb(running_machine *machine, int state)
{
cpu_set_input_line(machine->cpu[sound_cpunum], INPUT_LINE_NMI, state ? ASSERT_LINE : CLEAR_LINE);
cpu_set_input_line(sound_cpu, INPUT_LINE_NMI, state ? ASSERT_LINE : CLEAR_LINE);
}
@ -429,7 +429,7 @@ static void cvsd_irqb(running_machine *machine, int state)
static void adpcm_ym2151_irq(running_machine *machine, int state)
{
cpu_set_input_line(machine->cpu[sound_cpunum], M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
cpu_set_input_line(sound_cpu, M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
}
@ -484,16 +484,18 @@ void williams_cvsd_data_w(int data)
void williams_cvsd_reset_w(int state)
{
const address_space *space = cpu_get_address_space(sound_cpu, ADDRESS_SPACE_PROGRAM);
/* going high halts the CPU */
if (state)
{
cvsd_bank_select_w(Machine, 0, 0);
init_audio_state(Machine);
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_RESET, ASSERT_LINE);
cvsd_bank_select_w(space, 0, 0);
init_audio_state(space->machine);
cpu_set_input_line(space->cpu, INPUT_LINE_RESET, ASSERT_LINE);
}
/* going low resets and reactivates the CPU */
else
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_RESET, CLEAR_LINE);
cpu_set_input_line(space->cpu, INPUT_LINE_RESET, CLEAR_LINE);
}
@ -516,7 +518,7 @@ static WRITE8_HANDLER( narc_slave_bank_select_w )
static READ8_HANDLER( narc_command_r )
{
cpu_set_input_line(space->machine->cpu[sound_cpunum], M6809_IRQ_LINE, CLEAR_LINE);
cpu_set_input_line(sound_cpu, M6809_IRQ_LINE, CLEAR_LINE);
williams_sound_int_state = 0;
return soundlatch_r(space, 0);
}
@ -525,13 +527,13 @@ static READ8_HANDLER( narc_command_r )
static WRITE8_HANDLER( narc_command2_w )
{
soundlatch2_w(space, 0, data & 0xff);
cpu_set_input_line(space->machine->cpu[soundalt_cpunum], M6809_FIRQ_LINE, ASSERT_LINE);
cpu_set_input_line(soundalt_cpu, M6809_FIRQ_LINE, ASSERT_LINE);
}
static READ8_HANDLER( narc_command2_r )
{
cpu_set_input_line(space->machine->cpu[soundalt_cpunum], M6809_FIRQ_LINE, CLEAR_LINE);
cpu_set_input_line(soundalt_cpu, M6809_FIRQ_LINE, CLEAR_LINE);
return soundlatch2_r(space, 0);
}
@ -577,11 +579,13 @@ static WRITE8_HANDLER( narc_slave_sync_w )
void williams_narc_data_w(int data)
{
soundlatch_w(Machine, 0, data & 0xff);
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_NMI, (data & 0x100) ? CLEAR_LINE : ASSERT_LINE);
const address_space *space = cpu_get_address_space(sound_cpu, ADDRESS_SPACE_PROGRAM);
soundlatch_w(space, 0, data & 0xff);
cpu_set_input_line(sound_cpu, INPUT_LINE_NMI, (data & 0x100) ? CLEAR_LINE : ASSERT_LINE);
if (!(data & 0x200))
{
cpu_set_input_line(Machine->cpu[sound_cpunum], M6809_IRQ_LINE, ASSERT_LINE);
cpu_set_input_line(sound_cpu, M6809_IRQ_LINE, ASSERT_LINE);
williams_sound_int_state = 1;
}
}
@ -592,17 +596,18 @@ void williams_narc_reset_w(int state)
/* going high halts the CPU */
if (state)
{
narc_master_bank_select_w(Machine, 0, 0);
narc_slave_bank_select_w(Machine, 0, 0);
init_audio_state(Machine);
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_RESET, ASSERT_LINE);
cpu_set_input_line(Machine->cpu[soundalt_cpunum], INPUT_LINE_RESET, ASSERT_LINE);
const address_space *space = cpu_get_address_space(sound_cpu, ADDRESS_SPACE_PROGRAM);
narc_master_bank_select_w(space, 0, 0);
narc_slave_bank_select_w(space, 0, 0);
init_audio_state(space->machine);
cpu_set_input_line(sound_cpu, INPUT_LINE_RESET, ASSERT_LINE);
cpu_set_input_line(soundalt_cpu, INPUT_LINE_RESET, ASSERT_LINE);
}
/* going low resets and reactivates the CPU */
else
{
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_RESET, CLEAR_LINE);
cpu_set_input_line(Machine->cpu[soundalt_cpunum], INPUT_LINE_RESET, CLEAR_LINE);
cpu_set_input_line(sound_cpu, INPUT_LINE_RESET, CLEAR_LINE);
cpu_set_input_line(soundalt_cpu, INPUT_LINE_RESET, CLEAR_LINE);
}
}
@ -638,7 +643,7 @@ static TIMER_CALLBACK( clear_irq_state )
static READ8_HANDLER( adpcm_command_r )
{
cpu_set_input_line(space->machine->cpu[sound_cpunum], M6809_IRQ_LINE, CLEAR_LINE);
cpu_set_input_line(sound_cpu, M6809_IRQ_LINE, CLEAR_LINE);
/* don't clear the external IRQ state for a short while; this allows the
self-tests to pass */
@ -661,12 +666,13 @@ static WRITE8_HANDLER( adpcm_talkback_w )
void williams_adpcm_data_w(int data)
{
soundlatch_w(Machine, 0, data & 0xff);
const address_space *space = cpu_get_address_space(sound_cpu, ADDRESS_SPACE_PROGRAM);
soundlatch_w(space, 0, data & 0xff);
if (!(data & 0x200))
{
cpu_set_input_line(Machine->cpu[sound_cpunum], M6809_IRQ_LINE, ASSERT_LINE);
cpu_set_input_line(sound_cpu, M6809_IRQ_LINE, ASSERT_LINE);
williams_sound_int_state = 1;
cpuexec_boost_interleave(Machine, attotime_zero, ATTOTIME_IN_USEC(100));
cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(100));
}
}
@ -676,13 +682,14 @@ void williams_adpcm_reset_w(int state)
/* going high halts the CPU */
if (state)
{
adpcm_bank_select_w(Machine, 0, 0);
init_audio_state(Machine);
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_RESET, ASSERT_LINE);
const address_space *space = cpu_get_address_space(sound_cpu, ADDRESS_SPACE_PROGRAM);
adpcm_bank_select_w(space, 0, 0);
init_audio_state(space->machine);
cpu_set_input_line(sound_cpu, INPUT_LINE_RESET, ASSERT_LINE);
}
/* going low resets and reactivates the CPU */
else
cpu_set_input_line(Machine->cpu[sound_cpunum], INPUT_LINE_RESET, CLEAR_LINE);
cpu_set_input_line(sound_cpu, INPUT_LINE_RESET, CLEAR_LINE);
}

14
src/mame/drivers/seattle.c
View File

@ -468,7 +468,7 @@ static UINT32 cmos_write_enabled;
*
*************************************/
static void vblank_assert(running_machine *machine, int state);
static void vblank_assert(const device_config *device, int state);
static void update_vblank_irq(running_machine *machine);
static void galileo_reset(void);
static TIMER_CALLBACK( galileo_timer_callback );
@ -567,12 +567,12 @@ static MACHINE_RESET( seattle )
cpu_stalled_on_voodoo = FALSE;
/* reset either the DCS2 board or the CAGE board */
if (mame_find_cpu_index(machine, "dcs2") != -1)
if (cputag_get_cpu(machine, "dcs2") != NULL)
{
dcs_reset_w(1);
dcs_reset_w(0);
}
else if (mame_find_cpu_index(machine, "cage") != -1)
else if (cputag_get_cpu(machine, "cage") != NULL)
{
cage_control_w(machine, 0);
cage_control_w(machine, 3);
@ -743,7 +743,7 @@ static WRITE32_HANDLER( vblank_clear_w )
}
static void vblank_assert(running_machine *machine, int state)
static void vblank_assert(const device_config *device, int state)
{
/* cache the raw state */
vblank_state = state;
@ -752,7 +752,7 @@ static void vblank_assert(running_machine *machine, int state)
if ((state && !(*interrupt_enable & 0x100)) || (!state && (*interrupt_enable & 0x100)))
{
vblank_latch = 1;
update_vblank_irq(machine);
update_vblank_irq(device->machine);
}
}
@ -1531,7 +1531,7 @@ static READ32_DEVICE_HANDLER( widget_r )
break;
case WREG_ANALOG:
result = analog_port_r(device->machine, 0, mem_mask);
result = analog_port_r(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0, mem_mask);
break;
case WREG_ETHER_DATA:
@ -1562,7 +1562,7 @@ static WRITE32_DEVICE_HANDLER( widget_w )
break;
case WREG_ANALOG:
analog_port_w(device->machine, 0, data, mem_mask);
analog_port_w(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0, data, mem_mask);
break;
case WREG_ETHER_DATA:

6
src/mame/drivers/segaorun.c
View File

@ -93,7 +93,7 @@ static const ppi8255_interface single_ppi_intf =
*
*************************************/
static const struct segaic16_memory_map_entry outrun_info[] =
static const segaic16_memory_map_entry outrun_info[] =
{
{ 0x35/2, 0x90000, 0x10000, 0xf00000, ~0, segaic16_road_control_0_r, segaic16_road_control_0_w, NULL, "road control" },
{ 0x35/2, 0x80000, 0x01000, 0xf0f000, ~0, SMH_BANK10, SMH_BANK10, &segaic16_roadram_0, "road RAM" },
@ -125,7 +125,7 @@ static TIMER_CALLBACK( delayed_sound_data_w )
}
static void sound_data_w(UINT8 data)
static void sound_data_w(running_machine *machine, UINT8 data)
{
timer_call_after_resynch(NULL, data, delayed_sound_data_w);
}
@ -149,7 +149,7 @@ static void outrun_generic_init(running_machine *machine)
workram = auto_malloc(0x08000);
/* init the memory mapper */
segaic16_memory_mapper_init(machine, "main", outrun_info, sound_data_w, NULL);
segaic16_memory_mapper_init(cputag_get_cpu(machine, "main"), outrun_info, sound_data_w, NULL);
/* init the FD1094 */
fd1094_driver_init(machine, segaic16_memory_mapper_set_decrypted);

43
src/mame/drivers/segas16b.c
View File

@ -946,7 +946,7 @@ static WRITE16_HANDLER( atomicp_sound_w );
*
*************************************/
static const struct segaic16_memory_map_entry rom_171_5358_info_small[] =
static const segaic16_memory_map_entry rom_171_5358_info_small[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x01000, 0xfff000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -960,7 +960,7 @@ static const struct segaic16_memory_map_entry rom_171_5358_info_small[] =
{ 0 }
};
static const struct segaic16_memory_map_entry rom_171_5358_info[] =
static const segaic16_memory_map_entry rom_171_5358_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x01000, 0xfff000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -974,7 +974,7 @@ static const struct segaic16_memory_map_entry rom_171_5358_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry rom_171_5704_info[] =
static const segaic16_memory_map_entry rom_171_5704_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x01000, 0xfff000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -988,7 +988,7 @@ static const struct segaic16_memory_map_entry rom_171_5704_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry rom_atomicp_info[] =
static const segaic16_memory_map_entry rom_atomicp_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x01000, 0xfff000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -1002,7 +1002,7 @@ static const struct segaic16_memory_map_entry rom_atomicp_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry rom_171_5797_info[] =
static const segaic16_memory_map_entry rom_171_5797_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x01000, 0xfff000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -1016,7 +1016,7 @@ static const struct segaic16_memory_map_entry rom_171_5797_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry *const region_info_list[] =
static const segaic16_memory_map_entry *const region_info_list[] =
{
&rom_171_5358_info_small[0],
&rom_171_5358_info[0],
@ -1033,12 +1033,13 @@ static const struct segaic16_memory_map_entry *const region_info_list[] =
*
*************************************/
static void sound_w(UINT8 data)
static void sound_w(running_machine *machine, UINT8 data)
{
if (has_sound_cpu)
{
soundlatch_w(Machine, 0, data & 0xff);
cpu_set_input_line(Machine->cpu[1], 0, HOLD_LINE);
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
soundlatch_w(space, 0, data & 0xff);
cpu_set_input_line(machine->cpu[1], 0, HOLD_LINE);
}
}
@ -1056,7 +1057,7 @@ static void system16b_generic_init(running_machine *machine, int _rom_board)
workram = auto_malloc(0x04000);
/* init the memory mapper */
segaic16_memory_mapper_init(machine, "main", region_info_list[rom_board], sound_w, NULL);
segaic16_memory_mapper_init(cputag_get_cpu(machine, "main"), region_info_list[rom_board], sound_w, NULL);
/* init the FD1094 */
fd1094_driver_init(machine, segaic16_memory_mapper_set_decrypted);
@ -1075,7 +1076,7 @@ static void system16b_generic_init(running_machine *machine, int _rom_board)
static TIMER_CALLBACK( suspend_i8751 )
{
cpu_suspend(machine->cpu[mame_find_cpu_index(machine, "mcu")], SUSPEND_REASON_DISABLE, 1);
cpu_suspend(cputag_get_cpu(machine, "mcu"), SUSPEND_REASON_DISABLE, 1);
}
@ -1380,19 +1381,20 @@ static INTERRUPT_GEN( i8751_main_cpu_vblank )
static void altbeast_common_i8751_sim(running_machine *machine, offs_t soundoffs, offs_t inputoffs)
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
UINT16 temp;
/* signal a VBLANK to the main CPU */
cpu_set_input_line(machine->cpu[0], 4, HOLD_LINE);
/* set tile banks */
rom_5704_bank_w(machine, 1, workram[0x3094/2] & 0x00ff, 0x00ff);
rom_5704_bank_w(space, 1, workram[0x3094/2] & 0x00ff, 0x00ff);
/* process any new sound data */
temp = workram[soundoffs];
if ((temp & 0xff00) != 0x0000)
{
segaic16_memory_mapper_w(machine, 0x03, temp >> 8);
segaic16_memory_mapper_w(space, 0x03, temp >> 8);
workram[soundoffs] = temp & 0x00ff;
}
@ -1418,6 +1420,7 @@ static void altbeast_i8751_sim(running_machine *machine)
static void ddux_i8751_sim(running_machine *machine)
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
UINT16 temp;
/* signal a VBLANK to the main CPU */
@ -1427,7 +1430,7 @@ static void ddux_i8751_sim(running_machine *machine)
temp = workram[0x0bd0/2];
if ((temp & 0xff00) != 0x0000)
{
segaic16_memory_mapper_w(machine, 0x03, temp >> 8);
segaic16_memory_mapper_w(space, 0x03, temp >> 8);
workram[0x0bd0/2] = temp & 0x00ff;
}
}
@ -1453,6 +1456,7 @@ static void goldnaxe_i8751_init(running_machine *machine)
static void goldnaxe_i8751_sim(running_machine *machine)
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
UINT16 temp;
/* signal a VBLANK to the main CPU */
@ -1471,7 +1475,7 @@ static void goldnaxe_i8751_sim(running_machine *machine)
temp = workram[0x2cfc/2];
if ((temp & 0xff00) != 0x0000)
{
segaic16_memory_mapper_w(machine, 0x03, temp >> 8);
segaic16_memory_mapper_w(space, 0x03, temp >> 8);
workram[0x2cfc/2] = temp & 0x00ff;
}
@ -1483,6 +1487,7 @@ static void goldnaxe_i8751_sim(running_machine *machine)
static void tturf_i8751_sim(running_machine *machine)
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
UINT16 temp;
/* signal a VBLANK to the main CPU */
@ -1492,7 +1497,7 @@ static void tturf_i8751_sim(running_machine *machine)
temp = workram[0x01d0/2];
if ((temp & 0xff00) != 0x0000)
{
segaic16_memory_mapper_w(machine, 0x03, temp);
segaic16_memory_mapper_w(space, 0x03, temp);
workram[0x01d0/2] = temp & 0x00ff;
}
@ -1505,6 +1510,7 @@ static void tturf_i8751_sim(running_machine *machine)
static void wb3_i8751_sim(running_machine *machine)
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
UINT16 temp;
/* signal a VBLANK to the main CPU */
@ -1514,7 +1520,7 @@ static void wb3_i8751_sim(running_machine *machine)
temp = workram[0x0008/2];
if ((temp & 0x00ff) != 0x0000)
{
segaic16_memory_mapper_w(machine, 0x03, temp >> 8);
segaic16_memory_mapper_w(space, 0x03, temp >> 8);
workram[0x0008/2] = temp & 0xff00;
}
}
@ -1522,6 +1528,7 @@ static void wb3_i8751_sim(running_machine *machine)
static void wrestwar_i8751_sim(running_machine *machine)
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
UINT16 temp;
/* signal a VBLANK to the main CPU */
@ -1531,7 +1538,7 @@ static void wrestwar_i8751_sim(running_machine *machine)
temp = workram[0x208e/2];
if ((temp & 0xff00) != 0x0000)
{
segaic16_memory_mapper_w(machine, 0x03, temp);
segaic16_memory_mapper_w(space, 0x03, temp);
workram[0x208e/2] = temp & 0x00ff;
}

19
src/mame/drivers/segas18.c
View File

@ -87,7 +87,7 @@ static WRITE16_HANDLER( rom_5987_bank_w );
*
*************************************/
static const struct segaic16_memory_map_entry rom_171_shad_info[] =
static const segaic16_memory_map_entry rom_171_shad_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x02000, 0xffe000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -101,7 +101,7 @@ static const struct segaic16_memory_map_entry rom_171_shad_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry rom_171_5874_info[] =
static const segaic16_memory_map_entry rom_171_5874_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x02000, 0xffe000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -115,7 +115,7 @@ static const struct segaic16_memory_map_entry rom_171_5874_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry rom_171_5987_info[] =
static const segaic16_memory_map_entry rom_171_5987_info[] =
{
{ 0x3d/2, 0x00000, 0x04000, 0xffc000, ~0, misc_io_r, misc_io_w, NULL, "I/O space" },
{ 0x39/2, 0x00000, 0x02000, 0xffe000, ~0, SMH_BANK10, segaic16_paletteram_w, &paletteram16, "color RAM" },
@ -129,7 +129,7 @@ static const struct segaic16_memory_map_entry rom_171_5987_info[] =
{ 0 }
};
static const struct segaic16_memory_map_entry *const region_info_list[] =
static const segaic16_memory_map_entry *const region_info_list[] =
{
&rom_171_shad_info[0],
&rom_171_5874_info[0],
@ -144,14 +144,15 @@ static const struct segaic16_memory_map_entry *const region_info_list[] =
*
*************************************/
static void sound_w(UINT8 data)
static void sound_w(running_machine *machine, UINT8 data)
{
soundlatch_w(Machine, 0, data & 0xff);
cpu_set_input_line(Machine->cpu[1], INPUT_LINE_NMI, PULSE_LINE);
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
soundlatch_w(space, 0, data & 0xff);
cpu_set_input_line(machine->cpu[1], INPUT_LINE_NMI, PULSE_LINE);
}
static UINT8 sound_r(void)
static UINT8 sound_r(running_machine *machine)
{
return mcu_data;
}
@ -170,7 +171,7 @@ static void system18_generic_init(running_machine *machine, int _rom_board)
workram = auto_malloc(0x04000);
/* init the memory mapper */
segaic16_memory_mapper_init(machine, "main", region_info_list[rom_board], sound_w, sound_r);
segaic16_memory_mapper_init(cputag_get_cpu(machine, "main"), region_info_list[rom_board], sound_w, sound_r);
/* init the FD1094 */
fd1094_driver_init(machine, segaic16_memory_mapper_set_decrypted);

4
src/mame/drivers/vegas.c
View File

@ -1283,12 +1283,12 @@ static void update_sio_irqs(running_machine *machine)
}
static void vblank_assert(running_machine *machine, int state)
static void vblank_assert(const device_config *device, int state)
{
if (!vblank_state && state)
{
sio_irq_state |= 0x20;
update_sio_irqs(machine);
update_sio_irqs(device->machine);
}
vblank_state = state;

46
src/mame/machine/segaic16.c
View File

@ -33,10 +33,10 @@
struct memory_mapper_chip
{
UINT8 regs[0x20];
const char *cpu;
const struct segaic16_memory_map_entry *map;
void (*sound_w)(UINT8);
UINT8 (*sound_r)(void);
const device_config *cpu;
const segaic16_memory_map_entry *map;
void (*sound_w)(running_machine *, UINT8);
UINT8 (*sound_r)(running_machine *);
};
@ -57,7 +57,7 @@ struct compare_timer_chip
UINT16 regs[16];
UINT16 counter;
UINT8 bit;
void (*sound_w)(UINT8);
void (*sound_w)(running_machine *, UINT8);
void (*timer_ack)(running_machine *);
};
@ -124,7 +124,7 @@ READ16_HANDLER( segaic16_open_bus_r )
*
*************************************/
void segaic16_memory_mapper_init(running_machine *machine, const char *cpu, const struct segaic16_memory_map_entry *entrylist, void (*sound_w_callback)(UINT8), UINT8 (*sound_r_callback)(void))
void segaic16_memory_mapper_init(const device_config *cpu, const segaic16_memory_map_entry *entrylist, void (*sound_w_callback)(running_machine *, UINT8), UINT8 (*sound_r_callback)(running_machine *))
{
struct memory_mapper_chip *chip = &memory_mapper;
@ -136,7 +136,7 @@ void segaic16_memory_mapper_init(running_machine *machine, const char *cpu, cons
chip->sound_r = sound_r_callback;
/* create the initial regions */
segaic16_memory_mapper_reset(machine);
segaic16_memory_mapper_reset(cpu->machine);
}
@ -163,14 +163,14 @@ void segaic16_memory_mapper_config(running_machine *machine, const UINT8 *map_da
void segaic16_memory_mapper_set_decrypted(running_machine *machine, UINT8 *decrypted)
{
struct memory_mapper_chip *chip = &memory_mapper;
offs_t romsize = memory_region_length(machine, chip->cpu);
offs_t romsize = chip->cpu->regionbytes;
int rgnum;
/* loop over the regions */
for (rgnum = 0; chip->map[rgnum].regbase != 0; rgnum++)
{
static const offs_t region_size_map[4] = { 0x00ffff, 0x01ffff, 0x07ffff, 0x1fffff };
const struct segaic16_memory_map_entry *rgn = &chip->map[rgnum];
const segaic16_memory_map_entry *rgn = &chip->map[rgnum];
offs_t region_size = region_size_map[chip->regs[rgn->regbase] & 3];
offs_t region_base = (chip->regs[rgn->regbase + 1] << 16) & ~region_size;
offs_t region_start = region_base + (rgn->regoffs & region_size);
@ -215,7 +215,7 @@ static void memory_mapper_w(const address_space *space, struct memory_mapper_chi
/* 03 - maybe controls halt and reset lines together? */
if ((oldval ^ chip->regs[offset]) & 3)
{
cputag_set_input_line(space->machine, chip->cpu, INPUT_LINE_RESET, (chip->regs[offset] & 3) == 3 ? ASSERT_LINE : CLEAR_LINE);
cpu_set_input_line(chip->cpu, INPUT_LINE_RESET, (chip->regs[offset] & 3) == 3 ? ASSERT_LINE : CLEAR_LINE);
if ((chip->regs[offset] & 3) == 3)
fd1094_machine_init(space->machine->cpu[0]);
}
@ -223,13 +223,13 @@ static void memory_mapper_w(const address_space *space, struct memory_mapper_chi
case 0x03:
if (chip->sound_w)
(*chip->sound_w)(data);
(*chip->sound_w)(space->machine, data);
break;
case 0x04:
/* controls IRQ lines to 68000, negative logic -- write $B to signal IRQ4 */
if ((chip->regs[offset] & 7) != 7)
cputag_set_input_line(space->machine, chip->cpu, (~chip->regs[offset] & 7), HOLD_LINE);
cpu_set_input_line(chip->cpu, (~chip->regs[offset] & 7), HOLD_LINE);
break;
case 0x05:
@ -239,7 +239,7 @@ static void memory_mapper_w(const address_space *space, struct memory_mapper_chi
if (data == 0x01)
{
offs_t addr = (chip->regs[0x0a] << 17) | (chip->regs[0x0b] << 9) | (chip->regs[0x0c] << 1);
cpu_push_context(space->machine->cpu[mame_find_cpu_index(space->machine, chip->cpu)]);
cpu_push_context(chip->cpu);
program_write_word_16be(addr, (chip->regs[0x00] << 8) | chip->regs[0x01]);
cpu_pop_context();
}
@ -247,7 +247,7 @@ static void memory_mapper_w(const address_space *space, struct memory_mapper_chi
{
offs_t addr = (chip->regs[0x07] << 17) | (chip->regs[0x08] << 9) | (chip->regs[0x09] << 1);
UINT16 result;
cpu_push_context(space->machine->cpu[mame_find_cpu_index(space->machine, chip->cpu)]);
cpu_push_context(chip->cpu);
result = program_read_word_16be(addr);
cpu_pop_context();
chip->regs[0x00] = result >> 8;
@ -309,7 +309,7 @@ static UINT16 memory_mapper_r(struct memory_mapper_chip *chip, offs_t offset, UI
case 0x03:
/* this returns data that the sound CPU writes */
if (chip->sound_r)
return (*chip->sound_r)();
return (*chip->sound_r)(chip->cpu->machine);
return 0xff;
default:
@ -327,13 +327,13 @@ static void update_memory_mapping(running_machine *machine, struct memory_mapper
if (LOG_MEMORY_MAP) mame_printf_debug("----\nRemapping:\n");
/* first reset everything back to the beginning */
memory_install_readwrite16_handler(machine, mame_find_cpu_index(machine, chip->cpu), ADDRESS_SPACE_PROGRAM, 0x000000, 0xffffff, 0, 0, segaic16_memory_mapper_lsb_r, segaic16_memory_mapper_lsb_w);
memory_install_readwrite16_handler(machine, cpu_get_index(chip->cpu), ADDRESS_SPACE_PROGRAM, 0x000000, 0xffffff, 0, 0, segaic16_memory_mapper_lsb_r, segaic16_memory_mapper_lsb_w);
/* loop over the regions */
for (rgnum = 0; chip->map[rgnum].regbase != 0; rgnum++)
{
static const offs_t region_size_map[4] = { 0x00ffff, 0x01ffff, 0x07ffff, 0x1fffff };
const struct segaic16_memory_map_entry *rgn = &chip->map[rgnum];
const segaic16_memory_map_entry *rgn = &chip->map[rgnum];
offs_t region_size = region_size_map[chip->regs[rgn->regbase] & 3];
offs_t region_base = (chip->regs[rgn->regbase + 1] << 16) & ~region_size;
offs_t region_mirror = rgn->mirror & region_size;
@ -352,7 +352,7 @@ static void update_memory_mapping(running_machine *machine, struct memory_mapper
/* ROM areas need extra clamping */
if (rgn->romoffset != ~0)
{
offs_t romsize = memory_region_length(machine, chip->cpu);
offs_t romsize = chip->cpu->regionbytes;
if (region_start >= romsize)
read = NULL;
else if (region_start + rgn->length > romsize)
@ -361,9 +361,9 @@ static void update_memory_mapping(running_machine *machine, struct memory_mapper
/* map it */
if (read)
memory_install_read16_handler(machine, mame_find_cpu_index(machine, chip->cpu), ADDRESS_SPACE_PROGRAM, region_start, region_end, 0, region_mirror, read);
memory_install_read16_handler(machine, cpu_get_index(chip->cpu), ADDRESS_SPACE_PROGRAM, region_start, region_end, 0, region_mirror, read);
if (write)
memory_install_write16_handler(machine, mame_find_cpu_index(machine, chip->cpu), ADDRESS_SPACE_PROGRAM, region_start, region_end, 0, region_mirror, write);
memory_install_write16_handler(machine, cpu_get_index(chip->cpu), ADDRESS_SPACE_PROGRAM, region_start, region_end, 0, region_mirror, write);
/* set the bank pointer */
if (banknum && read)
@ -381,7 +381,7 @@ static void update_memory_mapping(running_machine *machine, struct memory_mapper
if (!decrypted)
decrypted = fd1089_get_decrypted_base();
memory_configure_bank(banknum, 0, 1, memory_region(machine, chip->cpu) + region_start, 0);
memory_configure_bank(banknum, 0, 1, (UINT8 *)chip->cpu->region + region_start, 0);
if (decrypted)
memory_configure_bank_decrypted(banknum, 0, 1, decrypted ? (decrypted + region_start) : 0, 0);
memory_set_bank(banknum, 0);
@ -582,7 +582,7 @@ WRITE16_HANDLER( segaic16_divide_2_w ) { divide_w(space, 2, offset, data, mem_ma
*
*************************************/
void segaic16_compare_timer_init(int which, void (*sound_write_callback)(UINT8), void (*timer_ack_callback)(running_machine *))
void segaic16_compare_timer_init(int which, void (*sound_write_callback)(running_machine *, UINT8), void (*timer_ack_callback)(running_machine *))
{
compare_timer[which].sound_w = sound_write_callback;
compare_timer[which].timer_ack = timer_ack_callback;
@ -687,7 +687,7 @@ static void compare_timer_w(const address_space *space, int which, offs_t offset
case 0xf:
COMBINE_DATA(&compare_timer[which].regs[11]);
if (compare_timer[which].sound_w)
(*compare_timer[which].sound_w)(compare_timer[which].regs[11]);
(*compare_timer[which].sound_w)(space->machine, compare_timer[which].regs[11]);
break;
}
}

7
src/mame/machine/segaic16.h
View File

@ -8,7 +8,8 @@
READ16_HANDLER( segaic16_open_bus_r );
/* memory mapping chip */
struct segaic16_memory_map_entry
typedef struct _segaic16_memory_map_entry segaic16_memory_map_entry;
struct _segaic16_memory_map_entry
{
UINT8 regbase; /* register offset for this region */
offs_t regoffs; /* offset within the region for this entry */
@ -21,7 +22,7 @@ struct segaic16_memory_map_entry
const char * name; /* friendly name for debugging */
};
void segaic16_memory_mapper_init(running_machine *machine, const char *cpu, const struct segaic16_memory_map_entry *entrylist, void (*sound_w_callback)(UINT8), UINT8 (*sound_r_callback)(void));
void segaic16_memory_mapper_init(const device_config *cpu, const segaic16_memory_map_entry *entrylist, void (*sound_w_callback)(running_machine *, UINT8), UINT8 (*sound_r_callback)(running_machine *));
void segaic16_memory_mapper_reset(running_machine *machine);
void segaic16_memory_mapper_config(running_machine *machine, const UINT8 *map_data);
void segaic16_memory_mapper_set_decrypted(running_machine *machine, UINT8 *decrypted);
@ -47,7 +48,7 @@ WRITE16_HANDLER( segaic16_divide_1_w );
WRITE16_HANDLER( segaic16_divide_2_w );
/* compare/timer chip */
void segaic16_compare_timer_init(int which, void (*sound_write_callback)(UINT8), void (*timer_ack_callback)(running_machine *));
void segaic16_compare_timer_init(int which, void (*sound_write_callback)(running_machine *, UINT8), void (*timer_ack_callback)(running_machine *));
int segaic16_compare_timer_clock(int which);
READ16_HANDLER( segaic16_compare_timer_0_r );
READ16_HANDLER( segaic16_compare_timer_1_r );

55
src/mame/machine/williams.c
View File

@ -256,10 +256,11 @@ const pia6821_interface joust2_pia_1_intf =
static TIMER_CALLBACK( williams_va11_callback )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
int scanline = param;
/* the IRQ signal comes into CB1, and is set to VA11 */
pia_1_cb1_w(machine, 0, scanline & 0x20);
pia_1_cb1_w(space, 0, scanline & 0x20);
/* set a timer for the next update */
scanline += 0x20;
@ -270,15 +271,19 @@ static TIMER_CALLBACK( williams_va11_callback )
static TIMER_CALLBACK( williams_count240_off_callback )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
/* the COUNT240 signal comes into CA1, and is set to the logical AND of VA10-VA13 */
pia_1_ca1_w(machine, 0, 0);
pia_1_ca1_w(space, 0, 0);
}
static TIMER_CALLBACK( williams_count240_callback )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
/* the COUNT240 signal comes into CA1, and is set to the logical AND of VA10-VA13 */
pia_1_ca1_w(machine, 0, 1);
pia_1_ca1_w(space, 0, 1);
/* set a timer to turn it off once the scanline counter resets */
timer_set(video_screen_get_time_until_pos(machine->primary_screen, 0, 0), NULL, 0, williams_count240_off_callback);
@ -384,11 +389,12 @@ MACHINE_RESET( williams )
static TIMER_CALLBACK( williams2_va11_callback )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
int scanline = param;
/* the IRQ signal comes into CB1, and is set to VA11 */
pia_0_cb1_w(machine, 0, scanline & 0x20);
pia_1_ca1_w(machine, 0, scanline & 0x20);
pia_0_cb1_w(space, 0, scanline & 0x20);
pia_1_ca1_w(space, 0, scanline & 0x20);
/* set a timer for the next update */
scanline += 0x20;
@ -399,15 +405,19 @@ static TIMER_CALLBACK( williams2_va11_callback )
static TIMER_CALLBACK( williams2_endscreen_off_callback )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
/* the /ENDSCREEN signal comes into CA1 */
pia_0_ca1_w(machine, 0, 1);
pia_0_ca1_w(space, 0, 1);
}
static TIMER_CALLBACK( williams2_endscreen_callback )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
/* the /ENDSCREEN signal comes into CA1 */
pia_0_ca1_w(machine, 0, 0);
pia_0_ca1_w(space, 0, 0);
/* set a timer to turn it off once the scanline counter resets */
timer_set(video_screen_get_time_until_pos(machine->primary_screen, 8, 0), NULL, 0, williams2_endscreen_off_callback);
@ -426,12 +436,15 @@ static TIMER_CALLBACK( williams2_endscreen_callback )
static STATE_POSTLOAD( williams2_postload )
{
williams2_bank_select_w(machine, 0, vram_bank);
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
williams2_bank_select_w(space, 0, vram_bank);
}
MACHINE_RESET( williams2 )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
/* reset the PIAs */
pia_reset();
@ -440,7 +453,7 @@ MACHINE_RESET( williams2 )
memory_configure_bank(1, 1, 4, memory_region(machine, "main") + 0x10000, 0x10000);
/* make sure our banking is reset */
williams2_bank_select_w(machine, 0, 0);
williams2_bank_select_w(space, 0, 0);
/* set a timer to go off every 16 scanlines, to toggle the VA11 line and update the screen */
scanline_timer = timer_alloc(williams2_va11_callback, NULL);
@ -516,30 +529,32 @@ WRITE8_HANDLER( williams2_bank_select_w )
static TIMER_CALLBACK( williams_deferred_snd_cmd_w )
{
pia_2_portb_w(machine, 0, param);
pia_2_cb1_w(machine, 0, (param == 0xff) ? 0 : 1);
const address_space *space = ptr;
pia_2_portb_w(space, 0, param);
pia_2_cb1_w(space, 0, (param == 0xff) ? 0 : 1);
}
WRITE8_HANDLER( williams_snd_cmd_w )
{
/* the high two bits are set externally, and should be 1 */
timer_call_after_resynch(NULL, data | 0xc0, williams_deferred_snd_cmd_w);
timer_call_after_resynch((void *)space, data | 0xc0, williams_deferred_snd_cmd_w);
}
WRITE8_HANDLER( playball_snd_cmd_w )
{
timer_call_after_resynch(NULL, data, williams_deferred_snd_cmd_w);
timer_call_after_resynch((void *)space, data, williams_deferred_snd_cmd_w);
}
static TIMER_CALLBACK( williams2_deferred_snd_cmd_w )
{
pia_2_porta_w(machine, 0, param);
const address_space *space = ptr;
pia_2_porta_w(space, 0, param);
}
static WRITE8_HANDLER( williams2_snd_cmd_w )
{
timer_call_after_resynch(NULL, data, williams2_deferred_snd_cmd_w);
timer_call_after_resynch((void *)space, data, williams2_deferred_snd_cmd_w);
}
@ -700,17 +715,20 @@ WRITE8_HANDLER( williams2_7segment_w )
static STATE_POSTLOAD( defender_postload )
{
defender_bank_select_w(machine, 0, vram_bank);
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
defender_bank_select_w(space, 0, vram_bank);
}
MACHINE_RESET( defender )
{
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
MACHINE_RESET_CALL(williams_common);
/* configure the banking and make sure it is reset to 0 */
memory_configure_bank(1, 0, 9, &memory_region(machine, "main")[0x10000], 0x1000);
defender_bank_select_w(machine, 0, 0);
defender_bank_select_w(space, 0, 0);
state_save_register_postload(machine, defender_postload, NULL);
}
@ -930,7 +948,8 @@ MACHINE_RESET( joust2 )
static TIMER_CALLBACK( joust2_deferred_snd_cmd_w )
{
pia_2_porta_w(machine, 0, param & 0xff);
const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
pia_2_porta_w(space, 0, param & 0xff);
}

6
src/mame/video/segas32.c
View File

@ -438,7 +438,7 @@ INLINE UINT16 common_paletteram_r(int which, offs_t offset)
}
static void common_paletteram_w(running_machine *machine, int which, offs_t offset, UINT16 data, UINT16 mem_mask)
static void common_paletteram_w(const address_space *space, int which, offs_t offset, UINT16 data, UINT16 mem_mask)
{
UINT16 value;
int convert;
@ -456,7 +456,7 @@ static void common_paletteram_w(running_machine *machine, int which, offs_t offs
COMBINE_DATA(&value);
if (convert) value = xBGRBBBBGGGGRRRR_to_xBBBBBGGGGGRRRRR(value);
system32_paletteram[which][offset] = value;
update_color(machine, 0x4000*which + offset, value);
update_color(space->machine, 0x4000*which + offset, value);
/* if blending is enabled, writes go to both halves of palette RAM */
if (mixer_control[which][0x4e/2] & 0x0880)
@ -469,7 +469,7 @@ static void common_paletteram_w(running_machine *machine, int which, offs_t offs
COMBINE_DATA(&value);
if (convert) value = xBGRBBBBGGGGRRRR_to_xBBBBBGGGGGRRRRR(value);
system32_paletteram[which][offset] = value;
update_color(machine, 0x4000*which + offset, value);
update_color(space->machine, 0x4000*which + offset, value);
}
}