diff --git a/src/emu/cpu/minx/minx.c b/src/emu/cpu/minx/minx.c index d34f08398d1..7f36244622c 100644 --- a/src/emu/cpu/minx/minx.c +++ b/src/emu/cpu/minx/minx.c @@ -37,11 +37,8 @@ TODO: - Add support for O and C flags in NEG8 instruction -- Add support for CE D8 (MUL) and CE D9 (DIV) -- Add support for CF xx instructions +- Verify MUL (CE D8) and DIV (CE D9) - Doublecheck behaviour of CMPN instructions ( CF 60 .. CF 63 ) -- Figure out the number of cycles taken by each instruction (this - information is currently not known/available). */ @@ -69,100 +66,162 @@ TODO: typedef struct { // MINX_CONFIG config; - UINT16 PC; - UINT16 SP; - UINT16 BA; - UINT16 HL; - UINT16 X; - UINT16 Y; - UINT8 U; - UINT8 V; - UINT8 F; - UINT8 E; - UINT8 N; - UINT8 I; - UINT8 XI; - UINT8 YI; - UINT8 check_interrupt; + UINT16 PC; + UINT16 SP; + UINT16 BA; + UINT16 HL; + UINT16 X; + UINT16 Y; + UINT8 U; + UINT8 V; + UINT8 F; + UINT8 E; + UINT8 N; + UINT8 I; + UINT8 XI; + UINT8 YI; + UINT8 halted; + UINT8 interrupt_pending; + int (*irq_callback)(int irqline); } minx_regs; static minx_regs regs; static int minx_icount; -#define rd(offset) program_read_byte_8be( offset ) -#define wr(offset,data) program_write_byte_8be( offset, data ) -#define minx_PC ( ( regs.PC & 0x8000 ) ? ( regs.V << 15 ) | (regs.PC & 0x7FFF ) : regs.PC ) +#define RD(offset) program_read_byte_8be( offset ) +#define WR(offset,data) program_write_byte_8be( offset, data ) +#define GET_MINX_PC ( ( regs.PC & 0x8000 ) ? ( regs.V << 15 ) | (regs.PC & 0x7FFF ) : regs.PC ) -INLINE UINT16 rd16( UINT32 offset ) { - return rd( offset ) | ( rd( offset + 1 ) << 8 ); + +INLINE UINT16 rd16( UINT32 offset ) +{ + return RD( offset ) | ( RD( offset + 1 ) << 8 ); } -INLINE void wr16( UINT32 offset, UINT16 data ) { - wr( offset, ( data & 0x00FF ) ); - wr( offset + 1, ( data >> 8 ) ); + +INLINE void wr16( UINT32 offset, UINT16 data ) +{ + WR( offset, ( data & 0x00FF ) ); + WR( offset + 1, ( data >> 8 ) ); } -static void minx_init(int index, int clock, const void *config, int (*irqcallback)(int)) { - if ( config != NULL ) { - } else { + +static void minx_init(int index, int clock, const void *config, int (*irqcallback)(int)) +{ + regs.irq_callback = irqcallback; + if ( config != NULL ) + { + } + else + { } } -static void minx_reset( void ) { - memset( ®s, 0, sizeof(regs) ); - regs.PC = ( rd( 1 ) << 8 ) | rd( 0 ); + +static void minx_reset( void ) +{ + regs.SP = regs.BA = regs.HL = regs.X = regs.Y = 0; + regs.U = regs.V = regs.F = regs.E = regs.I = regs.XI = regs.YI = 0; + regs.halted = regs.interrupt_pending = 0; + + regs.PC = rd16( 0 ); change_pc( regs.PC ); } -static void minx_exit( void ) { + +static void minx_exit( void ) +{ } -INLINE UINT8 rdop( void ) { - UINT8 op = rd( minx_PC ); + +INLINE UINT8 rdop( void ) +{ + UINT8 op = RD( GET_MINX_PC ); regs.PC++; return op; } -INLINE UINT16 rdop16( void ) { + +INLINE UINT16 rdop16( void ) +{ UINT16 op = rdop(); op = op | ( rdop() << 8 ); return op; } + #include "minxfunc.h" #include "minxopce.h" #include "minxopcf.h" #include "minxops.h" -static int minx_execute( int cycles ) { + +static int minx_execute( int cycles ) +{ UINT32 oldpc; UINT8 op; minx_icount = cycles; - do { - CALL_DEBUGGER(minx_PC); - oldpc = minx_PC; - op = rdop(); - insnminx[op](); - minx_icount -= insnminx_cycles[op]; + do + { + CALL_DEBUGGER(GET_MINX_PC); + oldpc = GET_MINX_PC; + + if ( regs.interrupt_pending ) + { + regs.halted = 0; + if ( ( regs.F & 0xc0 ) == 0x40 ) + { + logerror("minx_execute(): taking IRQ\n"); + PUSH8( regs.V ); + PUSH16( regs.PC ); + PUSH8( regs.F ); + + /* Set Interrupt Branch flag */ + regs.F |= 0x80; + regs.V = 0; + regs.PC = rd16( regs.irq_callback( 0 ) << 1 ); + minx_icount -= 28; /* This cycle count is a guess */ + } + } + + if ( regs.halted ) + { + minx_icount -= insnminx_cycles_CE[0xAE]; + } + else + { + op = rdop(); + insnminx[op](); + minx_icount -= insnminx_cycles[op]; + } } while ( minx_icount > 0 ); return cycles - minx_icount; } -static void minx_burn( int cycles ) { + +static void minx_burn( int cycles ) +{ minx_icount = 0; } -static void minx_set_context( void *src ) { + +static void minx_set_context( void *src ) +{ } -static void minx_get_context( void *dst ) { + +static void minx_get_context( void *dst ) +{ } -static unsigned minx_get_reg( int regnum ) { - switch( regnum ) { - case REG_PC: return (regs.PC & 0x8000) ? ( regs.V << 15 ) | ( regs.PC & 0x7FFF ) : regs.PC; + +static unsigned minx_get_reg( int regnum ) +{ + switch( regnum ) + { + case REG_PC: return GET_MINX_PC; case MINX_PC: return regs.PC; case REG_SP: case MINX_SP: return regs.SP; @@ -182,9 +241,12 @@ static unsigned minx_get_reg( int regnum ) { return 0; } -static void minx_set_reg( int regnum, unsigned val ) { - switch( regnum ) { - case REG_PC: + +static void minx_set_reg( int regnum, unsigned val ) +{ + switch( regnum ) + { + case REG_PC: break; case MINX_PC: regs.PC = val; break; case REG_SP: case MINX_SP: regs.SP = val; break; @@ -203,14 +265,24 @@ static void minx_set_reg( int regnum, unsigned val ) { } } -static void minx_set_irq_line( int irqline, int state ) { - if ( state == ASSERT_LINE ) { - } else { + +static void minx_set_irq_line( int irqline, int state ) +{ + if ( state == ASSERT_LINE ) + { + regs.interrupt_pending = 1; + } + else + { + regs.interrupt_pending = 0; } } -static void minx_set_info( UINT32 state, cpuinfo *info ) { - switch( state ) { + +static void minx_set_info( UINT32 state, cpuinfo *info ) +{ + switch( state ) + { case CPUINFO_INT_INPUT_STATE + 0: minx_set_irq_line( state - CPUINFO_INT_INPUT_STATE, info->i ); break; @@ -232,29 +304,32 @@ static void minx_set_info( UINT32 state, cpuinfo *info ) { } } -void minx_get_info( UINT32 state, cpuinfo *info ) { - switch( state ) { - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(minx_regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break; - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 4; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 23; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; break; - case CPUINFO_INT_REGISTER + REG_PC: + +void minx_get_info( UINT32 state, cpuinfo *info ) +{ + switch( state ) + { + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(minx_regs); break; + case CPUINFO_INT_INPUT_LINES: info->i = 1; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0x00; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 4; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 24; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; break; + case CPUINFO_INT_REGISTER + REG_PC: info->i = GET_MINX_PC; break; case CPUINFO_INT_REGISTER + REG_SP: case CPUINFO_INT_REGISTER + MINX_PC: case CPUINFO_INT_REGISTER + MINX_SP: @@ -269,25 +344,25 @@ void minx_get_info( UINT32 state, cpuinfo *info ) { case CPUINFO_INT_REGISTER + MINX_N: case CPUINFO_INT_REGISTER + MINX_I: case CPUINFO_INT_REGISTER + MINX_XI: - case CPUINFO_INT_REGISTER + MINX_YI: info->i = minx_get_reg( state - CPUINFO_INT_REGISTER ); break; - case CPUINFO_INT_PREVIOUSPC: info->i = 0x0000; break; - case CPUINFO_PTR_SET_INFO: info->setinfo = minx_set_info; break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = minx_get_context; break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = minx_set_context; break; - case CPUINFO_PTR_INIT: info->init = minx_init; break; - case CPUINFO_PTR_RESET: info->reset = minx_reset; break; - case CPUINFO_PTR_EXIT: info->exit = minx_exit; break; - case CPUINFO_PTR_EXECUTE: info->execute = minx_execute; break; - case CPUINFO_PTR_BURN: info->burn = minx_burn; break; + case CPUINFO_INT_REGISTER + MINX_YI: info->i = minx_get_reg( state - CPUINFO_INT_REGISTER ); break; + case CPUINFO_INT_PREVIOUSPC: info->i = 0x0000; break; + case CPUINFO_PTR_SET_INFO: info->setinfo = minx_set_info; break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = minx_get_context; break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = minx_set_context; break; + case CPUINFO_PTR_INIT: info->init = minx_init; break; + case CPUINFO_PTR_RESET: info->reset = minx_reset; break; + case CPUINFO_PTR_EXIT: info->exit = minx_exit; break; + case CPUINFO_PTR_EXECUTE: info->execute = minx_execute; break; + case CPUINFO_PTR_BURN: info->burn = minx_burn; break; #ifdef ENABLE_DEBUGGER - case CPUINFO_PTR_DISASSEMBLE: info->disassemble = minx_dasm; break; + case CPUINFO_PTR_DISASSEMBLE: info->disassemble = minx_dasm; break; #endif - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx_icount; break; - case CPUINFO_STR_NAME: strcpy( info->s = cpuintrf_temp_str(), "Minx" ); break; - case CPUINFO_STR_CORE_FAMILY: strcpy( info->s = cpuintrf_temp_str(), "Nintendo Minx" ); break; - case CPUINFO_STR_CORE_VERSION: strcpy( info->s = cpuintrf_temp_str(), "0.1" ); break; - case CPUINFO_STR_CORE_FILE: strcpy( info->s = cpuintrf_temp_str(), __FILE__ ); break; - case CPUINFO_STR_CORE_CREDITS: strcpy( info->s = cpuintrf_temp_str(), "Copyright The MESS Team." ); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx_icount; break; + case CPUINFO_STR_NAME: strcpy( info->s = cpuintrf_temp_str(), "Minx" ); break; + case CPUINFO_STR_CORE_FAMILY: strcpy( info->s = cpuintrf_temp_str(), "Nintendo Minx" ); break; + case CPUINFO_STR_CORE_VERSION: strcpy( info->s = cpuintrf_temp_str(), "0.1" ); break; + case CPUINFO_STR_CORE_FILE: strcpy( info->s = cpuintrf_temp_str(), __FILE__ ); break; + case CPUINFO_STR_CORE_CREDITS: strcpy( info->s = cpuintrf_temp_str(), "Copyright The MESS Team." ); break; case CPUINFO_STR_FLAGS: sprintf( info->s = cpuintrf_temp_str(), "%c%c%c%c%c%c%c%c-%c%c%c%c%c", regs.F & FLAG_I ? 'I' : '.', @@ -304,23 +379,20 @@ void minx_get_info( UINT32 state, cpuinfo *info ) { regs.E & EXEC_DZ ? 'z' : '.', regs.E & EXEC_EN ? 'E' : '.' ); break; - case CPUINFO_STR_REGISTER + MINX_PC: sprintf( info->s = cpuintrf_temp_str(), "PC:%04X", regs.PC ); break; - case CPUINFO_STR_REGISTER + MINX_SP: sprintf( info->s = cpuintrf_temp_str(), "SP:%04X", regs.SP ); break; - case CPUINFO_STR_REGISTER + MINX_BA: sprintf( info->s = cpuintrf_temp_str(), "BA:%04X", regs.BA ); break; - case CPUINFO_STR_REGISTER + MINX_HL: sprintf( info->s = cpuintrf_temp_str(), "HL:%04X", regs.HL ); break; - case CPUINFO_STR_REGISTER + MINX_X: sprintf( info->s = cpuintrf_temp_str(), "X:%04X", regs.X ); break; - case CPUINFO_STR_REGISTER + MINX_Y: sprintf( info->s = cpuintrf_temp_str(), "Y:%04X", regs.Y ); break; - case CPUINFO_STR_REGISTER + MINX_U: sprintf( info->s = cpuintrf_temp_str(), "U:%02X", regs.U ); break; - case CPUINFO_STR_REGISTER + MINX_V: sprintf( info->s = cpuintrf_temp_str(), "V:%02X", regs.V ); break; - case CPUINFO_STR_REGISTER + MINX_F: sprintf( info->s = cpuintrf_temp_str(), "F:%02X", regs.F ); break; - case CPUINFO_STR_REGISTER + MINX_E: sprintf( info->s = cpuintrf_temp_str(), "E:%02X", regs.E ); break; - case CPUINFO_STR_REGISTER + MINX_N: sprintf( info->s = cpuintrf_temp_str(), "N:%02X", regs.N ); break; - case CPUINFO_STR_REGISTER + MINX_I: sprintf( info->s = cpuintrf_temp_str(), "I:%02X", regs.I ); break; - case CPUINFO_STR_REGISTER + MINX_XI: sprintf( info->s = cpuintrf_temp_str(), "XI:%02X", regs.XI ); break; - case CPUINFO_STR_REGISTER + MINX_YI: sprintf( info->s = cpuintrf_temp_str(), "YI:%02X", regs.YI ); break; + case CPUINFO_STR_REGISTER + MINX_PC: sprintf( info->s = cpuintrf_temp_str(), "PC:%04X", regs.PC ); break; + case CPUINFO_STR_REGISTER + MINX_SP: sprintf( info->s = cpuintrf_temp_str(), "SP:%04X", regs.SP ); break; + case CPUINFO_STR_REGISTER + MINX_BA: sprintf( info->s = cpuintrf_temp_str(), "BA:%04X", regs.BA ); break; + case CPUINFO_STR_REGISTER + MINX_HL: sprintf( info->s = cpuintrf_temp_str(), "HL:%04X", regs.HL ); break; + case CPUINFO_STR_REGISTER + MINX_X: sprintf( info->s = cpuintrf_temp_str(), "X:%04X", regs.X ); break; + case CPUINFO_STR_REGISTER + MINX_Y: sprintf( info->s = cpuintrf_temp_str(), "Y:%04X", regs.Y ); break; + case CPUINFO_STR_REGISTER + MINX_U: sprintf( info->s = cpuintrf_temp_str(), "U:%02X", regs.U ); break; + case CPUINFO_STR_REGISTER + MINX_V: sprintf( info->s = cpuintrf_temp_str(), "V:%02X", regs.V ); break; + case CPUINFO_STR_REGISTER + MINX_F: sprintf( info->s = cpuintrf_temp_str(), "F:%02X", regs.F ); break; + case CPUINFO_STR_REGISTER + MINX_E: sprintf( info->s = cpuintrf_temp_str(), "E:%02X", regs.E ); break; + case CPUINFO_STR_REGISTER + MINX_N: sprintf( info->s = cpuintrf_temp_str(), "N:%02X", regs.N ); break; + case CPUINFO_STR_REGISTER + MINX_I: sprintf( info->s = cpuintrf_temp_str(), "I:%02X", regs.I ); break; + case CPUINFO_STR_REGISTER + MINX_XI: sprintf( info->s = cpuintrf_temp_str(), "XI:%02X", regs.XI ); break; + case CPUINFO_STR_REGISTER + MINX_YI: sprintf( info->s = cpuintrf_temp_str(), "YI:%02X", regs.YI ); break; } } - - - diff --git a/src/emu/cpu/minx/minxfunc.h b/src/emu/cpu/minx/minxfunc.h index 1a59dd1f2c9..ee170722ef0 100644 --- a/src/emu/cpu/minx/minxfunc.h +++ b/src/emu/cpu/minx/minxfunc.h @@ -1,5 +1,6 @@ -INLINE UINT8 ADD8( UINT8 arg1, UINT8 arg2 ) { +INLINE UINT8 ADD8( UINT8 arg1, UINT8 arg2 ) +{ UINT32 res = arg1 + arg2; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -10,7 +11,9 @@ INLINE UINT8 ADD8( UINT8 arg1, UINT8 arg2 ) { return res & 0xFF; } -INLINE UINT16 ADD16( UINT16 arg1, UINT16 arg2 ) { + +INLINE UINT16 ADD16( UINT16 arg1, UINT16 arg2 ) +{ UINT32 res = arg1 + arg2; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) @@ -21,7 +24,9 @@ INLINE UINT16 ADD16( UINT16 arg1, UINT16 arg2 ) { return res & 0xFFFF; } -INLINE UINT8 ADDC8( UINT8 arg1, UINT8 arg2 ) { + +INLINE UINT8 ADDC8( UINT8 arg1, UINT8 arg2 ) +{ UINT32 res = arg1 + arg2 + ( ( regs.F & FLAG_C ) ? 1 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -32,7 +37,9 @@ INLINE UINT8 ADDC8( UINT8 arg1, UINT8 arg2 ) { return res & 0xFF; } -INLINE UINT16 ADDC16( UINT16 arg1, UINT16 arg2 ) { + +INLINE UINT16 ADDC16( UINT16 arg1, UINT16 arg2 ) +{ UINT32 res = arg1 + arg2 + ( ( regs.F & FLAG_C ) ? 1 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) @@ -43,15 +50,21 @@ INLINE UINT16 ADDC16( UINT16 arg1, UINT16 arg2 ) { return res & 0xFFFF; } -INLINE UINT8 INC8( UINT8 arg ) { + +INLINE UINT8 INC8( UINT8 arg ) +{ return ADD8( arg, 1 ); } -INLINE UINT16 INC16( UINT16 arg ) { + +INLINE UINT16 INC16( UINT16 arg ) +{ return ADD16( arg, 1 ); } -INLINE UINT8 SUB8( UINT8 arg1, UINT8 arg2 ) { + +INLINE UINT8 SUB8( UINT8 arg1, UINT8 arg2 ) +{ UINT32 res = arg1 - arg2; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -62,7 +75,9 @@ INLINE UINT8 SUB8( UINT8 arg1, UINT8 arg2 ) { return res & 0xFF; } -INLINE UINT16 SUB16( UINT16 arg1, UINT16 arg2 ) { + +INLINE UINT16 SUB16( UINT16 arg1, UINT16 arg2 ) +{ UINT32 res = arg1 - arg2; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) @@ -73,7 +88,9 @@ INLINE UINT16 SUB16( UINT16 arg1, UINT16 arg2 ) { return res & 0xFFFF; } -INLINE UINT8 SUBC8( UINT8 arg1, UINT8 arg2 ) { + +INLINE UINT8 SUBC8( UINT8 arg1, UINT8 arg2 ) +{ UINT32 res = arg1 - arg2 - ( ( regs.F & FLAG_C ) ? 1 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -84,7 +101,9 @@ INLINE UINT8 SUBC8( UINT8 arg1, UINT8 arg2 ) { return res & 0xFF; } -INLINE UINT16 SUBC16( UINT16 arg1, UINT16 arg2 ) { + +INLINE UINT16 SUBC16( UINT16 arg1, UINT16 arg2 ) +{ UINT32 res = arg1 - arg2 - ( ( regs.F & FLAG_C ) ? 1 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) @@ -95,30 +114,42 @@ INLINE UINT16 SUBC16( UINT16 arg1, UINT16 arg2 ) { return res & 0xFFFF; } -INLINE UINT8 DEC8( UINT8 arg ) { + +INLINE UINT8 DEC8( UINT8 arg ) +{ return SUB8( arg, 1 ); } -INLINE UINT16 DEC16( UINT16 arg ) { + +INLINE UINT16 DEC16( UINT16 arg ) +{ return SUB16( arg, 1 ); } -INLINE UINT8 AND8( UINT8 arg1, UINT8 arg2 ) { + +INLINE UINT8 AND8( UINT8 arg1, UINT8 arg2 ) +{ UINT8 res = arg1 & arg2; return res; } -INLINE UINT8 OR8( UINT8 arg1, UINT8 arg2 ) { + +INLINE UINT8 OR8( UINT8 arg1, UINT8 arg2 ) +{ UINT8 res = arg1 | arg2; return res; } -INLINE UINT8 XOR8( UINT8 arg1, UINT8 arg2 ) { + +INLINE UINT8 XOR8( UINT8 arg1, UINT8 arg2 ) +{ UINT8 res = arg1 ^ arg2; return res; } -INLINE UINT8 NOT8( UINT8 arg ) { + +INLINE UINT8 NOT8( UINT8 arg ) +{ UINT8 res = ~arg; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -127,7 +158,9 @@ INLINE UINT8 NOT8( UINT8 arg ) { return res; } -INLINE UINT8 NEG8( UINT8 arg ) { + +INLINE UINT8 NEG8( UINT8 arg ) +{ UINT8 res = -arg; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -136,7 +169,9 @@ INLINE UINT8 NEG8( UINT8 arg ) { return res; } -INLINE UINT8 SAL8( UINT8 arg ) { + +INLINE UINT8 SAL8( UINT8 arg ) +{ UINT16 res = arg << 1; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -147,7 +182,9 @@ INLINE UINT8 SAL8( UINT8 arg ) { return res; } -INLINE UINT8 SAR8( UINT8 arg ) { + +INLINE UINT8 SAR8( UINT8 arg ) +{ UINT16 res = ( arg >> 1 ) | ( arg & 0x80 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -158,7 +195,9 @@ INLINE UINT8 SAR8( UINT8 arg ) { return res & 0xFF; } -INLINE UINT8 SHL8( UINT8 arg ) { + +INLINE UINT8 SHL8( UINT8 arg ) +{ UINT16 res = arg << 1; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -168,7 +207,9 @@ INLINE UINT8 SHL8( UINT8 arg ) { return res; } -INLINE UINT8 SHR8( UINT8 arg ) { + +INLINE UINT8 SHR8( UINT8 arg ) +{ UINT16 res = arg >> 1; regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -178,7 +219,9 @@ INLINE UINT8 SHR8( UINT8 arg ) { return res & 0xFF; } -INLINE UINT8 ROLC8( UINT8 arg ) { + +INLINE UINT8 ROLC8( UINT8 arg ) +{ UINT16 res = ( arg << 1 ) | ( ( regs.F & FLAG_C ) ? 1 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -188,7 +231,9 @@ INLINE UINT8 ROLC8( UINT8 arg ) { return res & 0xFF; } -INLINE UINT8 RORC8( UINT8 arg ) { + +INLINE UINT8 RORC8( UINT8 arg ) +{ UINT16 res = ( arg >> 1 ) | ( ( regs.F & FLAG_C ) ? 0x80 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -198,7 +243,9 @@ INLINE UINT8 RORC8( UINT8 arg ) { return res & 0xFF; } -INLINE UINT8 ROL8( UINT8 arg ) { + +INLINE UINT8 ROL8( UINT8 arg ) +{ UINT16 res = ( arg << 1 ) | ( ( arg & 0x80 ) ? 1 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -208,7 +255,9 @@ INLINE UINT8 ROL8( UINT8 arg ) { return res & 0xFF; } -INLINE UINT8 ROR8( UINT8 arg ) { + +INLINE UINT8 ROR8( UINT8 arg ) +{ UINT16 res = ( arg >> 1 ) | ( ( arg & 0x01 ) ? 0x80 : 0 ); regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) @@ -218,55 +267,67 @@ INLINE UINT8 ROR8( UINT8 arg ) { return res & 0xFF; } -INLINE void PUSH8( UINT8 arg ) { + +INLINE void PUSH8( UINT8 arg ) +{ regs.SP = regs.SP - 1; - wr( regs.SP, arg ); + WR( regs.SP, arg ); } -INLINE void PUSH16( UINT16 arg ) { + +INLINE void PUSH16( UINT16 arg ) +{ PUSH8( arg >> 8 ); PUSH8( arg & 0x00FF ); } -INLINE UINT8 POP8( void ) { - UINT8 res = rd( regs.SP ); + +INLINE UINT8 POP8( void ) +{ + UINT8 res = RD( regs.SP ); regs.SP = regs.SP + 1; return res; } -INLINE UINT16 POP16( void ) { + +INLINE UINT16 POP16( void ) +{ return POP8() | ( POP8() << 8 ); } -INLINE void JMP( UINT16 arg ) { + +INLINE void JMP( UINT16 arg ) +{ regs.V = regs.U; regs.PC = arg; + change_pc( GET_MINX_PC ); } -INLINE void CALL( UINT16 arg ) { + +INLINE void CALL( UINT16 arg ) +{ PUSH8( regs.V ); PUSH16( regs.PC ); JMP( arg ); } -static UINT32 addr1, addr2; -#define AD1_IHL addr1 = ( regs.I << 16 ) | regs.HL; -#define AD1_IN8 addr1 = ( regs.I << 16 ) | ( regs.N << 8 ) | rdop(); -#define AD1_I16 addr1 = ( regs.I << 16 ) | rdop(); addr1 |= ( rdop() << 8 ); -#define AD1_XIX addr1 = ( regs.XI << 16 ) | regs.X; -#define AD1_YIY addr1 = ( regs.YI << 16 ) | regs.Y; -#define AD1_X8 addr1 = ( regs.XI << 16 ) | ( regs.X + rdop() ); -#define AD1_Y8 addr1 = ( regs.YI << 16 ) | ( regs.Y + rdop() ); -#define AD1_XL addr1 = ( regs.XI << 16 ) | ( regs.X + ( regs.HL & 0x00FF ) ); -#define AD1_YL addr1 = ( regs.YI << 16 ) | ( regs.Y + ( regs.HL & 0x00FF ) ); -#define AD2_IHL addr2 = ( regs.I << 16 ) | regs.HL; -#define AD2_IN8 addr2 = ( regs.I << 16 ) | ( regs.N << 8 ) | rdop(); -#define AD2_I16 addr2 = ( regs.I << 16 ) | rdop(); addr2 |= ( rdop() << 8 ); -#define AD2_XIX addr2 = ( regs.XI << 16 ) | regs.X; -#define AD2_YIY addr2 = ( regs.YI << 16 ) | regs.Y; -#define AD2_X8 addr2 = ( regs.XI << 16 ) | ( regs.X + rdop() ); -#define AD2_Y8 addr2 = ( regs.YI << 16 ) | ( regs.Y + rdop() ); -#define AD2_XL addr2 = ( regs.XI << 16 ) | ( regs.X + ( regs.HL & 0x00FF ) ); -#define AD2_YL addr2 = ( regs.YI << 16 ) | ( regs.Y + ( regs.HL & 0x00FF ) ); +#define AD1_IHL UINT32 addr1 = ( regs.I << 16 ) | regs.HL +#define AD1_IN8 UINT32 addr1 = ( regs.I << 16 ) | ( regs.N << 8 ) | rdop() +#define AD1_I16 UINT32 addr1 = ( regs.I << 16 ) | rdop16() +#define AD1_XIX UINT32 addr1 = ( regs.XI << 16 ) | regs.X +#define AD1_YIY UINT32 addr1 = ( regs.YI << 16 ) | regs.Y +#define AD1_X8 UINT32 addr1 = ( regs.XI << 16 ) | ( regs.X + rdop() ) +#define AD1_Y8 UINT32 addr1 = ( regs.YI << 16 ) | ( regs.Y + rdop() ) +#define AD1_XL UINT32 addr1 = ( regs.XI << 16 ) | ( regs.X + ( regs.HL & 0x00FF ) ) +#define AD1_YL UINT32 addr1 = ( regs.YI << 16 ) | ( regs.Y + ( regs.HL & 0x00FF ) ) +#define AD2_IHL UINT32 addr2 = ( regs.I << 16 ) | regs.HL +#define AD2_IN8 UINT32 addr2 = ( regs.I << 16 ) | ( regs.N << 8 ) | rdop() +#define AD2_I16 UINT32 addr2 = ( regs.I << 16 ) | rdop(); addr2 |= ( rdop() << 8 ) +#define AD2_XIX UINT32 addr2 = ( regs.XI << 16 ) | regs.X +#define AD2_YIY UINT32 addr2 = ( regs.YI << 16 ) | regs.Y +#define AD2_X8 UINT32 addr2 = ( regs.XI << 16 ) | ( regs.X + rdop() ) +#define AD2_Y8 UINT32 addr2 = ( regs.YI << 16 ) | ( regs.Y + rdop() ) +#define AD2_XL UINT32 addr2 = ( regs.XI << 16 ) | ( regs.X + ( regs.HL & 0x00FF ) ) +#define AD2_YL UINT32 addr2 = ( regs.YI << 16 ) | ( regs.Y + ( regs.HL & 0x00FF ) ) diff --git a/src/emu/cpu/minx/minxopce.h b/src/emu/cpu/minx/minxopce.h index 7e2aa3251a7..24b88675a13 100644 --- a/src/emu/cpu/minx/minxopce.h +++ b/src/emu/cpu/minx/minxopce.h @@ -2,120 +2,120 @@ #undef OP #define OP(nn) INLINE void minx_CE_##nn(void) -OP(00) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(01) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(02) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(03) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(04) { AD1_IHL; wr( addr1, ADD8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(05) { AD1_IHL; wr( addr1, ADD8( rd( addr1 ), rdop() ) ); } -OP(06) { AD1_IHL; AD2_XIX; wr( addr1, ADD8( rd( addr1 ), rd( addr2 ) ) ); } -OP(07) { AD1_IHL; AD2_YIY; wr( addr1, ADD8( rd( addr1 ), rd( addr2 ) ) ); } -OP(08) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(09) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0C) { AD1_IHL; wr( addr1, ADDC8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(0D) { AD1_IHL; wr( addr1, ADDC8( rd( addr1 ), rdop() ) ); } -OP(0E) { AD1_IHL; AD2_XIX; wr( addr1, ADDC8( rd( addr1 ), rd( addr2 ) ) ); } -OP(0F) { AD1_IHL; AD2_YIY; wr( addr1, ADDC8( rd( addr1 ), rd( addr2 ) ) ); } +OP(00) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(01) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(02) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(03) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(04) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(05) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), rdop() ) ); } +OP(06) { AD1_IHL; AD2_XIX; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); } +OP(07) { AD1_IHL; AD2_YIY; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); } +OP(08) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(09) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0C) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(0D) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), rdop() ) ); } +OP(0E) { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); } +OP(0F) { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); } -OP(10) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(11) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(12) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(13) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(14) { AD1_IHL; wr( addr1, SUB8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(15) { AD1_IHL; wr( addr1, SUB8( rd( addr1 ), rdop() ) ); } -OP(16) { AD1_IHL; AD2_XIX; wr( addr1, SUB8( rd( addr1 ), rd( addr2 ) ) ); } -OP(17) { AD1_IHL; AD2_YIY; wr( addr1, SUB8( rd( addr1 ), rd( addr2 ) ) ); } -OP(18) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(19) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1C) { AD1_IHL; wr( addr1, SUBC8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(1D) { AD1_IHL; wr( addr1, SUBC8( rd( addr1 ), rdop() ) ); } -OP(1E) { AD1_IHL; AD2_XIX; wr( addr1, SUBC8( rd( addr1 ), rd( addr2 ) ) ); } -OP(1F) { AD1_IHL; AD2_YIY; wr( addr1, SUBC8( rd( addr1 ), rd( addr2 ) ) ); } +OP(10) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(11) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(12) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(13) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(14) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(15) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), rdop() ) ); } +OP(16) { AD1_IHL; AD2_XIX; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); } +OP(17) { AD1_IHL; AD2_YIY; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); } +OP(18) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(19) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1C) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(1D) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), rdop() ) ); } +OP(1E) { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); } +OP(1F) { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); } -OP(20) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(21) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(22) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(23) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(24) { AD1_IHL; wr( addr1, AND8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(25) { AD1_IHL; wr( addr1, AND8( rd( addr1 ), rdop() ) ); } -OP(26) { AD1_IHL; AD2_XIX; wr( addr1, AND8( rd( addr1 ), rd( addr2 ) ) ); } -OP(27) { AD1_IHL; AD2_YIY; wr( addr1, AND8( rd( addr1 ), rd( addr2 ) ) ); } -OP(28) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(29) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2C) { AD1_IHL; wr( addr1, OR8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(2D) { AD1_IHL; wr( addr1, OR8( rd( addr1 ), rdop() ) ); } -OP(2E) { AD1_IHL; AD2_XIX; wr( addr1, OR8( rd( addr1 ), rd( addr2 ) ) ); } -OP(2F) { AD1_IHL; AD2_YIY; wr( addr1, OR8( rd( addr1 ), rd( addr2 ) ) ); } +OP(20) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(21) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(22) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(23) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(24) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(25) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), rdop() ) ); } +OP(26) { AD1_IHL; AD2_XIX; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); } +OP(27) { AD1_IHL; AD2_YIY; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); } +OP(28) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(29) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2C) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(2D) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), rdop() ) ); } +OP(2E) { AD1_IHL; AD2_XIX; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); } +OP(2F) { AD1_IHL; AD2_YIY; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); } -OP(30) { AD2_X8; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(31) { AD2_Y8; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(32) { AD2_XL; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(33) { AD2_YL; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(34) { AD1_IHL; SUB8( rd( addr1 ), ( regs.BA & 0x00FF ) ); } -OP(35) { AD1_IHL; SUB8( rd( addr1 ), rdop() ); } -OP(36) { AD1_IHL; AD2_XIX; SUB8( rd( addr1 ), rd( addr2 ) ); } -OP(37) { AD1_IHL; AD2_YIY; SUB8( rd( addr1 ), rd( addr2 ) ); } -OP(38) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(39) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3C) { AD1_IHL; wr( addr1, XOR8( rd( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(3D) { AD1_IHL; wr( addr1, XOR8( rd( addr1 ), rdop() ) ); } -OP(3E) { AD1_IHL; AD2_XIX; wr( addr1, XOR8( rd( addr1 ), rd( addr2 ) ) ); } -OP(3F) { AD1_IHL; AD2_YIY; wr( addr1, XOR8( rd( addr1 ), rd( addr2 ) ) ); } +OP(30) { AD2_X8; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(31) { AD2_Y8; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(32) { AD2_XL; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(33) { AD2_YL; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(34) { AD1_IHL; SUB8( RD( addr1 ), ( regs.BA & 0x00FF ) ); } +OP(35) { AD1_IHL; SUB8( RD( addr1 ), rdop() ); } +OP(36) { AD1_IHL; AD2_XIX; SUB8( RD( addr1 ), RD( addr2 ) ); } +OP(37) { AD1_IHL; AD2_YIY; SUB8( RD( addr1 ), RD( addr2 ) ); } +OP(38) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(39) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3C) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } +OP(3D) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); } +OP(3E) { AD1_IHL; AD2_XIX; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); } +OP(3F) { AD1_IHL; AD2_YIY; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); } -OP(40) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(41) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(42) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(43) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(44) { AD1_X8; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(45) { AD1_Y8; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(46) { AD1_XL; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(47) { AD1_YL; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(48) { AD2_X8; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(49) { AD2_Y8; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(4A) { AD2_XL; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(4B) { AD2_YL; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(4C) { AD1_X8; wr( addr1, ( regs.BA >> 8 ) ); } -OP(4D) { AD1_Y8; wr( addr1, ( regs.BA >> 8 ) ); } -OP(4E) { AD1_XL; wr( addr1, ( regs.BA >> 8 ) ); } -OP(4F) { AD1_YL; wr( addr1, ( regs.BA >> 8 ) ); } +OP(40) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(41) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(42) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(43) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(44) { AD1_X8; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(45) { AD1_Y8; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(46) { AD1_XL; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(47) { AD1_YL; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(48) { AD2_X8; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(49) { AD2_Y8; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4A) { AD2_XL; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4B) { AD2_YL; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4C) { AD1_X8; WR( addr1, ( regs.BA >> 8 ) ); } +OP(4D) { AD1_Y8; WR( addr1, ( regs.BA >> 8 ) ); } +OP(4E) { AD1_XL; WR( addr1, ( regs.BA >> 8 ) ); } +OP(4F) { AD1_YL; WR( addr1, ( regs.BA >> 8 ) ); } -OP(50) { AD2_X8; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(51) { AD2_Y8; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(52) { AD2_XL; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(53) { AD2_YL; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(54) { AD1_X8; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(55) { AD1_Y8; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(56) { AD1_XL; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(57) { AD1_YL; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(58) { AD2_X8; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(59) { AD2_Y8; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(5A) { AD2_XL; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(5B) { AD2_YL; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(5C) { AD1_X8; wr( addr1, ( regs.HL >> 8 ) ); } -OP(5D) { AD1_Y8; wr( addr1, ( regs.HL >> 8 ) ); } -OP(5E) { AD1_XL; wr( addr1, ( regs.HL >> 8 ) ); } -OP(5F) { AD1_YL; wr( addr1, ( regs.HL >> 8 ) ); } +OP(50) { AD2_X8; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(51) { AD2_Y8; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(52) { AD2_XL; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(53) { AD2_YL; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(54) { AD1_X8; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(55) { AD1_Y8; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(56) { AD1_XL; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(57) { AD1_YL; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(58) { AD2_X8; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(59) { AD2_Y8; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5A) { AD2_XL; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5B) { AD2_YL; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5C) { AD1_X8; WR( addr1, ( regs.HL >> 8 ) ); } +OP(5D) { AD1_Y8; WR( addr1, ( regs.HL >> 8 ) ); } +OP(5E) { AD1_XL; WR( addr1, ( regs.HL >> 8 ) ); } +OP(5F) { AD1_YL; WR( addr1, ( regs.HL >> 8 ) ); } -OP(60) { AD1_IHL; AD2_X8; wr( addr1, rd( addr2 ) ); } -OP(61) { AD1_IHL; AD2_Y8; wr( addr1, rd( addr2 ) ); } -OP(62) { AD1_IHL; AD2_XL; wr( addr1, rd( addr2 ) ); } -OP(63) { AD1_IHL; AD2_YL; wr( addr1, rd( addr2 ) ); } +OP(60) { AD1_IHL; AD2_X8; WR( addr1, RD( addr2 ) ); } +OP(61) { AD1_IHL; AD2_Y8; WR( addr1, RD( addr2 ) ); } +OP(62) { AD1_IHL; AD2_XL; WR( addr1, RD( addr2 ) ); } +OP(63) { AD1_IHL; AD2_YL; WR( addr1, RD( addr2 ) ); } OP(64) { /* illegal operation? */ } OP(65) { /* illegal operation? */ } OP(66) { /* illegal operation? */ } OP(67) { /* illegal operation? */ } -OP(68) { AD1_XIX; AD2_X8; wr( addr1, rd( addr2 ) ); } -OP(69) { AD1_XIX; AD2_Y8; wr( addr1, rd( addr2 ) ); } -OP(6A) { AD1_XIX; AD2_XL; wr( addr1, rd( addr2 ) ); } -OP(6B) { AD1_XIX; AD2_YL; wr( addr1, rd( addr2 ) ); } +OP(68) { AD1_XIX; AD2_X8; WR( addr1, RD( addr2 ) ); } +OP(69) { AD1_XIX; AD2_Y8; WR( addr1, RD( addr2 ) ); } +OP(6A) { AD1_XIX; AD2_XL; WR( addr1, RD( addr2 ) ); } +OP(6B) { AD1_XIX; AD2_YL; WR( addr1, RD( addr2 ) ); } OP(6C) { /* illegal operation? */ } OP(6D) { /* illegal operation? */ } OP(6E) { /* illegal operation? */ } @@ -129,10 +129,10 @@ OP(74) { /* illegal operation? */ } OP(75) { /* illegal operation? */ } OP(76) { /* illegal operation? */ } OP(77) { /* illegal operation? */ } -OP(78) { AD1_YIY; AD2_X8; wr( addr1, rd( addr2 ) ); } -OP(79) { AD1_YIY; AD2_Y8; wr( addr1, rd( addr2 ) ); } -OP(7A) { AD1_YIY; AD2_XL; wr( addr1, rd( addr2 ) ); } -OP(7B) { AD1_YIY; AD2_YL; wr( addr1, rd( addr2 ) ); } +OP(78) { AD1_YIY; AD2_X8; WR( addr1, RD( addr2 ) ); } +OP(79) { AD1_YIY; AD2_Y8; WR( addr1, RD( addr2 ) ); } +OP(7A) { AD1_YIY; AD2_XL; WR( addr1, RD( addr2 ) ); } +OP(7B) { AD1_YIY; AD2_YL; WR( addr1, RD( addr2 ) ); } OP(7C) { /* illegal operation? */ } OP(7D) { /* illegal operation? */ } OP(7E) { /* illegal operation? */ } @@ -140,53 +140,53 @@ OP(7F) { /* illegal operation? */ } OP(80) { regs.BA = ( regs.BA & 0xFF00 ) | SAL8( regs.BA & 0x00FF ); } OP(81) { regs.BA = ( regs.BA & 0x00FF ) | ( SAL8( regs.BA >> 8 )<< 8 ); } -OP(82) { AD1_IN8; wr( addr1, SAL8( rd( addr1 ) ) ); } -OP(83) { AD1_IHL; wr( addr1, SAL8( rd( addr1 ) ) ); } +OP(82) { AD1_IN8; WR( addr1, SAL8( RD( addr1 ) ) ); } +OP(83) { AD1_IHL; WR( addr1, SAL8( RD( addr1 ) ) ); } OP(84) { regs.BA = ( regs.BA & 0xFF00 ) | SHL8( regs.BA & 0x00FF ); } OP(85) { regs.BA = ( regs.BA & 0x00FF ) | ( SHL8( regs.BA >> 8 ) << 8 ); } -OP(86) { AD1_IN8; wr( addr1, SHL8( rd( addr1 ) ) ); } -OP(87) { AD1_IHL; wr( addr1, SHL8( rd( addr1 ) ) ); } +OP(86) { AD1_IN8; WR( addr1, SHL8( RD( addr1 ) ) ); } +OP(87) { AD1_IHL; WR( addr1, SHL8( RD( addr1 ) ) ); } OP(88) { regs.BA = ( regs.BA & 0xFF00 ) | SAR8( regs.BA & 0x00FF ); } OP(89) { regs.BA = ( regs.BA & 0x00FF ) | ( SAR8( regs.BA >> 8 ) << 8 ); } -OP(8A) { AD1_IN8; wr( addr1, SAR8( rd( addr1 ) ) ); } -OP(8B) { AD1_IHL; wr( addr1, SAR8( rd( addr1 ) ) ); } +OP(8A) { AD1_IN8; WR( addr1, SAR8( RD( addr1 ) ) ); } +OP(8B) { AD1_IHL; WR( addr1, SAR8( RD( addr1 ) ) ); } OP(8C) { regs.BA = ( regs.BA & 0xFF00 ) | SHR8( regs.BA & 0x00FF ); } OP(8D) { regs.BA = ( regs.BA & 0x00FF ) | ( SHR8( regs.BA >> 8 ) << 8 ); } -OP(8E) { AD1_IN8; wr( addr1, SHR8( rd( addr1 ) ) ); } -OP(8F) { AD1_IHL; wr( addr1, SHR8( rd( addr1 ) ) ); } +OP(8E) { AD1_IN8; WR( addr1, SHR8( RD( addr1 ) ) ); } +OP(8F) { AD1_IHL; WR( addr1, SHR8( RD( addr1 ) ) ); } OP(90) { regs.BA = ( regs.BA & 0xFF00 ) | ROLC8( regs.BA & 0x00FF ); } OP(91) { regs.BA = ( regs.BA & 0x00FF ) | ( ROLC8( regs.BA >> 8 ) << 8 ); } -OP(92) { AD1_IN8; wr( addr1, ROLC8( rd( addr1 ) ) ); } -OP(93) { AD1_IHL; wr( addr1, ROLC8( rd( addr1 ) ) ); } +OP(92) { AD1_IN8; WR( addr1, ROLC8( RD( addr1 ) ) ); } +OP(93) { AD1_IHL; WR( addr1, ROLC8( RD( addr1 ) ) ); } OP(94) { regs.BA = ( regs.BA & 0xFF00 ) | ROL8( regs.BA & 0x00FF ); } OP(95) { regs.BA = ( regs.BA & 0x00FF ) | ( ROL8( regs.BA >> 8 ) << 8 ); } -OP(96) { AD1_IN8; wr( addr1, ROL8( rd( addr1 ) ) ); } -OP(97) { AD1_IHL; wr( addr1, ROL8( rd( addr1 ) ) ); } +OP(96) { AD1_IN8; WR( addr1, ROL8( RD( addr1 ) ) ); } +OP(97) { AD1_IHL; WR( addr1, ROL8( RD( addr1 ) ) ); } OP(98) { regs.BA = ( regs.BA & 0xFF00 ) | RORC8( regs.BA & 0x00FF ); } OP(99) { regs.BA = ( regs.BA & 0x00FF ) | ( RORC8( regs.BA >> 8 ) << 8 ); } -OP(9A) { AD1_IN8; wr( addr1, RORC8( rd( addr1 ) ) ); } -OP(9B) { AD1_IHL; wr( addr1, RORC8( rd( addr1 ) ) ); } +OP(9A) { AD1_IN8; WR( addr1, RORC8( RD( addr1 ) ) ); } +OP(9B) { AD1_IHL; WR( addr1, RORC8( RD( addr1 ) ) ); } OP(9C) { regs.BA = ( regs.BA & 0xFF00 ) | ROR8( regs.BA & 0x00FF ); } OP(9D) { regs.BA = ( regs.BA & 0x00FF ) | ( ROR8( regs.BA >> 8 ) << 8 ); } -OP(9E) { AD1_IN8; wr( addr1, ROR8( rd( addr1 ) ) ); } -OP(9F) { AD1_IHL; wr( addr1, ROR8( rd( addr1 ) ) ); } +OP(9E) { AD1_IN8; WR( addr1, ROR8( RD( addr1 ) ) ); } +OP(9F) { AD1_IHL; WR( addr1, ROR8( RD( addr1 ) ) ); } OP(A0) { regs.BA = ( regs.BA & 0xFF00 ) | NOT8( regs.BA & 0x00FF ); } OP(A1) { regs.BA = ( regs.BA & 0x00FF ) | ( NOT8( regs.BA >> 8 ) << 8 ); } -OP(A2) { AD1_IN8; wr( addr1, NOT8( rd( addr1 ) ) ); } -OP(A3) { AD1_IHL; wr( addr1, NOT8( rd( addr1 ) ) ); } +OP(A2) { AD1_IN8; WR( addr1, NOT8( RD( addr1 ) ) ); } +OP(A3) { AD1_IHL; WR( addr1, NOT8( RD( addr1 ) ) ); } OP(A4) { regs.BA = ( regs.BA & 0xFF00 ) | NEG8( regs.BA & 0x00FF ); } OP(A5) { regs.BA = ( regs.BA & 0x00FF ) | ( NEG8( regs.BA >> 8 ) << 8 ); } -OP(A6) { AD1_IN8; wr( addr1, NEG8( rd( addr1 ) ) ); } -OP(A7) { AD1_IHL; wr( addr1, NEG8( rd( addr1 ) ) ); } +OP(A6) { AD1_IN8; WR( addr1, NEG8( RD( addr1 ) ) ); } +OP(A7) { AD1_IHL; WR( addr1, NEG8( RD( addr1 ) ) ); } OP(A8) { regs.BA = ( ( regs.BA & 0x0080 ) ? ( 0xFF00 | regs.BA ) : ( regs.BA & 0x00FF ) ); } OP(A9) { /* illegal operation? */ } OP(AA) { /* illegal operation? */ } OP(AB) { /* illegal operation? */ } OP(AC) { /* illegal operation? */ } OP(AD) { /* illegal operation? */ } -OP(AE) { /* HALT */ } +OP(AE) { /* HALT */ regs.halted = 1; } OP(AF) { } OP(B0) { regs.BA = ( regs.BA & 0x00FF ) | ( AND8( ( regs.BA >> 8 ), rdop() ) << 8 ); } @@ -223,16 +223,16 @@ OP(CD) { regs.I = ( regs.BA & 0x00FF ); } OP(CE) { regs.XI = ( regs.BA & 0x00FF ); } OP(CF) { regs.YI = ( regs.BA & 0x00FF ); } -OP(D0) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(D1) { AD2_I16; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(D2) { AD2_I16; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(D3) { AD2_I16; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(D4) { AD1_I16; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(D5) { AD1_I16; wr( addr1, ( regs.BA >> 8 ) ); } -OP(D6) { AD1_I16; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(D7) { AD1_I16; wr( addr1, ( regs.HL >> 8 ) ); } -OP(D8) { } -OP(D9) { } +OP(D0) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(D1) { AD2_I16; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(D2) { AD2_I16; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(D3) { AD2_I16; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(D4) { AD1_I16; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(D5) { AD1_I16; WR( addr1, ( regs.BA >> 8 ) ); } +OP(D6) { AD1_I16; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(D7) { AD1_I16; WR( addr1, ( regs.HL >> 8 ) ); } +OP(D8) { regs.HL = ( regs.HL & 0x00FF ) * ( regs.BA & 0x00FF ); } +OP(D9) { int d = regs.HL / ( regs.BA & 0x00FF ); regs.HL = ( ( regs.HL - ( ( regs.BA & 0x00FF ) * d ) ) << 8 ) | d; } OP(DA) { /* illegal operation? */ } OP(DB) { /* illegal operation? */ } OP(DC) { /* illegal operation? */ } @@ -257,22 +257,22 @@ OP(ED) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X1 ) ) { JMP( regs.PC + d8 - 1 ) OP(EE) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X2 ) ) { JMP( regs.PC + d8 - 1 ); } } OP(EF) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_DZ ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(F0) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F1) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_Z ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F2) { INT8 d8 = rdop(); if ( !( regs.F & FLAG_Z ) && ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( regs.PC + d8 - 1 ); } } +OP(F0) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F1) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_Z ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F2) { INT8 d8 = rdop(); if ( !( regs.F & FLAG_Z ) && ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } OP(F3) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F4) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F5) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F6) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_S ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F7) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_S ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F8) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X0 ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F9) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X1 ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(FA) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X2 ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(FB) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_DZ ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(FC) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X0 ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(FD) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X1 ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(FE) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X2 ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(FF) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_DZ ) ) { CALL( regs.PC + d8 - 1 ); } } +OP(F4) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F5) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F6) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_S ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F7) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_S ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F8) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X0 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F9) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X1 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(FA) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X2 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(FB) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_DZ ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(FC) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X0 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(FD) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X1 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(FE) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X2 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(FF) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_DZ ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } static void (*const insnminx_CE[256])(void) = { minx_CE_00, minx_CE_01, minx_CE_02, minx_CE_03, minx_CE_04, minx_CE_05, minx_CE_06, minx_CE_07, @@ -310,22 +310,25 @@ static void (*const insnminx_CE[256])(void) = { }; static const int insnminx_cycles_CE[256] = { - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + 16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20, + 16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20, + 16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20, + 16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20, + + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 20, 20, 20, 20, 1, 1, 1, 1, 20, 20, 20, 20, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 20, 20, 20, 20, 1, 1, 1, 1, + + 12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16, + 12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16, 12, 12, 20, 16, + 12, 12, 20, 16, 12, 12, 20, 16, 12, 1, 1, 1, 1, 1, 8, 8, + 12, 12, 12, 1, 12, 12, 12, 1, 20, 20, 20, 20, 12, 12, 12, 1, + + 8, 8, 8, 12, 16, 12, 12, 12, 8, 8, 8, 8, 12, 8, 8, 8, + 20, 20, 20, 20, 20, 20, 20, 20, 48, 52, 1, 1, 1, 1, 1, 1, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12 }; diff --git a/src/emu/cpu/minx/minxopcf.h b/src/emu/cpu/minx/minxopcf.h index fefea13354f..01a942c47cc 100644 --- a/src/emu/cpu/minx/minxopcf.h +++ b/src/emu/cpu/minx/minxopcf.h @@ -121,14 +121,14 @@ OP(6D) { /* illegal instruction? */ } OP(6E) { regs.SP = rdop16(); } OP(6F) { /* illegal instruction? */ } -OP(70) { UINT8 ofs8 = rdop(); regs.BA = rd( regs.SP + ofs8 ); } -OP(71) { UINT8 ofs8 = rdop(); regs.HL = rd( regs.SP + ofs8 ); } -OP(72) { UINT8 ofs8 = rdop(); regs.X = rd( regs.SP + ofs8 ); } -OP(73) { UINT8 ofs8 = rdop(); regs.Y = rd( regs.SP + ofs8 ); } -OP(74) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.BA ); } -OP(75) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.HL ); } -OP(76) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.X ); } -OP(77) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.Y ); } +OP(70) { UINT8 ofs8 = rdop(); regs.BA = RD( regs.SP + ofs8 ); } +OP(71) { UINT8 ofs8 = rdop(); regs.HL = RD( regs.SP + ofs8 ); } +OP(72) { UINT8 ofs8 = rdop(); regs.X = RD( regs.SP + ofs8 ); } +OP(73) { UINT8 ofs8 = rdop(); regs.Y = RD( regs.SP + ofs8 ); } +OP(74) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.BA ); } +OP(75) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.HL ); } +OP(76) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.X ); } +OP(77) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.Y ); } OP(78) { AD2_I16; regs.SP = rd16( addr2 ); } OP(79) { /* illegal instruction? */ } OP(7A) { /* illegal instruction? */ } @@ -310,21 +310,24 @@ static void (*const insnminx_CF[256])(void) = { }; static const int insnminx_cycles_CF[256] = { - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1, + + 16, 16, 16, 16, 16, 16, 1, 1, 16, 16, 16, 16, 16, 16, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 1, 1, + 16, 16, 16, 16, 1, 1, 1, 1, 16, 1, 16, 1, 16, 1, 16, 1, + 24, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 24, 1, 1, 1, + + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 12, 12, 12, 12, 12, 12, 12, 12, 48, 60, 1, 1, 32, 40, 1, 1, + + 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 1, 1, 8, 8, 8, 1, 1, 1, 8, 1 }; diff --git a/src/emu/cpu/minx/minxops.h b/src/emu/cpu/minx/minxops.h index 68a0bac5ab4..e0f6fa516c6 100644 --- a/src/emu/cpu/minx/minxops.h +++ b/src/emu/cpu/minx/minxops.h @@ -5,154 +5,154 @@ OP(00) { regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(01) { regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(02) { regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rdop() ); } -OP(03) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(04) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(05) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(06) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(07) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(03) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(04) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(05) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(06) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(07) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(08) { regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(09) { regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(0A) { regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rdop() ); } -OP(0B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(0F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(0B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(0F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(10) { regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(11) { regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(12) { regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rdop() ); } -OP(13) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(14) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(15) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(16) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(17) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(13) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(14) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(15) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(16) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(17) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(18) { regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(19) { regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(1A) { regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rdop() ); } -OP(1B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(1F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(1B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(1F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(20) { regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(21) { regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(22) { regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rdop() ); } -OP(23) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(24) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(25) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(26) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(27) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(23) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(24) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(25) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(26) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(27) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(28) { regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(29) { regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(2A) { regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rdop() ); } -OP(2B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(2F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(2B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(2F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(30) { SUB8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(31) { SUB8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(32) { SUB8( ( regs.BA & 0x00FF ), rdop() ); } -OP(33) { AD2_IHL; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(34) { AD2_IN8; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(35) { AD2_I16; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(36) { AD2_XIX; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(37) { AD2_YIY; SUB8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(33) { AD2_IHL; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(34) { AD2_IN8; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(35) { AD2_I16; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(36) { AD2_XIX; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(37) { AD2_YIY; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(38) { regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } OP(39) { regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } OP(3A) { regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rdop() ); } -OP(3B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } -OP(3F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rd( addr2 ) ); } +OP(3B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(3F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } OP(40) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.BA & 0x00FF); } OP(41) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.BA >> 8 ); } OP(42) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.HL & 0x00FF); } OP(43) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.HL >> 8 ); } -OP(44) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(45) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(46) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } -OP(47) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | rd( addr2 ); } +OP(44) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(45) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(46) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } +OP(47) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } OP(48) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.BA & 0x00FF) << 8 ); } OP(49) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.BA >> 8 ) << 8 ); } OP(4A) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.HL & 0x00FF) << 8 ); } OP(4B) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.HL >> 8 ) << 8 ); } -OP(4C) { AD2_IN8; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(4D) { AD2_I16; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(4E) { AD2_XIX; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(4F) { AD2_YIY; regs.BA = ( regs.BA & 0x00FF ) | ( rd( addr2 ) << 8 ); } +OP(4C) { AD2_IN8; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4D) { AD2_I16; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4E) { AD2_XIX; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4F) { AD2_YIY; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } OP(50) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.BA & 0x00FF); } OP(51) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.BA >> 8 ); } OP(52) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.HL & 0x00FF); } OP(53) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.HL >> 8 ); } -OP(54) { AD2_IN8; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(55) { AD2_I16; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(56) { AD2_XIX; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } -OP(57) { AD2_YIY; regs.HL = ( regs.HL & 0xFF00 ) | rd( addr2 ); } +OP(54) { AD2_IN8; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(55) { AD2_I16; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(56) { AD2_XIX; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } +OP(57) { AD2_YIY; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } OP(58) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.BA & 0x00FF) << 8 ); } OP(59) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.BA >> 8 ) << 8 ); } OP(5A) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.HL & 0x00FF) << 8 ); } OP(5B) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.HL >> 8 ) << 8 ); } -OP(5C) { AD2_IN8; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(5D) { AD2_I16; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(5E) { AD2_XIX; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } -OP(5F) { AD2_YIY; regs.HL = ( regs.HL & 0x00FF ) | ( rd( addr2 ) << 8 ); } +OP(5C) { AD2_IN8; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5D) { AD2_I16; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5E) { AD2_XIX; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5F) { AD2_YIY; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(60) { AD1_XIX; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(61) { AD1_XIX; wr( addr1, ( regs.BA >> 8 ) ); } -OP(62) { AD1_XIX; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(63) { AD1_XIX; wr( addr1, ( regs.HL >> 8 ) ); } -OP(64) { AD1_XIX; AD2_IN8; wr( addr1, rd( addr2 ) ); } -OP(65) { AD1_XIX; AD2_IHL; wr( addr1, rd( addr2 ) ); } -OP(66) { AD1_XIX; AD2_XIX; wr( addr1, rd( addr2 ) ); } -OP(67) { AD1_XIX; AD2_YIY; wr( addr1, rd( addr2 ) ); } -OP(68) { AD1_IHL; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(69) { AD1_IHL; wr( addr1, ( regs.BA >> 8 ) ); } -OP(6A) { AD1_IHL; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(6B) { AD1_IHL; wr( addr1, ( regs.HL >> 8 ) ); } -OP(6C) { AD1_IHL; AD2_IN8; wr( addr1, rd( addr2 ) ); } -OP(6D) { AD1_IHL; AD2_IHL; wr( addr1, rd( addr2 ) ); } -OP(6E) { AD1_IHL; AD2_XIX; wr( addr1, rd( addr2 ) ); } -OP(6F) { AD1_IHL; AD2_YIY; wr( addr1, rd( addr2 ) ); } +OP(60) { AD1_XIX; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(61) { AD1_XIX; WR( addr1, ( regs.BA >> 8 ) ); } +OP(62) { AD1_XIX; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(63) { AD1_XIX; WR( addr1, ( regs.HL >> 8 ) ); } +OP(64) { AD1_XIX; AD2_IN8; WR( addr1, RD( addr2 ) ); } +OP(65) { AD1_XIX; AD2_IHL; WR( addr1, RD( addr2 ) ); } +OP(66) { AD1_XIX; AD2_XIX; WR( addr1, RD( addr2 ) ); } +OP(67) { AD1_XIX; AD2_YIY; WR( addr1, RD( addr2 ) ); } +OP(68) { AD1_IHL; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(69) { AD1_IHL; WR( addr1, ( regs.BA >> 8 ) ); } +OP(6A) { AD1_IHL; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(6B) { AD1_IHL; WR( addr1, ( regs.HL >> 8 ) ); } +OP(6C) { AD1_IHL; AD2_IN8; WR( addr1, RD( addr2 ) ); } +OP(6D) { AD1_IHL; AD2_IHL; WR( addr1, RD( addr2 ) ); } +OP(6E) { AD1_IHL; AD2_XIX; WR( addr1, RD( addr2 ) ); } +OP(6F) { AD1_IHL; AD2_YIY; WR( addr1, RD( addr2 ) ); } -OP(70) { AD1_YIY; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(71) { AD1_YIY; wr( addr1, ( regs.BA >> 8 ) ); } -OP(72) { AD1_YIY; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(73) { AD1_YIY; wr( addr1, ( regs.HL >> 8 ) ); } -OP(74) { AD1_YIY; AD2_IN8; wr( addr1, rd( addr2 ) ); } -OP(75) { AD1_YIY; AD2_IHL; wr( addr1, rd( addr2 ) ); } -OP(76) { AD1_YIY; AD2_XIX; wr( addr1, rd( addr2 ) ); } -OP(77) { AD1_YIY; AD2_YIY; wr( addr1, rd( addr2 ) ); } -OP(78) { AD1_IN8; wr( addr1, ( regs.BA & 0x00FF ) ); } -OP(79) { AD1_IN8; wr( addr1, ( regs.BA >> 8 ) ); } -OP(7A) { AD1_IN8; wr( addr1, ( regs.HL & 0x00FF ) ); } -OP(7B) { AD1_IN8; wr( addr1, ( regs.HL >> 8 ) ); } +OP(70) { AD1_YIY; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(71) { AD1_YIY; WR( addr1, ( regs.BA >> 8 ) ); } +OP(72) { AD1_YIY; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(73) { AD1_YIY; WR( addr1, ( regs.HL >> 8 ) ); } +OP(74) { AD1_YIY; AD2_IN8; WR( addr1, RD( addr2 ) ); } +OP(75) { AD1_YIY; AD2_IHL; WR( addr1, RD( addr2 ) ); } +OP(76) { AD1_YIY; AD2_XIX; WR( addr1, RD( addr2 ) ); } +OP(77) { AD1_YIY; AD2_YIY; WR( addr1, RD( addr2 ) ); } +OP(78) { AD1_IN8; WR( addr1, ( regs.BA & 0x00FF ) ); } +OP(79) { AD1_IN8; WR( addr1, ( regs.BA >> 8 ) ); } +OP(7A) { AD1_IN8; WR( addr1, ( regs.HL & 0x00FF ) ); } +OP(7B) { AD1_IN8; WR( addr1, ( regs.HL >> 8 ) ); } OP(7C) { /* illegal operation? */ } -OP(7D) { AD1_IN8; AD2_IHL; wr( addr1, rd( addr2 ) ); } -OP(7E) { AD1_IN8; AD2_XIX; wr( addr1, rd( addr2 ) ); } -OP(7F) { AD1_IN8; AD2_YIY; wr( addr1, rd( addr2 ) ); } +OP(7D) { AD1_IN8; AD2_IHL; WR( addr1, RD( addr2 ) ); } +OP(7E) { AD1_IN8; AD2_XIX; WR( addr1, RD( addr2 ) ); } +OP(7F) { AD1_IN8; AD2_YIY; WR( addr1, RD( addr2 ) ); } OP(80) { regs.BA = ( regs.BA & 0xFF00 ) | INC8( regs.BA & 0x00FF ); } OP(81) { regs.BA = ( regs.BA & 0x00FF ) | ( INC8( regs.BA >> 8 ) << 8 ); } OP(82) { regs.HL = ( regs.HL & 0xFF00 ) | INC8( regs.HL & 0x00FF ); } OP(83) { regs.HL = ( regs.HL & 0x00FF ) | ( INC8( regs.HL >> 8 ) << 8 ); } OP(84) { regs.N = INC8( regs.N ); } -OP(85) { AD1_IN8; wr( addr1, INC8( rd( addr1 ) ) ); } -OP(86) { AD1_IHL; wr( addr1, INC8( rd( addr1 ) ) ); } +OP(85) { AD1_IN8; WR( addr1, INC8( RD( addr1 ) ) ); } +OP(86) { AD1_IHL; WR( addr1, INC8( RD( addr1 ) ) ); } OP(87) { regs.SP = INC16( regs.SP ); } OP(88) { regs.BA = ( regs.BA & 0xFF00 ) | DEC8( regs.BA & 0x00FF ); } OP(89) { regs.BA = ( regs.BA & 0x00FF ) | ( DEC8( regs.BA >> 8 ) << 8 ); } OP(8A) { regs.HL = ( regs.HL & 0xFF00 ) | DEC8( regs.HL & 0x00FF ); } OP(8B) { regs.HL = ( regs.HL & 0x00FF ) | ( DEC8( regs.HL >> 8 ) << 8 ); } OP(8C) { regs.N = DEC8( regs.N ); } -OP(8D) { AD1_IN8; wr( addr1, DEC8( rd( addr1 ) ) ); } -OP(8E) { AD1_IHL; wr( addr1, DEC8( rd( addr1 ) ) ); } +OP(8D) { AD1_IN8; WR( addr1, DEC8( RD( addr1 ) ) ); } +OP(8E) { AD1_IHL; WR( addr1, DEC8( RD( addr1 ) ) ); } OP(8F) { regs.SP = DEC8( regs.SP ); } OP(90) { regs.BA = INC16( regs.BA ); } @@ -160,7 +160,7 @@ OP(91) { regs.HL = INC16( regs.HL ); } OP(92) { regs.X = INC16( regs.X ); } OP(93) { regs.Y = INC16( regs.Y ); } OP(94) { regs.F = ( AND8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z;} -OP(95) { AD1_IHL; regs.F = ( AND8( rd( addr1 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } +OP(95) { AD1_IHL; regs.F = ( AND8( RD( addr1 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } OP(96) { regs.F = ( AND8( ( regs.BA & 0x00FF ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } OP(97) { regs.F = ( AND8( ( regs.BA >> 8 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } OP(98) { regs.BA = DEC16( regs.BA ); } @@ -194,15 +194,15 @@ OP(B1) { UINT8 op = rdop(); regs.BA = ( regs.BA & 0x00FF ) | ( op << 8 ); } OP(B2) { UINT8 op = rdop(); regs.HL = ( regs.HL & 0xFF00 ) | op; } OP(B3) { UINT8 op = rdop(); regs.HL = ( regs.HL & 0x00FF ) | ( op << 8 ); } OP(B4) { UINT8 op = rdop(); regs.N = op; } -OP(B5) { UINT8 op = rdop(); wr( ( regs.I << 16 ) | regs.HL, op); } -OP(B6) { UINT8 op = rdop(); wr( ( regs.X << 16 ), op ); } -OP(B7) { UINT8 op = rdop(); wr( ( regs.Y << 16 ), op ); } +OP(B5) { UINT8 op = rdop(); WR( ( regs.I << 16 ) | regs.HL, op); } +OP(B6) { UINT8 op = rdop(); WR( ( regs.X << 16 ), op ); } +OP(B7) { UINT8 op = rdop(); WR( ( regs.Y << 16 ), op ); } OP(B8) { AD2_I16; regs.BA = rd16( addr2 ); } OP(B9) { AD2_I16; regs.HL = rd16( addr2 ); } OP(BA) { AD2_I16; regs.X = rd16( addr2 ); } OP(BB) { AD2_I16; regs.Y = rd16( addr2 ); } -OP(BC) { AD1_I16; wr( addr1, regs.BA ); } -OP(BD) { AD1_I16; wr( addr1, regs.HL ); } +OP(BC) { AD1_I16; wr16( addr1, regs.BA ); } +OP(BD) { AD1_I16; wr16( addr1, regs.HL ); } OP(BE) { AD1_I16; wr16( addr1, regs.X ); } OP(BF) { AD1_I16; wr16( addr1, regs.Y ); } @@ -219,7 +219,7 @@ OP(C9) { UINT16 t = regs.BA; regs.BA = regs.X; regs.X = t; } OP(CA) { UINT16 t = regs.BA; regs.BA = regs.Y; regs.Y = t; } OP(CB) { UINT16 t = regs.BA; regs.BA = regs.SP; regs.SP = t; } OP(CC) { regs.BA = ( regs.BA >> 8 ) | ( ( regs.BA & 0x00FF ) << 8 ); } -OP(CD) { UINT8 t; AD2_IHL; t = rd( addr2 ); wr( addr2, ( regs.BA & 0x00FF ) ); regs.BA = ( regs.BA & 0xFF00 ) | t; } +OP(CD) { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( regs.BA & 0x00FF ) ); regs.BA = ( regs.BA & 0xFF00 ) | t; } OP(CE) { UINT8 op = rdop(); insnminx_CE[op](); minx_icount -= insnminx_cycles_CE[op]; } OP(CF) { UINT8 op = rdop(); insnminx_CF[op](); minx_icount -= insnminx_cycles_CF[op]; } @@ -231,27 +231,27 @@ OP(D4) { SUB16( regs.BA, rdop16() ); } OP(D5) { SUB16( regs.HL, rdop16() ); } OP(D6) { SUB16( regs.X, rdop16() ); } OP(D7) { SUB16( regs.Y, rdop16() ); } -OP(D8) { AD1_IN8; wr( addr1, AND8( rd( addr1 ), rdop() ) ); } -OP(D9) { AD1_IN8; wr( addr1, OR8( rd( addr1 ), rdop() ) ); } -OP(DA) { AD1_IN8; wr( addr1, XOR8( rd( addr1 ), rdop() ) ); } -OP(DB) { AD1_IN8; SUB8( rd( addr1 ), rdop() ); } -OP(DC) { AD1_IN8; regs.F = ( AND8( rd( addr1 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } -OP(DD) { AD1_IN8; wr( addr1, rdop() ); } +OP(D8) { AD1_IN8; WR( addr1, AND8( RD( addr1 ), rdop() ) ); } +OP(D9) { AD1_IN8; WR( addr1, OR8( RD( addr1 ), rdop() ) ); } +OP(DA) { AD1_IN8; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); } +OP(DB) { AD1_IN8; SUB8( RD( addr1 ), rdop() ); } +OP(DC) { AD1_IN8; regs.F = ( AND8( RD( addr1 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } +OP(DD) { AD1_IN8; WR( addr1, rdop() ); } OP(DE) { regs.BA = ( regs.BA & 0xFF00 ) | ( ( regs.BA & 0x000F ) | ( ( regs.BA & 0x0F00 ) >> 4 ) ); } OP(DF) { regs.BA = ( ( regs.BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( regs.BA & 0x000F ); } -OP(E0) { INT8 d8 = rdop(); if ( regs.F & FLAG_C ) { CALL( regs.PC + d8 - 1 ); } } -OP(E1) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_C ) ) { CALL( regs.PC + d8- 1 ); } } -OP(E2) { INT8 d8 = rdop(); if ( regs.F & FLAG_Z ) { CALL( regs.PC + d8 - 1 ); } } -OP(E3) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_Z ) ) { CALL( regs.PC + d8 - 1 ); } } +OP(E0) { INT8 d8 = rdop(); if ( regs.F & FLAG_C ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(E1) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_C ) ) { CALL( regs.PC + d8- 1 ); minx_icount -= 12; } } +OP(E2) { INT8 d8 = rdop(); if ( regs.F & FLAG_Z ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(E3) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_Z ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } OP(E4) { INT8 d8 = rdop(); if ( regs.F & FLAG_C ) { JMP( regs.PC + d8 - 1 ); } } OP(E5) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_C ) ) { JMP( regs.PC + d8 - 1 ); } } OP(E6) { INT8 d8 = rdop(); if ( regs.F & FLAG_Z ) { JMP( regs.PC + d8 - 1 ); } } OP(E7) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_Z ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E8) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_C ) { CALL( regs.PC + d16 - 1 ); } } -OP(E9) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_C ) ) { CALL( regs.PC + d16 - 1 ); } } -OP(EA) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_Z ) { CALL( regs.PC + d16 - 1 ); } } -OP(EB) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_Z ) ) { CALL( regs.PC + d16 - 1 ); } } +OP(E8) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_C ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } +OP(E9) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_C ) ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } +OP(EA) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_Z ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } +OP(EB) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_Z ) ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } OP(EC) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_C ) { JMP( regs.PC + d16 - 1 ); } } OP(ED) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_C ) ) { JMP( regs.PC + d16 - 1 ); } } OP(EE) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_Z ) { JMP( regs.PC + d16 - 1 ); } } @@ -264,12 +264,12 @@ OP(F3) { UINT16 d16 = rdop16(); JMP( regs.PC + d16 - 1 ); } OP(F4) { JMP( regs.HL ); } OP(F5) { INT8 d8 = rdop(); regs.BA = regs.BA - 0x0100; if ( regs.BA & 0xFF00 ) { JMP( regs.PC + d8 - 1 ); } } OP(F6) { regs.BA = ( regs.BA & 0xFF00 ) | ( ( regs.BA & 0x00F0 ) >> 4 ) | ( ( regs.BA & 0x000F ) << 4 ); } -OP(F7) { UINT8 d; AD1_IHL; d = rd( addr1 ); wr( addr1, ( ( d & 0xF0 ) >> 4 ) | ( ( d & 0x0F ) << 4 ) ); } +OP(F7) { UINT8 d; AD1_IHL; d = RD( addr1 ); WR( addr1, ( ( d & 0xF0 ) >> 4 ) | ( ( d & 0x0F ) << 4 ) ); } OP(F8) { regs.PC = POP16(); regs.V = POP8(); } OP(F9) { regs.F = POP8(); regs.PC = POP16(); regs.V = POP8(); } OP(FA) { regs.PC = POP16() + 2; regs.V = POP8(); } OP(FB) { AD1_I16; CALL( rd16( addr1 ) ); } -OP(FC) { UINT16 i = rdop() << 1; CALL( i ); PUSH8( regs.F ); } +OP(FC) { UINT16 i = rdop(); CALL( rd16(i) ); PUSH8( regs.F ); } OP(FD) { UINT16 i = rdop() << 1; JMP( i ); /* PUSH8( regs.F );?? */ } OP(FE) { /* illegal operation? */ } OP(FF) { } @@ -310,21 +310,24 @@ static void (*const insnminx[256])(void) = { }; static const int insnminx_cycles[256] = { - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + 8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8, + 8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8, + 8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8, + 8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8, + + 4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8, + 4, 4, 4, 4, 12, 8, 8, 8, 4, 4, 4, 4, 12, 8, 8, 8, + 8, 8, 8, 8, 16, 12, 12, 12, 8, 8, 8, 8, 16, 12, 12, 12, + 8, 8, 8, 8, 16, 12, 12, 12, 12, 12, 12, 12, 1, 16, 16, 16, + + 8, 8, 8, 8, 8, 16, 12, 8, 8, 8, 8, 8, 8, 16, 12, 8, + 8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12, + 16, 16, 16, 16, 12, 12, 16, 12, 12, 12, 12, 12, 8, 8, 12, 8, + 8, 8, 8, 8, 8, 12, 12, 12, 20, 20, 20, 20, 1, 1, 1, 1, + + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 8, 12, 0, 0, + 12, 12, 12, 12, 12, 12, 12, 12, 20, 20, 20, 16, 16, 16, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12, 12, 12, 12, 12, + 20, 8, 24, 12, 8, 1, 8, 12, 8, 8, 8, 20, 20, 1, 1, 8 };