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https://github.com/holub/mame
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video/mga2064w.cpp: basic drawing log
This commit is contained in:
angelosa
parent
e9972826d5
commit
6b271ec10c
@ -5,13 +5,15 @@
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#define LOG_WARN (1U << 1)
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#define LOG_ALIAS (1U << 2) // log mgabase1 index setups thru the back door
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#define LOG_DRAW (1U << 3) // log drawing engine accesses
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#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_ALIAS)
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#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_DRAW)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__)
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#define LOGALIAS(...) LOGMASKED(LOG_ALIAS, __VA_ARGS__)
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#define LOGDRAW(...) LOGMASKED(LOG_DRAW, __VA_ARGS__)
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DEFINE_DEVICE_TYPE(MGA2064W, mga2064w_device, "mga2064w", "Matrox Millennium \"IS-STORM / MGA-2064W\"")
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@ -94,39 +96,7 @@ void mga2064w_device::config_map(address_map &map)
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void mga2064w_device::mgabase1_map(address_map &map)
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{
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// map(0x0000, 0x1bff).rw(FUNC(mga2064w_device::dmawin_iload_r), FUNC(mga2064w_device::dmawin_idump_w));
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// map(0x1c00, 0x1cff).mirror(0x100).m(FUNC(mga2064w_device::dwgreg_map);
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// map(0x1c00, 0x1c03) DWGCTL
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// map(0x1c04, 0x1c07) MACCESS
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// map(0x1c08, 0x1c0b) <reserved> MCTLWTST
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// map(0x1c0c, 0x1c0f) ZORG
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// map(0x1c10, 0x1c13) PAT0
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// map(0x1c14, 0x1c17) PAT1
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// map(0x1c1c, 0x1c1f) PLNWT
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// map(0x1c20, 0x1c23) BCOL
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// map(0x1c24, 0x1c27) FCOL
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// map(0x1c2c, 0x1c2f) <reserved> SRCBLT
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// map(0x1c30, 0x1c3f) SRC0-3
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// map(0x1c40, 0x1c43) XYSTRT
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// map(0x1c44, 0x1c47) XYEND
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// map(0x1c50, 0x1c53) SHIFT
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// map(0x1c58, 0x1c5b) SGN
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// map(0x1c5c, 0x1c5f) LEN
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// map(0x1c60, 0x1c7b) AR0-6
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// map(0x1c80, 0x1c83) CXBNDRY
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// map(0x1c84, 0x1c87) FXBNDRY
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// map(0x1c88, 0x1c8b) YDSTLEN
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// map(0x1c8c, 0x1c8f) PITCH
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// map(0x1c90, 0x1c93) YDST
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// map(0x1c94, 0x1c97) YDSTORG
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// map(0x1c98, 0x1c9b) YTOP
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// map(0x1c9c, 0x1c9f) YBOT
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// map(0x1ca0, 0x1ca3) CXLEFT
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// map(0x1ca4, 0x1ca7) CXRIGHT
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// map(0x1ca8, 0x1cab) FXLEFT
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// map(0x1cac, 0x1caf) FXRIGHT
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// map(0x1cb0, 0x1cb3) XDST
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// map(0x1cc0, 0x1cff) DR0-DR15 (DR1-5-9-13 <reserved>)
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map(0x1c00, 0x1cff).mirror(0x100).m(FUNC(mga2064w_device::dwgreg_map));
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// map(0x1e00, 0x1eff) HSTREG Host registers
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map(0x1e10, 0x1e13).r(FUNC(mga2064w_device::fifo_status_r));
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map(0x1e14, 0x1e17).r(FUNC(mga2064w_device::status_r));
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@ -146,6 +116,246 @@ void mga2064w_device::mgabase2_map(address_map &map)
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map(0x000000, 0x7fffff).rw(m_svga, FUNC(matrox_vga_device::mem_linear_r), FUNC(matrox_vga_device::mem_linear_w));
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}
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// base + $1cxx
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void mga2064w_device::dwgreg_map(address_map &map)
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{
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// DWGCTL
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map(0x0000, 0x0003).w(FUNC(mga2064w_device::dwgctl_w));
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// map(0x0004, 0x0007) MACCESS
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// map(0x0008, 0x000b) <reserved> MCTLWTST
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// map(0x000c, 0x000f) ZORG
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// map(0x0010, 0x0013) PAT0
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// map(0x0014, 0x0017) PAT1
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// map(0x001c, 0x001f) PLNWT
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// BCOL / backcol
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map(0x0020, 0x0023).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOGDRAW("dwgreg: BCOL %08x & %08x\n", data, mem_mask);
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COMBINE_DATA(&m_dwgreg.bcol);
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})
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);
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// FCOL / forcol
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map(0x0024, 0x0027).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOGDRAW("dwgreg: FCOL %08x & %08x\n", data, mem_mask);
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COMBINE_DATA(&m_dwgreg.fcol);
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})
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);
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// map(0x002c, 0x002f) <reserved> SRCBLT
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// SRC0-3
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map(0x0030, 0x003f).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOGDRAW("dwgreg: SRC[%01d] -> %08x & %08x\n", offset, data, mem_mask);
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COMBINE_DATA(&m_dwgreg.src[offset]);
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})
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);
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// map(0x0040, 0x0043) XYSTRT
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// map(0x0044, 0x0047) XYEND
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// map(0x0050, 0x0053) SHIFT
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// SGN
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map(0x0058, 0x005b).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOGDRAW("dwgreg: SGN %08x & %08x\n", offset, data, mem_mask);
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LOGDRAW("\tsdydxl %s|scanleft %d|sdxl %s|sdy %s|sdxr %d\n"
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, BIT(data, 0) ? "x major axis" : "y major axis"
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// not a mistake: sdydxl and scanleft are shared
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, BIT(data, 0)
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, BIT(data, 1) ? "-x delta" : "+x delta"
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, BIT(data, 2) ? "-y delta" : "+y delta"
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, BIT(data, 5) ? "-x delta" : "+x delta"
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);
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})
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);
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// LEN
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map(0x005c, 0x005f).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.len = data & 0xffff;
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LOGDRAW("dwgreg: LEN %08x & %08x %d\n", data, mem_mask, m_dwgreg.len);
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})
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);
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// AR0-6
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map(0x0060, 0x007b).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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// TODO: 18-bit signed
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LOGDRAW("dwgreg: AR[%01d] -> %08x & %08x\n", offset, data, mem_mask);
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COMBINE_DATA(&m_dwgreg.ar[offset]);
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})
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);
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// CXBNDRY
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map(0x0080, 0x0083).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.cxleft = data & 0x7ff;
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m_dwgreg.cxright = (data >> 16) & 0x7ff;
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LOGDRAW("dwgreg: CXBNDRY %08x & %08x (CXLEFT %d|CXRIGHT %d)\n"
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, data, mem_mask
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, m_dwgreg.cxleft, m_dwgreg.cxright
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);
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})
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);
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// FXBNDRY
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map(0x0084, 0x0087).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.fxleft = (s16)(data & 0xffff);
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m_dwgreg.fxright = (s16)(data >> 16);
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LOGDRAW("dwgreg: FXBNDRY %08x & %08x (FXLEFT %d|FXRIGHT %d)\n"
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, data, mem_mask
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, m_dwgreg.fxleft, m_dwgreg.fxright
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);
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// accessed thru the mirror at $1d84 on Windows 3.1 boot
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})
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);
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// YDSTLEN
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// alternative way to access YDST (bits 31-16) and LEN (15-0) with a single dword
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map(0x0088, 0x008b).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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// TODO: YDST (bits 31-16)
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// YDST is 22 bits with sign extension ...
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m_dwgreg.len = data & 0xffff;
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LOGDRAW("dwgreg: YDSTLEN %08x & %08x (YDST %d|LEN %d)\n"
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, data, mem_mask
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, data >> 16, m_dwgreg.len
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);
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})
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);
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// PITCH
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map(0x008c, 0x008f).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.pitch = data & 0xfff;
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LOGDRAW("dwgreg: PITCH %08x & %08x %d|ylin %d\n"
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, data, mem_mask
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, m_dwgreg.pitch
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, BIT(data, 15)
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);
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})
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);
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// map(0x0090, 0x0093) YDST
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// map(0x0094, 0x0097) YDSTORG
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// YTOP / cytop
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map(0x0098, 0x009b).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.cytop = data & 0x7fffff;
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LOGDRAW("dwgreg: YTOP %08x & %08x %d\n"
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, data, mem_mask
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, m_dwgreg.cytop
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);
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})
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);
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// YBOT / cybot
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map(0x009c, 0x009f).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.cybot = data & 0x7fffff;
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LOGDRAW("dwgreg: YBOT %08x & %08x %d\n"
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, data, mem_mask
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, m_dwgreg.cybot
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);
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})
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);
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// CXLEFT
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map(0x00a0, 0x00a3).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.cxleft = data & 0x7ff;
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LOGDRAW("dwgreg: CXLEFT %08x & %08x %d\n"
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, data, mem_mask
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, m_dwgreg.cxleft
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);
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})
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);
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// CXRIGHT
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map(0x00a4, 0x00a7).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.cxright = data & 0x7ff;
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LOGDRAW("dwgreg: CXRIGHT %08x & %08x %d\n"
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, data, mem_mask
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, m_dwgreg.cxright
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);
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})
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);
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// FXLEFT
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map(0x00a8, 0x00ab).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.fxleft = (s16)(data & 0xffff);
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LOGDRAW("dwgreg: FXLEFT %08x & %08x %d\n"
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, data, mem_mask
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, m_dwgreg.fxleft
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);
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})
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);
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// FXRIGHT
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map(0x00ac, 0x00af).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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m_dwgreg.fxright = (s16)(data & 0xffff);
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LOGDRAW("dwgreg: FXRIGHT %08x & %08x %d\n"
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, data, mem_mask
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, m_dwgreg.fxright
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);
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})
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);
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// map(0x00b0, 0x00b3) XDST
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// DR0-DR15 (DR1-5-9-13 <reserved>)
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map(0x00c0, 0x00ff).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOGDRAW("dwgreg: DR[%01d] -> %08x\n", offset, data, mem_mask);
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if ((offset & 3) == 1)
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{
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LOGWARN("dwgreg: attempt to setup reserved DR%01d (ignored)\n", offset);
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return;
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}
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COMBINE_DATA(&m_dwgreg.dr[offset]);
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})
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);
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}
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void mga2064w_device::dwgctl_w(offs_t offset, u32 data, u32 mem_mask)
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{
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COMBINE_DATA(&m_dwgreg.dwgctl);
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LOGDRAW("dwgreg: DWGCTRL -> %08x & %08x\n", data, mem_mask);
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const char *const opcode_mnemonics[16] = {
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"LINE_OPEN", "AUTOLINE_OPEN", "LINE_CLOSE", "AUTOLINE_CLOSE",
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"TRAP", "TEXTURE_TRAP", "<reserved>", "<reserved>",
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"BITBLT", "ILOAD", "IDUMP", "<reserved>",
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"FBITBLIT", "ILOAD_SCALE", "<reserved>", "ILOAD_FILTER"
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};
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const char *const atype_mnemonics[8] = {
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"RPL", "RSTR", "<reserved>", "ZI",
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"BLK", "<reserved>", "<reserved>", "I"
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};
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const char *const zmode_mnemonics[8] = {
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"NOZCMP", "<reserved>", "ZE", "ZNE",
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"ZLT", "ZLTE", "ZGT", "ZGTE"
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};
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const char *const bop_mnemonics[16] = {
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"0", "~(D | S)", "D & ~S", "~S",
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"(~D) & S", "~D", "D ^ S", "~(D & S)",
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"D & S", "~(D ^ S)", "D", "D | ~S",
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"S", "(~D) | S", "D | S", "1"
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};
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const char *const bltmod_mnemonics[16] = {
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"BMONOLEF", "BPLAN", "BFCOL", "BU32BGR",
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"BMONOWF", "<reserved>", "<reserved>", "BU32RGB",
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"<reserved>", "<reserved>", "<reserved>", "BU24BGR",
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"<reserved>", "<reserved>", "BUYUV", "BU24RGB"
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};
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LOGDRAW("\topcod %02x %s|atype %02x %s|%s mode|zmode %02x %s|\n"
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, m_dwgreg.dwgctl & 0xf, opcode_mnemonics[m_dwgreg.dwgctl & 0xf]
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, (m_dwgreg.dwgctl >> 4) & 7, atype_mnemonics[(m_dwgreg.dwgctl >> 4) & 7]
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, BIT(m_dwgreg.dwgctl, 7) ? "linear bitblt" : "xy bitblt"
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, (m_dwgreg.dwgctl >> 8) & 7, zmode_mnemonics[(m_dwgreg.dwgctl >> 8) & 7]
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);
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LOGDRAW("\tbop %02x %s|bltmod %02x %s|pattern %d|transc %d|\n"
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, (m_dwgreg.dwgctl >> 16) & 0xf, bop_mnemonics[(m_dwgreg.dwgctl >> 16) & 0xf]
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, (m_dwgreg.dwgctl >> 25) & 0xf, bltmod_mnemonics[(m_dwgreg.dwgctl >> 25) & 0xf]
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, BIT(m_dwgreg.dwgctl, 29)
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, BIT(m_dwgreg.dwgctl, 30)
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);
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LOGDRAW("\tsolid %d|arzero %d|sgnzero %d|shftzero %d|trans %02x|\n"
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, BIT(m_dwgreg.dwgctl, 11)
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, BIT(m_dwgreg.dwgctl, 12)
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, BIT(m_dwgreg.dwgctl, 13)
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, BIT(m_dwgreg.dwgctl, 14)
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, (m_dwgreg.dwgctl >> 20) & 0xf
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);
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}
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/*
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* MGABASE1 + 1e10h FIFO Status (r/o)
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*
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@ -31,6 +31,8 @@ protected:
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void mgabase1_map(address_map &map);
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void mgabase2_map(address_map &map);
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void dwgreg_map(address_map &map);
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required_device<matrox_vga_device> m_svga;
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required_memory_region m_vga_rom;
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private:
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@ -46,6 +48,25 @@ private:
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u32 status_r();
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u32 fifo_status_r();
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// DWGREG section
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void dwgctl_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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struct {
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u32 src[4]{};
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u32 dr[16]{};
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u32 ar[7]{};
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u32 dwgctl = 0;
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u16 pitch = 0;
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u16 len = 0;
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u32 cytop = 0;
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u32 cybot = 0;
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u16 cxleft = 0;
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u16 cxright = 0;
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s16 fxleft = 0;
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s16 fxright = 0;
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u32 bcol = 0;
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u32 fcol = 0;
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} m_dwgreg;
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};
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DECLARE_DEVICE_TYPE(MGA2064W, mga2064w_device);
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