mirror of
https://github.com/holub/mame
synced 2025-06-16 09:20:04 +03:00
naomi: converted 315-6154 device into a real pci host [Samuele Zannoli]
And updated dimm board accordingly.
This commit is contained in:
yz70s
parent
a0a658a111
commit
6b3a689ce1
@ -7,10 +7,9 @@
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DEFINE_DEVICE_TYPE(SEGA315_6154, sega_315_6154_device, "sega315_6154", "Sega 315-6154 Northbridge")
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sega_315_6154_device::sega_315_6154_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, SEGA315_6154, tag, owner, clock),
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device_memory_interface(mconfig, *this),
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m_memory_config("memory", ENDIANNESS_LITTLE, 32, 32),
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m_configuration_config("configuration", ENDIANNESS_LITTLE, 32, 32)
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: pci_host_device(mconfig, SEGA315_6154, tag, owner, clock),
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m_configuration_config("configuration_space", ENDIANNESS_LITTLE, 32, 20),
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m_memory_config("memory_space", ENDIANNESS_LITTLE, 32, 32)
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{
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memset(m_registers, 0, sizeof(m_registers));
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memset(m_bases, 0, sizeof(m_bases));
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@ -20,8 +19,19 @@ sega_315_6154_device::sega_315_6154_device(const machine_config &mconfig, const
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void sega_315_6154_device::device_start()
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{
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m_memory = &space(AS_PCI_MEMORY);
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m_configuration = &space(AS_PCI_CONFIGURATION);
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pci_host_device::device_start();
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memory_space = &space(AS_PCI_MEMORY);
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// never unmap addresses lower than start
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memory_window_start = 0x80000000;
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memory_window_end = 0xffffffff;
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memory_offset = 0;
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m_configuration = &space(AS_PCI_CONFIG);
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io_space = memory_space;
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io_window_start = 0xc0000000;
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io_window_end = 0xc000ffff;
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io_offset = 0xc0000000;
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save_item(NAME(m_registers));
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save_item(NAME(m_bases));
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@ -31,17 +41,34 @@ void sega_315_6154_device::device_start()
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void sega_315_6154_device::device_reset()
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{
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pci_host_device::device_reset();
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memset(m_registers, 0, sizeof(m_registers));
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}
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device_memory_interface::space_config_vector sega_315_6154_device::memory_space_config() const
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{
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return space_config_vector{
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std::make_pair(AS_PCI_MEMORY, &m_memory_config),
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std::make_pair(AS_PCI_CONFIGURATION, &m_configuration_config)
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std::make_pair(AS_PCI_CONFIG, &m_configuration_config),
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std::make_pair(AS_PCI_MEMORY, &m_memory_config)
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};
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}
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void sega_315_6154_device::regenerate_config_mapping()
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{
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// like pci_bridge_device::regenerate_config_mapping() in pci.cpp
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// but each device n is assigned bit n+11 in the configuration space
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// devices in different buses must have different numbers
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address_space *config_space = &space(AS_PCI_CONFIG);
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config_space->unmap_readwrite(0x00000, 0xfffff);
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for (int i = 0; i < 9; i++)
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if (sub_devices[i])
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{
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const int s = i >> 3;
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const int o = (i & 7) << 8;
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config_space->install_device((0x800 << s) + o, ((0x800 << s) + o) | 0xff, *sub_devices[i], &pci_device::config_map);
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}
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}
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READ32_MEMBER(sega_315_6154_device::registers_r)
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{
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return m_registers[offset];
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@ -85,7 +112,7 @@ WRITE32_MEMBER(sega_315_6154_device::registers_w)
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logerror("got dma transfer request from 0x%08x to 0x%08x size 0x%08x bytes\n", s, d, l << 2);
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while (l != 0)
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{
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m_memory->write_dword(d, m_memory->read_dword(s));
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memory_space->write_dword(d, memory_space->read_dword(s));
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s += 4;
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d += 4;
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l--;
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@ -106,7 +133,7 @@ u32 sega_315_6154_device::aperture_r(address_space &space, offs_t offset, u32 me
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return m_configuration->read_dword(destination_offset << 2, mem_mask);
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if ((Aperture == 1) && (destination == 0) && (m_useconfig_18x == true))
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return m_configuration->read_dword(destination_offset << 2, mem_mask);
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return m_memory->read_dword(m_bases[index] + (destination_offset << 2), mem_mask);
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return memory_space->read_dword(m_bases[index] + (destination_offset << 2), mem_mask);
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}
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template u32 sega_315_6154_device::aperture_r<0>(address_space &space, offs_t offset, u32 mem_mask);
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@ -130,7 +157,7 @@ void sega_315_6154_device::aperture_w(address_space &space, offs_t offset, u32 d
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m_configuration->write_dword(destination_offset << 2, data, mem_mask);
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return;
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}
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m_memory->write_dword(m_bases[index] + (destination_offset << 2), data, mem_mask);
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memory_space->write_dword(m_bases[index] + (destination_offset << 2), data, mem_mask);
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}
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template void sega_315_6154_device::aperture_w<0>(address_space &space, offs_t offset, u32 data, u32 mem_mask);
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@ -5,14 +5,16 @@
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#pragma once
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#include "machine/pci.h"
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DECLARE_DEVICE_TYPE(SEGA315_6154, sega_315_6154_device)
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class sega_315_6154_device : public device_t, public device_memory_interface
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class sega_315_6154_device : public pci_host_device
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{
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public:
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// construction/destruction
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sega_315_6154_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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address_space *memory() { return m_memory; }
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address_space *memory() { return memory_space; }
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DECLARE_READ32_MEMBER(registers_r);
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DECLARE_WRITE32_MEMBER(registers_w);
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@ -22,8 +24,7 @@ public:
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void aperture_w(address_space &space, offs_t offset, u32 data, u32 mem_mask = 0xffffffff);
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enum {
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AS_PCI_MEMORY = 0,
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AS_PCI_CONFIGURATION = 1
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AS_PCI_MEMORY = 1
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};
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protected:
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@ -32,11 +33,11 @@ protected:
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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virtual void regenerate_config_mapping() override;
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private:
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address_space_config m_memory_config;
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address_space_config m_configuration_config;
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address_space *m_memory;
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address_space_config m_memory_config;
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address_space *m_configuration;
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u32 m_registers[0x100 / 4];
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@ -401,6 +401,117 @@ void naomi_gdrom_board::write_from_qword(uint8_t *region, uint64_t qword)
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region[i] = qword >> (56-(i*8));
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}
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// For ide gdrom controller
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DEFINE_DEVICE_TYPE(IDE_GDROM, idegdrom_device, "ide_gdrom", "ide gdrom controller")
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idegdrom_device::idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, const char *image_tag, const char *space_tag, int space_id)
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: idegdrom_device(mconfig, tag, owner, clock)
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{
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space_owner_tag = space_tag;
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space_owner_id = space_id;
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}
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idegdrom_device::idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_device(mconfig, IDE_GDROM, tag, owner, clock),
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m_ide(*this, "ide"),
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irq_cb(*this)
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{
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set_ids(0x11db189d, 0, 0, 0); // 0x10221000 or 0x00011172 possible too
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}
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void idegdrom_device::device_start()
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{
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pci_device::device_start();
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irq_cb.resolve_safe();
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add_map(0x00000020, M_IO, FUNC(idegdrom_device::map_command));
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bank_infos[0].adr = 0x01c0;
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// pci system does not support base addresses not multiples of size
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add_map(0x00000020, M_IO | M_DISABLED, FUNC(idegdrom_device::map_control));
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bank_infos[1].adr = 0x03b0;
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add_map(0x00000010, M_IO, FUNC(idegdrom_device::map_dma));
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bank_infos[2].adr = 0xcc00;
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command = 0x0083;
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}
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void idegdrom_device::device_reset()
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{
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pci_device::device_reset();
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}
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void idegdrom_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
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{
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io_space->install_device(io_offset + 0x03b0, io_offset + 0x03cf, *static_cast<idegdrom_device*>(this), &idegdrom_device::map_control);
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}
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static void gdrom_devices(device_slot_interface &device)
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{
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device.option_add(":gdrom", GDROM);
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}
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WRITE_LINE_MEMBER(idegdrom_device::ide_irq)
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{
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irq_cb(state);
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}
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void idegdrom_device::device_add_mconfig(machine_config &config)
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{
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BUS_MASTER_IDE_CONTROLLER(config, m_ide).options(gdrom_devices, ":gdrom", nullptr, true);
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m_ide->irq_handler().set(*this, FUNC(idegdrom_device::ide_irq));
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m_ide->set_bus_master_space(space_owner_tag, space_owner_id);
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}
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void idegdrom_device::map_command(address_map &map)
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{
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map(0x0000, 0x001f).rw(FUNC(idegdrom_device::ide_cs0_r), FUNC(idegdrom_device::ide_cs0_w));
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}
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void idegdrom_device::map_control(address_map &map)
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{
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map(0x0000, 0x001f).rw(FUNC(idegdrom_device::ide_cs1_r), FUNC(idegdrom_device::ide_cs1_w));
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}
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void idegdrom_device::map_dma(address_map &map)
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{
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map(0x0000, 0x000f).rw("ide", FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
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}
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READ32_MEMBER(idegdrom_device::ide_cs0_r)
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{
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const int o = offset >> 2;
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const int r = (offset & 3) << 3;
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return m_ide->cs0_r(space, o, mem_mask << r) >> r;
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}
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READ32_MEMBER(idegdrom_device::ide_cs1_r)
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{
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const int o = offset >> 2;
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const int r = (offset & 3) << 3;
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return m_ide->cs1_r(space, o, mem_mask << r) >> r;
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}
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WRITE32_MEMBER(idegdrom_device::ide_cs0_w)
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{
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const int o = offset >> 2;
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const int r = (offset & 3) << 3;
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m_ide->cs0_w(space, o, data << r, mem_mask << r);
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}
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WRITE32_MEMBER(idegdrom_device::ide_cs1_w)
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{
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const int o = offset >> 2;
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const int r = (offset & 3) << 3;
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m_ide->cs1_w(space, o, data << r, mem_mask << r);
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}
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// The board
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naomi_gdrom_board::naomi_gdrom_board(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: naomi_board(mconfig, NAOMI_GDROM_BOARD, tag, owner, clock),
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m_maincpu(*this, "dimmcpu"),
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@ -408,8 +519,8 @@ naomi_gdrom_board::naomi_gdrom_board(const machine_config &mconfig, const char *
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m_i2c0(*this, "i2c_0"),
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m_i2c1(*this, "i2c_1"),
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m_eeprom(*this, "eeprom"),
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m_315_6154(*this, "northbridge"),
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m_ide(*this, "ide"),
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m_315_6154(*this, "pci:00.0"),
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m_idegdrom(*this, "pci:01.0"),
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picdata(*this, finder_base::DUMMY_TAG),
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dimm_command(0xffff),
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dimm_offsetl(0xffff),
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@ -442,8 +553,8 @@ void naomi_gdrom_board::sh4_map(address_map &map)
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{
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map(0x00000000, 0x001fffff).mirror(0xa0000000).rom().region("bios", 0);
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map(0x04000000, 0x040000ff).rw(m_315_6154, FUNC(sega_315_6154_device::registers_r), FUNC(sega_315_6154_device::registers_w));
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map(0x0c000000, 0x0cffffff).ram().share("sh4sdram");
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map(0x10000000, 0x103fffff).ram().share("6154sdram");
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map(0x0c000000, 0x0cffffff).ram().share("pci:sh4sdram");
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map(0x10000000, 0x103fffff).ram().share("pci:6154sdram");
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map(0x14000000, 0x17ffffff).rw(m_315_6154, FUNC(sega_315_6154_device::aperture_r<0>), FUNC(sega_315_6154_device::aperture_w<0>));
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map(0x18000000, 0x1bffffff).rw(m_315_6154, FUNC(sega_315_6154_device::aperture_r<1>), FUNC(sega_315_6154_device::aperture_w<1>));
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map.unmap_value_high();
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@ -454,28 +565,22 @@ void naomi_gdrom_board::sh4_io_map(address_map &map)
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map(0x00, 0x0f).rw(FUNC(naomi_gdrom_board::i2cmem_dimm_r), FUNC(naomi_gdrom_board::i2cmem_dimm_w));
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}
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void naomi_gdrom_board::pci_map(address_map& map)
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void naomi_gdrom_board::pci_map(address_map &map)
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{
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map(0x00000000, 0x00000003).rw(FUNC(naomi_gdrom_board::sh4_unknown_r), FUNC(naomi_gdrom_board::sh4_unknown_w));
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map(0x00000014, 0x00000017).rw(FUNC(naomi_gdrom_board::sh4_command_r), FUNC(naomi_gdrom_board::sh4_command_w));
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map(0x00000018, 0x0000001b).rw(FUNC(naomi_gdrom_board::sh4_offsetl_r), FUNC(naomi_gdrom_board::sh4_offsetl_w));
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map(0x0000001c, 0x0000001f).rw(FUNC(naomi_gdrom_board::sh4_parameterl_r), FUNC(naomi_gdrom_board::sh4_parameterl_w));
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map(0x00000020, 0x00000023).rw(FUNC(naomi_gdrom_board::sh4_parameterh_r), FUNC(naomi_gdrom_board::sh4_parameterh_w));
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map(0x00000024, 0x00000027).rw(FUNC(naomi_gdrom_board::sh4_status_r), FUNC(naomi_gdrom_board::sh4_status_w));
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map(0x00000028, 0x0000002b).rw(FUNC(naomi_gdrom_board::sh4_control_r), FUNC(naomi_gdrom_board::sh4_control_w));
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const char *t = tag();
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map(0x00000000, 0x00000003).rw(t, FUNC(naomi_gdrom_board::sh4_unknown_r), FUNC(naomi_gdrom_board::sh4_unknown_w));
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map(0x00000014, 0x00000017).rw(t, FUNC(naomi_gdrom_board::sh4_command_r), FUNC(naomi_gdrom_board::sh4_command_w));
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map(0x00000018, 0x0000001b).rw(t, FUNC(naomi_gdrom_board::sh4_offsetl_r), FUNC(naomi_gdrom_board::sh4_offsetl_w));
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map(0x0000001c, 0x0000001f).rw(t, FUNC(naomi_gdrom_board::sh4_parameterl_r), FUNC(naomi_gdrom_board::sh4_parameterl_w));
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map(0x00000020, 0x00000023).rw(t, FUNC(naomi_gdrom_board::sh4_parameterh_r), FUNC(naomi_gdrom_board::sh4_parameterh_w));
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map(0x00000024, 0x00000027).rw(t, FUNC(naomi_gdrom_board::sh4_status_r), FUNC(naomi_gdrom_board::sh4_status_w));
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map(0x00000028, 0x0000002b).rw(t, FUNC(naomi_gdrom_board::sh4_control_r), FUNC(naomi_gdrom_board::sh4_control_w));
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map(0x0000002c, 0x0000002f).lr32([]() { return 0x0c; }, "Constant 0x0c"); // 0x0a or 0x0e possible too
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map(0x00000030, 0x00000033).rw(FUNC(naomi_gdrom_board::sh4_des_keyl_r), FUNC(naomi_gdrom_board::sh4_des_keyl_w));
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map(0x00000034, 0x00000037).rw(FUNC(naomi_gdrom_board::sh4_des_keyh_r), FUNC(naomi_gdrom_board::sh4_des_keyh_w));
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map(0x00000030, 0x00000033).rw(t, FUNC(naomi_gdrom_board::sh4_des_keyl_r), FUNC(naomi_gdrom_board::sh4_des_keyl_w));
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map(0x00000034, 0x00000037).rw(t, FUNC(naomi_gdrom_board::sh4_des_keyh_r), FUNC(naomi_gdrom_board::sh4_des_keyh_w));
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map(0x70000000, 0x70ffffff).ram().share("sh4sdram");
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map(0x78000000, 0x783fffff).ram().share("6154sdram");
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map(0xc00001c0, 0xc00001df).rw(FUNC(naomi_gdrom_board::ide_cs0_r), FUNC(naomi_gdrom_board::ide_cs0_w));
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map(0xc00003b0, 0xc00003cf).rw(FUNC(naomi_gdrom_board::ide_cs1_r), FUNC(naomi_gdrom_board::ide_cs1_w));
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map(0xc000cc00, 0xc000cc0f).rw(m_ide, FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
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}
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void naomi_gdrom_board::pci_config_map(address_map& map)
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{
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map(0x1000, 0x1003).lr32([]() { return 0x189d11db; }, "Constant 0x189d11db"); // 0x10001022 or 0x11720001 possible too
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}
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WRITE16_MEMBER(naomi_gdrom_board::dimm_command_w)
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@ -683,38 +788,6 @@ WRITE64_MEMBER(naomi_gdrom_board::i2cmem_dimm_w)
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}
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}
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READ32_MEMBER(naomi_gdrom_board::ide_cs0_r)
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{
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const int o = offset >> 2;
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const int r = (offset & 3) << 3;
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return m_ide->cs0_r(space, o, mem_mask << r) >> r;
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}
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READ32_MEMBER(naomi_gdrom_board::ide_cs1_r)
|
||||
{
|
||||
const int o = offset >> 2;
|
||||
const int r = (offset & 3) << 3;
|
||||
|
||||
return m_ide->cs1_r(space, o, mem_mask << r) >> r;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(naomi_gdrom_board::ide_cs0_w)
|
||||
{
|
||||
const int o = offset >> 2;
|
||||
const int r = (offset & 3) << 3;
|
||||
|
||||
m_ide->cs0_w(space, o, data << r, mem_mask << r);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(naomi_gdrom_board::ide_cs1_w)
|
||||
{
|
||||
const int o = offset >> 2;
|
||||
const int r = (offset & 3) << 3;
|
||||
|
||||
m_ide->cs1_w(space, o, data << r, mem_mask << r);
|
||||
}
|
||||
|
||||
void naomi_gdrom_board::pic_map(address_map &map)
|
||||
{
|
||||
map(0x00, 0x1f).rw(FUNC(naomi_gdrom_board::pic_dimm_r), FUNC(naomi_gdrom_board::pic_dimm_w));
|
||||
@ -972,11 +1045,6 @@ void naomi_gdrom_board::board_advance(uint32_t size)
|
||||
dimm_cur_address %= dimm_data_size;
|
||||
}
|
||||
|
||||
static void gdrom_devices(device_slot_interface& device)
|
||||
{
|
||||
device.option_add(":gdrom", GDROM);
|
||||
}
|
||||
|
||||
#define CPU_CLOCK 200000000 // need to set the correct value here
|
||||
#define PIC_CLOCK 20000000 // and here
|
||||
|
||||
@ -995,12 +1063,13 @@ void naomi_gdrom_board::device_add_mconfig(machine_config &config)
|
||||
m_maincpu->set_sh4_clock(CPU_CLOCK);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &naomi_gdrom_board::sh4_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &naomi_gdrom_board::sh4_io_map);
|
||||
|
||||
|
||||
PCI_ROOT(config, "pci", 0);
|
||||
SEGA315_6154(config, m_315_6154, 0);
|
||||
m_315_6154->set_addrmap(sega_315_6154_device::AS_PCI_MEMORY, &naomi_gdrom_board::pci_map);
|
||||
m_315_6154->set_addrmap(sega_315_6154_device::AS_PCI_CONFIGURATION, &naomi_gdrom_board::pci_config_map);
|
||||
BUS_MASTER_IDE_CONTROLLER(config, m_ide).options(gdrom_devices, ":gdrom", nullptr, true);
|
||||
m_ide->irq_handler().set_inputline(m_maincpu, SH4_IRL2);
|
||||
m_ide->set_bus_master_space(m_315_6154, sega_315_6154_device::AS_PCI_MEMORY);
|
||||
IDE_GDROM(config, m_idegdrom, 0, image_tag, m_315_6154->tag(), sega_315_6154_device::AS_PCI_MEMORY);
|
||||
m_idegdrom->irq_callback().set_inputline(m_maincpu, SH4_IRL2);
|
||||
PIC16C622(config, m_securitycpu, PIC_CLOCK);
|
||||
m_securitycpu->set_addrmap(AS_IO, &naomi_gdrom_board::pic_map);
|
||||
m_securitycpu->set_config(0x3fff - 0x04);
|
||||
|
||||
@ -13,6 +13,43 @@
|
||||
#include "machine/idectrl.h"
|
||||
#include "machine/gdrom.h"
|
||||
|
||||
// For ide gdrom controller
|
||||
|
||||
class idegdrom_device : public pci_device {
|
||||
public:
|
||||
idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, const char *image_tag, const char *space_tag, int space_id);
|
||||
idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
auto irq_callback() { return irq_cb.bind(); }
|
||||
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
|
||||
void map_command(address_map &map);
|
||||
void map_control(address_map &map);
|
||||
void map_dma(address_map &map);
|
||||
|
||||
DECLARE_READ32_MEMBER(ide_cs0_r);
|
||||
DECLARE_READ32_MEMBER(ide_cs1_r);
|
||||
DECLARE_WRITE32_MEMBER(ide_cs0_w);
|
||||
DECLARE_WRITE32_MEMBER(ide_cs1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_irq);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
|
||||
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
|
||||
|
||||
private:
|
||||
required_device<bus_master_ide_controller_device> m_ide;
|
||||
devcb_write_line irq_cb;
|
||||
const char *space_owner_tag;
|
||||
int space_owner_id;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(IDE_GDROM, idegdrom_device)
|
||||
|
||||
class naomi_gdrom_board : public naomi_board
|
||||
{
|
||||
public:
|
||||
@ -36,7 +73,7 @@ public:
|
||||
naomi_gdrom_board(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void submap(address_map& map) override;
|
||||
virtual void submap(address_map &map) override;
|
||||
void sh4_map(address_map &map);
|
||||
void sh4_io_map(address_map &map);
|
||||
void pic_map(address_map &map);
|
||||
@ -87,11 +124,6 @@ public:
|
||||
DECLARE_READ8_MEMBER(pic_dimm_r);
|
||||
DECLARE_WRITE8_MEMBER(pic_dimm_w);
|
||||
|
||||
DECLARE_READ32_MEMBER(ide_cs0_r);
|
||||
DECLARE_READ32_MEMBER(ide_cs1_r);
|
||||
DECLARE_WRITE32_MEMBER(ide_cs0_w);
|
||||
DECLARE_WRITE32_MEMBER(ide_cs1_w);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
@ -102,7 +134,7 @@ protected:
|
||||
|
||||
private:
|
||||
enum { FILENAME_LENGTH=24 };
|
||||
const int work_mode = 0; // set to 1 and rebuild to enable the cpus
|
||||
const int work_mode = 0; // set to 1 and rebuild to enable the cpus and full dimm board emulation
|
||||
|
||||
required_device<sh4_device> m_maincpu;
|
||||
required_device<pic16c622_device> m_securitycpu;
|
||||
@ -110,7 +142,7 @@ private:
|
||||
required_device<i2cmem_device> m_i2c1;
|
||||
required_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||
required_device<sega_315_6154_device> m_315_6154;
|
||||
required_device<bus_master_ide_controller_device> m_ide;
|
||||
required_device<idegdrom_device> m_idegdrom;
|
||||
|
||||
const char *image_tag;
|
||||
optional_region_ptr<uint8_t> picdata;
|
||||
@ -159,4 +191,5 @@ private:
|
||||
|
||||
DECLARE_DEVICE_TYPE(NAOMI_GDROM_BOARD, naomi_gdrom_board)
|
||||
|
||||
|
||||
#endif // MAME_MACHINE_NAOMIGD_H
|
||||
|
||||
Loading…
Reference in New Issue
Block a user