From 6c2a2a22c2d4b7474a7382b5daa445bcd4546ef9 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Mon, 19 Aug 2013 18:40:10 +0000 Subject: [PATCH] m37710.c: Modernized cpu core (nw) --- src/emu/cpu/m37710/m37710.c | 1134 +++++++++++-------- src/emu/cpu/m37710/m37710.h | 1937 ++++++++++++++++++++++++++++++++- src/emu/cpu/m37710/m37710cm.h | 348 +++--- src/emu/cpu/m37710/m37710op.h | 909 +++++----------- 4 files changed, 3065 insertions(+), 1263 deletions(-) diff --git a/src/emu/cpu/m37710/m37710.c b/src/emu/cpu/m37710/m37710.c index aa73ec1392d..6de5592c37d 100644 --- a/src/emu/cpu/m37710/m37710.c +++ b/src/emu/cpu/m37710/m37710.c @@ -58,12 +58,43 @@ #define M37710_DEBUG (0) // enables verbose logging for peripherals, etc. -static void m37710_set_irq_line(m37710i_cpu_struct *cpustate, int line, int state); + +const device_type M37710 = &device_creator; +const device_type M37702 = &device_creator; + + +// On-board RAM and peripherals +static ADDRESS_MAP_START( m37710_internal_map, AS_PROGRAM, 16, m37710_cpu_device ) + AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w) + AM_RANGE(0x000080, 0x00027f) AM_RAM +ADDRESS_MAP_END + + +m37710_cpu_device::m37710_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, M37710, "M37710", tag, owner, clock, "m37710", __FILE__) + , m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(m37710_internal_map)) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0) +{ +} + + +m37710_cpu_device::m37710_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) + , m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(m37710_internal_map)) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0) +{ +} + + +m37702_cpu_device::m37702_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : m37710_cpu_device(mconfig, M37702, "M37702", tag, owner, clock, "m37702", __FILE__) +{ +} + /* interrupt control mapping */ -extern const int m37710_irq_levels[M37710_LINE_MAX]; -const int m37710_irq_levels[M37710_LINE_MAX] = +const int m37710_cpu_device::m37710_irq_levels[M37710_LINE_MAX] = { // maskable 0x70, // ADC 0 @@ -91,7 +122,7 @@ const int m37710_irq_levels[M37710_LINE_MAX] = 0, // reset }; -static const int m37710_irq_vectors[M37710_LINE_MAX] = +const int m37710_cpu_device::m37710_irq_vectors[M37710_LINE_MAX] = { // maskable 0xffd6, // A-D converter @@ -121,8 +152,7 @@ static const int m37710_irq_vectors[M37710_LINE_MAX] = // M37710 internal peripherals -#if M37710_DEBUG -static const char *const m37710_rnames[128] = +const char *const m37710_cpu_device::m37710_rnames[128] = { "", "", @@ -254,25 +284,23 @@ static const char *const m37710_rnames[128] = "INT2 IRQ ctrl", }; -static const char *const m37710_tnames[8] = +const char *const m37710_cpu_device::m37710_tnames[8] = { "A0", "A1", "A2", "A3", "A4", "B0", "B1", "B2" }; -#endif -static TIMER_CALLBACK( m37710_timer_cb ) +TIMER_CALLBACK_MEMBER( m37710_cpu_device::m37710_timer_cb ) { - m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)ptr; int which = param; int curirq = M37710_LINE_TIMERA0 - which; - cpustate->timers[which]->adjust(cpustate->reload[which], param); + m_timers[which]->adjust(m_reload[which], param); - m37710_set_irq_line(cpustate, curirq, HOLD_LINE); - cpustate->device->signal_interrupt_trigger(); + m37710_set_irq_line(curirq, HOLD_LINE); + signal_interrupt_trigger(); } -static void m37710_external_tick(m37710i_cpu_struct *cpustate, int timer, int state) +void m37710_cpu_device::m37710_external_tick(int timer, int state) { // we only care if the state is "on" if (!state) @@ -281,18 +309,18 @@ static void m37710_external_tick(m37710i_cpu_struct *cpustate, int timer, int st } // check if enabled - if (cpustate->m37710_regs[0x40] & (1<m37710_regs[0x56+timer] & 0x3) == 1) + if ((m_m37710_regs[0x56+timer] & 0x3) == 1) { - if (cpustate->m37710_regs[0x46+(timer*2)] == 0xff) + if (m_m37710_regs[0x46+(timer*2)] == 0xff) { - cpustate->m37710_regs[0x46+(timer*2)] = 0; - cpustate->m37710_regs[0x46+(timer*2)+1]++; + m_m37710_regs[0x46+(timer*2)] = 0; + m_m37710_regs[0x46+(timer*2)+1]++; } else { - cpustate->m37710_regs[0x46+(timer*2)]++; + m_m37710_regs[0x46+(timer*2)]++; } } else @@ -302,41 +330,41 @@ static void m37710_external_tick(m37710i_cpu_struct *cpustate, int timer, int st } } -static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, int timer) +void m37710_cpu_device::m37710_recalc_timer(int timer) { int tval; attotime time; static const int tscales[4] = { 2, 16, 64, 512 }; // check if enabled - if (cpustate->m37710_regs[0x40] & (1<m37710_regs[0x46+(timer*2)] | (cpustate->m37710_regs[0x47+(timer*2)]<<8); + tval = m_m37710_regs[0x46+(timer*2)] | (m_m37710_regs[0x47+(timer*2)]<<8); // HACK: ignore if timer is 8MHz (MAME slows down to a crawl) - if (tval == 0 && (cpustate->m37710_regs[0x56+timer]&0xc0) == 0) return; + if (tval == 0 && (m_m37710_regs[0x56+timer]&0xc0) == 0) return; // check timer's mode // modes are slightly different between timer groups A and B if (timer < 5) { - switch (cpustate->m37710_regs[0x56+timer] & 0x3) + switch (m_m37710_regs[0x56+timer] & 0x3) { case 0: // timer mode - time = attotime::from_hz(cpustate->device->unscaled_clock()) * tscales[cpustate->m37710_regs[0x56+timer]>>6]; + time = attotime::from_hz(unscaled_clock()) * tscales[m_m37710_regs[0x56+timer]>>6]; time *= (tval + 1); #if M37710_DEBUG logerror("Timer %d in timer mode, %f Hz\n", timer, 1.0 / time.as_double()); #endif - cpustate->timers[timer]->adjust(time, timer); - cpustate->reload[timer] = time; + m_timers[timer]->adjust(time, timer); + m_reload[timer] = time; break; case 1: // event counter mode @@ -360,18 +388,18 @@ static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, int timer) } else { - switch (cpustate->m37710_regs[0x56+timer] & 0x3) + switch (m_m37710_regs[0x56+timer] & 0x3) { case 0: // timer mode - time = attotime::from_hz(cpustate->device->unscaled_clock()) * tscales[cpustate->m37710_regs[0x56+timer]>>6]; + time = attotime::from_hz(unscaled_clock()) * tscales[m_m37710_regs[0x56+timer]>>6]; time *= (tval + 1); #if M37710_DEBUG logerror("Timer %d in timer mode, %f Hz\n", timer, 1.0 / time.as_double()); #endif - cpustate->timers[timer]->adjust(time, timer); - cpustate->reload[timer] = time; + m_timers[timer]->adjust(time, timer); + m_reload[timer] = time; break; case 1: // event counter mode @@ -396,7 +424,7 @@ static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, int timer) } } -static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset) +UINT8 m37710_cpu_device::m37710_internal_r(int offset) { UINT8 d; @@ -409,84 +437,84 @@ static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset) { // ports case 0x02: // p0 - d = cpustate->m37710_regs[0x04]; + d = m_m37710_regs[0x04]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT0)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT0)&~d) | (m_m37710_regs[offset]&d); break; case 0x03: // p1 - d = cpustate->m37710_regs[0x05]; + d = m_m37710_regs[0x05]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT1)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT1)&~d) | (m_m37710_regs[offset]&d); break; case 0x06: // p2 - d = cpustate->m37710_regs[0x08]; + d = m_m37710_regs[0x08]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT2)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT2)&~d) | (m_m37710_regs[offset]&d); break; case 0x07: // p3 - d = cpustate->m37710_regs[0x09]; + d = m_m37710_regs[0x09]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT3)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT3)&~d) | (m_m37710_regs[offset]&d); break; case 0x0a: // p4 - d = cpustate->m37710_regs[0x0c]; + d = m_m37710_regs[0x0c]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT4)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT4)&~d) | (m_m37710_regs[offset]&d); break; case 0x0b: // p5 - d = cpustate->m37710_regs[0x0d]; + d = m_m37710_regs[0x0d]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT5)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT5)&~d) | (m_m37710_regs[offset]&d); break; case 0x0e: // p6 - d = cpustate->m37710_regs[0x10]; + d = m_m37710_regs[0x10]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT6)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT6)&~d) | (m_m37710_regs[offset]&d); break; case 0x0f: // p7 - d = cpustate->m37710_regs[0x11]; + d = m_m37710_regs[0x11]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT7)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT7)&~d) | (m_m37710_regs[offset]&d); break; case 0x12: // p8 - d = cpustate->m37710_regs[0x14]; + d = m_m37710_regs[0x14]; if (d != 0xff) - return (cpustate->io->read_byte(M37710_PORT8)&~d) | (cpustate->m37710_regs[offset]&d); + return (m_io->read_byte(M37710_PORT8)&~d) | (m_m37710_regs[offset]&d); break; // A-D regs case 0x20: - return cpustate->io->read_byte(M37710_ADC0_L); + return m_io->read_byte(M37710_ADC0_L); case 0x21: - return cpustate->io->read_byte(M37710_ADC0_H); + return m_io->read_byte(M37710_ADC0_H); case 0x22: - return cpustate->io->read_byte(M37710_ADC1_L); + return m_io->read_byte(M37710_ADC1_L); case 0x23: - return cpustate->io->read_byte(M37710_ADC1_H); + return m_io->read_byte(M37710_ADC1_H); case 0x24: - return cpustate->io->read_byte(M37710_ADC2_L); + return m_io->read_byte(M37710_ADC2_L); case 0x25: - return cpustate->io->read_byte(M37710_ADC2_H); + return m_io->read_byte(M37710_ADC2_H); case 0x26: - return cpustate->io->read_byte(M37710_ADC3_L); + return m_io->read_byte(M37710_ADC3_L); case 0x27: - return cpustate->io->read_byte(M37710_ADC3_H); + return m_io->read_byte(M37710_ADC3_H); case 0x28: - return cpustate->io->read_byte(M37710_ADC4_L); + return m_io->read_byte(M37710_ADC4_L); case 0x29: - return cpustate->io->read_byte(M37710_ADC4_H); + return m_io->read_byte(M37710_ADC4_H); case 0x2a: - return cpustate->io->read_byte(M37710_ADC5_L); + return m_io->read_byte(M37710_ADC5_L); case 0x2b: - return cpustate->io->read_byte(M37710_ADC5_H); + return m_io->read_byte(M37710_ADC5_H); case 0x2c: - return cpustate->io->read_byte(M37710_ADC6_L); + return m_io->read_byte(M37710_ADC6_L); case 0x2d: - return cpustate->io->read_byte(M37710_ADC6_H); + return m_io->read_byte(M37710_ADC6_H); case 0x2e: - return cpustate->io->read_byte(M37710_ADC7_L); + return m_io->read_byte(M37710_ADC7_L); case 0x2f: - return cpustate->io->read_byte(M37710_ADC7_H); + return m_io->read_byte(M37710_ADC7_H); // UART control (not hooked up yet) case 0x34: case 0x3c: @@ -496,16 +524,16 @@ static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset) // A-D IRQ control (also not properly hooked up yet) case 0x70: - return cpustate->m37710_regs[offset] | 8; + return m_m37710_regs[offset] | 8; default: - return cpustate->m37710_regs[offset]; + return m_m37710_regs[offset]; } - return cpustate->m37710_regs[offset]; + return m_m37710_regs[offset]; } -static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 data) +void m37710_cpu_device::m37710_internal_w(int offset, UINT8 data) { int i; UINT8 prevdata; @@ -513,80 +541,80 @@ static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 da #if M37710_DEBUG if (offset != 0x60) // filter out watchdog - logerror("m37710_internal_w %x to %02x: %s = %x\n", data, (int)offset, m37710_rnames[(int)offset], cpustate->m37710_regs[offset]); + logerror("m37710_internal_w %x to %02x: %s = %x\n", data, (int)offset, m37710_rnames[(int)offset], m_m37710_regs[offset]); #endif - prevdata = cpustate->m37710_regs[offset]; - cpustate->m37710_regs[offset] = data; + prevdata = m_m37710_regs[offset]; + m_m37710_regs[offset] = data; switch(offset) { // ports case 0x02: // p0 - d = cpustate->m37710_regs[0x04]; + d = m_m37710_regs[0x04]; if (d != 0) - cpustate->io->write_byte(M37710_PORT0, data&d); + m_io->write_byte(M37710_PORT0, data&d); break; case 0x03: // p1 - d = cpustate->m37710_regs[0x05]; + d = m_m37710_regs[0x05]; if (d != 0) - cpustate->io->write_byte(M37710_PORT1, data&d); + m_io->write_byte(M37710_PORT1, data&d); break; case 0x06: // p2 - d = cpustate->m37710_regs[0x08]; + d = m_m37710_regs[0x08]; if (d != 0) - cpustate->io->write_byte(M37710_PORT2, data&d); + m_io->write_byte(M37710_PORT2, data&d); break; case 0x07: // p3 - d = cpustate->m37710_regs[0x09]; + d = m_m37710_regs[0x09]; if (d != 0) - cpustate->io->write_byte(M37710_PORT3, data&d); + m_io->write_byte(M37710_PORT3, data&d); break; case 0x0a: // p4 - d = cpustate->m37710_regs[0x0c]; + d = m_m37710_regs[0x0c]; if (d != 0) - cpustate->io->write_byte(M37710_PORT4, data&d); + m_io->write_byte(M37710_PORT4, data&d); break; case 0x0b: // p5 - d = cpustate->m37710_regs[0x0d]; + d = m_m37710_regs[0x0d]; if (d != 0) - cpustate->io->write_byte(M37710_PORT5, data&d); + m_io->write_byte(M37710_PORT5, data&d); break; case 0x0e: // p6 - d = cpustate->m37710_regs[0x10]; + d = m_m37710_regs[0x10]; if (d != 0) - cpustate->io->write_byte(M37710_PORT6, data&d); + m_io->write_byte(M37710_PORT6, data&d); break; case 0x0f: // p7 - d = cpustate->m37710_regs[0x11]; + d = m_m37710_regs[0x11]; if (d != 0) - cpustate->io->write_byte(M37710_PORT7, data&d); + m_io->write_byte(M37710_PORT7, data&d); break; case 0x12: // p8 - d = cpustate->m37710_regs[0x14]; + d = m_m37710_regs[0x14]; if (d != 0) - cpustate->io->write_byte(M37710_PORT8, data&d); + m_io->write_byte(M37710_PORT8, data&d); break; case 0x40: // count start for (i = 0; i < 8; i++) { if ((data & (1<>8); + m37710_internal_w(offset*2+1, data>>8); } -extern void (*const m37710i_opcodes_M0X0[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes42_M0X0[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes89_M0X0[])(m37710i_cpu_struct *cpustate); -extern uint m37710i_get_reg_M0X0(m37710i_cpu_struct *cpustate, int regnum); -extern void m37710i_set_reg_M0X0(m37710i_cpu_struct *cpustate, int regnum, uint val); -extern void m37710i_set_line_M0X0(m37710i_cpu_struct *cpustate, int line, int state); -extern int m37710i_execute_M0X0(m37710i_cpu_struct *cpustate, int cycles); -extern void (*const m37710i_opcodes_M0X1[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes42_M0X1[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes89_M0X1[])(m37710i_cpu_struct *cpustate); -extern uint m37710i_get_reg_M0X1(m37710i_cpu_struct *cpustate, int regnum); -extern void m37710i_set_reg_M0X1(m37710i_cpu_struct *cpustate, int regnum, uint val); -extern void m37710i_set_line_M0X1(m37710i_cpu_struct *cpustate, int line, int state); -extern int m37710i_execute_M0X1(m37710i_cpu_struct *cpustate, int cycles); - -extern void (*const m37710i_opcodes_M1X0[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes42_M1X0[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes89_M1X0[])(m37710i_cpu_struct *cpustate); -extern uint m37710i_get_reg_M1X0(m37710i_cpu_struct *cpustate, int regnum); -extern void m37710i_set_reg_M1X0(m37710i_cpu_struct *cpustate, int regnum, uint val); -extern void m37710i_set_line_M1X0(m37710i_cpu_struct *cpustate, int line, int state); -extern int m37710i_execute_M1X0(m37710i_cpu_struct *cpustate, int cycles); - -extern void (*const m37710i_opcodes_M1X1[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes42_M1X1[])(m37710i_cpu_struct *cpustate); -extern void (*const m37710i_opcodes89_M1X1[])(m37710i_cpu_struct *cpustate); -extern uint m37710i_get_reg_M1X1(m37710i_cpu_struct *cpustate, int regnum); -extern void m37710i_set_reg_M1X1(m37710i_cpu_struct *cpustate, int regnum, uint val); -extern void m37710i_set_line_M1X1(m37710i_cpu_struct *cpustate, int line, int state); -extern int m37710i_execute_M1X1(m37710i_cpu_struct *cpustate, int cycles); - -void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *cpustate) = +const m37710_cpu_device::opcode_func *m37710_cpu_device::m37710i_opcodes[4] = { m37710i_opcodes_M0X0, m37710i_opcodes_M0X1, @@ -660,7 +654,7 @@ void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *cpustate) = m37710i_opcodes_M1X1, }; -void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *cpustate) = +const m37710_cpu_device::opcode_func *m37710_cpu_device::m37710i_opcodes2[4] = { m37710i_opcodes42_M0X0, m37710i_opcodes42_M0X1, @@ -668,7 +662,7 @@ void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *cpustate) = m37710i_opcodes42_M1X1, }; -void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *cpustate) = +const m37710_cpu_device::opcode_func *m37710_cpu_device::m37710i_opcodes3[4] = { m37710i_opcodes89_M0X0, m37710i_opcodes89_M0X1, @@ -676,53 +670,53 @@ void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *cpustate) = m37710i_opcodes89_M1X1, }; -uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *cpustate, int regnum) = +const m37710_cpu_device::get_reg_func m37710_cpu_device::m37710i_get_reg[4] = { - m37710i_get_reg_M0X0, - m37710i_get_reg_M0X1, - m37710i_get_reg_M1X0, - m37710i_get_reg_M1X1, + &m37710_cpu_device::m37710i_get_reg_M0X0, + &m37710_cpu_device::m37710i_get_reg_M0X1, + &m37710_cpu_device::m37710i_get_reg_M1X0, + &m37710_cpu_device::m37710i_get_reg_M1X1, }; -void (*const m37710i_set_reg[4])(m37710i_cpu_struct *cpustate, int regnum, uint val) = +const m37710_cpu_device::set_reg_func m37710_cpu_device::m37710i_set_reg[4] = { - m37710i_set_reg_M0X0, - m37710i_set_reg_M0X1, - m37710i_set_reg_M1X0, - m37710i_set_reg_M1X1, + &m37710_cpu_device::m37710i_set_reg_M0X0, + &m37710_cpu_device::m37710i_set_reg_M0X1, + &m37710_cpu_device::m37710i_set_reg_M1X0, + &m37710_cpu_device::m37710i_set_reg_M1X1, }; -void (*const m37710i_set_line[4])(m37710i_cpu_struct *cpustate, int line, int state) = +const m37710_cpu_device::set_line_func m37710_cpu_device::m37710i_set_line[4] = { - m37710i_set_line_M0X0, - m37710i_set_line_M0X1, - m37710i_set_line_M1X0, - m37710i_set_line_M1X1, + &m37710_cpu_device::m37710i_set_line_M0X0, + &m37710_cpu_device::m37710i_set_line_M0X1, + &m37710_cpu_device::m37710i_set_line_M1X0, + &m37710_cpu_device::m37710i_set_line_M1X1, }; -int (*const m37710i_execute[4])(m37710i_cpu_struct *cpustate, int cycles) = +const m37710_cpu_device::execute_func m37710_cpu_device::m37710i_execute[4] = { - m37710i_execute_M0X0, - m37710i_execute_M0X1, - m37710i_execute_M1X0, - m37710i_execute_M1X1, + &m37710_cpu_device::m37710i_execute_M0X0, + &m37710_cpu_device::m37710i_execute_M0X1, + &m37710_cpu_device::m37710i_execute_M1X0, + &m37710_cpu_device::m37710i_execute_M1X1, }; /* internal functions */ -INLINE void m37710i_push_8(m37710i_cpu_struct *cpustate, uint value) +void m37710_cpu_device::m37710i_push_8(UINT32 value) { m37710_write_8(REG_S, value); REG_S = MAKE_UINT_16(REG_S-1); } -INLINE void m37710i_push_16(m37710i_cpu_struct *cpustate, uint value) +void m37710_cpu_device::m37710i_push_16(UINT32 value) { - m37710i_push_8(cpustate, value>>8); - m37710i_push_8(cpustate, value&0xff); + m37710i_push_8(value>>8); + m37710i_push_8(value&0xff); } -INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate) +UINT32 m37710_cpu_device::m37710i_get_reg_p() { return (FLAG_N&0x80) | ((FLAG_V>>1)&0x40) | @@ -734,7 +728,7 @@ INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate) ((FLAG_C>>8)&1); } -void m37710i_update_irqs(m37710i_cpu_struct *cpustate) +void m37710_cpu_device::m37710i_update_irqs() { int curirq, pending = LINE_IRQ; int wantedIRQ = -1; @@ -747,11 +741,11 @@ void m37710i_update_irqs(m37710i_cpu_struct *cpustate) // this IRQ is set if (m37710_irq_levels[curirq]) { - int control = cpustate->m37710_regs[m37710_irq_levels[curirq]]; + int control = m_m37710_regs[m37710_irq_levels[curirq]]; int thispri = control & 7; - // logerror("line %d set, level %x curpri %x IPL %x\n", curirq, thispri, curpri, cpustate->ipl); + // logerror("line %d set, level %x curpri %x IPL %x\n", curirq, thispri, curpri, m_ipl); // it's maskable, check if the level works, also make sure it's acceptable for the current CPU level - if (!FLAG_I && thispri > curpri && thispri > cpustate->ipl) + if (!FLAG_I && thispri > curpri && thispri > m_ipl) { // mark us as the best candidate wantedIRQ = curirq; @@ -770,26 +764,26 @@ void m37710i_update_irqs(m37710i_cpu_struct *cpustate) if (wantedIRQ != -1) { - if (INT_ACK) INT_ACK(cpustate->device, wantedIRQ); + standard_irq_callback(wantedIRQ); // make sure we're running to service the interrupt CPU_STOPPED &= ~STOP_LEVEL_WAI; // auto-clear line - m37710_set_irq_line(cpustate, wantedIRQ, CLEAR_LINE); + m37710_set_irq_line(wantedIRQ, CLEAR_LINE); // let's do it... // push PB, then PC, then status CLK(13); -// mame_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, cpustate->ipl); - m37710i_push_8(cpustate, REG_PB>>16); - m37710i_push_16(cpustate, REG_PC); - m37710i_push_8(cpustate, cpustate->ipl); - m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); +// mame_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, m_ipl); + m37710i_push_8(REG_PB>>16); + m37710i_push_16(REG_PC); + m37710i_push_8(m_ipl); + m37710i_push_8(m37710i_get_reg_p()); // set I to 1, set IPL to the interrupt we're taking FLAG_I = IFLAG_SET; - cpustate->ipl = curpri; + m_ipl = curpri; // then PB=0, PC=(vector) REG_PB = 0; REG_PC = m37710_read_8(m37710_irq_vectors[wantedIRQ]) | @@ -801,16 +795,15 @@ void m37710i_update_irqs(m37710i_cpu_struct *cpustate) /* external functions */ -static CPU_RESET( m37710 ) +void m37710_cpu_device::device_reset() { int i; - m37710i_cpu_struct *cpustate = get_safe_token(device); /* Reset MAME timers */ for (i = 0; i < 8; i++) { - cpustate->timers[i]->reset(); - cpustate->reload[i] = attotime::zero; + m_timers[i]->reset(); + m_reload[i] = attotime::zero; } /* Start the CPU */ @@ -818,48 +811,48 @@ static CPU_RESET( m37710 ) /* Reset internal registers */ // port direction - cpustate->m37710_regs[0x04] = 0; - cpustate->m37710_regs[0x05] = 0; - cpustate->m37710_regs[0x08] = 0; - cpustate->m37710_regs[0x09] = 0; - cpustate->m37710_regs[0x0c] = 0; - cpustate->m37710_regs[0x0d] = 0; - cpustate->m37710_regs[0x10] = 0; - cpustate->m37710_regs[0x11] = 0; - cpustate->m37710_regs[0x14] = 0; + m_m37710_regs[0x04] = 0; + m_m37710_regs[0x05] = 0; + m_m37710_regs[0x08] = 0; + m_m37710_regs[0x09] = 0; + m_m37710_regs[0x0c] = 0; + m_m37710_regs[0x0d] = 0; + m_m37710_regs[0x10] = 0; + m_m37710_regs[0x11] = 0; + m_m37710_regs[0x14] = 0; - cpustate->m37710_regs[0x1e] &= 7; // A-D control - cpustate->m37710_regs[0x1f] |= 3; // A-D sweep + m_m37710_regs[0x1e] &= 7; // A-D control + m_m37710_regs[0x1f] |= 3; // A-D sweep // UART - cpustate->m37710_regs[0x30] = 0; - cpustate->m37710_regs[0x38] = 0; - cpustate->m37710_regs[0x34] = (cpustate->m37710_regs[0x34] & 0xf0) | 8; - cpustate->m37710_regs[0x3c] = (cpustate->m37710_regs[0x3c] & 0xf0) | 8; - cpustate->m37710_regs[0x35] = 2; - cpustate->m37710_regs[0x3d] = 2; - cpustate->m37710_regs[0x37]&= 1; - cpustate->m37710_regs[0x3f]&= 1; + m_m37710_regs[0x30] = 0; + m_m37710_regs[0x38] = 0; + m_m37710_regs[0x34] = (m_m37710_regs[0x34] & 0xf0) | 8; + m_m37710_regs[0x3c] = (m_m37710_regs[0x3c] & 0xf0) | 8; + m_m37710_regs[0x35] = 2; + m_m37710_regs[0x3d] = 2; + m_m37710_regs[0x37]&= 1; + m_m37710_regs[0x3f]&= 1; // timer - cpustate->m37710_regs[0x40] = 0; - cpustate->m37710_regs[0x42]&= 0x1f; - cpustate->m37710_regs[0x44] = 0; + m_m37710_regs[0x40] = 0; + m_m37710_regs[0x42]&= 0x1f; + m_m37710_regs[0x44] = 0; for (i = 0x56; i < 0x5e; i++) - cpustate->m37710_regs[i] = 0; + m_m37710_regs[i] = 0; - cpustate->m37710_regs[0x5e] = 0; // processor mode - cpustate->m37710_regs[0x61]&= 1; // watchdog frequency + m_m37710_regs[0x5e] = 0; // processor mode + m_m37710_regs[0x61]&= 1; // watchdog frequency // interrupt control - cpustate->m37710_regs[0x7d] &= 0x3f; - cpustate->m37710_regs[0x7e] &= 0x3f; - cpustate->m37710_regs[0x7f] &= 0x3f; + m_m37710_regs[0x7d] &= 0x3f; + m_m37710_regs[0x7e] &= 0x3f; + m_m37710_regs[0x7f] &= 0x3f; for (i = 0x70; i < 0x7d; i++) - cpustate->m37710_regs[i] &= 0xf; + m_m37710_regs[i] &= 0xf; /* Clear IPL, m, x, D and set I */ - cpustate->ipl = 0; + m_ipl = 0; FLAG_M = MFLAG_CLEAR; FLAG_X = XFLAG_CLEAR; FLAG_D = DFLAG_CLEAR; @@ -880,334 +873,549 @@ static CPU_RESET( m37710 ) REG_BB = REG_BA & 0xff00; REG_BA &= 0xff; /* Set the function tables to emulation mode */ - m37710i_set_execution_mode(cpustate, EXECUTION_MODE_M0X0); + m37710i_set_execution_mode(EXECUTION_MODE_M0X0); /* Fetch the reset vector */ REG_PC = m37710_read_8(0xfffe) | (m37710_read_8(0xffff)<<8); m37710i_jumping(REG_PB | REG_PC); } -/* Exit and clean up */ -static CPU_EXIT( m37710 ) -{ - /* nothing to do yet */ -} - /* Execute some instructions */ -static CPU_EXECUTE( m37710 ) +void m37710_cpu_device::execute_run() { - m37710i_cpu_struct *m37710 = get_safe_token(device); + m37710i_update_irqs(); - m37710i_update_irqs(m37710); - - int clocks = m37710->ICount; - m37710->ICount = clocks - m37710->execute(m37710, m37710->ICount); + int clocks = m_ICount; + m_ICount = clocks - (this->*m_execute)(m_ICount); } /* Set the Program Counter */ -static void m37710_set_pc(m37710i_cpu_struct *cpustate, unsigned val) +void m37710_cpu_device::m37710_set_pc(unsigned val) { REG_PC = MAKE_UINT_16(val); m37710_jumping(REG_PB | REG_PC); } /* Get the current Stack Pointer */ -static unsigned m37710_get_sp(m37710i_cpu_struct *cpustate) +unsigned m37710_cpu_device::m37710_get_sp() { return REG_S; } /* Set the Stack Pointer */ -static void m37710_set_sp(m37710i_cpu_struct *cpustate, unsigned val) +void m37710_cpu_device::m37710_set_sp(unsigned val) { REG_S = MAKE_UINT_16(val); } /* Get a register */ -static unsigned m37710_get_reg(m37710i_cpu_struct *cpustate, int regnum) +unsigned m37710_cpu_device::m37710_get_reg(int regnum) { - return FTABLE_GET_REG(cpustate, regnum); + return (this->*m_get_reg)(regnum); } /* Set a register */ -static void m37710_set_reg(m37710i_cpu_struct *cpustate, int regnum, unsigned value) +void m37710_cpu_device::m37710_set_reg(int regnum, unsigned value) { - FTABLE_SET_REG(cpustate, regnum, value); + (this->*m_set_reg)(regnum, value); } /* Set an interrupt line */ -static void m37710_set_irq_line(m37710i_cpu_struct *cpustate, int line, int state) +void m37710_cpu_device::m37710_set_irq_line(int line, int state) { - FTABLE_SET_LINE(cpustate, line, state); + (this->*m_set_line)(line, state); } -/* Set the callback that is called when servicing an interrupt */ -#ifdef UNUSED_FUNCTION -void m37710_set_irq_callback(device_irq_acknowledge_callback callback) -{ - INT_ACK = callback; -} -#endif - /* Disassemble an instruction */ #include "m7700ds.h" -static CPU_DISASSEMBLE( m37710 ) -{ - m37710i_cpu_struct *cpustate = get_safe_token(device); +CPU_DISASSEMBLE( m37710 ) +{ + return m7700_disassemble(buffer, (pc&0xffff), pc>>16, oprom, 0, 0); +} + + +offs_t m37710_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ return m7700_disassemble(buffer, (pc&0xffff), pc>>16, oprom, FLAG_M, FLAG_X); } -static void m37710_restore_state(m37710i_cpu_struct *cpustate) + +void m37710_cpu_device::m37710_restore_state() { // restore proper function pointers - m37710i_set_execution_mode(cpustate, (FLAG_M>>4) | (FLAG_X>>4)); + m37710i_set_execution_mode((FLAG_M>>4) | (FLAG_X>>4)); // make sure the memory system can keep up m37710i_jumping(REG_PB | REG_PC); } -static CPU_INIT( m37710 ) +void m37710_cpu_device::device_start() { - m37710i_cpu_struct *cpustate = get_safe_token(device); - int i; + m_a = 0; + m_b = 0; + m_ba = 0; + m_bb = 0; + m_x = 0; + m_y = 0; + m_xh = 0; + m_yh = 0; + m_s = 0; + m_pc = 0; + m_ppc = 0; + m_pb = 0; + m_db = 0; + m_d = 0; + m_flag_e = 0; + m_flag_m = 0; + m_flag_x = 0; + m_flag_n = 0; + m_flag_v = 0; + m_flag_d = 0; + m_flag_i = 0; + m_flag_z = 0; + m_flag_c = 0; + m_line_irq = 0; + m_ipl = 0; + m_ir = 0; + m_im = 0; + m_im2 = 0; + m_im3 = 0; + m_im4 = 0; + m_irq_delay = 0; + m_irq_level = 0; + m_stopped = 0; + memset(m_m37710_regs, 0, sizeof(m_m37710_regs)); - memset(cpustate, 0, sizeof(*cpustate)); + m_program = &space(AS_PROGRAM); + m_io = &space(AS_IO); - INT_ACK = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->io = &device->space(AS_IO); + m_ICount = 0; - cpustate->ICount = 0; + m_source = 0; + m_destination = 0; - cpustate->source = 0; - cpustate->destination = 0; - - for (i = 0; i < 8; i++) - cpustate->timers[i] = device->machine().scheduler().timer_alloc(FUNC(m37710_timer_cb), cpustate); - - device->save_item(NAME(cpustate->a)); - device->save_item(NAME(cpustate->b)); - device->save_item(NAME(cpustate->ba)); - device->save_item(NAME(cpustate->bb)); - device->save_item(NAME(cpustate->x)); - device->save_item(NAME(cpustate->y)); - device->save_item(NAME(cpustate->xh)); - device->save_item(NAME(cpustate->yh)); - device->save_item(NAME(cpustate->s)); - device->save_item(NAME(cpustate->pc)); - device->save_item(NAME(cpustate->ppc)); - device->save_item(NAME(cpustate->pb)); - device->save_item(NAME(cpustate->db)); - device->save_item(NAME(cpustate->d)); - device->save_item(NAME(cpustate->flag_e)); - device->save_item(NAME(cpustate->flag_m)); - device->save_item(NAME(cpustate->flag_x)); - device->save_item(NAME(cpustate->flag_n)); - device->save_item(NAME(cpustate->flag_v)); - device->save_item(NAME(cpustate->flag_d)); - device->save_item(NAME(cpustate->flag_i)); - device->save_item(NAME(cpustate->flag_z)); - device->save_item(NAME(cpustate->flag_c)); - device->save_item(NAME(cpustate->line_irq)); - device->save_item(NAME(cpustate->ipl)); - device->save_item(NAME(cpustate->ir)); - device->save_item(NAME(cpustate->im)); - device->save_item(NAME(cpustate->im2)); - device->save_item(NAME(cpustate->im3)); - device->save_item(NAME(cpustate->im4)); - device->save_item(NAME(cpustate->irq_delay)); - device->save_item(NAME(cpustate->irq_level)); - device->save_item(NAME(cpustate->stopped)); - device->save_item(NAME(cpustate->m37710_regs)); - device->save_item(NAME(cpustate->reload[0])); - device->save_item(NAME(cpustate->reload[1])); - device->save_item(NAME(cpustate->reload[2])); - device->save_item(NAME(cpustate->reload[3])); - device->save_item(NAME(cpustate->reload[4])); - device->save_item(NAME(cpustate->reload[5])); - device->save_item(NAME(cpustate->reload[6])); - device->save_item(NAME(cpustate->reload[7])); - - device->machine().save().register_postload(save_prepost_delegate(FUNC(m37710_restore_state), cpustate)); -} - -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( m37710 ) -{ - m37710i_cpu_struct *cpustate = get_safe_token(device); - - switch (state) + for (int i = 0; i < 8; i++) { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M37710_LINE_ADC: m37710_set_irq_line(cpustate, M37710_LINE_ADC, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ0: m37710_set_irq_line(cpustate, M37710_LINE_IRQ0, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ1: m37710_set_irq_line(cpustate, M37710_LINE_IRQ1, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ2: m37710_set_irq_line(cpustate, M37710_LINE_IRQ2, info->i); break; - - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA0TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA1TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA2TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA3TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA4TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB0TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB1TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB2TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break; - - case CPUINFO_INT_PC: REG_PB = info->i & 0xff0000; m37710_set_pc(cpustate, info->i & 0xffff); break; - case CPUINFO_INT_SP: m37710_set_sp(cpustate, info->i); break; - - case CPUINFO_INT_REGISTER + M37710_PC: m37710_set_reg(cpustate, M37710_PC, info->i); break; - case CPUINFO_INT_REGISTER + M37710_S: m37710_set_reg(cpustate, M37710_S, info->i); break; - case CPUINFO_INT_REGISTER + M37710_P: m37710_set_reg(cpustate, M37710_P, info->i&0xff); cpustate->ipl = (info->i>>8)&0xff; break; - case CPUINFO_INT_REGISTER + M37710_A: m37710_set_reg(cpustate, M37710_A, info->i); break; - case CPUINFO_INT_REGISTER + M37710_X: m37710_set_reg(cpustate, M37710_X, info->i); break; - case CPUINFO_INT_REGISTER + M37710_Y: m37710_set_reg(cpustate, M37710_Y, info->i); break; - case CPUINFO_INT_REGISTER + M37710_PB: m37710_set_reg(cpustate, M37710_PB, info->i); break; - case CPUINFO_INT_REGISTER + M37710_DB: m37710_set_reg(cpustate, M37710_DB, info->i); break; - case CPUINFO_INT_REGISTER + M37710_D: m37710_set_reg(cpustate, M37710_D, info->i); break; - case CPUINFO_INT_REGISTER + M37710_E: m37710_set_reg(cpustate, M37710_E, info->i); break; - case CPUINFO_INT_REGISTER + M37710_NMI_STATE: m37710_set_reg(cpustate, M37710_NMI_STATE, info->i); break; - case CPUINFO_INT_REGISTER + M37710_IRQ_STATE: m37710_set_reg(cpustate, M37710_IRQ_STATE, info->i); break; + m_timers[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m37710_cpu_device::m37710_timer_cb), this)); + m_reload[i] = attotime::never; } + + save_item(NAME(m_a)); + save_item(NAME(m_b)); + save_item(NAME(m_ba)); + save_item(NAME(m_bb)); + save_item(NAME(m_x)); + save_item(NAME(m_y)); + save_item(NAME(m_xh)); + save_item(NAME(m_yh)); + save_item(NAME(m_s)); + save_item(NAME(m_pc)); + save_item(NAME(m_ppc)); + save_item(NAME(m_pb)); + save_item(NAME(m_db)); + save_item(NAME(m_d)); + save_item(NAME(m_flag_e)); + save_item(NAME(m_flag_m)); + save_item(NAME(m_flag_x)); + save_item(NAME(m_flag_n)); + save_item(NAME(m_flag_v)); + save_item(NAME(m_flag_d)); + save_item(NAME(m_flag_i)); + save_item(NAME(m_flag_z)); + save_item(NAME(m_flag_c)); + save_item(NAME(m_line_irq)); + save_item(NAME(m_ipl)); + save_item(NAME(m_ir)); + save_item(NAME(m_im)); + save_item(NAME(m_im2)); + save_item(NAME(m_im3)); + save_item(NAME(m_im4)); + save_item(NAME(m_irq_delay)); + save_item(NAME(m_irq_level)); + save_item(NAME(m_stopped)); + save_item(NAME(m_m37710_regs)); + save_item(NAME(m_reload[0])); + save_item(NAME(m_reload[1])); + save_item(NAME(m_reload[2])); + save_item(NAME(m_reload[3])); + save_item(NAME(m_reload[4])); + save_item(NAME(m_reload[5])); + save_item(NAME(m_reload[6])); + save_item(NAME(m_reload[7])); + + machine().save().register_postload(save_prepost_delegate(save_prepost_delegate(FUNC(m37710_cpu_device::m37710_restore_state), this))); + + state_add( M37710_PC, "PC", m_pc).formatstr("%04X"); + state_add( M37710_PB, "PB", m_debugger_pb).callimport().callexport().formatstr("%02X"); + state_add( M37710_DB, "DB", m_debugger_db).callimport().callexport().formatstr("%02X"); + state_add( M37710_D, "D", m_d).formatstr("%04X"); + state_add( M37710_S, "S", m_s).formatstr("%04X"); + state_add( M37710_P, "P", m_debugger_p).callimport().callexport().formatstr("%04X"); + state_add( M37710_E, "E", m_flag_e).formatstr("%01X"); + state_add( M37710_A, "A", m_debugger_a).callimport().callexport().formatstr("%04X"); + state_add( M37710_B, "B", m_debugger_b).callimport().callexport().formatstr("%04X"); + state_add( M37710_X, "X", m_x).formatstr("%04X"); + state_add( M37710_Y, "Y", m_y).formatstr("%04X"); + state_add( M37710_IRQ_STATE, "IRQ", m_line_irq).formatstr("%01X"); + + state_add( STATE_GENPC, "GENPC", m_debugger_pc ).callimport().callexport().noshow(); + state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_p ).formatstr("%8s").noshow(); + + m_icountptr = &m_ICount; } -// On-board RAM and peripherals -static ADDRESS_MAP_START( m37710_internal_map, AS_PROGRAM, 16, legacy_cpu_device ) - AM_RANGE(0x000000, 0x00007f) AM_READWRITE_LEGACY(m37710_internal_word_r, m37710_internal_word_w) - AM_RANGE(0x000080, 0x00027f) AM_RAM -ADDRESS_MAP_END -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( m37710 ) +void m37710_cpu_device::state_import(const device_state_entry &entry) { - m37710i_cpu_struct *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) + switch (entry.index()) { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m37710i_cpu_struct); break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 6; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break; - case CPUINFO_INT_INPUT_LINES: info->i = M37710_LINE_MAX; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ0: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ1: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ2: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + M37710_LINE_RESET: info->i = 0; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = REG_PPC; break; - case CPUINFO_INT_PC: info->i = (REG_PB | REG_PC); break; - case CPUINFO_INT_SP: info->i = m37710_get_sp(cpustate); break; - - case CPUINFO_INT_REGISTER + M37710_PC: info->i = m37710_get_reg(cpustate, M37710_PC); break; - case CPUINFO_INT_REGISTER + M37710_S: info->i = m37710_get_reg(cpustate, M37710_S); break; - case CPUINFO_INT_REGISTER + M37710_P: info->i = m37710_get_reg(cpustate, M37710_P) | (cpustate->ipl<<8); break; - case CPUINFO_INT_REGISTER + M37710_A: info->i = m37710_get_reg(cpustate, M37710_A); break; - case CPUINFO_INT_REGISTER + M37710_B: info->i = m37710_get_reg(cpustate, M37710_B); break; - case CPUINFO_INT_REGISTER + M37710_X: info->i = m37710_get_reg(cpustate, M37710_X); break; - case CPUINFO_INT_REGISTER + M37710_Y: info->i = m37710_get_reg(cpustate, M37710_Y); break; - case CPUINFO_INT_REGISTER + M37710_PB: info->i = m37710_get_reg(cpustate, M37710_PB); break; - case CPUINFO_INT_REGISTER + M37710_DB: info->i = m37710_get_reg(cpustate, M37710_DB); break; - case CPUINFO_INT_REGISTER + M37710_D: info->i = m37710_get_reg(cpustate, M37710_D); break; - case CPUINFO_INT_REGISTER + M37710_E: info->i = m37710_get_reg(cpustate, M37710_E); break; - case CPUINFO_INT_REGISTER + M37710_NMI_STATE: info->i = m37710_get_reg(cpustate, M37710_NMI_STATE); break; - case CPUINFO_INT_REGISTER + M37710_IRQ_STATE: info->i = m37710_get_reg(cpustate, M37710_IRQ_STATE); break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m37710); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m37710); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m37710); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m37710); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m37710); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m37710); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->ICount; break; - - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(m37710_internal_map); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map16 = NULL; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map8 = NULL; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M37710"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "M7700"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.2"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright R. Belmont, based on G65816 by Karl Stenerud"); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - cpustate->flag_n & NFLAG_SET ? 'N':'.', - cpustate->flag_v & VFLAG_SET ? 'V':'.', - cpustate->flag_m & MFLAG_SET ? 'M':'.', - cpustate->flag_x & XFLAG_SET ? 'X':'.', - cpustate->flag_d & DFLAG_SET ? 'D':'.', - cpustate->flag_i & IFLAG_SET ? 'I':'.', - cpustate->flag_z == 0 ? 'Z':'.', - cpustate->flag_c & CFLAG_SET ? 'C':'.'); + case M37710_PB: + m37710_set_reg(M37710_PB, m_debugger_pb); break; - case CPUINFO_STR_REGISTER + M37710_PC: sprintf(info->s, "PC:%04X", cpustate->pc); break; - case CPUINFO_STR_REGISTER + M37710_PB: sprintf(info->s, "PB:%02X", cpustate->pb>>16); break; - case CPUINFO_STR_REGISTER + M37710_DB: sprintf(info->s, "DB:%02X", cpustate->db>>16); break; - case CPUINFO_STR_REGISTER + M37710_D: sprintf(info->s, "D:%04X", cpustate->d); break; - case CPUINFO_STR_REGISTER + M37710_S: sprintf(info->s, "S:%04X", cpustate->s); break; - case CPUINFO_STR_REGISTER + M37710_P: sprintf(info->s, "P:%04X", - (cpustate->flag_n&0x80) | - ((cpustate->flag_v>>1)&0x40) | - cpustate->flag_m | - cpustate->flag_x | - cpustate->flag_d | - cpustate->flag_i | - ((!cpustate->flag_z)<<1) | - ((cpustate->flag_c>>8)&1) | (cpustate->ipl<<8)); break; - case CPUINFO_STR_REGISTER + M37710_E: sprintf(info->s, "E:%d", cpustate->flag_e); break; - case CPUINFO_STR_REGISTER + M37710_A: sprintf(info->s, "A:%04X", cpustate->a | cpustate->b); break; - case CPUINFO_STR_REGISTER + M37710_B: sprintf(info->s, "B:%04X", cpustate->ba | cpustate->bb); break; - case CPUINFO_STR_REGISTER + M37710_X: sprintf(info->s, "X:%04X", cpustate->x); break; - case CPUINFO_STR_REGISTER + M37710_Y: sprintf(info->s, "Y:%04X", cpustate->y); break; - case CPUINFO_STR_REGISTER + M37710_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->line_irq); break; + case M37710_DB: + m37710_set_reg(M37710_DB, m_debugger_db); + break; + + case M37710_P: + m37710_set_reg(M37710_P, m_debugger_p&0xff); + m_ipl = (m_debugger_p>>8)&0xff; + break; + + case M37710_A: + m37710_set_reg(M37710_A, m_debugger_a); + break; + + case M37710_B: + m37710_set_reg(M37710_B, m_debugger_b); + break; + + case STATE_GENPC: + REG_PB = m_debugger_pc & 0xff0000; + m37710_set_pc(m_debugger_pc & 0xffff); + break; } } -// 37702 is identical except with an internal ROM, so just change the name -CPU_GET_INFO( m37702 ) + +void m37710_cpu_device::state_export(const device_state_entry &entry) { - switch (state) + switch (entry.index()) { - case CPUINFO_STR_NAME: strcpy(info->s, "M37702"); break; - default: CPU_GET_INFO_CALL(m37710); break; - } + case M37710_PB: + m_debugger_pb = m_pb >> 16; + break; + case M37710_DB: + m_debugger_db = m_db >> 16; + break; + + case M37710_P: + m_debugger_p = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8); + break; + + case M37710_A: + m_debugger_a = m_a | m_b; + break; + + case M37710_B: + m_debugger_b = m_ba | m_bb; + break; + + case STATE_GENPC: + m_debugger_pc = (REG_PB | REG_PC); + break; + } } -DEFINE_LEGACY_CPU_DEVICE(M37710, m37710); -DEFINE_LEGACY_CPU_DEVICE(M37702, m37702); + +void m37710_cpu_device::state_string_export(const device_state_entry &entry, astring &string) +{ + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("%c%c%c%c%c%c%c%c", + m_flag_n & NFLAG_SET ? 'N':'.', + m_flag_v & VFLAG_SET ? 'V':'.', + m_flag_m & MFLAG_SET ? 'M':'.', + m_flag_x & XFLAG_SET ? 'X':'.', + m_flag_d & DFLAG_SET ? 'D':'.', + m_flag_i & IFLAG_SET ? 'I':'.', + m_flag_z == 0 ? 'Z':'.', + m_flag_c & CFLAG_SET ? 'C':'.'); + break; + } +} + + +void m37710_cpu_device::execute_set_input(int inputnum, int state) +{ + switch( inputnum ) + { + case M37710_LINE_ADC: + case M37710_LINE_IRQ0: + case M37710_LINE_IRQ1: + case M37710_LINE_IRQ2: + m37710_set_irq_line(inputnum, state); + break; + + case M37710_LINE_TIMERA0TICK: + case M37710_LINE_TIMERA1TICK: + case M37710_LINE_TIMERA2TICK: + case M37710_LINE_TIMERA3TICK: + case M37710_LINE_TIMERA4TICK: + case M37710_LINE_TIMERB0TICK: + case M37710_LINE_TIMERB1TICK: + case M37710_LINE_TIMERB2TICK: + m37710_external_tick(inputnum - M37710_LINE_TIMERA0TICK, state); + break; + } +} + + +void m37710_cpu_device::m37710i_set_execution_mode(UINT32 mode) +{ + m_opcodes = m37710i_opcodes[mode]; + m_opcodes42 = m37710i_opcodes2[mode]; + m_opcodes89 = m37710i_opcodes3[mode]; + FTABLE_GET_REG = m37710i_get_reg[mode]; + FTABLE_SET_REG = m37710i_set_reg[mode]; + FTABLE_SET_LINE = m37710i_set_line[mode]; + m_execute = m37710i_execute[mode]; +} + + +/* ======================================================================== */ +/* ================================= MEMORY =============================== */ +/* ======================================================================== */ + +#define ADDRESS_37710(A) ((A)&0xffffff) + +UINT32 m37710_cpu_device::m37710i_read_8_normal(UINT32 address) +{ + address = ADDRESS_37710(address); + return m37710_read_8(address); +} + +UINT32 m37710_cpu_device::m37710i_read_8_immediate(UINT32 address) +{ + address = ADDRESS_37710(address); + return m37710_read_8_immediate(address); +} + +UINT32 m37710_cpu_device::m37710i_read_8_direct(UINT32 address) +{ + address = ADDRESS_37710(address); + return m37710_read_8(address); +} + +void m37710_cpu_device::m37710i_write_8_normal(UINT32 address, UINT32 value) +{ + address = ADDRESS_37710(address); + m37710_write_8(address, MAKE_UINT_8(value)); +} + +void m37710_cpu_device::m37710i_write_8_direct(UINT32 address, UINT32 value) +{ + address = ADDRESS_37710(address); + m37710_write_8(address, MAKE_UINT_8(value)); +} + +UINT32 m37710_cpu_device::m37710i_read_16_normal(UINT32 address) +{ + address = ADDRESS_37710(address); + if (address & 1) + return m37710i_read_8_normal(address) | m37710i_read_8_normal(address+1)<<8; + else + return m37710_read_16(address); +} + +UINT32 m37710_cpu_device::m37710i_read_16_immediate(UINT32 address) +{ + address = ADDRESS_37710(address); + if (address & 1) + return m37710_read_8_immediate(address) | m37710_read_8_immediate(address+1)<<8; + else + return m37710_read_16(address); +} + +UINT32 m37710_cpu_device::m37710i_read_16_direct(UINT32 address) +{ + address = ADDRESS_37710(address); + if (address & 1) + return m37710_read_8(address) | m37710_read_8((address)+1)<<8; + else + return m37710_read_16(address); +} + +void m37710_cpu_device::m37710i_write_16_normal(UINT32 address, UINT32 value) +{ + address = ADDRESS_37710(address); + if (address & 1) + { + m37710_write_8(address, value); + m37710_write_8(address+1, value>>8); + } + else + m37710_write_16(address, value); +} + +void m37710_cpu_device::m37710i_write_16_direct(UINT32 address, UINT32 value) +{ + address = ADDRESS_37710(address); + if (address & 1) + { + m37710_write_8(address, value); + m37710_write_8(address+1, value>>8); + } + else + m37710_write_16(address, value); +} + +UINT32 m37710_cpu_device::m37710i_read_24_normal(UINT32 address) +{ + return m37710i_read_16_normal(address) | + (m37710i_read_8_normal(address+2)<<16); +} + +UINT32 m37710_cpu_device::m37710i_read_24_immediate(UINT32 address) +{ + return m37710i_read_16_immediate(address) | + (m37710i_read_8_immediate(address+2)<<16); +} + +UINT32 m37710_cpu_device::m37710i_read_24_direct(UINT32 address) +{ + return m37710i_read_16_direct(address) | + (m37710i_read_8_direct(address+2)<<16); +} + + + +/* ======================================================================== */ +/* ================================= STACK ================================ */ +/* ======================================================================== */ + +UINT32 m37710_cpu_device::m37710i_pull_8() +{ + REG_S = MAKE_UINT_16(REG_S+1); + return m37710i_read_8_normal(REG_S); +} + +UINT32 m37710_cpu_device::m37710i_pull_16() +{ + UINT32 res = m37710i_pull_8(); + return res | (m37710i_pull_8() << 8); +} + +void m37710_cpu_device::m37710i_push_24(UINT32 value) +{ + m37710i_push_8(value>>16); + m37710i_push_8((value>>8)&0xff); + m37710i_push_8(value&0xff); +} + +UINT32 m37710_cpu_device::m37710i_pull_24() +{ + UINT32 res = m37710i_pull_8(); + res |= m37710i_pull_8() << 8; + return res | (m37710i_pull_8() << 16); +} + + +/* ======================================================================== */ +/* ============================ PROGRAM COUNTER =========================== */ +/* ======================================================================== */ + +void m37710_cpu_device::m37710i_jump_16(UINT32 address) +{ + REG_PC = MAKE_UINT_16(address); + m37710i_jumping(REG_PC); +} + +void m37710_cpu_device::m37710i_jump_24(UINT32 address) +{ + REG_PB = address&0xff0000; + REG_PC = MAKE_UINT_16(address); + m37710i_jumping(REG_PC); +} + +void m37710_cpu_device::m37710i_branch_8(UINT32 offset) +{ + REG_PC = MAKE_UINT_16(REG_PC + MAKE_INT_8(offset)); + m37710i_branching(REG_PC); +} + +void m37710_cpu_device::m37710i_branch_16(UINT32 offset) +{ + REG_PC = MAKE_UINT_16(REG_PC + offset); + m37710i_branching(REG_PC); +} + + +/* ======================================================================== */ +/* ============================ STATUS REGISTER =========================== */ +/* ======================================================================== */ + +void m37710_cpu_device::m37710i_set_flag_i(UINT32 value) +{ + value &= FLAGPOS_I; + if(!FLAG_I || value) + { + FLAG_I = value; + return; + } + FLAG_I = value; +} + + +void m37710_cpu_device::m37710i_set_reg_ipl(UINT32 value) +{ + m_ipl = value & 7; +} + + +/* ======================================================================== */ +/* =============================== INTERRUPTS ============================= */ +/* ======================================================================== */ + +void m37710_cpu_device::m37710i_interrupt_software(UINT32 vector) +{ + CLK(13); + m37710i_push_8(REG_PB>>16); + m37710i_push_16(REG_PC); + m37710i_push_8(m_ipl); + m37710i_push_8(m37710i_get_reg_p()); + m37710i_set_flag_i(IFLAG_SET); + REG_PB = 0; + m37710i_jump_16(m37710i_read_16_normal(vector)); +} + + +UINT32 m37710_cpu_device::EA_IMM8() {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);} +UINT32 m37710_cpu_device::EA_IMM16() {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);} +UINT32 m37710_cpu_device::EA_IMM24() {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);} +UINT32 m37710_cpu_device::EA_D() {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM());} +UINT32 m37710_cpu_device::EA_A() {return REG_DB | OPER_16_IMM();} +UINT32 m37710_cpu_device::EA_AL() {return OPER_24_IMM();} +UINT32 m37710_cpu_device::EA_DX() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_X);} +UINT32 m37710_cpu_device::EA_DY() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_Y);} +UINT32 m37710_cpu_device::EA_AX() {UINT32 tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;} +UINT32 m37710_cpu_device::EA_ALX() {return EA_AL() + REG_X;} +UINT32 m37710_cpu_device::EA_AY() {UINT32 tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;} +UINT32 m37710_cpu_device::EA_DI() {return REG_DB | OPER_16_D();} +UINT32 m37710_cpu_device::EA_DLI() {return OPER_24_D();} +UINT32 m37710_cpu_device::EA_AI() {return read_16_A(OPER_16_IMM());} +UINT32 m37710_cpu_device::EA_ALI() {return OPER_24_A();} +UINT32 m37710_cpu_device::EA_DXI() {return REG_DB | OPER_16_DX();} +UINT32 m37710_cpu_device::EA_DIY() {UINT32 tmp = REG_DB | OPER_16_D(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;} +UINT32 m37710_cpu_device::EA_DLIY() {return OPER_24_D() + REG_Y;} +UINT32 m37710_cpu_device::EA_AXI() {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM() + REG_X));} +UINT32 m37710_cpu_device::EA_S() {return MAKE_UINT_16(REG_S + OPER_8_IMM());} +UINT32 m37710_cpu_device::EA_SIY() {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM()) + REG_Y) | REG_DB;} /* ======================================================================== */ /* ============================== END OF FILE ============================= */ diff --git a/src/emu/cpu/m37710/m37710.h b/src/emu/cpu/m37710/m37710.h index a9a159d77cb..32f33a81067 100644 --- a/src/emu/cpu/m37710/m37710.h +++ b/src/emu/cpu/m37710/m37710.h @@ -1,5 +1,3 @@ -#pragma once - #ifndef __M37710_H__ #define __M37710_H__ @@ -85,8 +83,1939 @@ enum M37710_SER0_XMIT, M37710_SER1_REC, M37710_SER1_XMIT }; -DECLARE_LEGACY_CPU_DEVICE(M37710, m37710); -DECLARE_LEGACY_CPU_DEVICE(M37702, m37702); + +class m37710_cpu_device : public cpu_device +{ +public: + // construction/destruction + m37710_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + m37710_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + + DECLARE_READ16_MEMBER( m37710_internal_word_r ); + DECLARE_WRITE16_MEMBER( m37710_internal_word_w ); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 20; /* rough guess */ } + virtual UINT32 execute_input_lines() const { return M37710_LINE_MAX; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } + + // device_state_interface overrides + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 6; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + address_space_config m_program_config; + address_space_config m_io_config; + + UINT32 m_a; /* Accumulator */ + UINT32 m_b; /* holds high byte of accumulator */ + UINT32 m_ba; /* Secondary Accumulator */ + UINT32 m_bb; /* holds high byte of secondary accumulator */ + UINT32 m_x; /* Index Register X */ + UINT32 m_y; /* Index Register Y */ + UINT32 m_xh; /* holds high byte of x */ + UINT32 m_yh; /* holds high byte of y */ + UINT32 m_s; /* Stack Pointer */ + UINT32 m_pc; /* Program Counter */ + UINT32 m_ppc; /* Previous Program Counter */ + UINT32 m_pb; /* Program Bank (shifted left 16) */ + UINT32 m_db; /* Data Bank (shifted left 16) */ + UINT32 m_d; /* Direct Register */ + UINT32 m_flag_e; /* Emulation Mode Flag */ + UINT32 m_flag_m; /* Memory/Accumulator Select Flag */ + UINT32 m_flag_x; /* Index Select Flag */ + UINT32 m_flag_n; /* Negative Flag */ + UINT32 m_flag_v; /* Overflow Flag */ + UINT32 m_flag_d; /* Decimal Mode Flag */ + UINT32 m_flag_i; /* Interrupt Mask Flag */ + UINT32 m_flag_z; /* Zero Flag (inverted) */ + UINT32 m_flag_c; /* Carry Flag */ + UINT32 m_line_irq; /* Bitmask of pending IRQs */ + UINT32 m_ipl; /* Interrupt priority level (top of PSW) */ + UINT32 m_ir; /* Instruction Register */ + UINT32 m_im; /* Immediate load value */ + UINT32 m_im2; /* Immediate load target */ + UINT32 m_im3; /* Immediate load target */ + UINT32 m_im4; /* Immediate load target */ + UINT32 m_irq_delay; /* delay 1 instruction before checking irq */ + UINT32 m_irq_level; /* irq level */ + int m_ICount; /* cycle count */ + UINT32 m_source; /* temp register */ + UINT32 m_destination; /* temp register */ + address_space *m_program; + address_space *m_io; + UINT32 m_stopped; /* Sets how the CPU is stopped */ + + // on-board peripheral stuff + UINT8 m_m37710_regs[128]; + attotime m_reload[8]; + emu_timer *m_timers[8]; + + // for debugger + UINT32 m_debugger_pc; + UINT32 m_debugger_pb; + UINT32 m_debugger_db; + UINT32 m_debugger_p; + UINT32 m_debugger_a; + UINT32 m_debugger_b; + + // Statics + typedef void (m37710_cpu_device::*opcode_func)(); + typedef UINT32 (m37710_cpu_device::*get_reg_func)(int regnum); + typedef void (m37710_cpu_device::*set_reg_func)(int regnum, UINT32 val); + typedef void (m37710_cpu_device::*set_line_func)(int line, int state); + typedef int (m37710_cpu_device::*execute_func)(int cycles); + + static const int m37710_irq_levels[M37710_LINE_MAX]; + static const int m37710_irq_vectors[M37710_LINE_MAX]; + static const char *const m37710_rnames[128]; + static const char *const m37710_tnames[8]; + static const opcode_func *m37710i_opcodes[4]; + static const opcode_func *m37710i_opcodes2[4]; + static const opcode_func *m37710i_opcodes3[4]; + static const get_reg_func m37710i_get_reg[4]; + static const set_reg_func m37710i_set_reg[4]; + static const set_line_func m37710i_set_line[4]; + static const execute_func m37710i_execute[4]; + static const opcode_func m37710i_opcodes_M0X0[]; + static const opcode_func m37710i_opcodes_M0X1[]; + static const opcode_func m37710i_opcodes_M1X0[]; + static const opcode_func m37710i_opcodes_M1X1[]; + static const opcode_func m37710i_opcodes42_M0X0[]; + static const opcode_func m37710i_opcodes42_M0X1[]; + static const opcode_func m37710i_opcodes42_M1X0[]; + static const opcode_func m37710i_opcodes42_M1X1[]; + static const opcode_func m37710i_opcodes89_M0X0[]; + static const opcode_func m37710i_opcodes89_M0X1[]; + static const opcode_func m37710i_opcodes89_M1X0[]; + static const opcode_func m37710i_opcodes89_M1X1[]; + + const opcode_func *m_opcodes; /* opcodes with no prefix */ + const opcode_func *m_opcodes42; /* opcodes with 0x42 prefix */ + const opcode_func *m_opcodes89; /* opcodes with 0x89 prefix */ + get_reg_func m_get_reg; + set_reg_func m_set_reg; + set_line_func m_set_line; + execute_func m_execute; + + // Implementation + void m37710i_set_execution_mode(UINT32 mode); + TIMER_CALLBACK_MEMBER( m37710_timer_cb ); + void m37710_external_tick(int timer, int state); + void m37710_recalc_timer(int timer); + UINT8 m37710_internal_r(int offset); + void m37710_internal_w(int offset, UINT8 data); + UINT32 m37710i_get_reg_M0X0(int regnum); + UINT32 m37710i_get_reg_M0X1(int regnum); + UINT32 m37710i_get_reg_M1X0(int regnum); + UINT32 m37710i_get_reg_M1X1(int regnum); + void m37710i_set_reg_M0X0(int regnum, UINT32 val); + void m37710i_set_reg_M0X1(int regnum, UINT32 val); + void m37710i_set_reg_M1X0(int regnum, UINT32 val); + void m37710i_set_reg_M1X1(int regnum, UINT32 val); + void m37710i_set_line_M0X0(int line, int state); + void m37710i_set_line_M0X1(int line, int state); + void m37710i_set_line_M1X0(int line, int state); + void m37710i_set_line_M1X1(int line, int state); + int m37710i_execute_M0X0(int cycles); + int m37710i_execute_M0X1(int cycles); + int m37710i_execute_M1X0(int cycles); + int m37710i_execute_M1X1(int cycles); + void m37710i_push_8(UINT32 value); + void m37710i_push_16(UINT32 value); + UINT32 m37710i_get_reg_p(); + void m37710i_update_irqs(); + void m37710_set_pc(unsigned val); + unsigned m37710_get_sp(); + void m37710_set_sp(unsigned val); + unsigned m37710_get_reg(int regnum); + void m37710_set_reg(int regnum, unsigned value); + void m37710_set_irq_line(int line, int state); + void m37710_restore_state(); + UINT32 m37710i_read_8_normal(UINT32 address); + UINT32 m37710i_read_8_immediate(UINT32 address); + UINT32 m37710i_read_8_direct(UINT32 address); + void m37710i_write_8_normal(UINT32 address, UINT32 value); + void m37710i_write_8_direct(UINT32 address, UINT32 value); + UINT32 m37710i_read_16_normal(UINT32 address); + UINT32 m37710i_read_16_immediate(UINT32 address); + UINT32 m37710i_read_16_direct(UINT32 address); + void m37710i_write_16_normal(UINT32 address, UINT32 value); + void m37710i_write_16_direct(UINT32 address, UINT32 value); + UINT32 m37710i_read_24_normal(UINT32 address); + UINT32 m37710i_read_24_immediate(UINT32 address); + UINT32 m37710i_read_24_direct(UINT32 address); + UINT32 m37710i_pull_8(); + UINT32 m37710i_pull_16(); + void m37710i_push_24(UINT32 value); + UINT32 m37710i_pull_24(); + void m37710i_jump_16(UINT32 address); + void m37710i_jump_24(UINT32 address); + void m37710i_branch_8(UINT32 offset); + void m37710i_branch_16(UINT32 offset); + void m37710i_set_flag_i(UINT32 value); + void m37710i_set_reg_ipl(UINT32 value); + void m37710i_interrupt_software(UINT32 vector); + void m37710i_set_flag_m0x0(UINT32 value); + void m37710i_set_flag_m0x1(UINT32 value); + void m37710i_set_flag_m1x0(UINT32 value); + void m37710i_set_flag_m1x1(UINT32 value); + void m37710i_set_reg_p_m0x0(UINT32 value); + void m37710i_set_reg_p_m0x1(UINT32 value); + void m37710i_set_reg_p_m1x0(UINT32 value); + void m37710i_set_reg_p_m1x1(UINT32 value); + UINT32 EA_IMM8(); + UINT32 EA_IMM16(); + UINT32 EA_IMM24(); + UINT32 EA_D(); + UINT32 EA_A(); + UINT32 EA_AL(); + UINT32 EA_DX(); + UINT32 EA_DY(); + UINT32 EA_AX(); + UINT32 EA_ALX(); + UINT32 EA_AY(); + UINT32 EA_DI(); + UINT32 EA_DLI(); + UINT32 EA_AI(); + UINT32 EA_ALI(); + UINT32 EA_DXI(); + UINT32 EA_DIY(); + UINT32 EA_DLIY(); + UINT32 EA_AXI(); + UINT32 EA_S(); + UINT32 EA_SIY(); + void m37710i_00_M0X0(); + void m37710i_01_M0X0(); + void m37710i_02_M0X0(); + void m37710i_03_M0X0(); + void m37710i_04_M0X0(); + void m37710i_05_M0X0(); + void m37710i_06_M0X0(); + void m37710i_07_M0X0(); + void m37710i_08_M0X0(); + void m37710i_09_M0X0(); + void m37710i_0a_M0X0(); + void m37710i_0b_M0X0(); + void m37710i_0c_M0X0(); + void m37710i_0d_M0X0(); + void m37710i_0e_M0X0(); + void m37710i_0f_M0X0(); + void m37710i_10_M0X0(); + void m37710i_11_M0X0(); + void m37710i_12_M0X0(); + void m37710i_13_M0X0(); + void m37710i_14_M0X0(); + void m37710i_15_M0X0(); + void m37710i_16_M0X0(); + void m37710i_17_M0X0(); + void m37710i_18_M0X0(); + void m37710i_19_M0X0(); + void m37710i_1a_M0X0(); + void m37710i_1b_M0X0(); + void m37710i_1c_M0X0(); + void m37710i_1d_M0X0(); + void m37710i_1e_M0X0(); + void m37710i_1f_M0X0(); + void m37710i_20_M0X0(); + void m37710i_21_M0X0(); + void m37710i_22_M0X0(); + void m37710i_23_M0X0(); + void m37710i_24_M0X0(); + void m37710i_25_M0X0(); + void m37710i_26_M0X0(); + void m37710i_27_M0X0(); + void m37710i_28_M0X0(); + void m37710i_29_M0X0(); + void m37710i_2a_M0X0(); + void m37710i_2b_M0X0(); + void m37710i_2c_M0X0(); + void m37710i_2d_M0X0(); + void m37710i_2e_M0X0(); + void m37710i_2f_M0X0(); + void m37710i_30_M0X0(); + void m37710i_31_M0X0(); + void m37710i_32_M0X0(); + void m37710i_33_M0X0(); + void m37710i_34_M0X0(); + void m37710i_35_M0X0(); + void m37710i_36_M0X0(); + void m37710i_37_M0X0(); + void m37710i_38_M0X0(); + void m37710i_39_M0X0(); + void m37710i_3a_M0X0(); + void m37710i_3b_M0X0(); + void m37710i_3c_M0X0(); + void m37710i_3d_M0X0(); + void m37710i_3e_M0X0(); + void m37710i_3f_M0X0(); + void m37710i_40_M0X0(); + void m37710i_41_M0X0(); + void m37710i_42_M0X0(); + void m37710i_43_M0X0(); + void m37710i_44_M0X0(); + void m37710i_45_M0X0(); + void m37710i_46_M0X0(); + void m37710i_47_M0X0(); + void m37710i_48_M0X0(); + void m37710i_49_M0X0(); + void m37710i_4a_M0X0(); + void m37710i_4b_M0X0(); + void m37710i_4c_M0X0(); + void m37710i_4d_M0X0(); + void m37710i_4e_M0X0(); + void m37710i_4f_M0X0(); + void m37710i_50_M0X0(); + void m37710i_51_M0X0(); + void m37710i_52_M0X0(); + void m37710i_53_M0X0(); + void m37710i_54_M0X0(); + void m37710i_55_M0X0(); + void m37710i_56_M0X0(); + void m37710i_57_M0X0(); + void m37710i_58_M0X0(); + void m37710i_59_M0X0(); + void m37710i_5a_M0X0(); + void m37710i_5b_M0X0(); + void m37710i_5c_M0X0(); + void m37710i_5d_M0X0(); + void m37710i_5e_M0X0(); + void m37710i_5f_M0X0(); + void m37710i_60_M0X0(); + void m37710i_61_M0X0(); + void m37710i_62_M0X0(); + void m37710i_63_M0X0(); + void m37710i_64_M0X0(); + void m37710i_65_M0X0(); + void m37710i_66_M0X0(); + void m37710i_67_M0X0(); + void m37710i_68_M0X0(); + void m37710i_69_M0X0(); + void m37710i_6a_M0X0(); + void m37710i_6b_M0X0(); + void m37710i_6c_M0X0(); + void m37710i_6d_M0X0(); + void m37710i_6e_M0X0(); + void m37710i_6f_M0X0(); + void m37710i_70_M0X0(); + void m37710i_71_M0X0(); + void m37710i_72_M0X0(); + void m37710i_73_M0X0(); + void m37710i_74_M0X0(); + void m37710i_75_M0X0(); + void m37710i_76_M0X0(); + void m37710i_77_M0X0(); + void m37710i_78_M0X0(); + void m37710i_79_M0X0(); + void m37710i_7a_M0X0(); + void m37710i_7b_M0X0(); + void m37710i_7c_M0X0(); + void m37710i_7d_M0X0(); + void m37710i_7e_M0X0(); + void m37710i_7f_M0X0(); + void m37710i_80_M0X0(); + void m37710i_81_M0X0(); + void m37710i_82_M0X0(); + void m37710i_83_M0X0(); + void m37710i_84_M0X0(); + void m37710i_85_M0X0(); + void m37710i_86_M0X0(); + void m37710i_87_M0X0(); + void m37710i_88_M0X0(); + void m37710i_89_M0X0(); + void m37710i_8a_M0X0(); + void m37710i_8b_M0X0(); + void m37710i_8c_M0X0(); + void m37710i_8d_M0X0(); + void m37710i_8e_M0X0(); + void m37710i_8f_M0X0(); + void m37710i_90_M0X0(); + void m37710i_91_M0X0(); + void m37710i_92_M0X0(); + void m37710i_93_M0X0(); + void m37710i_94_M0X0(); + void m37710i_95_M0X0(); + void m37710i_96_M0X0(); + void m37710i_97_M0X0(); + void m37710i_98_M0X0(); + void m37710i_99_M0X0(); + void m37710i_9a_M0X0(); + void m37710i_9b_M0X0(); + void m37710i_9c_M0X0(); + void m37710i_9d_M0X0(); + void m37710i_9e_M0X0(); + void m37710i_9f_M0X0(); + void m37710i_a0_M0X0(); + void m37710i_a1_M0X0(); + void m37710i_a2_M0X0(); + void m37710i_a3_M0X0(); + void m37710i_a4_M0X0(); + void m37710i_a5_M0X0(); + void m37710i_a6_M0X0(); + void m37710i_a7_M0X0(); + void m37710i_a8_M0X0(); + void m37710i_a9_M0X0(); + void m37710i_aa_M0X0(); + void m37710i_ab_M0X0(); + void m37710i_ac_M0X0(); + void m37710i_ad_M0X0(); + void m37710i_ae_M0X0(); + void m37710i_af_M0X0(); + void m37710i_b0_M0X0(); + void m37710i_b1_M0X0(); + void m37710i_b2_M0X0(); + void m37710i_b3_M0X0(); + void m37710i_b4_M0X0(); + void m37710i_b5_M0X0(); + void m37710i_b6_M0X0(); + void m37710i_b7_M0X0(); + void m37710i_b8_M0X0(); + void m37710i_b9_M0X0(); + void m37710i_ba_M0X0(); + void m37710i_bb_M0X0(); + void m37710i_bc_M0X0(); + void m37710i_bd_M0X0(); + void m37710i_be_M0X0(); + void m37710i_bf_M0X0(); + void m37710i_c0_M0X0(); + void m37710i_c1_M0X0(); + void m37710i_c2_M0X0(); + void m37710i_c3_M0X0(); + void m37710i_c4_M0X0(); + void m37710i_c5_M0X0(); + void m37710i_c6_M0X0(); + void m37710i_c7_M0X0(); + void m37710i_c8_M0X0(); + void m37710i_c9_M0X0(); + void m37710i_ca_M0X0(); + void m37710i_cb_M0X0(); + void m37710i_cc_M0X0(); + void m37710i_cd_M0X0(); + void m37710i_ce_M0X0(); + void m37710i_cf_M0X0(); + void m37710i_d0_M0X0(); + void m37710i_d1_M0X0(); + void m37710i_d2_M0X0(); + void m37710i_d3_M0X0(); + void m37710i_d4_M0X0(); + void m37710i_d5_M0X0(); + void m37710i_d6_M0X0(); + void m37710i_d7_M0X0(); + void m37710i_d8_M0X0(); + void m37710i_d9_M0X0(); + void m37710i_da_M0X0(); + void m37710i_db_M0X0(); + void m37710i_dc_M0X0(); + void m37710i_dd_M0X0(); + void m37710i_de_M0X0(); + void m37710i_df_M0X0(); + void m37710i_e0_M0X0(); + void m37710i_e1_M0X0(); + void m37710i_e2_M0X0(); + void m37710i_e3_M0X0(); + void m37710i_e4_M0X0(); + void m37710i_e5_M0X0(); + void m37710i_e6_M0X0(); + void m37710i_e7_M0X0(); + void m37710i_e8_M0X0(); + void m37710i_e9_M0X0(); + void m37710i_ea_M0X0(); + void m37710i_eb_M0X0(); + void m37710i_ec_M0X0(); + void m37710i_ed_M0X0(); + void m37710i_ee_M0X0(); + void m37710i_ef_M0X0(); + void m37710i_f0_M0X0(); + void m37710i_f1_M0X0(); + void m37710i_f2_M0X0(); + void m37710i_f3_M0X0(); + void m37710i_f4_M0X0(); + void m37710i_f5_M0X0(); + void m37710i_f6_M0X0(); + void m37710i_f7_M0X0(); + void m37710i_f8_M0X0(); + void m37710i_f9_M0X0(); + void m37710i_fa_M0X0(); + void m37710i_fb_M0X0(); + void m37710i_fc_M0X0(); + void m37710i_fd_M0X0(); + void m37710i_fe_M0X0(); + void m37710i_ff_M0X0(); + void m37710i_101_M0X0(); + void m37710i_103_M0X0(); + void m37710i_105_M0X0(); + void m37710i_107_M0X0(); + void m37710i_109_M0X0(); + void m37710i_10a_M0X0(); + void m37710i_10d_M0X0(); + void m37710i_10f_M0X0(); + void m37710i_111_M0X0(); + void m37710i_112_M0X0(); + void m37710i_113_M0X0(); + void m37710i_115_M0X0(); + void m37710i_117_M0X0(); + void m37710i_119_M0X0(); + void m37710i_11a_M0X0(); + void m37710i_11b_M0X0(); + void m37710i_11d_M0X0(); + void m37710i_11f_M0X0(); + void m37710i_121_M0X0(); + void m37710i_123_M0X0(); + void m37710i_125_M0X0(); + void m37710i_127_M0X0(); + void m37710i_129_M0X0(); + void m37710i_12a_M0X0(); + void m37710i_12d_M0X0(); + void m37710i_12f_M0X0(); + void m37710i_131_M0X0(); + void m37710i_132_M0X0(); + void m37710i_133_M0X0(); + void m37710i_135_M0X0(); + void m37710i_137_M0X0(); + void m37710i_139_M0X0(); + void m37710i_13a_M0X0(); + void m37710i_13b_M0X0(); + void m37710i_13d_M0X0(); + void m37710i_13f_M0X0(); + void m37710i_141_M0X0(); + void m37710i_143_M0X0(); + void m37710i_145_M0X0(); + void m37710i_147_M0X0(); + void m37710i_148_M0X0(); + void m37710i_149_M0X0(); + void m37710i_14a_M0X0(); + void m37710i_14d_M0X0(); + void m37710i_14f_M0X0(); + void m37710i_151_M0X0(); + void m37710i_152_M0X0(); + void m37710i_153_M0X0(); + void m37710i_155_M0X0(); + void m37710i_157_M0X0(); + void m37710i_159_M0X0(); + void m37710i_15b_M0X0(); + void m37710i_15d_M0X0(); + void m37710i_15f_M0X0(); + void m37710i_161_M0X0(); + void m37710i_163_M0X0(); + void m37710i_165_M0X0(); + void m37710i_167_M0X0(); + void m37710i_168_M0X0(); + void m37710i_169_M0X0(); + void m37710i_16a_M0X0(); + void m37710i_16d_M0X0(); + void m37710i_16f_M0X0(); + void m37710i_171_M0X0(); + void m37710i_172_M0X0(); + void m37710i_173_M0X0(); + void m37710i_175_M0X0(); + void m37710i_177_M0X0(); + void m37710i_179_M0X0(); + void m37710i_17b_M0X0(); + void m37710i_17d_M0X0(); + void m37710i_17f_M0X0(); + void m37710i_181_M0X0(); + void m37710i_183_M0X0(); + void m37710i_185_M0X0(); + void m37710i_187_M0X0(); + void m37710i_18a_M0X0(); + void m37710i_18d_M0X0(); + void m37710i_18f_M0X0(); + void m37710i_191_M0X0(); + void m37710i_192_M0X0(); + void m37710i_193_M0X0(); + void m37710i_195_M0X0(); + void m37710i_197_M0X0(); + void m37710i_198_M0X0(); + void m37710i_199_M0X0(); + void m37710i_19d_M0X0(); + void m37710i_19f_M0X0(); + void m37710i_1a1_M0X0(); + void m37710i_1a3_M0X0(); + void m37710i_1a5_M0X0(); + void m37710i_1a7_M0X0(); + void m37710i_1a8_M0X0(); + void m37710i_1a9_M0X0(); + void m37710i_1aa_M0X0(); + void m37710i_1ad_M0X0(); + void m37710i_1af_M0X0(); + void m37710i_1b1_M0X0(); + void m37710i_1b2_M0X0(); + void m37710i_1b3_M0X0(); + void m37710i_1b5_M0X0(); + void m37710i_1b7_M0X0(); + void m37710i_1b9_M0X0(); + void m37710i_1bd_M0X0(); + void m37710i_1bf_M0X0(); + void m37710i_1c1_M0X0(); + void m37710i_1c3_M0X0(); + void m37710i_1c5_M0X0(); + void m37710i_1c7_M0X0(); + void m37710i_1c9_M0X0(); + void m37710i_1cd_M0X0(); + void m37710i_1cf_M0X0(); + void m37710i_1d1_M0X0(); + void m37710i_1d2_M0X0(); + void m37710i_1d3_M0X0(); + void m37710i_1d5_M0X0(); + void m37710i_1d7_M0X0(); + void m37710i_1d9_M0X0(); + void m37710i_1dd_M0X0(); + void m37710i_1df_M0X0(); + void m37710i_1e1_M0X0(); + void m37710i_1e3_M0X0(); + void m37710i_1e5_M0X0(); + void m37710i_1e7_M0X0(); + void m37710i_1e9_M0X0(); + void m37710i_1ed_M0X0(); + void m37710i_1ef_M0X0(); + void m37710i_1f1_M0X0(); + void m37710i_1f2_M0X0(); + void m37710i_1f3_M0X0(); + void m37710i_1f5_M0X0(); + void m37710i_1f7_M0X0(); + void m37710i_1f9_M0X0(); + void m37710i_1fd_M0X0(); + void m37710i_1ff_M0X0(); + void m37710i_200_M0X0(); + void m37710i_201_M0X0(); + void m37710i_203_M0X0(); + void m37710i_205_M0X0(); + void m37710i_207_M0X0(); + void m37710i_209_M0X0(); + void m37710i_20d_M0X0(); + void m37710i_20f_M0X0(); + void m37710i_211_M0X0(); + void m37710i_212_M0X0(); + void m37710i_213_M0X0(); + void m37710i_215_M0X0(); + void m37710i_217_M0X0(); + void m37710i_219_M0X0(); + void m37710i_21d_M0X0(); + void m37710i_21f_M0X0(); + void m37710i_221_M0X0(); + void m37710i_223_M0X0(); + void m37710i_225_M0X0(); + void m37710i_227_M0X0(); + void m37710i_228_M0X0(); + void m37710i_229_M0X0(); + void m37710i_22d_M0X0(); + void m37710i_22f_M0X0(); + void m37710i_231_M0X0(); + void m37710i_232_M0X0(); + void m37710i_233_M0X0(); + void m37710i_235_M0X0(); + void m37710i_237_M0X0(); + void m37710i_239_M0X0(); + void m37710i_23d_M0X0(); + void m37710i_23f_M0X0(); + void m37710i_249_M0X0(); + void m37710i_2c2_M0X0(); + void m37710i_00_M0X1(); + void m37710i_01_M0X1(); + void m37710i_02_M0X1(); + void m37710i_03_M0X1(); + void m37710i_04_M0X1(); + void m37710i_05_M0X1(); + void m37710i_06_M0X1(); + void m37710i_07_M0X1(); + void m37710i_08_M0X1(); + void m37710i_09_M0X1(); + void m37710i_0a_M0X1(); + void m37710i_0b_M0X1(); + void m37710i_0c_M0X1(); + void m37710i_0d_M0X1(); + void m37710i_0e_M0X1(); + void m37710i_0f_M0X1(); + void m37710i_10_M0X1(); + void m37710i_11_M0X1(); + void m37710i_12_M0X1(); + void m37710i_13_M0X1(); + void m37710i_14_M0X1(); + void m37710i_15_M0X1(); + void m37710i_16_M0X1(); + void m37710i_17_M0X1(); + void m37710i_18_M0X1(); + void m37710i_19_M0X1(); + void m37710i_1a_M0X1(); + void m37710i_1b_M0X1(); + void m37710i_1c_M0X1(); + void m37710i_1d_M0X1(); + void m37710i_1e_M0X1(); + void m37710i_1f_M0X1(); + void m37710i_20_M0X1(); + void m37710i_21_M0X1(); + void m37710i_22_M0X1(); + void m37710i_23_M0X1(); + void m37710i_24_M0X1(); + void m37710i_25_M0X1(); + void m37710i_26_M0X1(); + void m37710i_27_M0X1(); + void m37710i_28_M0X1(); + void m37710i_29_M0X1(); + void m37710i_2a_M0X1(); + void m37710i_2b_M0X1(); + void m37710i_2c_M0X1(); + void m37710i_2d_M0X1(); + void m37710i_2e_M0X1(); + void m37710i_2f_M0X1(); + void m37710i_30_M0X1(); + void m37710i_31_M0X1(); + void m37710i_32_M0X1(); + void m37710i_33_M0X1(); + void m37710i_34_M0X1(); + void m37710i_35_M0X1(); + void m37710i_36_M0X1(); + void m37710i_37_M0X1(); + void m37710i_38_M0X1(); + void m37710i_39_M0X1(); + void m37710i_3a_M0X1(); + void m37710i_3b_M0X1(); + void m37710i_3c_M0X1(); + void m37710i_3d_M0X1(); + void m37710i_3e_M0X1(); + void m37710i_3f_M0X1(); + void m37710i_40_M0X1(); + void m37710i_41_M0X1(); + void m37710i_42_M0X1(); + void m37710i_43_M0X1(); + void m37710i_44_M0X1(); + void m37710i_45_M0X1(); + void m37710i_46_M0X1(); + void m37710i_47_M0X1(); + void m37710i_48_M0X1(); + void m37710i_49_M0X1(); + void m37710i_4a_M0X1(); + void m37710i_4b_M0X1(); + void m37710i_4c_M0X1(); + void m37710i_4d_M0X1(); + void m37710i_4e_M0X1(); + void m37710i_4f_M0X1(); + void m37710i_50_M0X1(); + void m37710i_51_M0X1(); + void m37710i_52_M0X1(); + void m37710i_53_M0X1(); + void m37710i_54_M0X1(); + void m37710i_55_M0X1(); + void m37710i_56_M0X1(); + void m37710i_57_M0X1(); + void m37710i_58_M0X1(); + void m37710i_59_M0X1(); + void m37710i_5a_M0X1(); + void m37710i_5b_M0X1(); + void m37710i_5c_M0X1(); + void m37710i_5d_M0X1(); + void m37710i_5e_M0X1(); + void m37710i_5f_M0X1(); + void m37710i_60_M0X1(); + void m37710i_61_M0X1(); + void m37710i_62_M0X1(); + void m37710i_63_M0X1(); + void m37710i_64_M0X1(); + void m37710i_65_M0X1(); + void m37710i_66_M0X1(); + void m37710i_67_M0X1(); + void m37710i_68_M0X1(); + void m37710i_69_M0X1(); + void m37710i_6a_M0X1(); + void m37710i_6b_M0X1(); + void m37710i_6c_M0X1(); + void m37710i_6d_M0X1(); + void m37710i_6e_M0X1(); + void m37710i_6f_M0X1(); + void m37710i_70_M0X1(); + void m37710i_71_M0X1(); + void m37710i_72_M0X1(); + void m37710i_73_M0X1(); + void m37710i_74_M0X1(); + void m37710i_75_M0X1(); + void m37710i_76_M0X1(); + void m37710i_77_M0X1(); + void m37710i_78_M0X1(); + void m37710i_79_M0X1(); + void m37710i_7a_M0X1(); + void m37710i_7b_M0X1(); + void m37710i_7c_M0X1(); + void m37710i_7d_M0X1(); + void m37710i_7e_M0X1(); + void m37710i_7f_M0X1(); + void m37710i_80_M0X1(); + void m37710i_81_M0X1(); + void m37710i_82_M0X1(); + void m37710i_83_M0X1(); + void m37710i_84_M0X1(); + void m37710i_85_M0X1(); + void m37710i_86_M0X1(); + void m37710i_87_M0X1(); + void m37710i_88_M0X1(); + void m37710i_89_M0X1(); + void m37710i_8a_M0X1(); + void m37710i_8b_M0X1(); + void m37710i_8c_M0X1(); + void m37710i_8d_M0X1(); + void m37710i_8e_M0X1(); + void m37710i_8f_M0X1(); + void m37710i_90_M0X1(); + void m37710i_91_M0X1(); + void m37710i_92_M0X1(); + void m37710i_93_M0X1(); + void m37710i_94_M0X1(); + void m37710i_95_M0X1(); + void m37710i_96_M0X1(); + void m37710i_97_M0X1(); + void m37710i_98_M0X1(); + void m37710i_99_M0X1(); + void m37710i_9a_M0X1(); + void m37710i_9b_M0X1(); + void m37710i_9c_M0X1(); + void m37710i_9d_M0X1(); + void m37710i_9e_M0X1(); + void m37710i_9f_M0X1(); + void m37710i_a0_M0X1(); + void m37710i_a1_M0X1(); + void m37710i_a2_M0X1(); + void m37710i_a3_M0X1(); + void m37710i_a4_M0X1(); + void m37710i_a5_M0X1(); + void m37710i_a6_M0X1(); + void m37710i_a7_M0X1(); + void m37710i_a8_M0X1(); + void m37710i_a9_M0X1(); + void m37710i_aa_M0X1(); + void m37710i_ab_M0X1(); + void m37710i_ac_M0X1(); + void m37710i_ad_M0X1(); + void m37710i_ae_M0X1(); + void m37710i_af_M0X1(); + void m37710i_b0_M0X1(); + void m37710i_b1_M0X1(); + void m37710i_b2_M0X1(); + void m37710i_b3_M0X1(); + void m37710i_b4_M0X1(); + void m37710i_b5_M0X1(); + void m37710i_b6_M0X1(); + void m37710i_b7_M0X1(); + void m37710i_b8_M0X1(); + void m37710i_b9_M0X1(); + void m37710i_ba_M0X1(); + void m37710i_bb_M0X1(); + void m37710i_bc_M0X1(); + void m37710i_bd_M0X1(); + void m37710i_be_M0X1(); + void m37710i_bf_M0X1(); + void m37710i_c0_M0X1(); + void m37710i_c1_M0X1(); + void m37710i_c2_M0X1(); + void m37710i_c3_M0X1(); + void m37710i_c4_M0X1(); + void m37710i_c5_M0X1(); + void m37710i_c6_M0X1(); + void m37710i_c7_M0X1(); + void m37710i_c8_M0X1(); + void m37710i_c9_M0X1(); + void m37710i_ca_M0X1(); + void m37710i_cb_M0X1(); + void m37710i_cc_M0X1(); + void m37710i_cd_M0X1(); + void m37710i_ce_M0X1(); + void m37710i_cf_M0X1(); + void m37710i_d0_M0X1(); + void m37710i_d1_M0X1(); + void m37710i_d2_M0X1(); + void m37710i_d3_M0X1(); + void m37710i_d4_M0X1(); + void m37710i_d5_M0X1(); + void m37710i_d6_M0X1(); + void m37710i_d7_M0X1(); + void m37710i_d8_M0X1(); + void m37710i_d9_M0X1(); + void m37710i_da_M0X1(); + void m37710i_db_M0X1(); + void m37710i_dc_M0X1(); + void m37710i_dd_M0X1(); + void m37710i_de_M0X1(); + void m37710i_df_M0X1(); + void m37710i_e0_M0X1(); + void m37710i_e1_M0X1(); + void m37710i_e2_M0X1(); + void m37710i_e3_M0X1(); + void m37710i_e4_M0X1(); + void m37710i_e5_M0X1(); + void m37710i_e6_M0X1(); + void m37710i_e7_M0X1(); + void m37710i_e8_M0X1(); + void m37710i_e9_M0X1(); + void m37710i_ea_M0X1(); + void m37710i_eb_M0X1(); + void m37710i_ec_M0X1(); + void m37710i_ed_M0X1(); + void m37710i_ee_M0X1(); + void m37710i_ef_M0X1(); + void m37710i_f0_M0X1(); + void m37710i_f1_M0X1(); + void m37710i_f2_M0X1(); + void m37710i_f3_M0X1(); + void m37710i_f4_M0X1(); + void m37710i_f5_M0X1(); + void m37710i_f6_M0X1(); + void m37710i_f7_M0X1(); + void m37710i_f8_M0X1(); + void m37710i_f9_M0X1(); + void m37710i_fa_M0X1(); + void m37710i_fb_M0X1(); + void m37710i_fc_M0X1(); + void m37710i_fd_M0X1(); + void m37710i_fe_M0X1(); + void m37710i_ff_M0X1(); + void m37710i_101_M0X1(); + void m37710i_103_M0X1(); + void m37710i_105_M0X1(); + void m37710i_107_M0X1(); + void m37710i_109_M0X1(); + void m37710i_10a_M0X1(); + void m37710i_10d_M0X1(); + void m37710i_10f_M0X1(); + void m37710i_111_M0X1(); + void m37710i_112_M0X1(); + void m37710i_113_M0X1(); + void m37710i_115_M0X1(); + void m37710i_117_M0X1(); + void m37710i_119_M0X1(); + void m37710i_11a_M0X1(); + void m37710i_11b_M0X1(); + void m37710i_11d_M0X1(); + void m37710i_11f_M0X1(); + void m37710i_121_M0X1(); + void m37710i_123_M0X1(); + void m37710i_125_M0X1(); + void m37710i_127_M0X1(); + void m37710i_129_M0X1(); + void m37710i_12a_M0X1(); + void m37710i_12d_M0X1(); + void m37710i_12f_M0X1(); + void m37710i_131_M0X1(); + void m37710i_132_M0X1(); + void m37710i_133_M0X1(); + void m37710i_135_M0X1(); + void m37710i_137_M0X1(); + void m37710i_139_M0X1(); + void m37710i_13a_M0X1(); + void m37710i_13b_M0X1(); + void m37710i_13d_M0X1(); + void m37710i_13f_M0X1(); + void m37710i_141_M0X1(); + void m37710i_143_M0X1(); + void m37710i_145_M0X1(); + void m37710i_147_M0X1(); + void m37710i_148_M0X1(); + void m37710i_149_M0X1(); + void m37710i_14a_M0X1(); + void m37710i_14d_M0X1(); + void m37710i_14f_M0X1(); + void m37710i_151_M0X1(); + void m37710i_152_M0X1(); + void m37710i_153_M0X1(); + void m37710i_155_M0X1(); + void m37710i_157_M0X1(); + void m37710i_159_M0X1(); + void m37710i_15b_M0X1(); + void m37710i_15d_M0X1(); + void m37710i_15f_M0X1(); + void m37710i_161_M0X1(); + void m37710i_163_M0X1(); + void m37710i_165_M0X1(); + void m37710i_167_M0X1(); + void m37710i_168_M0X1(); + void m37710i_169_M0X1(); + void m37710i_16a_M0X1(); + void m37710i_16d_M0X1(); + void m37710i_16f_M0X1(); + void m37710i_171_M0X1(); + void m37710i_172_M0X1(); + void m37710i_173_M0X1(); + void m37710i_175_M0X1(); + void m37710i_177_M0X1(); + void m37710i_179_M0X1(); + void m37710i_17b_M0X1(); + void m37710i_17d_M0X1(); + void m37710i_17f_M0X1(); + void m37710i_181_M0X1(); + void m37710i_183_M0X1(); + void m37710i_185_M0X1(); + void m37710i_187_M0X1(); + void m37710i_18a_M0X1(); + void m37710i_18d_M0X1(); + void m37710i_18f_M0X1(); + void m37710i_191_M0X1(); + void m37710i_192_M0X1(); + void m37710i_193_M0X1(); + void m37710i_195_M0X1(); + void m37710i_197_M0X1(); + void m37710i_198_M0X1(); + void m37710i_199_M0X1(); + void m37710i_19d_M0X1(); + void m37710i_19f_M0X1(); + void m37710i_1a1_M0X1(); + void m37710i_1a3_M0X1(); + void m37710i_1a5_M0X1(); + void m37710i_1a7_M0X1(); + void m37710i_1a8_M0X1(); + void m37710i_1a9_M0X1(); + void m37710i_1aa_M0X1(); + void m37710i_1ad_M0X1(); + void m37710i_1af_M0X1(); + void m37710i_1b1_M0X1(); + void m37710i_1b2_M0X1(); + void m37710i_1b3_M0X1(); + void m37710i_1b5_M0X1(); + void m37710i_1b7_M0X1(); + void m37710i_1b9_M0X1(); + void m37710i_1bd_M0X1(); + void m37710i_1bf_M0X1(); + void m37710i_1c1_M0X1(); + void m37710i_1c3_M0X1(); + void m37710i_1c5_M0X1(); + void m37710i_1c7_M0X1(); + void m37710i_1c9_M0X1(); + void m37710i_1cd_M0X1(); + void m37710i_1cf_M0X1(); + void m37710i_1d1_M0X1(); + void m37710i_1d2_M0X1(); + void m37710i_1d3_M0X1(); + void m37710i_1d5_M0X1(); + void m37710i_1d7_M0X1(); + void m37710i_1d9_M0X1(); + void m37710i_1dd_M0X1(); + void m37710i_1df_M0X1(); + void m37710i_1e1_M0X1(); + void m37710i_1e3_M0X1(); + void m37710i_1e5_M0X1(); + void m37710i_1e7_M0X1(); + void m37710i_1e9_M0X1(); + void m37710i_1ed_M0X1(); + void m37710i_1ef_M0X1(); + void m37710i_1f1_M0X1(); + void m37710i_1f2_M0X1(); + void m37710i_1f3_M0X1(); + void m37710i_1f5_M0X1(); + void m37710i_1f7_M0X1(); + void m37710i_1f9_M0X1(); + void m37710i_1fd_M0X1(); + void m37710i_1ff_M0X1(); + void m37710i_200_M0X1(); + void m37710i_201_M0X1(); + void m37710i_203_M0X1(); + void m37710i_205_M0X1(); + void m37710i_207_M0X1(); + void m37710i_209_M0X1(); + void m37710i_20d_M0X1(); + void m37710i_20f_M0X1(); + void m37710i_211_M0X1(); + void m37710i_212_M0X1(); + void m37710i_213_M0X1(); + void m37710i_215_M0X1(); + void m37710i_217_M0X1(); + void m37710i_219_M0X1(); + void m37710i_21d_M0X1(); + void m37710i_21f_M0X1(); + void m37710i_221_M0X1(); + void m37710i_223_M0X1(); + void m37710i_225_M0X1(); + void m37710i_227_M0X1(); + void m37710i_228_M0X1(); + void m37710i_229_M0X1(); + void m37710i_22d_M0X1(); + void m37710i_22f_M0X1(); + void m37710i_231_M0X1(); + void m37710i_232_M0X1(); + void m37710i_233_M0X1(); + void m37710i_235_M0X1(); + void m37710i_237_M0X1(); + void m37710i_239_M0X1(); + void m37710i_23d_M0X1(); + void m37710i_23f_M0X1(); + void m37710i_249_M0X1(); + void m37710i_2c2_M0X1(); + void m37710i_00_M1X0(); + void m37710i_01_M1X0(); + void m37710i_02_M1X0(); + void m37710i_03_M1X0(); + void m37710i_04_M1X0(); + void m37710i_05_M1X0(); + void m37710i_06_M1X0(); + void m37710i_07_M1X0(); + void m37710i_08_M1X0(); + void m37710i_09_M1X0(); + void m37710i_0a_M1X0(); + void m37710i_0b_M1X0(); + void m37710i_0c_M1X0(); + void m37710i_0d_M1X0(); + void m37710i_0e_M1X0(); + void m37710i_0f_M1X0(); + void m37710i_10_M1X0(); + void m37710i_11_M1X0(); + void m37710i_12_M1X0(); + void m37710i_13_M1X0(); + void m37710i_14_M1X0(); + void m37710i_15_M1X0(); + void m37710i_16_M1X0(); + void m37710i_17_M1X0(); + void m37710i_18_M1X0(); + void m37710i_19_M1X0(); + void m37710i_1a_M1X0(); + void m37710i_1b_M1X0(); + void m37710i_1c_M1X0(); + void m37710i_1d_M1X0(); + void m37710i_1e_M1X0(); + void m37710i_1f_M1X0(); + void m37710i_20_M1X0(); + void m37710i_21_M1X0(); + void m37710i_22_M1X0(); + void m37710i_23_M1X0(); + void m37710i_24_M1X0(); + void m37710i_25_M1X0(); + void m37710i_26_M1X0(); + void m37710i_27_M1X0(); + void m37710i_28_M1X0(); + void m37710i_29_M1X0(); + void m37710i_2a_M1X0(); + void m37710i_2b_M1X0(); + void m37710i_2c_M1X0(); + void m37710i_2d_M1X0(); + void m37710i_2e_M1X0(); + void m37710i_2f_M1X0(); + void m37710i_30_M1X0(); + void m37710i_31_M1X0(); + void m37710i_32_M1X0(); + void m37710i_33_M1X0(); + void m37710i_34_M1X0(); + void m37710i_35_M1X0(); + void m37710i_36_M1X0(); + void m37710i_37_M1X0(); + void m37710i_38_M1X0(); + void m37710i_39_M1X0(); + void m37710i_3a_M1X0(); + void m37710i_3b_M1X0(); + void m37710i_3c_M1X0(); + void m37710i_3d_M1X0(); + void m37710i_3e_M1X0(); + void m37710i_3f_M1X0(); + void m37710i_40_M1X0(); + void m37710i_41_M1X0(); + void m37710i_42_M1X0(); + void m37710i_43_M1X0(); + void m37710i_44_M1X0(); + void m37710i_45_M1X0(); + void m37710i_46_M1X0(); + void m37710i_47_M1X0(); + void m37710i_48_M1X0(); + void m37710i_49_M1X0(); + void m37710i_4a_M1X0(); + void m37710i_4b_M1X0(); + void m37710i_4c_M1X0(); + void m37710i_4d_M1X0(); + void m37710i_4e_M1X0(); + void m37710i_4f_M1X0(); + void m37710i_50_M1X0(); + void m37710i_51_M1X0(); + void m37710i_52_M1X0(); + void m37710i_53_M1X0(); + void m37710i_54_M1X0(); + void m37710i_55_M1X0(); + void m37710i_56_M1X0(); + void m37710i_57_M1X0(); + void m37710i_58_M1X0(); + void m37710i_59_M1X0(); + void m37710i_5a_M1X0(); + void m37710i_5b_M1X0(); + void m37710i_5c_M1X0(); + void m37710i_5d_M1X0(); + void m37710i_5e_M1X0(); + void m37710i_5f_M1X0(); + void m37710i_60_M1X0(); + void m37710i_61_M1X0(); + void m37710i_62_M1X0(); + void m37710i_63_M1X0(); + void m37710i_64_M1X0(); + void m37710i_65_M1X0(); + void m37710i_66_M1X0(); + void m37710i_67_M1X0(); + void m37710i_68_M1X0(); + void m37710i_69_M1X0(); + void m37710i_6a_M1X0(); + void m37710i_6b_M1X0(); + void m37710i_6c_M1X0(); + void m37710i_6d_M1X0(); + void m37710i_6e_M1X0(); + void m37710i_6f_M1X0(); + void m37710i_70_M1X0(); + void m37710i_71_M1X0(); + void m37710i_72_M1X0(); + void m37710i_73_M1X0(); + void m37710i_74_M1X0(); + void m37710i_75_M1X0(); + void m37710i_76_M1X0(); + void m37710i_77_M1X0(); + void m37710i_78_M1X0(); + void m37710i_79_M1X0(); + void m37710i_7a_M1X0(); + void m37710i_7b_M1X0(); + void m37710i_7c_M1X0(); + void m37710i_7d_M1X0(); + void m37710i_7e_M1X0(); + void m37710i_7f_M1X0(); + void m37710i_80_M1X0(); + void m37710i_81_M1X0(); + void m37710i_82_M1X0(); + void m37710i_83_M1X0(); + void m37710i_84_M1X0(); + void m37710i_85_M1X0(); + void m37710i_86_M1X0(); + void m37710i_87_M1X0(); + void m37710i_88_M1X0(); + void m37710i_89_M1X0(); + void m37710i_8a_M1X0(); + void m37710i_8b_M1X0(); + void m37710i_8c_M1X0(); + void m37710i_8d_M1X0(); + void m37710i_8e_M1X0(); + void m37710i_8f_M1X0(); + void m37710i_90_M1X0(); + void m37710i_91_M1X0(); + void m37710i_92_M1X0(); + void m37710i_93_M1X0(); + void m37710i_94_M1X0(); + void m37710i_95_M1X0(); + void m37710i_96_M1X0(); + void m37710i_97_M1X0(); + void m37710i_98_M1X0(); + void m37710i_99_M1X0(); + void m37710i_9a_M1X0(); + void m37710i_9b_M1X0(); + void m37710i_9c_M1X0(); + void m37710i_9d_M1X0(); + void m37710i_9e_M1X0(); + void m37710i_9f_M1X0(); + void m37710i_a0_M1X0(); + void m37710i_a1_M1X0(); + void m37710i_a2_M1X0(); + void m37710i_a3_M1X0(); + void m37710i_a4_M1X0(); + void m37710i_a5_M1X0(); + void m37710i_a6_M1X0(); + void m37710i_a7_M1X0(); + void m37710i_a8_M1X0(); + void m37710i_a9_M1X0(); + void m37710i_aa_M1X0(); + void m37710i_ab_M1X0(); + void m37710i_ac_M1X0(); + void m37710i_ad_M1X0(); + void m37710i_ae_M1X0(); + void m37710i_af_M1X0(); + void m37710i_b0_M1X0(); + void m37710i_b1_M1X0(); + void m37710i_b2_M1X0(); + void m37710i_b3_M1X0(); + void m37710i_b4_M1X0(); + void m37710i_b5_M1X0(); + void m37710i_b6_M1X0(); + void m37710i_b7_M1X0(); + void m37710i_b8_M1X0(); + void m37710i_b9_M1X0(); + void m37710i_ba_M1X0(); + void m37710i_bb_M1X0(); + void m37710i_bc_M1X0(); + void m37710i_bd_M1X0(); + void m37710i_be_M1X0(); + void m37710i_bf_M1X0(); + void m37710i_c0_M1X0(); + void m37710i_c1_M1X0(); + void m37710i_c2_M1X0(); + void m37710i_c3_M1X0(); + void m37710i_c4_M1X0(); + void m37710i_c5_M1X0(); + void m37710i_c6_M1X0(); + void m37710i_c7_M1X0(); + void m37710i_c8_M1X0(); + void m37710i_c9_M1X0(); + void m37710i_ca_M1X0(); + void m37710i_cb_M1X0(); + void m37710i_cc_M1X0(); + void m37710i_cd_M1X0(); + void m37710i_ce_M1X0(); + void m37710i_cf_M1X0(); + void m37710i_d0_M1X0(); + void m37710i_d1_M1X0(); + void m37710i_d2_M1X0(); + void m37710i_d3_M1X0(); + void m37710i_d4_M1X0(); + void m37710i_d5_M1X0(); + void m37710i_d6_M1X0(); + void m37710i_d7_M1X0(); + void m37710i_d8_M1X0(); + void m37710i_d9_M1X0(); + void m37710i_da_M1X0(); + void m37710i_db_M1X0(); + void m37710i_dc_M1X0(); + void m37710i_dd_M1X0(); + void m37710i_de_M1X0(); + void m37710i_df_M1X0(); + void m37710i_e0_M1X0(); + void m37710i_e1_M1X0(); + void m37710i_e2_M1X0(); + void m37710i_e3_M1X0(); + void m37710i_e4_M1X0(); + void m37710i_e5_M1X0(); + void m37710i_e6_M1X0(); + void m37710i_e7_M1X0(); + void m37710i_e8_M1X0(); + void m37710i_e9_M1X0(); + void m37710i_ea_M1X0(); + void m37710i_eb_M1X0(); + void m37710i_ec_M1X0(); + void m37710i_ed_M1X0(); + void m37710i_ee_M1X0(); + void m37710i_ef_M1X0(); + void m37710i_f0_M1X0(); + void m37710i_f1_M1X0(); + void m37710i_f2_M1X0(); + void m37710i_f3_M1X0(); + void m37710i_f4_M1X0(); + void m37710i_f5_M1X0(); + void m37710i_f6_M1X0(); + void m37710i_f7_M1X0(); + void m37710i_f8_M1X0(); + void m37710i_f9_M1X0(); + void m37710i_fa_M1X0(); + void m37710i_fb_M1X0(); + void m37710i_fc_M1X0(); + void m37710i_fd_M1X0(); + void m37710i_fe_M1X0(); + void m37710i_ff_M1X0(); + void m37710i_101_M1X0(); + void m37710i_103_M1X0(); + void m37710i_105_M1X0(); + void m37710i_107_M1X0(); + void m37710i_109_M1X0(); + void m37710i_10a_M1X0(); + void m37710i_10d_M1X0(); + void m37710i_10f_M1X0(); + void m37710i_111_M1X0(); + void m37710i_112_M1X0(); + void m37710i_113_M1X0(); + void m37710i_115_M1X0(); + void m37710i_117_M1X0(); + void m37710i_119_M1X0(); + void m37710i_11a_M1X0(); + void m37710i_11b_M1X0(); + void m37710i_11d_M1X0(); + void m37710i_11f_M1X0(); + void m37710i_121_M1X0(); + void m37710i_123_M1X0(); + void m37710i_125_M1X0(); + void m37710i_127_M1X0(); + void m37710i_129_M1X0(); + void m37710i_12a_M1X0(); + void m37710i_12d_M1X0(); + void m37710i_12f_M1X0(); + void m37710i_131_M1X0(); + void m37710i_132_M1X0(); + void m37710i_133_M1X0(); + void m37710i_135_M1X0(); + void m37710i_137_M1X0(); + void m37710i_139_M1X0(); + void m37710i_13a_M1X0(); + void m37710i_13b_M1X0(); + void m37710i_13d_M1X0(); + void m37710i_13f_M1X0(); + void m37710i_141_M1X0(); + void m37710i_143_M1X0(); + void m37710i_145_M1X0(); + void m37710i_147_M1X0(); + void m37710i_148_M1X0(); + void m37710i_149_M1X0(); + void m37710i_14a_M1X0(); + void m37710i_14d_M1X0(); + void m37710i_14f_M1X0(); + void m37710i_151_M1X0(); + void m37710i_152_M1X0(); + void m37710i_153_M1X0(); + void m37710i_155_M1X0(); + void m37710i_157_M1X0(); + void m37710i_159_M1X0(); + void m37710i_15b_M1X0(); + void m37710i_15d_M1X0(); + void m37710i_15f_M1X0(); + void m37710i_161_M1X0(); + void m37710i_163_M1X0(); + void m37710i_165_M1X0(); + void m37710i_167_M1X0(); + void m37710i_168_M1X0(); + void m37710i_169_M1X0(); + void m37710i_16a_M1X0(); + void m37710i_16d_M1X0(); + void m37710i_16f_M1X0(); + void m37710i_171_M1X0(); + void m37710i_172_M1X0(); + void m37710i_173_M1X0(); + void m37710i_175_M1X0(); + void m37710i_177_M1X0(); + void m37710i_179_M1X0(); + void m37710i_17b_M1X0(); + void m37710i_17d_M1X0(); + void m37710i_17f_M1X0(); + void m37710i_181_M1X0(); + void m37710i_183_M1X0(); + void m37710i_185_M1X0(); + void m37710i_187_M1X0(); + void m37710i_18a_M1X0(); + void m37710i_18d_M1X0(); + void m37710i_18f_M1X0(); + void m37710i_191_M1X0(); + void m37710i_192_M1X0(); + void m37710i_193_M1X0(); + void m37710i_195_M1X0(); + void m37710i_197_M1X0(); + void m37710i_198_M1X0(); + void m37710i_199_M1X0(); + void m37710i_19d_M1X0(); + void m37710i_19f_M1X0(); + void m37710i_1a1_M1X0(); + void m37710i_1a3_M1X0(); + void m37710i_1a5_M1X0(); + void m37710i_1a7_M1X0(); + void m37710i_1a8_M1X0(); + void m37710i_1a9_M1X0(); + void m37710i_1aa_M1X0(); + void m37710i_1ad_M1X0(); + void m37710i_1af_M1X0(); + void m37710i_1b1_M1X0(); + void m37710i_1b2_M1X0(); + void m37710i_1b3_M1X0(); + void m37710i_1b5_M1X0(); + void m37710i_1b7_M1X0(); + void m37710i_1b9_M1X0(); + void m37710i_1bd_M1X0(); + void m37710i_1bf_M1X0(); + void m37710i_1c1_M1X0(); + void m37710i_1c3_M1X0(); + void m37710i_1c5_M1X0(); + void m37710i_1c7_M1X0(); + void m37710i_1c9_M1X0(); + void m37710i_1cd_M1X0(); + void m37710i_1cf_M1X0(); + void m37710i_1d1_M1X0(); + void m37710i_1d2_M1X0(); + void m37710i_1d3_M1X0(); + void m37710i_1d5_M1X0(); + void m37710i_1d7_M1X0(); + void m37710i_1d9_M1X0(); + void m37710i_1dd_M1X0(); + void m37710i_1df_M1X0(); + void m37710i_1e1_M1X0(); + void m37710i_1e3_M1X0(); + void m37710i_1e5_M1X0(); + void m37710i_1e7_M1X0(); + void m37710i_1e9_M1X0(); + void m37710i_1ed_M1X0(); + void m37710i_1ef_M1X0(); + void m37710i_1f1_M1X0(); + void m37710i_1f2_M1X0(); + void m37710i_1f3_M1X0(); + void m37710i_1f5_M1X0(); + void m37710i_1f7_M1X0(); + void m37710i_1f9_M1X0(); + void m37710i_1fd_M1X0(); + void m37710i_1ff_M1X0(); + void m37710i_200_M1X0(); + void m37710i_201_M1X0(); + void m37710i_203_M1X0(); + void m37710i_205_M1X0(); + void m37710i_207_M1X0(); + void m37710i_209_M1X0(); + void m37710i_20d_M1X0(); + void m37710i_20f_M1X0(); + void m37710i_211_M1X0(); + void m37710i_212_M1X0(); + void m37710i_213_M1X0(); + void m37710i_215_M1X0(); + void m37710i_217_M1X0(); + void m37710i_219_M1X0(); + void m37710i_21d_M1X0(); + void m37710i_21f_M1X0(); + void m37710i_221_M1X0(); + void m37710i_223_M1X0(); + void m37710i_225_M1X0(); + void m37710i_227_M1X0(); + void m37710i_228_M1X0(); + void m37710i_229_M1X0(); + void m37710i_22d_M1X0(); + void m37710i_22f_M1X0(); + void m37710i_231_M1X0(); + void m37710i_232_M1X0(); + void m37710i_233_M1X0(); + void m37710i_235_M1X0(); + void m37710i_237_M1X0(); + void m37710i_239_M1X0(); + void m37710i_23d_M1X0(); + void m37710i_23f_M1X0(); + void m37710i_249_M1X0(); + void m37710i_2c2_M1X0(); + void m37710i_00_M1X1(); + void m37710i_01_M1X1(); + void m37710i_02_M1X1(); + void m37710i_03_M1X1(); + void m37710i_04_M1X1(); + void m37710i_05_M1X1(); + void m37710i_06_M1X1(); + void m37710i_07_M1X1(); + void m37710i_08_M1X1(); + void m37710i_09_M1X1(); + void m37710i_0a_M1X1(); + void m37710i_0b_M1X1(); + void m37710i_0c_M1X1(); + void m37710i_0d_M1X1(); + void m37710i_0e_M1X1(); + void m37710i_0f_M1X1(); + void m37710i_10_M1X1(); + void m37710i_11_M1X1(); + void m37710i_12_M1X1(); + void m37710i_13_M1X1(); + void m37710i_14_M1X1(); + void m37710i_15_M1X1(); + void m37710i_16_M1X1(); + void m37710i_17_M1X1(); + void m37710i_18_M1X1(); + void m37710i_19_M1X1(); + void m37710i_1a_M1X1(); + void m37710i_1b_M1X1(); + void m37710i_1c_M1X1(); + void m37710i_1d_M1X1(); + void m37710i_1e_M1X1(); + void m37710i_1f_M1X1(); + void m37710i_20_M1X1(); + void m37710i_21_M1X1(); + void m37710i_22_M1X1(); + void m37710i_23_M1X1(); + void m37710i_24_M1X1(); + void m37710i_25_M1X1(); + void m37710i_26_M1X1(); + void m37710i_27_M1X1(); + void m37710i_28_M1X1(); + void m37710i_29_M1X1(); + void m37710i_2a_M1X1(); + void m37710i_2b_M1X1(); + void m37710i_2c_M1X1(); + void m37710i_2d_M1X1(); + void m37710i_2e_M1X1(); + void m37710i_2f_M1X1(); + void m37710i_30_M1X1(); + void m37710i_31_M1X1(); + void m37710i_32_M1X1(); + void m37710i_33_M1X1(); + void m37710i_34_M1X1(); + void m37710i_35_M1X1(); + void m37710i_36_M1X1(); + void m37710i_37_M1X1(); + void m37710i_38_M1X1(); + void m37710i_39_M1X1(); + void m37710i_3a_M1X1(); + void m37710i_3b_M1X1(); + void m37710i_3c_M1X1(); + void m37710i_3d_M1X1(); + void m37710i_3e_M1X1(); + void m37710i_3f_M1X1(); + void m37710i_40_M1X1(); + void m37710i_41_M1X1(); + void m37710i_42_M1X1(); + void m37710i_43_M1X1(); + void m37710i_44_M1X1(); + void m37710i_45_M1X1(); + void m37710i_46_M1X1(); + void m37710i_47_M1X1(); + void m37710i_48_M1X1(); + void m37710i_49_M1X1(); + void m37710i_4a_M1X1(); + void m37710i_4b_M1X1(); + void m37710i_4c_M1X1(); + void m37710i_4d_M1X1(); + void m37710i_4e_M1X1(); + void m37710i_4f_M1X1(); + void m37710i_50_M1X1(); + void m37710i_51_M1X1(); + void m37710i_52_M1X1(); + void m37710i_53_M1X1(); + void m37710i_54_M1X1(); + void m37710i_55_M1X1(); + void m37710i_56_M1X1(); + void m37710i_57_M1X1(); + void m37710i_58_M1X1(); + void m37710i_59_M1X1(); + void m37710i_5a_M1X1(); + void m37710i_5b_M1X1(); + void m37710i_5c_M1X1(); + void m37710i_5d_M1X1(); + void m37710i_5e_M1X1(); + void m37710i_5f_M1X1(); + void m37710i_60_M1X1(); + void m37710i_61_M1X1(); + void m37710i_62_M1X1(); + void m37710i_63_M1X1(); + void m37710i_64_M1X1(); + void m37710i_65_M1X1(); + void m37710i_66_M1X1(); + void m37710i_67_M1X1(); + void m37710i_68_M1X1(); + void m37710i_69_M1X1(); + void m37710i_6a_M1X1(); + void m37710i_6b_M1X1(); + void m37710i_6c_M1X1(); + void m37710i_6d_M1X1(); + void m37710i_6e_M1X1(); + void m37710i_6f_M1X1(); + void m37710i_70_M1X1(); + void m37710i_71_M1X1(); + void m37710i_72_M1X1(); + void m37710i_73_M1X1(); + void m37710i_74_M1X1(); + void m37710i_75_M1X1(); + void m37710i_76_M1X1(); + void m37710i_77_M1X1(); + void m37710i_78_M1X1(); + void m37710i_79_M1X1(); + void m37710i_7a_M1X1(); + void m37710i_7b_M1X1(); + void m37710i_7c_M1X1(); + void m37710i_7d_M1X1(); + void m37710i_7e_M1X1(); + void m37710i_7f_M1X1(); + void m37710i_80_M1X1(); + void m37710i_81_M1X1(); + void m37710i_82_M1X1(); + void m37710i_83_M1X1(); + void m37710i_84_M1X1(); + void m37710i_85_M1X1(); + void m37710i_86_M1X1(); + void m37710i_87_M1X1(); + void m37710i_88_M1X1(); + void m37710i_89_M1X1(); + void m37710i_8a_M1X1(); + void m37710i_8b_M1X1(); + void m37710i_8c_M1X1(); + void m37710i_8d_M1X1(); + void m37710i_8e_M1X1(); + void m37710i_8f_M1X1(); + void m37710i_90_M1X1(); + void m37710i_91_M1X1(); + void m37710i_92_M1X1(); + void m37710i_93_M1X1(); + void m37710i_94_M1X1(); + void m37710i_95_M1X1(); + void m37710i_96_M1X1(); + void m37710i_97_M1X1(); + void m37710i_98_M1X1(); + void m37710i_99_M1X1(); + void m37710i_9a_M1X1(); + void m37710i_9b_M1X1(); + void m37710i_9c_M1X1(); + void m37710i_9d_M1X1(); + void m37710i_9e_M1X1(); + void m37710i_9f_M1X1(); + void m37710i_a0_M1X1(); + void m37710i_a1_M1X1(); + void m37710i_a2_M1X1(); + void m37710i_a3_M1X1(); + void m37710i_a4_M1X1(); + void m37710i_a5_M1X1(); + void m37710i_a6_M1X1(); + void m37710i_a7_M1X1(); + void m37710i_a8_M1X1(); + void m37710i_a9_M1X1(); + void m37710i_aa_M1X1(); + void m37710i_ab_M1X1(); + void m37710i_ac_M1X1(); + void m37710i_ad_M1X1(); + void m37710i_ae_M1X1(); + void m37710i_af_M1X1(); + void m37710i_b0_M1X1(); + void m37710i_b1_M1X1(); + void m37710i_b2_M1X1(); + void m37710i_b3_M1X1(); + void m37710i_b4_M1X1(); + void m37710i_b5_M1X1(); + void m37710i_b6_M1X1(); + void m37710i_b7_M1X1(); + void m37710i_b8_M1X1(); + void m37710i_b9_M1X1(); + void m37710i_ba_M1X1(); + void m37710i_bb_M1X1(); + void m37710i_bc_M1X1(); + void m37710i_bd_M1X1(); + void m37710i_be_M1X1(); + void m37710i_bf_M1X1(); + void m37710i_c0_M1X1(); + void m37710i_c1_M1X1(); + void m37710i_c2_M1X1(); + void m37710i_c3_M1X1(); + void m37710i_c4_M1X1(); + void m37710i_c5_M1X1(); + void m37710i_c6_M1X1(); + void m37710i_c7_M1X1(); + void m37710i_c8_M1X1(); + void m37710i_c9_M1X1(); + void m37710i_ca_M1X1(); + void m37710i_cb_M1X1(); + void m37710i_cc_M1X1(); + void m37710i_cd_M1X1(); + void m37710i_ce_M1X1(); + void m37710i_cf_M1X1(); + void m37710i_d0_M1X1(); + void m37710i_d1_M1X1(); + void m37710i_d2_M1X1(); + void m37710i_d3_M1X1(); + void m37710i_d4_M1X1(); + void m37710i_d5_M1X1(); + void m37710i_d6_M1X1(); + void m37710i_d7_M1X1(); + void m37710i_d8_M1X1(); + void m37710i_d9_M1X1(); + void m37710i_da_M1X1(); + void m37710i_db_M1X1(); + void m37710i_dc_M1X1(); + void m37710i_dd_M1X1(); + void m37710i_de_M1X1(); + void m37710i_df_M1X1(); + void m37710i_e0_M1X1(); + void m37710i_e1_M1X1(); + void m37710i_e2_M1X1(); + void m37710i_e3_M1X1(); + void m37710i_e4_M1X1(); + void m37710i_e5_M1X1(); + void m37710i_e6_M1X1(); + void m37710i_e7_M1X1(); + void m37710i_e8_M1X1(); + void m37710i_e9_M1X1(); + void m37710i_ea_M1X1(); + void m37710i_eb_M1X1(); + void m37710i_ec_M1X1(); + void m37710i_ed_M1X1(); + void m37710i_ee_M1X1(); + void m37710i_ef_M1X1(); + void m37710i_f0_M1X1(); + void m37710i_f1_M1X1(); + void m37710i_f2_M1X1(); + void m37710i_f3_M1X1(); + void m37710i_f4_M1X1(); + void m37710i_f5_M1X1(); + void m37710i_f6_M1X1(); + void m37710i_f7_M1X1(); + void m37710i_f8_M1X1(); + void m37710i_f9_M1X1(); + void m37710i_fa_M1X1(); + void m37710i_fb_M1X1(); + void m37710i_fc_M1X1(); + void m37710i_fd_M1X1(); + void m37710i_fe_M1X1(); + void m37710i_ff_M1X1(); + void m37710i_101_M1X1(); + void m37710i_103_M1X1(); + void m37710i_105_M1X1(); + void m37710i_107_M1X1(); + void m37710i_109_M1X1(); + void m37710i_10a_M1X1(); + void m37710i_10d_M1X1(); + void m37710i_10f_M1X1(); + void m37710i_111_M1X1(); + void m37710i_112_M1X1(); + void m37710i_113_M1X1(); + void m37710i_115_M1X1(); + void m37710i_117_M1X1(); + void m37710i_119_M1X1(); + void m37710i_11a_M1X1(); + void m37710i_11b_M1X1(); + void m37710i_11d_M1X1(); + void m37710i_11f_M1X1(); + void m37710i_121_M1X1(); + void m37710i_123_M1X1(); + void m37710i_125_M1X1(); + void m37710i_127_M1X1(); + void m37710i_129_M1X1(); + void m37710i_12a_M1X1(); + void m37710i_12d_M1X1(); + void m37710i_12f_M1X1(); + void m37710i_131_M1X1(); + void m37710i_132_M1X1(); + void m37710i_133_M1X1(); + void m37710i_135_M1X1(); + void m37710i_137_M1X1(); + void m37710i_139_M1X1(); + void m37710i_13a_M1X1(); + void m37710i_13b_M1X1(); + void m37710i_13d_M1X1(); + void m37710i_13f_M1X1(); + void m37710i_141_M1X1(); + void m37710i_143_M1X1(); + void m37710i_145_M1X1(); + void m37710i_147_M1X1(); + void m37710i_148_M1X1(); + void m37710i_149_M1X1(); + void m37710i_14a_M1X1(); + void m37710i_14d_M1X1(); + void m37710i_14f_M1X1(); + void m37710i_151_M1X1(); + void m37710i_152_M1X1(); + void m37710i_153_M1X1(); + void m37710i_155_M1X1(); + void m37710i_157_M1X1(); + void m37710i_159_M1X1(); + void m37710i_15b_M1X1(); + void m37710i_15d_M1X1(); + void m37710i_15f_M1X1(); + void m37710i_161_M1X1(); + void m37710i_163_M1X1(); + void m37710i_165_M1X1(); + void m37710i_167_M1X1(); + void m37710i_168_M1X1(); + void m37710i_169_M1X1(); + void m37710i_16a_M1X1(); + void m37710i_16d_M1X1(); + void m37710i_16f_M1X1(); + void m37710i_171_M1X1(); + void m37710i_172_M1X1(); + void m37710i_173_M1X1(); + void m37710i_175_M1X1(); + void m37710i_177_M1X1(); + void m37710i_179_M1X1(); + void m37710i_17b_M1X1(); + void m37710i_17d_M1X1(); + void m37710i_17f_M1X1(); + void m37710i_181_M1X1(); + void m37710i_183_M1X1(); + void m37710i_185_M1X1(); + void m37710i_187_M1X1(); + void m37710i_18a_M1X1(); + void m37710i_18d_M1X1(); + void m37710i_18f_M1X1(); + void m37710i_191_M1X1(); + void m37710i_192_M1X1(); + void m37710i_193_M1X1(); + void m37710i_195_M1X1(); + void m37710i_197_M1X1(); + void m37710i_198_M1X1(); + void m37710i_199_M1X1(); + void m37710i_19d_M1X1(); + void m37710i_19f_M1X1(); + void m37710i_1a1_M1X1(); + void m37710i_1a3_M1X1(); + void m37710i_1a5_M1X1(); + void m37710i_1a7_M1X1(); + void m37710i_1a8_M1X1(); + void m37710i_1a9_M1X1(); + void m37710i_1aa_M1X1(); + void m37710i_1ad_M1X1(); + void m37710i_1af_M1X1(); + void m37710i_1b1_M1X1(); + void m37710i_1b2_M1X1(); + void m37710i_1b3_M1X1(); + void m37710i_1b5_M1X1(); + void m37710i_1b7_M1X1(); + void m37710i_1b9_M1X1(); + void m37710i_1bd_M1X1(); + void m37710i_1bf_M1X1(); + void m37710i_1c1_M1X1(); + void m37710i_1c3_M1X1(); + void m37710i_1c5_M1X1(); + void m37710i_1c7_M1X1(); + void m37710i_1c9_M1X1(); + void m37710i_1cd_M1X1(); + void m37710i_1cf_M1X1(); + void m37710i_1d1_M1X1(); + void m37710i_1d2_M1X1(); + void m37710i_1d3_M1X1(); + void m37710i_1d5_M1X1(); + void m37710i_1d7_M1X1(); + void m37710i_1d9_M1X1(); + void m37710i_1dd_M1X1(); + void m37710i_1df_M1X1(); + void m37710i_1e1_M1X1(); + void m37710i_1e3_M1X1(); + void m37710i_1e5_M1X1(); + void m37710i_1e7_M1X1(); + void m37710i_1e9_M1X1(); + void m37710i_1ed_M1X1(); + void m37710i_1ef_M1X1(); + void m37710i_1f1_M1X1(); + void m37710i_1f2_M1X1(); + void m37710i_1f3_M1X1(); + void m37710i_1f5_M1X1(); + void m37710i_1f7_M1X1(); + void m37710i_1f9_M1X1(); + void m37710i_1fd_M1X1(); + void m37710i_1ff_M1X1(); + void m37710i_200_M1X1(); + void m37710i_201_M1X1(); + void m37710i_203_M1X1(); + void m37710i_205_M1X1(); + void m37710i_207_M1X1(); + void m37710i_209_M1X1(); + void m37710i_20d_M1X1(); + void m37710i_20f_M1X1(); + void m37710i_211_M1X1(); + void m37710i_212_M1X1(); + void m37710i_213_M1X1(); + void m37710i_215_M1X1(); + void m37710i_217_M1X1(); + void m37710i_219_M1X1(); + void m37710i_21d_M1X1(); + void m37710i_21f_M1X1(); + void m37710i_221_M1X1(); + void m37710i_223_M1X1(); + void m37710i_225_M1X1(); + void m37710i_227_M1X1(); + void m37710i_228_M1X1(); + void m37710i_229_M1X1(); + void m37710i_22d_M1X1(); + void m37710i_22f_M1X1(); + void m37710i_231_M1X1(); + void m37710i_232_M1X1(); + void m37710i_233_M1X1(); + void m37710i_235_M1X1(); + void m37710i_237_M1X1(); + void m37710i_239_M1X1(); + void m37710i_23d_M1X1(); + void m37710i_23f_M1X1(); + void m37710i_249_M1X1(); + void m37710i_2c2_M1X1(); + +}; + + +class m37702_cpu_device : public m37710_cpu_device +{ +public: + // construction/destruction + m37702_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +extern const device_type M37710; +extern const device_type M37702; + /* ======================================================================== */ /* ============================== END OF FILE ============================= */ diff --git a/src/emu/cpu/m37710/m37710cm.h b/src/emu/cpu/m37710/m37710cm.h index a22de90f1c4..0c77df11e5c 100644 --- a/src/emu/cpu/m37710/m37710cm.h +++ b/src/emu/cpu/m37710/m37710cm.h @@ -21,12 +21,12 @@ #undef M37710_CALL_DEBUGGER -#define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(cpustate->device, x) -#define m37710_read_8(addr) cpustate->program->read_byte(addr) -#define m37710_write_8(addr,data) cpustate->program->write_byte(addr,data) -#define m37710_read_8_immediate(A) cpustate->program->read_byte(A) -#define m37710_read_16(addr) cpustate->program->read_word(addr) -#define m37710_write_16(addr,data) cpustate->program->write_word(addr,data) +#define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(this, x) +#define m37710_read_8(addr) m_program->read_byte(addr) +#define m37710_write_8(addr,data) m_program->write_byte(addr,data) +#define m37710_read_8_immediate(A) m_program->read_byte(A) +#define m37710_read_16(addr) m_program->read_word(addr) +#define m37710_write_16(addr,data) m_program->write_word(addr,data) #define m37710_jumping(A) #define m37710_branching(A) @@ -35,13 +35,6 @@ /* ================================ GENERAL =============================== */ /* ======================================================================== */ -/* This should be set to the default size of your processor (min 16 bit) */ -#undef uint -#define uint unsigned int - -#undef uint8 -#define uint8 unsigned char - #undef int8 /* Allow for architectures that don't have 8-bit sizes */ @@ -71,121 +64,50 @@ INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;} /* ================================== CPU ================================= */ /* ======================================================================== */ -/* CPU Structure */ -struct m37710i_cpu_struct -{ - uint a; /* Accumulator */ - uint b; /* holds high byte of accumulator */ - uint ba; /* Secondary Accumulator */ - uint bb; /* holds high byte of secondary accumulator */ - uint x; /* Index Register X */ - uint y; /* Index Register Y */ - uint xh; /* holds high byte of x */ - uint yh; /* holds high byte of y */ - uint s; /* Stack Pointer */ - uint pc; /* Program Counter */ - uint ppc; /* Previous Program Counter */ - uint pb; /* Program Bank (shifted left 16) */ - uint db; /* Data Bank (shifted left 16) */ - uint d; /* Direct Register */ - uint flag_e; /* Emulation Mode Flag */ - uint flag_m; /* Memory/Accumulator Select Flag */ - uint flag_x; /* Index Select Flag */ - uint flag_n; /* Negative Flag */ - uint flag_v; /* Overflow Flag */ - uint flag_d; /* Decimal Mode Flag */ - uint flag_i; /* Interrupt Mask Flag */ - uint flag_z; /* Zero Flag (inverted) */ - uint flag_c; /* Carry Flag */ - uint line_irq; /* Bitmask of pending IRQs */ - uint ipl; /* Interrupt priority level (top of PSW) */ - uint ir; /* Instruction Register */ - uint im; /* Immediate load value */ - uint im2; /* Immediate load target */ - uint im3; /* Immediate load target */ - uint im4; /* Immediate load target */ - uint irq_delay; /* delay 1 instruction before checking irq */ - uint irq_level; /* irq level */ - int ICount; /* cycle count */ - uint source; /* temp register */ - uint destination; /* temp register */ - device_irq_acknowledge_callback int_ack; - legacy_cpu_device *device; - address_space *program; - address_space *io; - uint stopped; /* Sets how the CPU is stopped */ - void (*const *opcodes)(m37710i_cpu_struct *cpustate); /* opcodes with no prefix */ - void (*const *opcodes42)(m37710i_cpu_struct *cpustate); /* opcodes with 0x42 prefix */ - void (*const *opcodes89)(m37710i_cpu_struct *cpustate); /* opcodes with 0x89 prefix */ - uint (*get_reg)(m37710i_cpu_struct *cpustate, int regnum); - void (*set_reg)(m37710i_cpu_struct *cpustate, int regnum, uint val); - void (*set_line)(m37710i_cpu_struct *cpustate, int line, int state); - int (*execute)(m37710i_cpu_struct *cpustate, int cycles); - // on-board peripheral stuff - UINT8 m37710_regs[128]; - attotime reload[8]; - emu_timer *timers[8]; -}; +extern UINT32 m37710i_adc_tbl[]; +extern UINT32 m37710i_sbc_tbl[]; -INLINE m37710i_cpu_struct *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == M37710 || - device->type() == M37702); - return (m37710i_cpu_struct *)downcast(device)->token(); -} -extern uint m37710i_adc_tbl[]; -extern uint m37710i_sbc_tbl[]; +#define REG_A m_a /* Accumulator */ +#define REG_B m_b /* Accumulator hi byte */ +#define REG_BA m_ba /* Secondary Accumulator */ +#define REG_BB m_bb /* Secondary Accumulator hi byte */ +#define REG_X m_x /* Index X Register */ +#define REG_Y m_y /* Index Y Register */ +#define REG_XH m_xh /* X high byte */ +#define REG_YH m_yh /* Y high byte */ +#define REG_S m_s /* Stack Pointer */ +#define REG_PC m_pc /* Program Counter */ +#define REG_PPC m_ppc /* Previous Program Counter */ +#define REG_PB m_pb /* Program Bank */ +#define REG_DB m_db /* Data Bank */ +#define REG_D m_d /* Direct Register */ +#define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */ +#define FLAG_X m_flag_x /* Index Select Flag */ +#define FLAG_N m_flag_n /* Negative Flag */ +#define FLAG_V m_flag_v /* Overflow Flag */ +#define FLAG_D m_flag_d /* Decimal Mode Flag */ +#define FLAG_I m_flag_i /* Interrupt Mask Flag */ +#define FLAG_Z m_flag_z /* Zero Flag (inverted) */ +#define FLAG_C m_flag_c /* Carry Flag */ +#define LINE_IRQ m_line_irq /* Status of the IRQ line */ +#define REG_IR m_ir /* Instruction Register */ +#define REG_IM m_im /* Immediate load value */ +#define REG_IM2 m_im2 /* Immediate load target */ +#define REG_IM3 m_im3 /* Immediate load target */ +#define REG_IM4 m_im4 /* Immediate load target */ +#define INT_ACK m_int_ack /* Interrupt Acknowledge function pointer */ +#define CLOCKS m_ICount /* Clock cycles remaining */ +#define IRQ_DELAY m_irq_delay /* Delay 1 instruction before checking IRQ */ +#define CPU_STOPPED m_stopped /* Stopped status of the CPU */ -extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *cpustate); -extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *cpustate); -extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *cpustate); -extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *cpustate,int regnum); -extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *cpustate,int regnum, uint val); -extern void (*const m37710i_set_line[])(m37710i_cpu_struct *cpustate,int line, int state); -extern int (*const m37710i_execute[])(m37710i_cpu_struct *cpustate, int cycles); +#define FTABLE_GET_REG m_get_reg +#define FTABLE_SET_REG m_set_reg +#define FTABLE_SET_LINE m_set_line -#define REG_A cpustate->a /* Accumulator */ -#define REG_B cpustate->b /* Accumulator hi byte */ -#define REG_BA cpustate->ba /* Secondary Accumulator */ -#define REG_BB cpustate->bb /* Secondary Accumulator hi byte */ -#define REG_X cpustate->x /* Index X Register */ -#define REG_Y cpustate->y /* Index Y Register */ -#define REG_XH cpustate->xh /* X high byte */ -#define REG_YH cpustate->yh /* Y high byte */ -#define REG_S cpustate->s /* Stack Pointer */ -#define REG_PC cpustate->pc /* Program Counter */ -#define REG_PPC cpustate->ppc /* Previous Program Counter */ -#define REG_PB cpustate->pb /* Program Bank */ -#define REG_DB cpustate->db /* Data Bank */ -#define REG_D cpustate->d /* Direct Register */ -#define FLAG_M cpustate->flag_m /* Memory/Accumulator Select Flag */ -#define FLAG_X cpustate->flag_x /* Index Select Flag */ -#define FLAG_N cpustate->flag_n /* Negative Flag */ -#define FLAG_V cpustate->flag_v /* Overflow Flag */ -#define FLAG_D cpustate->flag_d /* Decimal Mode Flag */ -#define FLAG_I cpustate->flag_i /* Interrupt Mask Flag */ -#define FLAG_Z cpustate->flag_z /* Zero Flag (inverted) */ -#define FLAG_C cpustate->flag_c /* Carry Flag */ -#define LINE_IRQ cpustate->line_irq /* Status of the IRQ line */ -#define REG_IR cpustate->ir /* Instruction Register */ -#define REG_IM cpustate->im /* Immediate load value */ -#define REG_IM2 cpustate->im2 /* Immediate load target */ -#define REG_IM3 cpustate->im3 /* Immediate load target */ -#define REG_IM4 cpustate->im4 /* Immediate load target */ -#define INT_ACK cpustate->int_ack /* Interrupt Acknowledge function pointer */ -#define CLOCKS cpustate->ICount /* Clock cycles remaining */ -#define IRQ_DELAY cpustate->irq_delay /* Delay 1 instruction before checking IRQ */ -#define CPU_STOPPED cpustate->stopped /* Stopped status of the CPU */ - -#define FTABLE_GET_REG cpustate->get_reg -#define FTABLE_SET_REG cpustate->set_reg -#define FTABLE_SET_LINE cpustate->set_line - -#define SRC cpustate->source /* Source Operand */ -#define DST cpustate->destination /* Destination Operand */ +#define SRC m_source /* Source Operand */ +#define DST m_destination /* Destination Operand */ #define STOP_LEVEL_WAI 1 #define STOP_LEVEL_STOP 2 @@ -195,16 +117,6 @@ extern int (*const m37710i_execute[])(m37710i_cpu_struct *cpustate, int cycles); #define EXECUTION_MODE_M1X0 2 #define EXECUTION_MODE_M1X1 3 -INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *cpustate, uint mode) -{ - cpustate->opcodes = m37710i_opcodes[mode]; - cpustate->opcodes42 = m37710i_opcodes2[mode]; - cpustate->opcodes89 = m37710i_opcodes3[mode]; - FTABLE_GET_REG = m37710i_get_reg[mode]; - FTABLE_SET_REG = m37710i_set_reg[mode]; - FTABLE_SET_LINE = m37710i_set_line[mode]; - cpustate->execute = m37710i_execute[mode]; -} /* ======================================================================== */ /* ================================= CLOCK ================================ */ @@ -330,8 +242,174 @@ INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *cpustate, uint mode) #define CFLAG_AS_1() ((FLAG_C>>8)&1) -/* update IRQ state (internal use only) */ -void m37710i_update_irqs(m37710i_cpu_struct *cpustate); +/* ======================================================================== */ +/* ========================== EFFECTIVE ADDRESSES ========================= */ +/* ======================================================================== */ + +/* Effective-address based memory access macros */ +#define read_8_NORM(A) m37710i_read_8_normal(A) +#define read_8_IMM(A) m37710i_read_8_immediate(A) +#define read_8_D(A) m37710i_read_8_direct(A) +#define read_8_A(A) m37710i_read_8_normal(A) +#define read_8_AL(A) m37710i_read_8_normal(A) +#define read_8_DX(A) m37710i_read_8_direct(A) +#define read_8_DY(A) m37710i_read_8_direct(A) +#define read_8_AX(A) m37710i_read_8_normal(A) +#define read_8_ALX(A) m37710i_read_8_normal(A) +#define read_8_AY(A) m37710i_read_8_normal(A) +#define read_8_DI(A) m37710i_read_8_normal(A) +#define read_8_DLI(A) m37710i_read_8_normal(A) +#define read_8_AI(A) m37710i_read_8_normal(A) +#define read_8_ALI(A) m37710i_read_8_normal(A) +#define read_8_DXI(A) m37710i_read_8_normal(A) +#define read_8_DIY(A) m37710i_read_8_normal(A) +#define read_8_DLIY(A) m37710i_read_8_normal(A) +#define read_8_AXI(A) m37710i_read_8_normal(A) +#define read_8_S(A) m37710i_read_8_normal(A) +#define read_8_SIY(A) m37710i_read_8_normal(A) + +#define read_16_NORM(A) m37710i_read_16_normal(A) +#define read_16_IMM(A) m37710i_read_16_immediate(A) +#define read_16_D(A) m37710i_read_16_direct(A) +#define read_16_A(A) m37710i_read_16_normal(A) +#define read_16_AL(A) m37710i_read_16_normal(A) +#define read_16_DX(A) m37710i_read_16_direct(A) +#define read_16_DY(A) m37710i_read_16_direct(A) +#define read_16_AX(A) m37710i_read_16_normal(A) +#define read_16_ALX(A) m37710i_read_16_normal(A) +#define read_16_AY(A) m37710i_read_16_normal(A) +#define read_16_DI(A) m37710i_read_16_normal(A) +#define read_16_DLI(A) m37710i_read_16_normal(A) +#define read_16_AI(A) m37710i_read_16_normal(A) +#define read_16_ALI(A) m37710i_read_16_normal(A) +#define read_16_DXI(A) m37710i_read_16_normal(A) +#define read_16_DIY(A) m37710i_read_16_normal(A) +#define read_16_DLIY(A) m37710i_read_16_normal(A) +#define read_16_AXI(A) m37710i_read_16_normal(A) +#define read_16_S(A) m37710i_read_16_normal(A) +#define read_16_SIY(A) m37710i_read_16_normal(A) + +#define read_24_NORM(A) m37710i_read_24_normal(A) +#define read_24_IMM(A) m37710i_read_24_immediate(A) +#define read_24_D(A) m37710i_read_24_direct(A) +#define read_24_A(A) m37710i_read_24_normal(A) +#define read_24_AL(A) m37710i_read_24_normal(A) +#define read_24_DX(A) m37710i_read_24_direct(A) +#define read_24_DY(A) m37710i_read_24_direct(A) +#define read_24_AX(A) m37710i_read_24_normal(A) +#define read_24_ALX(A) m37710i_read_24_normal(A) +#define read_24_AY(A) m37710i_read_24_normal(A) +#define read_24_DI(A) m37710i_read_24_normal(A) +#define read_24_DLI(A) m37710i_read_24_normal(A) +#define read_24_AI(A) m37710i_read_24_normal(A) +#define read_24_ALI(A) m37710i_read_24_normal(A) +#define read_24_DXI(A) m37710i_read_24_normal(A) +#define read_24_DIY(A) m37710i_read_24_normal(A) +#define read_24_DLIY(A) m37710i_read_24_normal(A) +#define read_24_AXI(A) m37710i_read_24_normal(A) +#define read_24_S(A) m37710i_read_24_normal(A) +#define read_24_SIY(A) m37710i_read_24_normal(A) + +#define write_8_NORM(A, V) m37710i_write_8_normal(A, V) +#define write_8_D(A, V) m37710i_write_8_direct(A, V) +#define write_8_A(A, V) m37710i_write_8_normal(A, V) +#define write_8_AL(A, V) m37710i_write_8_normal(A, V) +#define write_8_DX(A, V) m37710i_write_8_direct(A, V) +#define write_8_DY(A, V) m37710i_write_8_direct(A, V) +#define write_8_AX(A, V) m37710i_write_8_normal(A, V) +#define write_8_ALX(A, V) m37710i_write_8_normal(A, V) +#define write_8_AY(A, V) m37710i_write_8_normal(A, V) +#define write_8_DI(A, V) m37710i_write_8_normal(A, V) +#define write_8_DLI(A, V) m37710i_write_8_normal(A, V) +#define write_8_AI(A, V) m37710i_write_8_normal(A, V) +#define write_8_ALI(A, V) m37710i_write_8_normal(A, V) +#define write_8_DXI(A, V) m37710i_write_8_normal(A, V) +#define write_8_DIY(A, V) m37710i_write_8_normal(A, V) +#define write_8_DLIY(A, V) m37710i_write_8_normal(A, V) +#define write_8_AXI(A, V) m37710i_write_8_normal(A, V) +#define write_8_S(A, V) m37710i_write_8_normal(A, V) +#define write_8_SIY(A, V) m37710i_write_8_normal(A, V) + +#define write_16_NORM(A, V) m37710i_write_16_normal(A, V) +#define write_16_D(A, V) m37710i_write_16_direct(A, V) +#define write_16_A(A, V) m37710i_write_16_normal(A, V) +#define write_16_AL(A, V) m37710i_write_16_normal(A, V) +#define write_16_DX(A, V) m37710i_write_16_direct(A, V) +#define write_16_DY(A, V) m37710i_write_16_direct(A, V) +#define write_16_AX(A, V) m37710i_write_16_normal(A, V) +#define write_16_ALX(A, V) m37710i_write_16_normal(A, V) +#define write_16_AY(A, V) m37710i_write_16_normal(A, V) +#define write_16_DI(A, V) m37710i_write_16_normal(A, V) +#define write_16_DLI(A, V) m37710i_write_16_normal(A, V) +#define write_16_AI(A, V) m37710i_write_16_normal(A, V) +#define write_16_ALI(A, V) m37710i_write_16_normal(A, V) +#define write_16_DXI(A, V) m37710i_write_16_normal(A, V) +#define write_16_DIY(A, V) m37710i_write_16_normal(A, V) +#define write_16_DLIY(A, V) m37710i_write_16_normal(A, V) +#define write_16_AXI(A, V) m37710i_write_16_normal(A, V) +#define write_16_S(A, V) m37710i_write_16_normal(A, V) +#define write_16_SIY(A, V) m37710i_write_16_normal(A, V) + + +#define OPER_8_IMM() read_8_IMM(EA_IMM8()) +#define OPER_8_D() read_8_D(EA_D()) +#define OPER_8_A() read_8_A(EA_A()) +#define OPER_8_AL() read_8_AL(EA_AL()) +#define OPER_8_DX() read_8_DX(EA_DX()) +#define OPER_8_DY() read_8_DY(EA_DY()) +#define OPER_8_AX() read_8_AX(EA_AX()) +#define OPER_8_ALX() read_8_ALX(EA_ALX()) +#define OPER_8_AY() read_8_AY(EA_AY()) +#define OPER_8_DI() read_8_DI(EA_DI()) +#define OPER_8_DLI() read_8_DLI(EA_DLI()) +#define OPER_8_AI() read_8_AI(EA_AI()) +#define OPER_8_ALI() read_8_ALI(EA_ALI()) +#define OPER_8_DXI() read_8_DXI(EA_DXI()) +#define OPER_8_DIY() read_8_DIY(EA_DIY()) +#define OPER_8_DLIY() read_8_DLIY(EA_DLIY()) +#define OPER_8_AXI() read_8_AXI(EA_AXI()) +#define OPER_8_S() read_8_S(EA_S()) +#define OPER_8_SIY() read_8_SIY(EA_SIY()) + +#define OPER_16_IMM() read_16_IMM(EA_IMM16()) +#define OPER_16_D() read_16_D(EA_D()) +#define OPER_16_A() read_16_A(EA_A()) +#define OPER_16_AL() read_16_AL(EA_AL()) +#define OPER_16_DX() read_16_DX(EA_DX()) +#define OPER_16_DY() read_16_DY(EA_DY()) +#define OPER_16_AX() read_16_AX(EA_AX()) +#define OPER_16_ALX() read_16_ALX(EA_ALX()) +#define OPER_16_AY() read_16_AY(EA_AY()) +#define OPER_16_DI() read_16_DI(EA_DI()) +#define OPER_16_DLI() read_16_DLI(EA_DLI()) +#define OPER_16_AI() read_16_AI(EA_AI()) +#define OPER_16_ALI() read_16_ALI(EA_ALI()) +#define OPER_16_DXI() read_16_DXI(EA_DXI()) +#define OPER_16_DIY() read_16_DIY(EA_DIY()) +#define OPER_16_DLIY() read_16_DLIY(EA_DLIY()) +#define OPER_16_AXI() read_16_AXI(EA_AXI()) +#define OPER_16_S() read_16_S(EA_S()) +#define OPER_16_SIY() read_16_SIY(EA_SIY()) + +#define OPER_24_IMM() read_24_IMM(EA_IMM24()) +#define OPER_24_D() read_24_D(EA_D()) +#define OPER_24_A() read_24_A(EA_A()) +#define OPER_24_AL() read_24_AL(EA_AL()) +#define OPER_24_DX() read_24_DX(EA_DX()) +#define OPER_24_DY() read_24_DY(EA_DY()) +#define OPER_24_AX() read_24_AX(EA_AX()) +#define OPER_24_ALX() read_24_ALX(EA_ALX()) +#define OPER_24_AY() read_24_AY(EA_AY()) +#define OPER_24_DI() read_24_DI(EA_DI()) +#define OPER_24_DLI() read_24_DLI(EA_DLI()) +#define OPER_24_AI() read_24_AI(EA_AI()) +#define OPER_24_ALI() read_24_ALI(EA_ALI()) +#define OPER_24_DXI() read_24_DXI(EA_DXI()) +#define OPER_24_DIY() read_24_DIY(EA_DIY()) +#define OPER_24_DLIY() read_24_DLIY(EA_DLIY()) +#define OPER_24_AXI() read_24_AXI(EA_AXI()) +#define OPER_24_S() read_24_S(EA_S()) +#define OPER_24_SIY() read_24_SIY(EA_SIY()) /* ======================================================================== */ /* ================================== CPU ================================= */ diff --git a/src/emu/cpu/m37710/m37710op.h b/src/emu/cpu/m37710/m37710op.h index 13b6c393ca4..047baf0ad63 100644 --- a/src/emu/cpu/m37710/m37710op.h +++ b/src/emu/cpu/m37710/m37710op.h @@ -4,201 +4,31 @@ #undef FLAG_SET_M #undef FLAG_SET_X +#undef m37710i_set_flag_mx +#undef m37710i_set_reg_p #if EXECUTION_MODE == EXECUTION_MODE_M0X0 #define FLAG_SET_M 0 #define FLAG_SET_X 0 +#define m37710i_set_flag_mx m37710i_set_flag_m0x0 +#define m37710i_set_reg_p m37710i_set_reg_p_m0x0 #elif EXECUTION_MODE == EXECUTION_MODE_M0X1 #define FLAG_SET_M 0 #define FLAG_SET_X 1 +#define m37710i_set_flag_mx m37710i_set_flag_m0x1 +#define m37710i_set_reg_p m37710i_set_reg_p_m0x1 #elif EXECUTION_MODE == EXECUTION_MODE_M1X0 #define FLAG_SET_M 1 #define FLAG_SET_X 0 +#define m37710i_set_flag_mx m37710i_set_flag_m1x0 +#define m37710i_set_reg_p m37710i_set_reg_p_m1x0 #elif EXECUTION_MODE == EXECUTION_MODE_M1X1 #define FLAG_SET_M 1 #define FLAG_SET_X 1 +#define m37710i_set_flag_mx m37710i_set_flag_m1x1 +#define m37710i_set_reg_p m37710i_set_reg_p_m1x1 #endif -/* ======================================================================== */ -/* ================================= MEMORY =============================== */ -/* ======================================================================== */ - -#define ADDRESS_37710(A) ((A)&0xffffff) - -INLINE uint m37710i_read_8_normal(m37710i_cpu_struct *cpustate, uint address) -{ - address = ADDRESS_37710(address); - return m37710_read_8(address); -} - -INLINE uint m37710i_read_8_immediate(m37710i_cpu_struct *cpustate, uint address) -{ - address = ADDRESS_37710(address); - return m37710_read_8_immediate(address); -} - -INLINE uint m37710i_read_8_direct(m37710i_cpu_struct *cpustate, uint address) -{ - address = ADDRESS_37710(address); - return m37710_read_8(address); -} - -INLINE void m37710i_write_8_normal(m37710i_cpu_struct *cpustate, uint address, uint value) -{ - address = ADDRESS_37710(address); - m37710_write_8(address, MAKE_UINT_8(value)); -} - -INLINE void m37710i_write_8_direct(m37710i_cpu_struct *cpustate, uint address, uint value) -{ - address = ADDRESS_37710(address); - m37710_write_8(address, MAKE_UINT_8(value)); -} - -INLINE uint m37710i_read_16_normal(m37710i_cpu_struct *cpustate, uint address) -{ - address = ADDRESS_37710(address); - if (address & 1) - return m37710i_read_8_normal(cpustate, address) | m37710i_read_8_normal(cpustate, address+1)<<8; - else - return m37710_read_16(address); -} - -INLINE uint m37710i_read_16_immediate(m37710i_cpu_struct *cpustate, uint address) -{ - address = ADDRESS_37710(address); - if (address & 1) - return m37710_read_8_immediate(address) | m37710_read_8_immediate(address+1)<<8; - else - return m37710_read_16(address); -} - -INLINE uint m37710i_read_16_direct(m37710i_cpu_struct *cpustate, uint address) -{ - address = ADDRESS_37710(address); - if (address & 1) - return m37710_read_8(address) | m37710_read_8((address)+1)<<8; - else - return m37710_read_16(address); -} - -INLINE void m37710i_write_16_normal(m37710i_cpu_struct *cpustate, uint address, uint value) -{ - address = ADDRESS_37710(address); - if (address & 1) - { - m37710_write_8(address, value); - m37710_write_8(address+1, value>>8); - } - else - m37710_write_16(address, value); -} - -INLINE void m37710i_write_16_direct(m37710i_cpu_struct *cpustate, uint address, uint value) -{ - address = ADDRESS_37710(address); - if (address & 1) - { - m37710_write_8(address, value); - m37710_write_8(address+1, value>>8); - } - else - m37710_write_16(address, value); -} - -INLINE uint m37710i_read_24_normal(m37710i_cpu_struct *cpustate, uint address) -{ - return m37710i_read_16_normal(cpustate, address) | - (m37710i_read_8_normal(cpustate, address+2)<<16); -} - -INLINE uint m37710i_read_24_immediate(m37710i_cpu_struct *cpustate, uint address) -{ - return m37710i_read_16_immediate(cpustate, address) | - (m37710i_read_8_immediate(cpustate, address+2)<<16); -} - -INLINE uint m37710i_read_24_direct(m37710i_cpu_struct *cpustate, uint address) -{ - return m37710i_read_16_direct(cpustate, address) | - (m37710i_read_8_direct(cpustate, address+2)<<16); -} - - - -/* ======================================================================== */ -/* ================================= STACK ================================ */ -/* ======================================================================== */ - -INLINE void m37710i_push_8(m37710i_cpu_struct *cpustate, uint value) -{ - m37710i_write_8_normal(cpustate, REG_S, value); - REG_S = MAKE_UINT_16(REG_S-1); -} - -INLINE uint m37710i_pull_8(m37710i_cpu_struct *cpustate) -{ - REG_S = MAKE_UINT_16(REG_S+1); - return m37710i_read_8_normal(cpustate, REG_S); -} - -INLINE void m37710i_push_16(m37710i_cpu_struct *cpustate, uint value) -{ - m37710i_push_8(cpustate, value>>8); - m37710i_push_8(cpustate, value&0xff); -} - -INLINE uint m37710i_pull_16(m37710i_cpu_struct *cpustate) -{ - uint res = m37710i_pull_8(cpustate); - return res | (m37710i_pull_8(cpustate) << 8); -} - -INLINE void m37710i_push_24(m37710i_cpu_struct *cpustate, uint value) -{ - m37710i_push_8(cpustate, value>>16); - m37710i_push_8(cpustate, (value>>8)&0xff); - m37710i_push_8(cpustate, value&0xff); -} - -INLINE uint m37710i_pull_24(m37710i_cpu_struct *cpustate) -{ - uint res = m37710i_pull_8(cpustate); - res |= m37710i_pull_8(cpustate) << 8; - return res | (m37710i_pull_8(cpustate) << 16); -} - - -/* ======================================================================== */ -/* ============================ PROGRAM COUNTER =========================== */ -/* ======================================================================== */ - -INLINE void m37710i_jump_16(m37710i_cpu_struct *cpustate, uint address) -{ - REG_PC = MAKE_UINT_16(address); - m37710i_jumping(REG_PC); -} - -INLINE void m37710i_jump_24(m37710i_cpu_struct *cpustate, uint address) -{ - REG_PB = address&0xff0000; - REG_PC = MAKE_UINT_16(address); - m37710i_jumping(REG_PC); -} - -INLINE void m37710i_branch_8(m37710i_cpu_struct *cpustate, uint offset) -{ - REG_PC = MAKE_UINT_16(REG_PC + MAKE_INT_8(offset)); - m37710i_branching(REG_PC); -} - -INLINE void m37710i_branch_16(m37710i_cpu_struct *cpustate, uint offset) -{ - REG_PC = MAKE_UINT_16(REG_PC + offset); - m37710i_branching(REG_PC); -} - - /* ======================================================================== */ /* ============================ STATUS REGISTER =========================== */ /* ======================================================================== */ @@ -206,7 +36,7 @@ INLINE void m37710i_branch_16(m37710i_cpu_struct *cpustate, uint offset) /* note: difference from 65816. when switching to 8-bit X/Y, X and Y are *not* truncated to 8 bits! */ -INLINE void m37710i_set_flag_mx(m37710i_cpu_struct *cpustate, uint value) +void m37710_cpu_device::m37710i_set_flag_mx(UINT32 value) { #if FLAG_SET_M if(!(value & FLAGPOS_M)) @@ -246,260 +76,21 @@ INLINE void m37710i_set_flag_mx(m37710i_cpu_struct *cpustate, uint value) FLAG_X = XFLAG_SET; } #endif - m37710i_set_execution_mode(cpustate, (FLAG_M>>4) | (FLAG_X>>4)); + m37710i_set_execution_mode((FLAG_M>>4) | (FLAG_X>>4)); } -INLINE void m37710i_set_flag_i(m37710i_cpu_struct *cpustate, uint value) -{ - value &= FLAGPOS_I; - if(!FLAG_I || value) - { - FLAG_I = value; - return; - } - FLAG_I = value; -} - - - - -/* Get the Processor Status Register */ -INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate) -{ - return (FLAG_N&0x80) | - ((FLAG_V>>1)&0x40) | - FLAG_M | - FLAG_X | - FLAG_D | - FLAG_I | - ((!FLAG_Z)<<1) | - ((FLAG_C>>8)&1); -} - -INLINE void m37710i_set_reg_p(m37710i_cpu_struct *cpustate, uint value) +void m37710_cpu_device::m37710i_set_reg_p(UINT32 value) { FLAG_N = value; FLAG_V = value << 1; FLAG_D = value & FLAGPOS_D; FLAG_Z = !(value & FLAGPOS_Z); FLAG_C = value << 8; - m37710i_set_flag_mx(cpustate, value); - m37710i_set_flag_i(cpustate, value); + m37710i_set_flag_mx(value); + m37710i_set_flag_i(value); } -INLINE void m37710i_set_reg_ipl(m37710i_cpu_struct *cpustate, uint value) -{ - cpustate->ipl = value & 7; -} - -/* ======================================================================== */ -/* =============================== INTERRUPTS ============================= */ -/* ======================================================================== */ - -INLINE void m37710i_interrupt_software(m37710i_cpu_struct *cpustate, uint vector) -{ - CLK(13); - m37710i_push_8(cpustate, REG_PB>>16); - m37710i_push_16(cpustate, REG_PC); - m37710i_push_8(cpustate, cpustate->ipl); - m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); - m37710i_set_flag_i(cpustate, IFLAG_SET); - REG_PB = 0; - m37710i_jump_16(cpustate, m37710i_read_16_normal(cpustate, vector)); -} - -/* ======================================================================== */ -/* ========================== EFFECTIVE ADDRESSES ========================= */ -/* ======================================================================== */ - -/* Effective-address based memory access macros */ -#define read_8_NORM(A) m37710i_read_8_normal(cpustate, A) -#define read_8_IMM(A) m37710i_read_8_immediate(cpustate, A) -#define read_8_D(A) m37710i_read_8_direct(cpustate, A) -#define read_8_A(A) m37710i_read_8_normal(cpustate, A) -#define read_8_AL(A) m37710i_read_8_normal(cpustate, A) -#define read_8_DX(A) m37710i_read_8_direct(cpustate, A) -#define read_8_DY(A) m37710i_read_8_direct(cpustate, A) -#define read_8_AX(A) m37710i_read_8_normal(cpustate, A) -#define read_8_ALX(A) m37710i_read_8_normal(cpustate, A) -#define read_8_AY(A) m37710i_read_8_normal(cpustate, A) -#define read_8_DI(A) m37710i_read_8_normal(cpustate, A) -#define read_8_DLI(A) m37710i_read_8_normal(cpustate, A) -#define read_8_AI(A) m37710i_read_8_normal(cpustate, A) -#define read_8_ALI(A) m37710i_read_8_normal(cpustate, A) -#define read_8_DXI(A) m37710i_read_8_normal(cpustate, A) -#define read_8_DIY(A) m37710i_read_8_normal(cpustate, A) -#define read_8_DLIY(A) m37710i_read_8_normal(cpustate, A) -#define read_8_AXI(A) m37710i_read_8_normal(cpustate, A) -#define read_8_S(A) m37710i_read_8_normal(cpustate, A) -#define read_8_SIY(A) m37710i_read_8_normal(cpustate, A) - -#define read_16_NORM(A) m37710i_read_16_normal(cpustate, A) -#define read_16_IMM(A) m37710i_read_16_immediate(cpustate, A) -#define read_16_D(A) m37710i_read_16_direct(cpustate, A) -#define read_16_A(A) m37710i_read_16_normal(cpustate, A) -#define read_16_AL(A) m37710i_read_16_normal(cpustate, A) -#define read_16_DX(A) m37710i_read_16_direct(cpustate, A) -#define read_16_DY(A) m37710i_read_16_direct(cpustate, A) -#define read_16_AX(A) m37710i_read_16_normal(cpustate, A) -#define read_16_ALX(A) m37710i_read_16_normal(cpustate, A) -#define read_16_AY(A) m37710i_read_16_normal(cpustate, A) -#define read_16_DI(A) m37710i_read_16_normal(cpustate, A) -#define read_16_DLI(A) m37710i_read_16_normal(cpustate, A) -#define read_16_AI(A) m37710i_read_16_normal(cpustate, A) -#define read_16_ALI(A) m37710i_read_16_normal(cpustate, A) -#define read_16_DXI(A) m37710i_read_16_normal(cpustate, A) -#define read_16_DIY(A) m37710i_read_16_normal(cpustate, A) -#define read_16_DLIY(A) m37710i_read_16_normal(cpustate, A) -#define read_16_AXI(A) m37710i_read_16_normal(cpustate, A) -#define read_16_S(A) m37710i_read_16_normal(cpustate, A) -#define read_16_SIY(A) m37710i_read_16_normal(cpustate, A) - -#define read_24_NORM(A) m37710i_read_24_normal(cpustate, A) -#define read_24_IMM(A) m37710i_read_24_immediate(cpustate, A) -#define read_24_D(A) m37710i_read_24_direct(cpustate, A) -#define read_24_A(A) m37710i_read_24_normal(cpustate, A) -#define read_24_AL(A) m37710i_read_24_normal(cpustate, A) -#define read_24_DX(A) m37710i_read_24_direct(cpustate, A) -#define read_24_DY(A) m37710i_read_24_direct(cpustate, A) -#define read_24_AX(A) m37710i_read_24_normal(cpustate, A) -#define read_24_ALX(A) m37710i_read_24_normal(cpustate, A) -#define read_24_AY(A) m37710i_read_24_normal(cpustate, A) -#define read_24_DI(A) m37710i_read_24_normal(cpustate, A) -#define read_24_DLI(A) m37710i_read_24_normal(cpustate, A) -#define read_24_AI(A) m37710i_read_24_normal(cpustate, A) -#define read_24_ALI(A) m37710i_read_24_normal(cpustate, A) -#define read_24_DXI(A) m37710i_read_24_normal(cpustate, A) -#define read_24_DIY(A) m37710i_read_24_normal(cpustate, A) -#define read_24_DLIY(A) m37710i_read_24_normal(cpustate, A) -#define read_24_AXI(A) m37710i_read_24_normal(cpustate, A) -#define read_24_S(A) m37710i_read_24_normal(cpustate, A) -#define read_24_SIY(A) m37710i_read_24_normal(cpustate, A) - -#define write_8_NORM(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_D(A, V) m37710i_write_8_direct(cpustate, A, V) -#define write_8_A(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_AL(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_DX(A, V) m37710i_write_8_direct(cpustate, A, V) -#define write_8_DY(A, V) m37710i_write_8_direct(cpustate, A, V) -#define write_8_AX(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_ALX(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_AY(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_DI(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_DLI(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_AI(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_ALI(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_DXI(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_DIY(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_DLIY(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_AXI(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_S(A, V) m37710i_write_8_normal(cpustate, A, V) -#define write_8_SIY(A, V) m37710i_write_8_normal(cpustate, A, V) - -#define write_16_NORM(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_D(A, V) m37710i_write_16_direct(cpustate, A, V) -#define write_16_A(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_AL(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_DX(A, V) m37710i_write_16_direct(cpustate, A, V) -#define write_16_DY(A, V) m37710i_write_16_direct(cpustate, A, V) -#define write_16_AX(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_ALX(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_AY(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_DI(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_DLI(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_AI(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_ALI(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_DXI(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_DIY(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_DLIY(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_AXI(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_S(A, V) m37710i_write_16_normal(cpustate, A, V) -#define write_16_SIY(A, V) m37710i_write_16_normal(cpustate, A, V) - - -#define OPER_8_IMM(cpustate) read_8_IMM(EA_IMM8(cpustate)) -#define OPER_8_D(cpustate) read_8_D(EA_D(cpustate)) -#define OPER_8_A(cpustate) read_8_A(EA_A(cpustate)) -#define OPER_8_AL(cpustate) read_8_AL(EA_AL(cpustate)) -#define OPER_8_DX(cpustate) read_8_DX(EA_DX(cpustate)) -#define OPER_8_DY(cpustate) read_8_DY(EA_DY(cpustate)) -#define OPER_8_AX(cpustate) read_8_AX(EA_AX(cpustate)) -#define OPER_8_ALX(cpustate) read_8_ALX(EA_ALX(cpustate)) -#define OPER_8_AY(cpustate) read_8_AY(EA_AY(cpustate)) -#define OPER_8_DI(cpustate) read_8_DI(EA_DI(cpustate)) -#define OPER_8_DLI(cpustate) read_8_DLI(EA_DLI(cpustate)) -#define OPER_8_AI(cpustate) read_8_AI(EA_AI(cpustate)) -#define OPER_8_ALI(cpustate) read_8_ALI(EA_ALI(cpustate)) -#define OPER_8_DXI(cpustate) read_8_DXI(EA_DXI(cpustate)) -#define OPER_8_DIY(cpustate) read_8_DIY(EA_DIY(cpustate)) -#define OPER_8_DLIY(cpustate) read_8_DLIY(EA_DLIY(cpustate)) -#define OPER_8_AXI(cpustate) read_8_AXI(EA_AXI(cpustate)) -#define OPER_8_S(cpustate) read_8_S(EA_S(cpustate)) -#define OPER_8_SIY(cpustate) read_8_SIY(EA_SIY(cpustate)) - -#define OPER_16_IMM(cpustate) read_16_IMM(EA_IMM16(cpustate)) -#define OPER_16_D(cpustate) read_16_D(EA_D(cpustate)) -#define OPER_16_A(cpustate) read_16_A(EA_A(cpustate)) -#define OPER_16_AL(cpustate) read_16_AL(EA_AL(cpustate)) -#define OPER_16_DX(cpustate) read_16_DX(EA_DX(cpustate)) -#define OPER_16_DY(cpustate) read_16_DY(EA_DY(cpustate)) -#define OPER_16_AX(cpustate) read_16_AX(EA_AX(cpustate)) -#define OPER_16_ALX(cpustate) read_16_ALX(EA_ALX(cpustate)) -#define OPER_16_AY(cpustate) read_16_AY(EA_AY(cpustate)) -#define OPER_16_DI(cpustate) read_16_DI(EA_DI(cpustate)) -#define OPER_16_DLI(cpustate) read_16_DLI(EA_DLI(cpustate)) -#define OPER_16_AI(cpustate) read_16_AI(EA_AI(cpustate)) -#define OPER_16_ALI(cpustate) read_16_ALI(EA_ALI(cpustate)) -#define OPER_16_DXI(cpustate) read_16_DXI(EA_DXI(cpustate)) -#define OPER_16_DIY(cpustate) read_16_DIY(EA_DIY(cpustate)) -#define OPER_16_DLIY(cpustate) read_16_DLIY(EA_DLIY(cpustate)) -#define OPER_16_AXI(cpustate) read_16_AXI(EA_AXI(cpustate)) -#define OPER_16_S(cpustate) read_16_S(EA_S(cpustate)) -#define OPER_16_SIY(cpustate) read_16_SIY(EA_SIY(cpustate)) - -#define OPER_24_IMM(cpustate) read_24_IMM(EA_IMM24(cpustate)) -#define OPER_24_D(cpustate) read_24_D(EA_D(cpustate)) -#define OPER_24_A(cpustate) read_24_A(EA_A(cpustate)) -#define OPER_24_AL(cpustate) read_24_AL(EA_AL(cpustate)) -#define OPER_24_DX(cpustate) read_24_DX(EA_DX(cpustate)) -#define OPER_24_DY(cpustate) read_24_DY(EA_DY(cpustate)) -#define OPER_24_AX(cpustate) read_24_AX(EA_AX(cpustate)) -#define OPER_24_ALX(cpustate) read_24_ALX(EA_ALX(cpustate)) -#define OPER_24_AY(cpustate) read_24_AY(EA_AY(cpustate)) -#define OPER_24_DI(cpustate) read_24_DI(EA_DI(cpustate)) -#define OPER_24_DLI(cpustate) read_24_DLI(EA_DLI(cpustate)) -#define OPER_24_AI(cpustate) read_24_AI(EA_AI(cpustate)) -#define OPER_24_ALI(cpustate) read_24_ALI(EA_ALI()) -#define OPER_24_DXI(cpustate) read_24_DXI(EA_DXI(cpustate)) -#define OPER_24_DIY(cpustate) read_24_DIY(EA_DIY(cpustate)) -#define OPER_24_DLIY(cpustate) read_24_DLIY(EA_DLIY(cpustate)) -#define OPER_24_AXI(cpustate) read_24_AXI(EA_AXI(cpustate)) -#define OPER_24_S(cpustate) read_24_S(EA_S(cpustate)) -#define OPER_24_SIY(cpustate) read_24_SIY(EA_SIY(cpustate)) - -INLINE uint EA_IMM8(m37710i_cpu_struct *cpustate) {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);} -INLINE uint EA_IMM16(m37710i_cpu_struct *cpustate) {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);} -INLINE uint EA_IMM24(m37710i_cpu_struct *cpustate) {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);} -INLINE uint EA_D(m37710i_cpu_struct *cpustate) {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM(cpustate));} -INLINE uint EA_A(m37710i_cpu_struct *cpustate) {return REG_DB | OPER_16_IMM(cpustate);} -INLINE uint EA_AL(m37710i_cpu_struct *cpustate) {return OPER_24_IMM(cpustate);} -INLINE uint EA_DX(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(REG_D + OPER_8_IMM(cpustate) + REG_X);} -INLINE uint EA_DY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(REG_D + OPER_8_IMM(cpustate) + REG_Y);} -INLINE uint EA_AX(m37710i_cpu_struct *cpustate) {uint tmp = EA_A(cpustate); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;} -INLINE uint EA_ALX(m37710i_cpu_struct *cpustate) {return EA_AL(cpustate) + REG_X;} -INLINE uint EA_AY(m37710i_cpu_struct *cpustate) {uint tmp = EA_A(cpustate); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;} -INLINE uint EA_DI(m37710i_cpu_struct *cpustate) {return REG_DB | OPER_16_D(cpustate);} -INLINE uint EA_DLI(m37710i_cpu_struct *cpustate) {return OPER_24_D(cpustate);} -INLINE uint EA_AI(m37710i_cpu_struct *cpustate) {return read_16_A(OPER_16_IMM(cpustate));} -INLINE uint EA_ALI(m37710i_cpu_struct *cpustate) {return OPER_24_A(cpustate);} -INLINE uint EA_DXI(m37710i_cpu_struct *cpustate) {return REG_DB | OPER_16_DX(cpustate);} -INLINE uint EA_DIY(m37710i_cpu_struct *cpustate) {uint tmp = REG_DB | OPER_16_D(cpustate); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;} -INLINE uint EA_DLIY(m37710i_cpu_struct *cpustate) {return OPER_24_D(cpustate) + REG_Y;} -INLINE uint EA_AXI(m37710i_cpu_struct *cpustate) {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X));} -INLINE uint EA_S(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(REG_S + OPER_8_IMM(cpustate));} -INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM(cpustate)) + REG_Y) | REG_DB;} - /* ======================================================================== */ /* =========================== OPERATION MACROS =========================== */ @@ -511,86 +102,86 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #if FLAG_SET_X #define OP_PSH(MODE) \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ CLK(12); \ if (SRC&0x1) \ - { m37710i_push_8(cpustate, REG_A); CLK(2); } \ + { m37710i_push_8(REG_A); CLK(2); } \ if (SRC&0x2) \ - { m37710i_push_8(cpustate, REG_BA); CLK(2); } \ + { m37710i_push_8(REG_BA); CLK(2); } \ if (SRC&0x4) \ - { m37710i_push_8(cpustate, REG_X); CLK(2); } \ + { m37710i_push_8(REG_X); CLK(2); } \ if (SRC&0x8) \ - { m37710i_push_8(cpustate, REG_Y); CLK(2); } \ + { m37710i_push_8(REG_Y); CLK(2); } \ if (SRC&0x10) \ - { m37710i_push_16(cpustate, REG_D); CLK(2); } \ + { m37710i_push_16(REG_D); CLK(2); } \ if (SRC&0x20) \ - { m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \ + { m37710i_push_8(REG_DB>>16); CLK(1); } \ if (SRC&0x40) \ - { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ + { m37710i_push_8(REG_PB>>16); CLK(1); } \ if (SRC&0x80) \ - { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } + { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } #else // FLAG_SET_X #define OP_PSH(MODE) \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ CLK(12); \ if (SRC&0x1) \ - { m37710i_push_8(cpustate, REG_A); CLK(2); } \ + { m37710i_push_8(REG_A); CLK(2); } \ if (SRC&0x2) \ - { m37710i_push_8(cpustate, REG_BA); CLK(2); } \ + { m37710i_push_8(REG_BA); CLK(2); } \ if (SRC&0x4) \ - { m37710i_push_16(cpustate, REG_X); CLK(2); } \ + { m37710i_push_16(REG_X); CLK(2); } \ if (SRC&0x8) \ - { m37710i_push_16(cpustate, REG_Y); CLK(2); } \ + { m37710i_push_16(REG_Y); CLK(2); } \ if (SRC&0x10) \ - { m37710i_push_16(cpustate, REG_D); CLK(2); } \ + { m37710i_push_16(REG_D); CLK(2); } \ if (SRC&0x20) \ - { m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \ + { m37710i_push_8(REG_DB>>16); CLK(1); } \ if (SRC&0x40) \ - { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ + { m37710i_push_8(REG_PB>>16); CLK(1); } \ if (SRC&0x80) \ - { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } + { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } #endif // FLAG_SET_X #else // FLAG_SET_M #if FLAG_SET_X #define OP_PSH(MODE) \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ CLK(12); \ if (SRC&0x1) \ - { m37710i_push_16(cpustate, REG_A); CLK(2); } \ + { m37710i_push_16(REG_A); CLK(2); } \ if (SRC&0x2) \ - { m37710i_push_16(cpustate, REG_BA); CLK(2); } \ + { m37710i_push_16(REG_BA); CLK(2); } \ if (SRC&0x4) \ - { m37710i_push_8(cpustate, REG_X); CLK(2); } \ + { m37710i_push_8(REG_X); CLK(2); } \ if (SRC&0x8) \ - { m37710i_push_8(cpustate, REG_Y); CLK(2); } \ + { m37710i_push_8(REG_Y); CLK(2); } \ if (SRC&0x10) \ - { m37710i_push_16(cpustate, REG_D); CLK(2); } \ + { m37710i_push_16(REG_D); CLK(2); } \ if (SRC&0x20) \ - { m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \ + { m37710i_push_8(REG_DB>>16); CLK(1); } \ if (SRC&0x40) \ - { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ + { m37710i_push_8(REG_PB>>16); CLK(1); } \ if (SRC&0x80) \ - { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } + { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } #else // FLAG_SET_X #define OP_PSH(MODE) \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ CLK(12); \ if (SRC&0x1) \ - { m37710i_push_16(cpustate, REG_A); CLK(2); } \ + { m37710i_push_16(REG_A); CLK(2); } \ if (SRC&0x2) \ - { m37710i_push_16(cpustate, REG_BA); CLK(2);} \ + { m37710i_push_16(REG_BA); CLK(2);} \ if (SRC&0x4) \ - { m37710i_push_16(cpustate, REG_X); CLK(2); } \ + { m37710i_push_16(REG_X); CLK(2); } \ if (SRC&0x8) \ - { m37710i_push_16(cpustate, REG_Y); CLK(2); } \ + { m37710i_push_16(REG_Y); CLK(2); } \ if (SRC&0x10) \ - { m37710i_push_16(cpustate, REG_D); CLK(2); } \ + { m37710i_push_16(REG_D); CLK(2); } \ if (SRC&0x20) \ - { m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \ + { m37710i_push_8(REG_DB>>16); CLK(1); } \ if (SRC&0x40) \ - { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ + { m37710i_push_8(REG_PB>>16); CLK(1); } \ if (SRC&0x80) \ - { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } + { m37710i_push_8(m_ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } #endif // FLAG_SET_X #endif // FLAG_SET_M @@ -598,55 +189,55 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ /* Unusual behavior: bit 6 has no effect */ #undef OP_PUL #define OP_PUL(MODE) \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ CLK(14); \ if (SRC&0x80) \ - { m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); CLK(3); } \ + { m37710i_set_reg_p(m37710i_pull_8()); m37710i_set_reg_ipl(m37710i_pull_8()); CLK(3); } \ if (SRC&0x20) \ - { REG_DB = m37710i_pull_8(cpustate) << 16; CLK(3); } \ + { REG_DB = m37710i_pull_8() << 16; CLK(3); } \ if (SRC&0x10) \ - { REG_D = m37710i_pull_16(cpustate); CLK(4); } \ - if (m37710i_get_reg_p(cpustate) & XFLAG_SET) \ + { REG_D = m37710i_pull_16(); CLK(4); } \ + if (m37710i_get_reg_p() & XFLAG_SET) \ { \ if (SRC&0x8) \ - { REG_Y = m37710i_pull_8(cpustate); CLK(3); } \ + { REG_Y = m37710i_pull_8(); CLK(3); } \ if (SRC&0x4) \ - { REG_X = m37710i_pull_8(cpustate); CLK(3); } \ + { REG_X = m37710i_pull_8(); CLK(3); } \ } \ else \ { \ if (SRC&0x8) \ - { REG_Y = m37710i_pull_16(cpustate); CLK(3); } \ + { REG_Y = m37710i_pull_16(); CLK(3); } \ if (SRC&0x4) \ - { REG_X = m37710i_pull_16(cpustate); CLK(3); } \ + { REG_X = m37710i_pull_16(); CLK(3); } \ } \ - if (m37710i_get_reg_p(cpustate) & MFLAG_SET) \ + if (m37710i_get_reg_p() & MFLAG_SET) \ { \ if (SRC&0x2) \ - { REG_BA = m37710i_pull_8(cpustate); CLK(3); } \ + { REG_BA = m37710i_pull_8(); CLK(3); } \ if (SRC&0x1) \ - { REG_A = m37710i_pull_8(cpustate); CLK(3); } \ + { REG_A = m37710i_pull_8(); CLK(3); } \ } \ else \ { \ if (SRC&0x2) \ - { REG_BA = m37710i_pull_16(cpustate); CLK(3); } \ + { REG_BA = m37710i_pull_16(); CLK(3); } \ if (SRC&0x1) \ - { REG_A = m37710i_pull_16(cpustate); CLK(3); } \ + { REG_A = m37710i_pull_16(); CLK(3); } \ } \ - m37710i_update_irqs(cpustate) + m37710i_update_irqs() /* M37710 Multiply */ #undef OP_MPY #if FLAG_SET_M #define OP_MPY(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE + 14); \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ { UINT16 temp = SRC * (REG_A&0xff); REG_A = temp & 0xff; REG_BA = (temp>>8)&0xff; FLAG_Z = temp; FLAG_N = (temp & 0x8000) ? 1 : 0; FLAG_C = 0; } #else #define OP_MPY(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE + 14+8); \ - SRC = OPER_16_##MODE(cpustate); \ + SRC = OPER_16_##MODE(); \ { UINT32 temp = SRC * REG_A; REG_A = temp & 0xffff; REG_BA = (temp>>16)&0xffff; FLAG_Z = temp; FLAG_N = (temp & 0x80000000) ? 1 : 0; FLAG_C = 0; } #endif @@ -656,7 +247,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #define OP_DIV(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE + 17); \ SRC = (REG_BA&0xff)<<8 | (REG_A & 0xff); \ - DST = OPER_8_##MODE(cpustate); \ + DST = OPER_8_##MODE(); \ if (DST != 0) \ { \ UINT16 tempa = SRC / DST; UINT16 tempb = SRC % DST; \ @@ -665,12 +256,12 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ if (!FLAG_V) { FLAG_N = (tempa & 0x80) ? 1 : 0; } \ FLAG_Z = REG_A = tempa & 0xff; REG_BA = tempb & 0xff; \ CLK(8); \ - } else m37710i_interrupt_software(cpustate, 0xfffc) + } else m37710i_interrupt_software(0xfffc) #else #define OP_DIV(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE + 17); \ SRC = (REG_BA<<16) | REG_A; \ - DST = OPER_16_##MODE(cpustate); \ + DST = OPER_16_##MODE(); \ if (DST != 0) \ { \ UINT32 tempa = SRC / DST; UINT32 tempb = SRC % DST; \ @@ -679,7 +270,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ if (!FLAG_V) { FLAG_N = (tempa & 0x8000) ? 1 : 0; } \ FLAG_Z = REG_A = tempa & 0xffff; REG_BA = tempb & 0xffff; \ CLK(8+15); \ - } else m37710i_interrupt_software(cpustate, 0xfffc) + } else m37710i_interrupt_software(0xfffc) #endif /* M37710 Add With Carry */ @@ -687,7 +278,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ADC(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ FLAG_C = REG_A + SRC + CFLAG_AS_1(); \ if(FLAG_D) \ { \ @@ -701,7 +292,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_ADC(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - SRC = OPER_16_##MODE(cpustate); \ + SRC = OPER_16_##MODE(); \ if(!FLAG_D) \ { \ FLAG_C = REG_A + SRC + CFLAG_AS_1(); \ @@ -734,7 +325,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ADCB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \ if(FLAG_D) \ { \ @@ -748,7 +339,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_ADCB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - SRC = OPER_16_##MODE(cpustate); \ + SRC = OPER_16_##MODE(); \ if(!FLAG_D) \ { \ FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \ @@ -781,11 +372,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_AND(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_A &= OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG_A &= OPER_8_##MODE() #else #define OP_AND(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_A &= OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_A &= OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_A) #endif @@ -794,11 +385,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ANDB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_BA &= OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG_BA &= OPER_8_##MODE() #else #define OP_ANDB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_BA &= OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_BA &= OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_BA) #endif @@ -839,14 +430,14 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ASLM(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_C = read_8_##MODE(DST) << 1; \ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ write_8_##MODE(DST, FLAG_Z) #else #define OP_ASLM(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_C = read_16_##MODE(DST) << 1; \ FLAG_Z = MAKE_UINT_16(FLAG_C); \ FLAG_N = NFLAG_16(FLAG_C); \ @@ -857,11 +448,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ /* M37710 Branch on Condition Code */ #undef OP_BCC #define OP_BCC(COND) \ - DST = OPER_8_IMM(cpustate); \ + DST = OPER_8_IMM(); \ if(COND) \ { \ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ - m37710i_branch_8(cpustate, DST); \ + m37710i_branch_8(DST); \ BREAKOUT; \ } \ CLK(CLK_OP + CLK_RELATIVE_8); @@ -870,19 +461,19 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #define OP_BRK() \ REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \ logerror("error M37710: BRK at PC=%06x\n", REG_PB|REG_PC); \ - m37710i_interrupt_software(cpustate, 0xfffa) + m37710i_interrupt_software(0xfffa) /* M37710 Branch Always */ #undef OP_BRA #define OP_BRA() \ CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \ - m37710i_branch_8(cpustate, OPER_8_IMM(cpustate)) + m37710i_branch_8(OPER_8_IMM()) /* M37710 Branch Always Long */ #undef OP_BRL #define OP_BRL() \ CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \ - m37710i_branch_16(cpustate, OPER_16_IMM(cpustate)) + m37710i_branch_16(OPER_16_IMM()) /* M37710 Clear Carry flag */ #undef OP_CLC @@ -894,8 +485,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_CLI #define OP_CLI() \ CLK(CLK_OP + CLK_IMPLIED); \ - m37710i_set_flag_i(cpustate, IFLAG_CLEAR); \ - m37710i_update_irqs(cpustate) + m37710i_set_flag_i(IFLAG_CLEAR); \ + m37710i_update_irqs() /* M37710 Clear oVerflow flag */ #undef OP_CLV @@ -909,13 +500,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_CMP(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_C = REG_A - OPER_8_##MODE(cpustate); \ + FLAG_C = REG_A - OPER_8_##MODE(); \ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ FLAG_C ^= CFLAG_SET #else #define OP_CMP(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_C = REG_A - OPER_16_##MODE(cpustate); \ + FLAG_C = REG_A - OPER_16_##MODE(); \ FLAG_Z = MAKE_UINT_16(FLAG_C); \ FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = ~CFLAG_16(FLAG_C) @@ -927,13 +518,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_CMPB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_C = REG_BA - OPER_8_##MODE(cpustate); \ + FLAG_C = REG_BA - OPER_8_##MODE(); \ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ FLAG_C ^= CFLAG_SET #else #define OP_CMPB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_C = REG_BA - OPER_16_##MODE(cpustate); \ + FLAG_C = REG_BA - OPER_16_##MODE(); \ FLAG_Z = MAKE_UINT_16(FLAG_C); \ FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = ~CFLAG_16(FLAG_C) @@ -945,13 +536,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_X #define OP_CMPX(REG, MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_C = REG - OPER_8_##MODE(cpustate); \ + FLAG_C = REG - OPER_8_##MODE(); \ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ FLAG_C ^= CFLAG_SET #else #define OP_CMPX(REG, MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_C = REG - OPER_16_##MODE(cpustate); \ + FLAG_C = REG - OPER_16_##MODE(); \ FLAG_Z = MAKE_UINT_16(FLAG_C); \ FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = ~CFLAG_16(FLAG_C) @@ -988,13 +579,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_DECM(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \ write_8_##MODE(DST, FLAG_Z) #else #define OP_DECM(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \ FLAG_N = NFLAG_16(FLAG_Z); \ write_16_##MODE(DST, FLAG_Z) @@ -1018,11 +609,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_EOR(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_A ^= OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG_A ^= OPER_8_##MODE() #else #define OP_EOR(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_A ^= OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_A ^= OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_A) #endif @@ -1031,11 +622,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_EORB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_BA ^= OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG_BA ^= OPER_8_##MODE() #else #define OP_EORB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_BA ^= OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_BA ^= OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_BA) #endif @@ -1070,13 +661,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_INCM(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \ write_8_##MODE(DST, FLAG_Z) #else #define OP_INCM(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \ FLAG_N = NFLAG_16(FLAG_Z); \ write_16_##MODE(DST, FLAG_Z) @@ -1099,61 +690,61 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_JMLAI #define OP_JMLAI() \ CLK(CLK_OP + CLK_AI + 1); \ - m37710i_jump_24(cpustate, read_24_A(OPER_16_IMM(cpustate))) + m37710i_jump_24(read_24_A(OPER_16_IMM())) /* M37710 Jump */ #undef OP_JMP #define OP_JMP(MODE) \ CLK(CLK_OP + CLK_##MODE); \ - m37710i_jump_16(cpustate, EA_##MODE(cpustate)) + m37710i_jump_16(EA_##MODE()) /* M37710 Jump absolute indexed indirect */ #undef OP_JMPAXI #define OP_JMPAXI() \ CLK(CLK_OP + CLK_AXI); \ - m37710i_jump_16(cpustate, read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X)))) + m37710i_jump_16(read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X)))) /* M37710 Jump absolute long */ #undef OP_JMPAL #define OP_JMPAL() \ CLK(CLK_OP + CLK_AL); \ - m37710i_jump_24(cpustate, EA_AL(cpustate)) + m37710i_jump_24(EA_AL()) /* M37710 Jump to Subroutine Long */ #undef OP_JSL #define OP_JSL(MODE) \ CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \ - DST = EA_##MODE(cpustate); \ - m37710i_push_8(cpustate, REG_PB>>16); \ - m37710i_push_16(cpustate, REG_PC); \ - m37710i_jump_24(cpustate, DST) + DST = EA_##MODE(); \ + m37710i_push_8(REG_PB>>16); \ + m37710i_push_16(REG_PC); \ + m37710i_jump_24(DST) /* M37710 Jump to Subroutine */ #undef OP_JSR #define OP_JSR(MODE) \ CLK(CLK_OP + CLK_W16 + CLK_##MODE); \ - DST = EA_##MODE(cpustate); \ - m37710i_push_16(cpustate, REG_PC); \ - m37710i_jump_16(cpustate, DST) + DST = EA_##MODE(); \ + m37710i_push_16(REG_PC); \ + m37710i_jump_16(DST) /* M37710 Jump to Subroutine */ #undef OP_JSRAXI #define OP_JSRAXI() \ CLK(CLK_OP + CLK_W16 + CLK_AXI); \ - DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X))); \ - m37710i_push_16(cpustate, REG_PC); \ - m37710i_jump_16(cpustate, DST) + DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X))); \ + m37710i_push_16(REG_PC); \ + m37710i_jump_16(DST) /* M37710 Load accumulator with operand */ #undef OP_LDA #if FLAG_SET_M #define OP_LDA(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_A = OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG_A = OPER_8_##MODE() #else #define OP_LDA(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_A = OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_A = OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_A) #endif @@ -1162,11 +753,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_LDB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_BA = OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG_BA = OPER_8_##MODE() #else #define OP_LDB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_BA = OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_BA = OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_BA) #endif @@ -1175,14 +766,14 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_LDM(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - REG_IM2 = EA_##MODE(cpustate); \ + REG_IM2 = EA_##MODE(); \ REG_IM = read_8_NORM(REG_PB|REG_PC); \ REG_PC++; \ write_8_##MODE(REG_IM2, REG_IM) #else #define OP_LDM(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - REG_IM2 = EA_##MODE(cpustate); \ + REG_IM2 = EA_##MODE(); \ REG_IM = read_16_NORM(REG_PB|REG_PC); \ REG_PC+=2; \ write_16_##MODE(REG_IM2, REG_IM) @@ -1193,28 +784,28 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_BBS(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); \ + REG_IM2 = read_8_NORM(EA_##MODE()); \ REG_IM = read_8_NORM(REG_PB | REG_PC); \ REG_PC++; \ - DST = OPER_8_IMM(cpustate); \ + DST = OPER_8_IMM(); \ if ((REG_IM2 & REG_IM) == REG_IM) \ { \ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ - m37710i_branch_8(cpustate, DST); \ + m37710i_branch_8(DST); \ BREAKOUT; \ } #else #define OP_BBS(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); \ + REG_IM2 = read_16_NORM(EA_##MODE()); \ REG_IM = read_16_NORM(REG_PB | REG_PC); \ REG_PC++; \ REG_PC++; \ - DST = OPER_8_IMM(cpustate); \ + DST = OPER_8_IMM(); \ if ((REG_IM2 & REG_IM) == REG_IM) \ { \ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ - m37710i_branch_8(cpustate, DST); \ + m37710i_branch_8(DST); \ BREAKOUT; \ } #endif @@ -1224,28 +815,28 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_BBC(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); \ + REG_IM2 = read_8_NORM(EA_##MODE()); \ REG_IM = read_8_NORM(REG_PB | REG_PC); \ REG_PC++; \ - DST = OPER_8_IMM(cpustate); \ + DST = OPER_8_IMM(); \ if ((REG_IM2 & REG_IM) == 0) \ { \ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ - m37710i_branch_8(cpustate, DST); \ + m37710i_branch_8(DST); \ BREAKOUT; \ } #else #define OP_BBC(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); \ + REG_IM2 = read_16_NORM(EA_##MODE()); \ REG_IM = read_16_NORM(REG_PB | REG_PC); \ REG_PC++; \ REG_PC++; \ - DST = OPER_8_IMM(cpustate); \ + DST = OPER_8_IMM(); \ if ((REG_IM2 & REG_IM) == 0) \ { \ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ - m37710i_branch_8(cpustate, DST); \ + m37710i_branch_8(DST); \ BREAKOUT; \ } #endif @@ -1272,11 +863,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_X #define OP_LDX(REG, MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG = OPER_8_##MODE(cpustate) + FLAG_N = FLAG_Z = REG = OPER_8_##MODE() #else #define OP_LDX(REG, MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG = OPER_16_##MODE(cpustate); \ + FLAG_Z = REG = OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG) #endif @@ -1317,7 +908,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_LSRM(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_N = 0; \ FLAG_Z = read_8_##MODE(DST); \ FLAG_C = FLAG_Z << 8; \ @@ -1326,7 +917,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_LSRM(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_N = 0; \ FLAG_Z = read_16_##MODE(DST); \ FLAG_C = FLAG_Z << 8; \ @@ -1338,8 +929,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_MVN #if FLAG_SET_X #define OP_MVN() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ + DST = OPER_8_IMM()<<16; \ + SRC = OPER_8_IMM()<<16; \ REG_DB = DST; \ REG_A |= REG_B; \ CLK(7); \ @@ -1368,8 +959,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ } #else #define OP_MVN() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ + DST = OPER_8_IMM()<<16; \ + SRC = OPER_8_IMM()<<16; \ REG_DB = DST; \ REG_A |= REG_B; \ CLK(7); \ @@ -1402,8 +993,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_MVP #if FLAG_SET_X #define OP_MVP() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ + DST = OPER_8_IMM()<<16; \ + SRC = OPER_8_IMM()<<16; \ REG_DB = DST; \ REG_A |= REG_B; \ CLK(7); \ @@ -1432,8 +1023,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ } #else #define OP_MVP() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ + DST = OPER_8_IMM()<<16; \ + SRC = OPER_8_IMM()<<16; \ REG_DB = DST; \ REG_A |= REG_B; \ CLK(7); \ @@ -1472,11 +1063,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ORA(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_A |= OPER_8_ ## MODE(cpustate) + FLAG_N = FLAG_Z = REG_A |= OPER_8_ ## MODE() #else #define OP_ORA(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_A |= OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_A |= OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_A) #endif @@ -1485,11 +1076,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ORB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = FLAG_Z = REG_BA |= OPER_8_ ## MODE(cpustate) + FLAG_N = FLAG_Z = REG_BA |= OPER_8_ ## MODE() #else #define OP_ORB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG_BA |= OPER_16_##MODE(cpustate); \ + FLAG_Z = REG_BA |= OPER_16_##MODE(); \ FLAG_N = NFLAG_16(REG_BA) #endif @@ -1497,31 +1088,31 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_PEA #define OP_PEA() \ CLK(CLK_OP + CLK_R16 + CLK_W16); \ - m37710i_push_16(cpustate, OPER_16_IMM(cpustate)) + m37710i_push_16(OPER_16_IMM()) /* M37710 Push Effective Indirect Address */ #undef OP_PEI #define OP_PEI() \ CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \ - m37710i_push_16(cpustate, EA_DI(cpustate)) + m37710i_push_16(EA_DI()) /* M37710 Push Effective PC-Relative Address */ #undef OP_PER #define OP_PER() \ CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \ - SRC = OPER_16_IMM(cpustate); \ - m37710i_push_16(cpustate, REG_PC + SRC) + SRC = OPER_16_IMM(); \ + m37710i_push_16(REG_PC + SRC) /* M37710 Push accumulator to the stack */ #undef OP_PHA #if FLAG_SET_M #define OP_PHA() \ CLK(CLK_OP + CLK_W8 + 1); \ - m37710i_push_8(cpustate, REG_A) + m37710i_push_8(REG_A) #else #define OP_PHA() \ CLK(CLK_OP + CLK_W16 + 1); \ - m37710i_push_16(cpustate, REG_A) + m37710i_push_16(REG_A) #endif /* M37710 Push B accumulator to the stack */ @@ -1529,11 +1120,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_PHAB() \ CLK(CLK_OP + CLK_W8 + 1); \ - m37710i_push_8(cpustate, REG_BA) + m37710i_push_8(REG_BA) #else #define OP_PHAB() \ CLK(CLK_OP + CLK_W16 + 1); \ - m37710i_push_16(cpustate, REG_BA) + m37710i_push_16(REG_BA) #endif /* M37710 Push index register to the stack */ @@ -1541,48 +1132,48 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_X #define OP_PHX(REG) \ CLK(CLK_OP + CLK_W8 + 1); \ - m37710i_push_8(cpustate, REG) + m37710i_push_8(REG) #else #define OP_PHX(REG) \ CLK(CLK_OP + CLK_W16 + 1); \ - m37710i_push_16(cpustate, REG) + m37710i_push_16(REG) #endif /* M37710 Push data bank register */ #undef OP_PHT #define OP_PHT() \ CLK(CLK_OP + CLK_W8 + 1); \ - m37710i_push_8(cpustate, REG_DB>>16) + m37710i_push_8(REG_DB>>16) /* M37710 Push direct register */ #undef OP_PHD #define OP_PHD() \ CLK(CLK_OP + CLK_W16 + 1); \ - m37710i_push_16(cpustate, REG_D) + m37710i_push_16(REG_D) /* M37710 Push program bank register */ #undef OP_PHK #define OP_PHK() \ CLK(CLK_OP + CLK_W8 + 1); \ - m37710i_push_8(cpustate, REG_PB>>16) + m37710i_push_8(REG_PB>>16) /* M37710 Push the Processor Status Register to the stack */ #undef OP_PHP #define OP_PHP() \ CLK(CLK_OP + CLK_W8 + 1); \ - m37710i_push_8(cpustate, cpustate->ipl); \ - m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)) + m37710i_push_8(m_ipl); \ + m37710i_push_8(m37710i_get_reg_p()) /* M37710 Pull accumulator from the stack */ #undef OP_PLA #if FLAG_SET_M #define OP_PLA() \ CLK(CLK_OP + CLK_R8 + 2); \ - FLAG_N = FLAG_Z = REG_A = m37710i_pull_8(cpustate) + FLAG_N = FLAG_Z = REG_A = m37710i_pull_8() #else #define OP_PLA() \ CLK(CLK_OP + CLK_R16 + 2); \ - FLAG_Z = REG_A = m37710i_pull_16(cpustate); \ + FLAG_Z = REG_A = m37710i_pull_16(); \ FLAG_N = NFLAG_16(FLAG_Z) #endif @@ -1591,11 +1182,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_PLAB() \ CLK(CLK_OP + CLK_R8 + 2); \ - FLAG_N = FLAG_Z = REG_BA = m37710i_pull_8(cpustate) + FLAG_N = FLAG_Z = REG_BA = m37710i_pull_8() #else #define OP_PLAB() \ CLK(CLK_OP + CLK_R16 + 2); \ - FLAG_Z = REG_BA = m37710i_pull_16(cpustate); \ + FLAG_Z = REG_BA = m37710i_pull_16(); \ FLAG_N = NFLAG_16(FLAG_Z) #endif @@ -1604,11 +1195,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_X #define OP_PLX(REG) \ CLK(CLK_OP + CLK_R8 + 2); \ - FLAG_N = FLAG_Z = REG = m37710i_pull_8(cpustate) + FLAG_N = FLAG_Z = REG = m37710i_pull_8() #else #define OP_PLX(REG) \ CLK(CLK_OP + CLK_R16 + 2); \ - FLAG_Z = REG = m37710i_pull_16(cpustate); \ + FLAG_Z = REG = m37710i_pull_16(); \ FLAG_N = NFLAG_16(FLAG_Z) #endif @@ -1616,35 +1207,35 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_PLT #define OP_PLT() \ CLK(CLK_OP + CLK_R8 + 2); \ - FLAG_N = FLAG_Z = m37710i_pull_8(cpustate); \ + FLAG_N = FLAG_Z = m37710i_pull_8(); \ REG_DB = FLAG_Z << 16 /* M37710 Pull direct register */ #undef OP_PLD #define OP_PLD() \ CLK(CLK_OP + CLK_R16 + 2); \ - REG_D = m37710i_pull_16(cpustate) + REG_D = m37710i_pull_16() /* M37710 Pull the Processor Status Register from the stack */ #undef OP_PLP #define OP_PLP() \ CLK(CLK_OP + CLK_R8 + 2); \ - m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \ - m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \ - m37710i_update_irqs(cpustate) + m37710i_set_reg_p(m37710i_pull_8()); \ + m37710i_set_reg_ipl(m37710i_pull_8()); \ + m37710i_update_irqs() /* M37710 Reset Program status word */ #undef OP_REP #define OP_REP() \ CLK(CLK_OP + CLK_R8 + 1); \ - m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~OPER_8_IMM(cpustate)); \ - m37710i_update_irqs(cpustate) + m37710i_set_reg_p(m37710i_get_reg_p() & ~OPER_8_IMM()); \ + m37710i_update_irqs() /* M37710 Clear "M" status bit */ #undef OP_CLM #define OP_CLM() \ CLK(CLK_OP + CLK_R8 + 1); \ - m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~FLAGPOS_M) + m37710i_set_reg_p(m37710i_get_reg_p() & ~FLAGPOS_M) /* M37710 Rotate Left the accumulator */ #undef OP_ROL @@ -1682,10 +1273,10 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_RLA #if FLAG_SET_M #define OP_RLA(MODE) \ - { int cnt = OPER_8_##MODE(cpustate); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>7&1))&0xff; cnt--; } } + { int cnt = OPER_8_##MODE(); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>7&1))&0xff; cnt--; } } #else #define OP_RLA(MODE) \ - { int cnt = OPER_16_##MODE(cpustate); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>15&1))&0xffff; cnt--; } } + { int cnt = OPER_16_##MODE(); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>15&1))&0xffff; cnt--; } } #endif /* M37710 Rotate Left an operand */ @@ -1693,14 +1284,14 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_ROLM(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ write_8_##MODE(DST, FLAG_Z) #else #define OP_ROLM(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \ FLAG_Z = MAKE_UINT_16(FLAG_C); \ FLAG_N = NFLAG_16(FLAG_C); \ @@ -1747,7 +1338,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_RORM(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \ FLAG_C = FLAG_Z << 8; \ FLAG_N = FLAG_Z >>= 1; \ @@ -1755,7 +1346,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_RORM(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \ FLAG_C = FLAG_Z << 8; \ FLAG_Z >>= 1; \ @@ -1767,25 +1358,25 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_RTI #define OP_RTI() \ CLK(8); \ - m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \ - m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \ - m37710i_jump_16(cpustate, m37710i_pull_16(cpustate)); \ - REG_PB = m37710i_pull_8(cpustate) << 16; \ + m37710i_set_reg_p(m37710i_pull_8()); \ + m37710i_set_reg_ipl(m37710i_pull_8()); \ + m37710i_jump_16(m37710i_pull_16()); \ + REG_PB = m37710i_pull_8() << 16; \ m37710i_jumping(REG_PB | REG_PC); \ - m37710i_update_irqs(cpustate) + m37710i_update_irqs() /* M37710 Return from Subroutine Long */ #undef OP_RTL #define OP_RTL() \ CLK(6); \ - m37710i_jump_24(cpustate, m37710i_pull_24(cpustate)) + m37710i_jump_24(m37710i_pull_24()) /* M37710 Return from Subroutine */ #undef OP_RTS #define OP_RTS() \ CLK(6); \ - DST = m37710i_pull_16(cpustate); \ - m37710i_jump_16(cpustate, DST) + DST = m37710i_pull_16(); \ + m37710i_jump_16(DST) /* M37710 Subtract with Carry */ /* Unusual behavior: C flag is inverted */ @@ -1793,7 +1384,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_SBC(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ FLAG_C = ~FLAG_C; \ if(!FLAG_D) \ { \ @@ -1815,7 +1406,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_SBC(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - SRC = OPER_16_##MODE(cpustate); \ + SRC = OPER_16_##MODE(); \ FLAG_C = ~FLAG_C; \ if(!FLAG_D) \ { \ @@ -1852,7 +1443,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_SBCB(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - SRC = OPER_8_##MODE(cpustate); \ + SRC = OPER_8_##MODE(); \ FLAG_C = ~FLAG_C; \ if(!FLAG_D) \ { \ @@ -1874,7 +1465,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_SBCB(MODE) \ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - SRC = OPER_16_##MODE(cpustate); \ + SRC = OPER_16_##MODE(); \ FLAG_C = ~FLAG_C; \ if(!FLAG_D) \ { \ @@ -1915,30 +1506,30 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_SEI #define OP_SEI() \ CLK(CLK_OP + CLK_IMPLIED); \ - m37710i_set_flag_i(cpustate, IFLAG_SET) + m37710i_set_flag_i(IFLAG_SET) /* M37710 Set Program status word */ #undef OP_SEP #define OP_SEP() \ CLK(CLK_OP + CLK_R8 + 1); \ - m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) | OPER_8_IMM(cpustate)) + m37710i_set_reg_p(m37710i_get_reg_p() | OPER_8_IMM()) /* M37710 Set "M" status bit */ #undef OP_SEM #define OP_SEM() \ CLK(CLK_OP + CLK_R8 + 1); \ - m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) | FLAGPOS_M) + m37710i_set_reg_p(m37710i_get_reg_p() | FLAGPOS_M) /* M37710 Store accumulator to memory */ #undef OP_STA #if FLAG_SET_M #define OP_STA(MODE) \ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ - write_8_##MODE(EA_##MODE(cpustate), REG_A) + write_8_##MODE(EA_##MODE(), REG_A) #else #define OP_STA(MODE) \ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ - write_16_##MODE(EA_##MODE(cpustate), REG_A) + write_16_##MODE(EA_##MODE(), REG_A) #endif /* M37710 Store B accumulator to memory */ @@ -1946,11 +1537,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_STB(MODE) \ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ - write_8_##MODE(EA_##MODE(cpustate), REG_BA) + write_8_##MODE(EA_##MODE(), REG_BA) #else #define OP_STB(MODE) \ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ - write_16_##MODE(EA_##MODE(cpustate), REG_BA) + write_16_##MODE(EA_##MODE(), REG_BA) #endif /* M37710 Store index register to memory */ @@ -1958,11 +1549,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_X #define OP_STX(REG, MODE) \ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ - write_8_##MODE(EA_##MODE(cpustate), REG) + write_8_##MODE(EA_##MODE(), REG) #else #define OP_STX(REG, MODE) \ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ - write_16_##MODE(EA_##MODE(cpustate), REG) + write_16_##MODE(EA_##MODE(), REG) #endif /* M37710 Stop the clock */ @@ -2227,7 +1818,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_CLB(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ REG_IM = read_8_##MODE(DST); \ REG_IM2 = read_8_NORM(REG_PB | REG_PC); \ REG_PC++; \ @@ -2235,7 +1826,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_CLB(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ REG_IM = read_16_##MODE(DST); \ REG_IM2 = read_16_NORM(REG_PB | REG_PC); \ REG_PC+=2; \ @@ -2247,7 +1838,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #if FLAG_SET_M #define OP_SEB(MODE) \ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ REG_IM = read_8_##MODE(DST); \ REG_IM2 = read_8_NORM(REG_PB | REG_PC); \ REG_PC++; \ @@ -2255,7 +1846,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #else #define OP_SEB(MODE) \ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ + DST = EA_##MODE(); \ REG_IM = read_16_##MODE(DST); \ REG_IM2 = read_16_NORM(REG_PB | REG_PC); \ REG_PC+=2; \ @@ -2272,7 +1863,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_LDT #define OP_LDT(MODE) \ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - REG_DB = OPER_8_##MODE(cpustate)<<16; + REG_DB = OPER_8_##MODE()<<16; /* M37710 prefix for B accumulator (0x42) */ @@ -2282,7 +1873,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ CLK(2); \ REG_IR = read_8_IMM(REG_PB | REG_PC); \ REG_PC++; \ - cpustate->opcodes42[REG_IR](cpustate); + (this->*m_opcodes42[REG_IR])(); /* M37710 prefix for multiply / divide instructions (0x89) */ @@ -2290,7 +1881,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #define OP_PFXM() \ REG_IR = read_8_IMM(REG_PB | REG_PC); \ REG_PC++; \ - cpustate->opcodes89[REG_IR](cpustate); + (this->*m_opcodes89[REG_IR])(); /* M37710 unimplemented opcode */ @@ -2308,39 +1899,39 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef TABLE_FUNCTION #if !FLAG_SET_M && !FLAG_SET_X -#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M0X0(m37710i_cpu_struct *cpustate) {OPERATION;} -#define O(CODE) m37710i_ ## CODE ## _M0X0 -#define TABLE_OPCODES void (*const m37710i_opcodes_M0X0[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X0[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X0[256])(m37710i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X0 ARGS +#define OP(CODE, OPERATION) void m37710_cpu_device::m37710i_ ## CODE ## _M0X0() {OPERATION;} +#define O(CODE) &m37710_cpu_device::m37710i_ ## CODE ## _M0X0 +#define TABLE_OPCODES const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes_M0X0[256] +#define TABLE_OPCODES2 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes42_M0X0[256] +#define TABLE_OPCODES3 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes89_M0X0[256] +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710_cpu_device::m37710i_ ## NAME ## _M0X0 ARGS #elif !FLAG_SET_M && FLAG_SET_X -#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M0X1(m37710i_cpu_struct *cpustate) {OPERATION;} -#define O(CODE) m37710i_ ## CODE ## _M0X1 -#define TABLE_OPCODES void (*const m37710i_opcodes_M0X1[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X1[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X1[256])(m37710i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X1 ARGS +#define OP(CODE, OPERATION) void m37710_cpu_device::m37710i_ ## CODE ## _M0X1() {OPERATION;} +#define O(CODE) &m37710_cpu_device::m37710i_ ## CODE ## _M0X1 +#define TABLE_OPCODES const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes_M0X1[256] +#define TABLE_OPCODES2 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes42_M0X1[256] +#define TABLE_OPCODES3 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes89_M0X1[256] +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710_cpu_device::m37710i_ ## NAME ## _M0X1 ARGS #elif FLAG_SET_M && !FLAG_SET_X -#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M1X0(m37710i_cpu_struct *cpustate) {OPERATION;} -#define O(CODE) m37710i_ ## CODE ## _M1X0 -#define TABLE_OPCODES void (*const m37710i_opcodes_M1X0[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X0[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X0[256])(m37710i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X0 ARGS +#define OP(CODE, OPERATION) void m37710_cpu_device::m37710i_ ## CODE ## _M1X0() {OPERATION;} +#define O(CODE) &m37710_cpu_device::m37710i_ ## CODE ## _M1X0 +#define TABLE_OPCODES const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes_M1X0[256] +#define TABLE_OPCODES2 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes42_M1X0[256] +#define TABLE_OPCODES3 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes89_M1X0[256] +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710_cpu_device::m37710i_ ## NAME ## _M1X0 ARGS #elif FLAG_SET_M && FLAG_SET_X -#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M1X1(m37710i_cpu_struct *cpustate) {OPERATION;} -#define O(CODE) m37710i_ ## CODE ## _M1X1 -#define TABLE_OPCODES void (*const m37710i_opcodes_M1X1[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X1[256])(m37710i_cpu_struct *cpustate) -#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X1[256])(m37710i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X1 ARGS +#define OP(CODE, OPERATION) void m37710_cpu_device::m37710i_ ## CODE ## _M1X1() {OPERATION;} +#define O(CODE) &m37710_cpu_device::m37710i_ ## CODE ## _M1X1 +#define TABLE_OPCODES const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes_M1X1[256] +#define TABLE_OPCODES2 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes42_M1X1[256] +#define TABLE_OPCODES3 const m37710_cpu_device::opcode_func m37710_cpu_device::m37710i_opcodes89_M1X1[256] +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710_cpu_device::m37710i_ ## NAME ## _M1X1 ARGS #endif @@ -2779,7 +2370,6 @@ OP(249,OP_RLA ( IMM ) ) /* RLA imm */ OP(2c2,OP_LDT ( IMM ) ) /* LDT imm */ // note: block 28x-2bx is for 7750 opcodes, not implemented yet -extern TABLE_OPCODES; TABLE_OPCODES = // 00 01 02 03 04 05 06 07 // 08 09 0a 0b 0c 0d 0e 0f @@ -2818,7 +2408,6 @@ TABLE_OPCODES = O(f8), O(f9), O(fa), O(fb), O(fc), O(fd), O(fe), O(ff) }; -extern TABLE_OPCODES2; TABLE_OPCODES2 = // 00 01 02 03 04 05 06 07 // 08 09 0a 0b 0c 0d 0e 0f @@ -2857,7 +2446,6 @@ TABLE_OPCODES2 = O(200),O(1f9),O(200),O(200),O(200),O(1fd),O(200),O(1ff) }; -extern TABLE_OPCODES3; TABLE_OPCODES3 = // 00 01 02 03 04 05 06 07 // 08 09 0a 0b 0c 0d 0e 0f @@ -2896,10 +2484,9 @@ TABLE_OPCODES3 = O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200) }; -extern const int m37710_irq_levels[M37710_LINE_MAX]; /* Assert or clear a line on the CPU */ -TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int state)) +TABLE_FUNCTION(void, set_line, (int line, int state)) { switch(line) { @@ -2926,7 +2513,7 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int stat LINE_IRQ &= ~(1 << line); if (m37710_irq_levels[line]) { - cpustate->m37710_regs[m37710_irq_levels[line]] &= ~8; + m_m37710_regs[m37710_irq_levels[line]] &= ~8; } break; @@ -2936,7 +2523,7 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int stat LINE_IRQ |= (1 << line); if (m37710_irq_levels[line]) { - cpustate->m37710_regs[m37710_irq_levels[line]] |= 8; + m_m37710_regs[m37710_irq_levels[line]] |= 8; } break; @@ -2951,7 +2538,7 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int stat /* Get a register from the CPU core */ -TABLE_FUNCTION(uint, get_reg, (m37710i_cpu_struct *cpustate, int regnum)) +TABLE_FUNCTION(UINT32, get_reg, (int regnum)) { switch(regnum) { @@ -2964,20 +2551,20 @@ TABLE_FUNCTION(uint, get_reg, (m37710i_cpu_struct *cpustate, int regnum)) case M37710_PB: return REG_PB >> 16; case M37710_DB: return REG_DB >> 16; case M37710_D: return REG_D; - case M37710_P: return m37710i_get_reg_p(cpustate); + case M37710_P: return m37710i_get_reg_p(); case M37710_IRQ_STATE: return LINE_IRQ; case STATE_GENPCBASE: return REG_PPC; } return 0; } -TABLE_FUNCTION(void, set_reg, (m37710i_cpu_struct *cpustate, int regnum, uint val)) +TABLE_FUNCTION(void, set_reg, (int regnum, UINT32 val)) { switch(regnum) { case M37710_PC: REG_PC = MAKE_UINT_16(val); break; case M37710_S: REG_S = MAKE_UINT_16(val); break; - case M37710_P: m37710i_set_reg_p(cpustate, val); break; + case M37710_P: m37710i_set_reg_p(val); break; #if FLAG_SET_M case M37710_A: REG_A = MAKE_UINT_8(val); REG_B = val&0xff00; break; case M37710_B: REG_BA = MAKE_UINT_8(val); REG_BB = val&0xff00; break; @@ -2992,11 +2579,11 @@ TABLE_FUNCTION(void, set_reg, (m37710i_cpu_struct *cpustate, int regnum, uint va case M37710_X: REG_X = MAKE_UINT_16(val); break; case M37710_Y: REG_Y = MAKE_UINT_16(val); break; #endif - case M37710_IRQ_STATE: FTABLE_SET_LINE(cpustate, M37710_LINE_IRQ0, val == 0 ? CLEAR_LINE : ASSERT_LINE); break; + case M37710_IRQ_STATE: (this->*FTABLE_SET_LINE)(M37710_LINE_IRQ0, val == 0 ? CLEAR_LINE : ASSERT_LINE); break; } } -TABLE_FUNCTION(int, execute, (m37710i_cpu_struct *cpustate, int clocks)) +TABLE_FUNCTION(int, execute, (int clocks)) { if(!CPU_STOPPED) { @@ -3007,7 +2594,7 @@ TABLE_FUNCTION(int, execute, (m37710i_cpu_struct *cpustate, int clocks)) M37710_CALL_DEBUGGER(REG_PB | REG_PC); REG_PC++; REG_IR = read_8_IMM(REG_PB | REG_PPC); - cpustate->opcodes[REG_IR](cpustate); + (this->*m_opcodes[REG_IR])(); } while(CLOCKS > 0); return clocks - CLOCKS; }