mirror of
https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
mcs40 updates:
* Split ROM and RAM port address spaces * Split RAM memory and status address spaces (no more read/modify/write) * Fixed bug in FIN handling * Exposed cycle callback * Implemented most of intelc440 front panel * Added preliminary internal artwork for intlc440 * Re-implmented flicker I/O based on how hardware actually works * Corrected flicker RAM size * Hooked up flicker playfield lamp outputs - this really needs PWM
This commit is contained in:
Vas Crabb
parent
76afa6e7d7
commit
6c42de79b7
@ -9,18 +9,14 @@
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*****************************************************************************/
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#include "emu.h"
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#include "mcs40.h"
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#include "debugger.h"
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/*
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MCS-40 uses an unusual scheme for memory. RAMs contain four registers,
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each of which has 16 memory characters and 4 status characters (all
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characters are 4 bits wide). We represent a register as 16 bytes,
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storing memory characters in the low nybbles and status characters in
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the high nybbles of the first four bytes. This necessitates a
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read/modify/write on each write, as MAME doesn't cater for nybble lane
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select.
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characters are 4 bits wide). We represent memory and status as separate
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address spaces, storing one nybble per byte.
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I/O is similarly unusual. It's assumed that there's one 4-bit I/O port
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per 256 bytes of ROM. The upper four bits of RC select the ROM I/O port
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@ -30,24 +26,28 @@ upper two bits of RC along with the lower three bits of CR select the
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RAM output port for WMP instructions. This isn't too bad, but it's
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complicated by the GPIO peripherals. These chips respond to WRR/RDR,
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but can be wired to the CM-RAM lines, so they can be selected by the
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combination of the lower three bits of RC along with the upper four bits
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combination of the lower three bits of CR along with the upper four bits
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of RC. On top of this, the 4289 latches the entire RC value on its A
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outputs at X1, allowing for a flat 8-bit I/O space using the WRR/RDR
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instructions, as well as having CM lines for devices selection. This
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instructions, as well as having CM lines for device selection. This
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means we need 12 bits to represent the entire range of possibilities
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using the WRR/RDR instructions. At this point, we're placing the
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ROM/RAM select in bit 12, CR in bits 11-8, and RC in bits 7-0. Ideally
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we'd be able to put the RAM output ports in a separate address space,
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but we're already running out.
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using the WRR/RDR instructions.
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CR RC
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4001: 0 B--- RRRR----
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4002: 1 -CCC RR------
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4207: 0 BCCC 11PP----
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4209: 0 BCCC 11PP----
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4211: 0 BCCC 11PP----
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4289: 0 B--- AAAAAAAA
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4308: 0 B--- RRPP----
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The WRR/RDR instructions operate on a flat 11- or 12-bit address space,
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depending on whether the CPU has ROM banking support. You can use
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AM_MIRROR to mask out unused chip select lines, and then shift the
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offset to mask out unused RC bits.
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CR RC
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4001: B--- RRRR----
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4207: BCCC 11PP----
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4209: BCCC 11PP----
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4211: BCCC 11PP----
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4289: B--- AAAAAAAA
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4308: B--- RRPP----
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The WMP instruction operates on a 5-bit address space - three low bits
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of CR and two high bits of RC.
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The "program memory" space is separate from the instruction, I/O and
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opcode spaces. It's accessed via a 4008/4009 pair, or a 4289. With a
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@ -65,7 +65,6 @@ write-back, using the RC value as the address and the first/last signal
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as nybble lane select.
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TODO: 4040 interrupt support (including BBS, EIN, DIN instructions)
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TODO: expose data bus
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*/
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@ -93,11 +92,17 @@ mcs40_cpu_device_base::mcs40_cpu_device_base(
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unsigned index_reg_cnt,
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unsigned cr_mask)
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: cpu_device(mconfig, type, tag, owner, clock)
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, m_program_config("program", ENDIANNESS_LITTLE, 8, 10, 0)
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, m_data_config("data", ENDIANNESS_LITTLE, 8, 11, 0)
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, m_io_config("io", ENDIANNESS_LITTLE, 8, 13, 0)
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, m_opcodes_config("opcodes", ENDIANNESS_LITTLE, 8, rom_width, 0)
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, m_program(nullptr), m_data(nullptr), m_io(nullptr), m_opcodes(nullptr), m_direct(nullptr)
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, m_space_config{
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{ "rom", ENDIANNESS_LITTLE, 8, u8(rom_width), 0 },
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{ "ram", ENDIANNESS_LITTLE, 8, u8(11), 0 },
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{ "romport", ENDIANNESS_LITTLE, 8, u8(rom_width - 1), 0 },
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{ "unused", ENDIANNESS_LITTLE, 8, u8(0), 0 },
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{ "status", ENDIANNESS_LITTLE, 8, u8(9), 0 },
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{ "ramport", ENDIANNESS_LITTLE, 8, u8(5), 0 },
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{ "program", ENDIANNESS_LITTLE, 8, u8(rom_width - 3), 0 }, }
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, m_spaces{ nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr }
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, m_direct(nullptr)
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, m_bus_cycle_cb()
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, m_sync_cb(*this)
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, m_cm_rom_cb{ { *this }, { *this } }
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, m_cm_ram_cb{ { *this }, { *this }, { *this }, { *this }, }
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@ -130,12 +135,15 @@ void mcs40_cpu_device_base::device_start()
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{
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m_icountptr = &m_icount;
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m_program = &space(AS_PROGRAM);
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m_data = &space(AS_DATA);
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m_io = &space(AS_IO);
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m_opcodes = &space(AS_OPCODES);
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m_direct = &m_opcodes->direct();
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m_spaces[AS_ROM] = &space(AS_ROM);
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m_spaces[AS_RAM_MEMORY] = &space(AS_RAM_MEMORY);
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m_spaces[AS_ROM_PORTS] = &space(AS_ROM_PORTS);
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m_spaces[AS_RAM_STATUS] = &space(AS_RAM_STATUS);
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m_spaces[AS_RAM_PORTS] = &space(AS_RAM_PORTS);
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m_spaces[AS_PROGRAM_MEMORY] = &space(AS_PROGRAM_MEMORY);
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m_direct = &m_spaces[AS_ROM]->direct();
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m_bus_cycle_cb.bind_relative_to(*owner());
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m_sync_cb.resolve_safe();
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m_cm_rom_cb[0].resolve_safe();
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m_cm_rom_cb[1].resolve_safe();
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@ -326,11 +334,12 @@ void mcs40_cpu_device_base::execute_run()
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std::vector<std::pair<int, const address_space_config *>> mcs40_cpu_device_base::memory_space_config() const
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{
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return std::vector<std::pair<int, const address_space_config *>> {
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std::make_pair(AS_PROGRAM, &m_program_config),
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std::make_pair(AS_DATA, &m_data_config),
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std::make_pair(AS_IO, &m_io_config),
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std::make_pair(AS_OPCODES, &m_opcodes_config)
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};
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std::make_pair(AS_ROM, &m_space_config[AS_ROM]),
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std::make_pair(AS_RAM_MEMORY, &m_space_config[AS_RAM_MEMORY]),
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std::make_pair(AS_ROM_PORTS, &m_space_config[AS_ROM_PORTS]),
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std::make_pair(AS_RAM_STATUS, &m_space_config[AS_RAM_STATUS]),
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std::make_pair(AS_RAM_PORTS, &m_space_config[AS_RAM_PORTS]),
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std::make_pair(AS_PROGRAM_MEMORY, &m_space_config[AS_PROGRAM_MEMORY]) };
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}
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@ -528,40 +537,39 @@ inline void mcs40_cpu_device_base::set_rc(u8 val)
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inline u8 mcs40_cpu_device_base::read_memory()
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{
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return m_data->read_byte((u16(m_cr & 0x7U) << 8) | m_latched_rc) & 0x0fU;
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return m_spaces[AS_RAM_MEMORY]->read_byte((u16(m_cr & 0x7U) << 8) | m_latched_rc) & 0x0fU;
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}
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inline void mcs40_cpu_device_base::write_memory(u8 val)
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{
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u16 const addr((u16(m_cr & 0x7U) << 8) | m_latched_rc);
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m_data->write_byte(addr, (m_data->read_byte(addr) & 0xf0U) | (val & 0x0fU));
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m_spaces[AS_RAM_MEMORY]->write_byte((u16(m_cr & 0x7U) << 8) | m_latched_rc, val & 0x0fU);
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}
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inline u8 mcs40_cpu_device_base::read_status()
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{
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u16 const addr((((u16(m_cr) << 8) | m_latched_rc) & 0x07f0U) | (m_opa & 0x0003U));
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return (m_data->read_byte(addr) >> 4) & 0x0fU;
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u16 const addr((((u16(m_cr) << 6) | (m_latched_rc >> 2)) & 0x01fcU) | (m_opa & 0x0003U));
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return m_spaces[AS_RAM_STATUS]->read_byte(addr) & 0x0fU;
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}
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inline void mcs40_cpu_device_base::write_status(u8 val)
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{
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u16 const addr((((u16(m_cr) << 8) | m_latched_rc) & 0x07f0U) | (m_opa & 0x0003U));
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m_data->write_byte(addr, (m_data->read_byte(addr) & 0x0fU) | (val << 4));
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u16 const addr((((u16(m_cr) << 6) | (m_latched_rc >> 2)) & 0x01fcU) | (m_opa & 0x0003U));
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m_spaces[AS_RAM_STATUS]->write_byte(addr, val & 0x0fU);
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}
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inline u8 mcs40_cpu_device_base::read_rom_port()
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{
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return m_io->read_byte((u16(m_cr) << 8) | m_latched_rc) & 0x0fU;
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return m_spaces[AS_ROM_PORTS]->read_byte((u16(m_cr) << 8) | m_latched_rc) & 0x0fU;
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}
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inline void mcs40_cpu_device_base::write_rom_port(u8 val)
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{
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m_io->write_byte((u16(m_cr) << 8) | m_latched_rc, val & 0x0fU);
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m_spaces[AS_ROM_PORTS]->write_byte((u16(m_cr) << 8) | m_latched_rc, val & 0x0fU);
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}
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inline void mcs40_cpu_device_base::write_memory_port(u8 val)
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{
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m_io->write_byte(0x1000U | (u16(m_cr) << 8) | m_latched_rc, val & 0x0fU);
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m_spaces[AS_RAM_PORTS]->write_byte(((m_cr << 2) & 0x1cU) | (m_latched_rc >> 6), val & 0x0fU);
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}
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@ -615,43 +623,38 @@ inline void mcs40_cpu_device_base::do_a1()
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m_sync_cb(1);
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update_4289_pm(1U);
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update_4289_f_l(1U);
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// low nybble of ROM address is output here
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::A1, 1U, m_rom_addr & 0x000fU);
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}
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inline void mcs40_cpu_device_base::do_a2()
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{
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// mid nybble of ROM address is output here
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m_4289_a = (m_4289_a & 0x0fU) | (m_rom_addr & 0xf0U);
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::A2, 1U, (m_rom_addr >> 4) & 0x000fU);
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}
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inline void mcs40_cpu_device_base::do_a3()
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{
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// high nybble of ROM address is output here
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m_4289_c = (m_rom_addr >> 8) & 0x0fU;
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update_cm_rom(BIT(m_cr, 3) ? 0x01U : 0x02U);
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update_cm_ram(f_cm_ram_table[m_cr & 0x07U]);
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::A3, 1U, (m_rom_addr >> 8) & 0x000fU);
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}
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inline void mcs40_cpu_device_base::do_m1()
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{
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// OPR is read here
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if (!m_extended_cm || (cycle::OP != m_cycle))
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update_cm_rom(0x03);
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else
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update_cm_ram(f_cm_ram_table[m_cr & 0x07U]);
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// TODO: split this up into two nybble reads - MAME doesn't support this
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{
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update_cm_rom(0x03U);
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update_cm_rom(0x0fU);
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}
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// TODO: just read the high nybble here - MAME doesn't support this
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u8 const read = m_direct->read_byte(rom_bank() | m_rom_addr);
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if (cycle::OP == m_cycle)
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{
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if (m_stop_ff)
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{
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m_opr = 0x0U;
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m_opa = 0x0U;
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}
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else
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{
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m_opr = read >> 4;
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m_opa = read & 0x0fU;
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}
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m_opr = (m_stop_ff) ? 0x0U : (read >> 4);
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m_io_pending = is_io_op(m_opr);
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}
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else
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@ -659,11 +662,18 @@ inline void mcs40_cpu_device_base::do_m1()
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m_arg = read;
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}
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m_decoded_halt = false;
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::M1, 1U, (read >> 4) & 0x0fU);
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}
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inline void mcs40_cpu_device_base::do_m2()
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{
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// OPA is read here
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// TODO: just read the low nybble here - MAME doesn't support this
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u8 const read = m_direct->read_byte(rom_bank() | m_rom_addr);
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if (cycle::OP == m_cycle)
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m_opa = (m_stop_ff) ? 0x0U : (read & 0x0fU);
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else
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m_arg = read;
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if (m_io_pending)
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{
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update_cm_rom(BIT(m_cr, 3) ? 0x01U : 0x02U);
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@ -671,13 +681,20 @@ inline void mcs40_cpu_device_base::do_m2()
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}
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m_resume = m_stop_latch && (CLEAR_LINE == m_stp);
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m_stop_latch = CLEAR_LINE != m_stp;
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if (!m_stop_ff && (cycle::IN != m_cycle))
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m_rom_addr = pc() = (pc() + 1) & 0x0fff;
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if (!m_stop_ff)
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{
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if (cycle::IN != m_cycle)
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pc() = (pc() + 1) & 0x0fff;
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m_rom_addr = pc();
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}
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::M2, 1U, read & 0x0fU);
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}
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inline void mcs40_cpu_device_base::do_x1()
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{
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// A or OPA is output here
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// FIXME: is 4004 output on the second cycle of two-cycle instruction OPA or low nybble of the argument?
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u8 const output(m_extended_cm ? m_a : (cycle::OP == m_cycle) ? m_opa : m_arg);
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update_cy(m_c);
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update_cm_rom(0x03U);
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update_cm_ram(0x0fU);
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@ -704,20 +721,23 @@ inline void mcs40_cpu_device_base::do_x1()
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update_4289_f_l(m_4289_first ? 0x01 : 0x00);
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m_4289_first = !m_4289_first;
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if (pmem::READ == m_program_op)
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m_arg = m_program->read_byte(program_addr()) & 0x0fU;
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m_arg = m_spaces[AS_PROGRAM_MEMORY]->read_byte(program_addr()) & 0x0fU;
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else
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assert(pmem::WRITE == m_program_op);
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}
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::X1, 1U, output);
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}
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void mcs40_cpu_device_base::do_x2()
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{
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u8 output((m_new_rc >> 4) & 0x0fU); // FIXME: what appears on the bus if it isn't SRC, I/O or program memory access?
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if (m_io_pending)
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{
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assert(phase::X2 == m_phase);
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assert(m_latched_rc == m_new_rc);
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assert(!m_rc_pending);
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do_io(m_opr, m_opa);
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output = do_io(m_opr, m_opa);
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m_io_pending = false;
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}
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if (m_rc_pending)
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@ -725,13 +745,18 @@ void mcs40_cpu_device_base::do_x2()
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update_cm_rom(BIT(m_cr, 3) ? 0x01U : 0x02U);
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update_cm_ram(f_cm_ram_table[m_cr & 0x07U]);
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m_latched_rc = (m_latched_rc & 0x0fU) | (m_new_rc & 0xf0U);
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output = (m_new_rc >> 4) & 0x0fU;
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}
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else
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{
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assert(m_latched_rc == m_new_rc);
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}
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if (pmem::READ == m_program_op)
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set_a(m_arg);
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set_a(output = m_arg & 0x0fU);
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else if (pmem::WRITE == m_program_op)
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output = get_a();
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::X2, 1U, output);
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}
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void mcs40_cpu_device_base::do_x3()
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@ -749,7 +774,7 @@ void mcs40_cpu_device_base::do_x3()
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assert(m_latched_rc == m_new_rc);
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}
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if (pmem::WRITE == m_program_op)
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m_program->write_byte(program_addr(), get_a());
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m_spaces[AS_PROGRAM_MEMORY]->write_byte(program_addr(), get_a());
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if (!m_stop_ff && m_decoded_halt)
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{
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m_stop_ff = true;
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@ -761,6 +786,8 @@ void mcs40_cpu_device_base::do_x3()
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m_stp_ack_cb(1U);
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}
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m_resume = false;
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if (!m_bus_cycle_cb.isnull())
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m_bus_cycle_cb(phase::X3, 0U, m_new_rc & 0x0fU); // FIXME: what appears on the bus if it isn't SRC?
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}
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@ -1049,7 +1076,7 @@ void i4004_cpu_device::do_cycle2(u8 opr, u8 opa, u8 arg)
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break;
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case 0x3: // FIN
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assert(BIT(opa, 0));
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assert(!BIT(opa, 0));
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index_reg_pair(opa >> 1) = arg;
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break;
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@ -1076,46 +1103,57 @@ void i4004_cpu_device::do_cycle2(u8 opr, u8 opa, u8 arg)
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}
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}
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|
||||
void i4004_cpu_device::do_io(u8 opr, u8 opa)
|
||||
u8 i4004_cpu_device::do_io(u8 opr, u8 opa)
|
||||
{
|
||||
assert(0xe == opr);
|
||||
u8 result;
|
||||
switch (opa)
|
||||
{
|
||||
case 0x0: // WRM
|
||||
write_memory(get_a());
|
||||
break;
|
||||
result = get_a();
|
||||
write_memory(result);
|
||||
return result;
|
||||
case 0x1: // WMP
|
||||
write_memory_port(get_a());
|
||||
break;
|
||||
result = get_a();
|
||||
write_memory_port(result);
|
||||
return result;
|
||||
case 0x2: // WRR
|
||||
write_rom_port(get_a());
|
||||
break;
|
||||
result = get_a();
|
||||
write_rom_port(result);
|
||||
return result;
|
||||
case 0x3: // WPM
|
||||
break;
|
||||
// FIXME: with early 4002 chips this overwrites memory
|
||||
return get_a();
|
||||
case 0x4: // WR0
|
||||
case 0x5: // WR1
|
||||
case 0x6: // WR2
|
||||
case 0x7: // WR3
|
||||
write_status(get_a());
|
||||
break;
|
||||
result = get_a();
|
||||
write_status(result);
|
||||
return result;
|
||||
case 0x8: // SBM
|
||||
set_a_c(get_a() + (read_memory() ^ 0x0fU) + (get_c() ^ 0x01U));
|
||||
break;
|
||||
result = read_memory();
|
||||
set_a_c(get_a() + (result ^ 0x0fU) + (get_c() ^ 0x01U));
|
||||
return result;
|
||||
case 0x9: // RDM
|
||||
set_a(read_memory());
|
||||
break;
|
||||
result = read_memory();
|
||||
set_a(result);
|
||||
return result;
|
||||
case 0xa: // RDR
|
||||
set_a(read_rom_port());
|
||||
break;
|
||||
result = read_rom_port();
|
||||
set_a(result);
|
||||
return result;
|
||||
case 0xb: // ADM
|
||||
set_a_c(get_a() + read_memory() + get_c());
|
||||
break;
|
||||
result = read_memory();
|
||||
set_a_c(get_a() + result + get_c());
|
||||
return result;
|
||||
case 0xc: // RD0
|
||||
case 0xd: // RD1
|
||||
case 0xe: // RD2
|
||||
case 0xf: // RD3
|
||||
set_a(read_status());
|
||||
break;
|
||||
result = read_status();
|
||||
set_a(result);
|
||||
return result;
|
||||
default: // something is badly wrong if we get here
|
||||
throw false;
|
||||
}
|
||||
|
||||
@ -25,6 +25,31 @@ enum
|
||||
CONFIGURATION MACROS
|
||||
***********************************************************************/
|
||||
|
||||
#define MCS40BUS_FUNC(cls, fnc) \
|
||||
mcs40_cpu_device_base::bus_cycle_delegate((&cls::fnc), (#cls "::" #fnc), DEVICE_SELF, (cls *)nullptr)
|
||||
|
||||
|
||||
#define MCFG_I4004_ROM_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4004_cpu_device::AS_ROM, map)
|
||||
|
||||
#define MCFG_I4004_RAM_MEMORY_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4004_cpu_device::AS_RAM_MEMORY, map)
|
||||
|
||||
#define MCFG_I4004_ROM_PORTS_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4004_cpu_device::AS_ROM_PORTS, map)
|
||||
|
||||
#define MCFG_I4004_RAM_STATUS_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4004_cpu_device::AS_RAM_STATUS, map)
|
||||
|
||||
#define MCFG_I4004_RAM_PORTS_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4004_cpu_device::AS_RAM_PORTS, map)
|
||||
|
||||
#define MCFG_I4004_PROGRAM_MEMORY_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4004_cpu_device::AS_PROGRAM_MEMORY, map)
|
||||
|
||||
#define MCFG_I4004_BUS_CYCLE_CB(obj) \
|
||||
i4004_cpu_device::set_bus_cycle_cb(*device, (MCS40BUS_##obj));
|
||||
|
||||
#define MCFG_I4004_SYNC_CB(obj) \
|
||||
devcb = &i4004_cpu_device::set_sync_cb(*device, DEVCB_##obj);
|
||||
|
||||
@ -50,6 +75,27 @@ enum
|
||||
devcb = &i4004_cpu_device::set_4289_f_l_cb(*device, DEVCB_##obj);
|
||||
|
||||
|
||||
#define MCFG_I4040_ROM_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4040_cpu_device::AS_ROM, map)
|
||||
|
||||
#define MCFG_I4040_RAM_MEMORY_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4040_cpu_device::AS_RAM_MEMORY, map)
|
||||
|
||||
#define MCFG_I4040_ROM_PORTS_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4040_cpu_device::AS_ROM_PORTS, map)
|
||||
|
||||
#define MCFG_I4040_RAM_STATUS_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4040_cpu_device::AS_RAM_STATUS, map)
|
||||
|
||||
#define MCFG_I4040_RAM_PORTS_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4040_cpu_device::AS_RAM_PORTS, map)
|
||||
|
||||
#define MCFG_I4040_PROGRAM_MEMORY_MAP(map) \
|
||||
MCFG_DEVICE_ADDRESS_MAP(i4040_cpu_device::AS_PROGRAM_MEMORY, map)
|
||||
|
||||
#define MCFG_I4040_BUS_CYCLE_CB(obj) \
|
||||
i4040_cpu_device::set_bus_cycle_cb(*device, (MCS40BUS_##obj));
|
||||
|
||||
#define MCFG_I4040_SYNC_CB(obj) \
|
||||
devcb = &i4040_cpu_device::set_sync_cb(*device, DEVCB_##obj);
|
||||
|
||||
@ -92,12 +138,31 @@ enum
|
||||
class mcs40_cpu_device_base : public cpu_device
|
||||
{
|
||||
public:
|
||||
enum {
|
||||
AS_ROM = AS_PROGRAM,
|
||||
AS_RAM_MEMORY = AS_DATA,
|
||||
AS_ROM_PORTS = AS_IO,
|
||||
AS_RAM_STATUS = AS_OPCODES + 1,
|
||||
AS_RAM_PORTS,
|
||||
AS_PROGRAM_MEMORY
|
||||
};
|
||||
enum class phase { A1, A2, A3, M1, M2, X1, X2, X3 };
|
||||
|
||||
// step isn't a real signal, but realistically anything watching the bus will have a counter to track it
|
||||
typedef device_delegate<void (phase step, u8 sync, u8 data)> bus_cycle_delegate;
|
||||
|
||||
// configuration helpers
|
||||
template <typename Obj> static void set_bus_cycle_cb(device_t &device, Obj &&cb)
|
||||
{ downcast<mcs40_cpu_device_base &>(device).m_bus_cycle_cb = std::forward<Obj>(cb); }
|
||||
template <typename Obj> static devcb_base &set_4289_pm_cb(device_t &device, Obj &&cb)
|
||||
{ return downcast<mcs40_cpu_device_base &>(device).m_4289_pm_cb.set_callback(std::forward<Obj>(cb)); }
|
||||
template <typename Obj> static devcb_base &set_4289_f_l_cb(device_t &device, Obj &&cb)
|
||||
{ return downcast<mcs40_cpu_device_base &>(device).m_4289_f_l_cb.set_callback(std::forward<Obj>(cb)); }
|
||||
|
||||
// chip select outputs
|
||||
u8 get_cm_rom() const { return m_cm_rom; }
|
||||
u8 get_cm_ram() const { return m_cm_ram; }
|
||||
|
||||
// 4008/4009 or 4289 outputs
|
||||
u8 get_4289_a() const { return m_4289_a; } // 8-bit address
|
||||
u8 get_4289_c() const { return m_4289_c; } // 4-bit chip select
|
||||
@ -143,7 +208,7 @@ protected:
|
||||
virtual bool is_io_op(u8 opr) = 0;
|
||||
virtual cycle do_cycle1(u8 opr, u8 opa, pmem &program_op) = 0;
|
||||
virtual void do_cycle2(u8 opr, u8 opa, u8 arg) = 0;
|
||||
virtual void do_io(u8 opr, u8 opa) = 0;
|
||||
virtual u8 do_io(u8 opr, u8 opa) = 0;
|
||||
|
||||
// register access
|
||||
u8 get_a() const;
|
||||
@ -207,8 +272,6 @@ private:
|
||||
I4040_SRC
|
||||
};
|
||||
|
||||
enum class phase { A1, A2, A3, M1, M2, X1, X2, X3 };
|
||||
|
||||
// instruction phases
|
||||
void do_a1();
|
||||
void do_a2();
|
||||
@ -230,10 +293,13 @@ private:
|
||||
void update_4289_f_l(u8 val);
|
||||
|
||||
// address spaces
|
||||
address_space_config m_program_config, m_data_config, m_io_config, m_opcodes_config;
|
||||
address_space *m_program, *m_data, *m_io, *m_opcodes;
|
||||
address_space_config m_space_config[7];
|
||||
address_space *m_spaces[7];
|
||||
direct_read_data *m_direct;
|
||||
|
||||
// bus snooping callback
|
||||
bus_cycle_delegate m_bus_cycle_cb;
|
||||
|
||||
// output callbacks
|
||||
devcb_write_line m_sync_cb;
|
||||
devcb_write_line m_cm_rom_cb[2], m_cm_ram_cb[4];
|
||||
@ -323,7 +389,7 @@ protected:
|
||||
virtual bool is_io_op(u8 opr) override;
|
||||
virtual cycle do_cycle1(u8 opr, u8 opa, pmem &program_op) override;
|
||||
virtual void do_cycle2(u8 opr, u8 opa, u8 arg) override;
|
||||
virtual void do_io(u8 opr, u8 opa) override;
|
||||
virtual u8 do_io(u8 opr, u8 opa) override;
|
||||
|
||||
// configuration helpers
|
||||
using mcs40_cpu_device_base::set_sync_cb;
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
|
||||
#include "4004clk.lh"
|
||||
|
||||
|
||||
class nixieclock_state : public driver_device
|
||||
{
|
||||
public:
|
||||
@ -77,21 +78,29 @@ WRITE8_MEMBER(nixieclock_state::neon_w)
|
||||
output_set_neon_value(3, BIT(data,0));
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START(4004clk_rom, AS_OPCODES, 8, nixieclock_state)
|
||||
AM_RANGE(0x0000, 0x0FFF) AM_ROM AM_REGION("maincpu", 0)
|
||||
static ADDRESS_MAP_START(4004clk_rom, i4004_cpu_device::AS_ROM, 8, nixieclock_state)
|
||||
AM_RANGE(0x0000, 0x0fff) AM_ROM AM_REGION("maincpu", 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(4004clk_mem, AS_DATA, 8, nixieclock_state)
|
||||
static ADDRESS_MAP_START(4004clk_mem, i4004_cpu_device::AS_RAM_MEMORY, 8, nixieclock_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x007F) AM_RAM
|
||||
AM_RANGE(0x0000, 0x007f) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( 4004clk_io, AS_IO, 8, nixieclock_state)
|
||||
static ADDRESS_MAP_START(4004clk_stat, i4004_cpu_device::AS_RAM_STATUS, 8, nixieclock_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x001f) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(4004clk_rp, i4004_cpu_device::AS_ROM_PORTS, 8, nixieclock_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x000f) AM_MIRROR(0x0700) AM_READ_PORT("INPUT")
|
||||
AM_RANGE(0x0000, 0x00ef) AM_MIRROR(0x0700) AM_WRITE(nixie_w)
|
||||
AM_RANGE(0x00f0, 0x00ff) AM_MIRROR(0x0700) AM_WRITE(neon_w)
|
||||
AM_RANGE(0x1000, 0x1000) AM_MIRROR(0x083f) AM_DEVWRITE("dac", dac_bit_interface, write)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(4004clk_mp, i4004_cpu_device::AS_RAM_PORTS, 8, nixieclock_state)
|
||||
AM_RANGE(0x00, 0x00) AM_DEVWRITE("dac", dac_bit_interface, write)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
@ -118,9 +127,11 @@ static MACHINE_CONFIG_START( 4004clk )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", I4004, XTAL_5MHz / 8)
|
||||
MCFG_CPU_DECRYPTED_OPCODES_MAP(4004clk_rom)
|
||||
MCFG_CPU_DATA_MAP(4004clk_mem)
|
||||
MCFG_CPU_IO_MAP(4004clk_io)
|
||||
MCFG_I4004_ROM_MAP(4004clk_rom)
|
||||
MCFG_I4004_RAM_MEMORY_MAP(4004clk_mem)
|
||||
MCFG_I4004_ROM_PORTS_MAP(4004clk_rp)
|
||||
MCFG_I4004_RAM_STATUS_MAP(4004clk_stat)
|
||||
MCFG_I4004_RAM_PORTS_MAP(4004clk_mp)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_DEFAULT_LAYOUT(layout_4004clk)
|
||||
|
||||
@ -99,23 +99,31 @@ WRITE8_MEMBER(busicom_state::printer_ctrl_w)
|
||||
{
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START(busicom_rom, AS_OPCODES, 8, busicom_state )
|
||||
static ADDRESS_MAP_START(busicom_rom, i4004_cpu_device::AS_ROM, 8, busicom_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x04FF) AM_ROM AM_REGION("maincpu", 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(busicom_mem, AS_DATA, 8, busicom_state )
|
||||
static ADDRESS_MAP_START(busicom_mem, i4004_cpu_device::AS_RAM_MEMORY, 8, busicom_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x07F) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( busicom_io , AS_IO, 8, busicom_state )
|
||||
static ADDRESS_MAP_START(busicom_stat, i4004_cpu_device::AS_RAM_STATUS, 8, busicom_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x01F) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( busicom_rp, i4004_cpu_device::AS_ROM_PORTS, 8, busicom_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x000f) AM_MIRROR(0x0700) AM_WRITE(shifter_w) // ROM0 I/O
|
||||
AM_RANGE(0x0010, 0x001f) AM_MIRROR(0x0700) AM_READWRITE(keyboard_r,printer_ctrl_w) // ROM1 I/O
|
||||
AM_RANGE(0x0020, 0x002f) AM_MIRROR(0x0700) AM_READ(printer_r) // ROM2 I/O
|
||||
AM_RANGE(0x1000, 0x103f) AM_MIRROR(0x0700) AM_WRITE(printer_w) // RAM0 output
|
||||
AM_RANGE(0x1040, 0x105f) AM_MIRROR(0x0800) AM_WRITE(status_w) // RAM1 output
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( busicom_mp, i4004_cpu_device::AS_RAM_PORTS, 8, busicom_state )
|
||||
AM_RANGE(0x00, 0x00) AM_WRITE(printer_w) // RAM0 output
|
||||
AM_RANGE(0x01, 0x01) AM_WRITE(status_w) // RAM1 output
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
@ -214,10 +222,11 @@ void busicom_state::machine_reset()
|
||||
static MACHINE_CONFIG_START( busicom )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", I4004, 750000)
|
||||
MCFG_CPU_DECRYPTED_OPCODES_MAP(busicom_rom)
|
||||
MCFG_CPU_DATA_MAP(busicom_mem)
|
||||
MCFG_CPU_IO_MAP(busicom_io)
|
||||
|
||||
MCFG_I4004_ROM_MAP(busicom_rom)
|
||||
MCFG_I4004_RAM_MEMORY_MAP(busicom_mem)
|
||||
MCFG_I4004_ROM_PORTS_MAP(busicom_rp)
|
||||
MCFG_I4004_RAM_STATUS_MAP(busicom_stat)
|
||||
MCFG_I4004_RAM_PORTS_MAP(busicom_mp)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
|
||||
@ -1,221 +1,279 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Robbbert
|
||||
/***********************************************************************************
|
||||
// copyright-holders:Robbbert, Vas Crabb
|
||||
/*************************************************************************
|
||||
|
||||
PINBALL
|
||||
Flicker was originally an EM machine, and Bally asked Nutting Associates
|
||||
to create a solid-state prototype.
|
||||
Flicker was originally an electromechanical machine, and Bally asked
|
||||
Nutting Associates to create a solid-state prototype.
|
||||
|
||||
Seems to be the first ever microprocessor-controlled pinball machine.
|
||||
|
||||
2012-08-23 Made working [Robbbert]
|
||||
|
||||
Inputs from US Patent 4093232
|
||||
Some clues from PinMAME
|
||||
|
||||
Note: If F3 pressed, or you start the system, it will remember any credits from
|
||||
last time. However, you still need to insert a coin before the start button
|
||||
will work.
|
||||
Note: If F3 pressed, or you start the system, it will remember any
|
||||
credits from last time. However, you still need to insert a coin
|
||||
before the start button will work.
|
||||
|
||||
************************************************************************************/
|
||||
The input/output multiplexing on this machine is quite clever. RAM0
|
||||
output connected to two 1-of-16 decoders. These are strobed using
|
||||
CM-RAM1 and CM-RAM2. There is no RAM or I/O mapped there - the
|
||||
additional chip select lines are just used to strobe the decoders.
|
||||
|
||||
*************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "machine/genpin.h"
|
||||
#include "cpu/mcs40/mcs40.h"
|
||||
|
||||
#include "flicker.lh"
|
||||
|
||||
|
||||
class flicker_state : public genpin_class
|
||||
{
|
||||
public:
|
||||
flicker_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
flicker_state(machine_config const &mconfig, device_type type, char const *tag)
|
||||
: genpin_class(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_testport(*this, "TEST")
|
||||
, m_coinport(*this, "COIN")
|
||||
, m_switch(*this, "SWITCH.%u", 0)
|
||||
{ }
|
||||
, m_switch(*this, "SWITCH.%X", 0)
|
||||
{
|
||||
}
|
||||
|
||||
DECLARE_WRITE8_MEMBER(ram0_out) { m_ram0_output = data; }
|
||||
DECLARE_WRITE8_MEMBER(rom0_out) { m_rom0_output = data; }
|
||||
DECLARE_WRITE8_MEMBER(rom1_out) { m_rom1_output = data; }
|
||||
DECLARE_READ8_MEMBER(rom2_in);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(cm_ram1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(cm_ram2_w);
|
||||
|
||||
DECLARE_CUSTOM_INPUT_MEMBER(coins_in);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(port00_w);
|
||||
DECLARE_WRITE8_MEMBER(port01_w);
|
||||
DECLARE_WRITE8_MEMBER(port10_w);
|
||||
DECLARE_READ8_MEMBER(port02_r);
|
||||
private:
|
||||
uint8_t m_out_data;
|
||||
required_device<i4004_cpu_device> m_maincpu;
|
||||
required_ioport m_testport;
|
||||
required_ioport m_coinport;
|
||||
required_ioport_array<7> m_switch;
|
||||
required_device<i4004_cpu_device> m_maincpu;
|
||||
required_ioport m_testport;
|
||||
required_ioport m_coinport;
|
||||
required_ioport_array<7> m_switch;
|
||||
|
||||
bool m_cm_ram1 = false, m_cm_ram2 = false;
|
||||
u8 m_ram0_output = 0U, m_rom0_output = 0U, m_rom1_output = 0U;
|
||||
u8 m_mux_col = 0U, m_relay_drive = 0U;
|
||||
};
|
||||
|
||||
|
||||
static ADDRESS_MAP_START( flicker_rom, AS_OPCODES, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x03FF) AM_ROM AM_REGION("maincpu", 0)
|
||||
static ADDRESS_MAP_START( flicker_rom, i4004_cpu_device::AS_ROM, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x03ff) AM_ROM AM_REGION("maincpu", 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(flicker_map, AS_DATA, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x00FF) AM_RAM AM_SHARE("nvram")
|
||||
static ADDRESS_MAP_START( flicker_memory, i4004_cpu_device::AS_RAM_MEMORY, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x003f) AM_RAM AM_SHARE("memory")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( flicker_io, AS_IO, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x000f) AM_MIRROR(0x0700) AM_WRITE(port00_w)
|
||||
AM_RANGE(0x0010, 0x001f) AM_MIRROR(0x0700) AM_WRITE(port01_w)
|
||||
AM_RANGE(0x0020, 0x002f) AM_MIRROR(0x0700) AM_READ(port02_r)
|
||||
AM_RANGE(0x1000, 0x103f) AM_MIRROR(0x0800) AM_WRITE(port10_w)
|
||||
static ADDRESS_MAP_START( flicker_status, i4004_cpu_device::AS_RAM_STATUS, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x000f) AM_RAM AM_SHARE("status")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( flicker_rom_ports, i4004_cpu_device::AS_ROM_PORTS, 8, flicker_state )
|
||||
AM_RANGE(0x0000, 0x000f) AM_MIRROR(0x0700) AM_WRITE(rom0_out)
|
||||
AM_RANGE(0x0010, 0x001f) AM_MIRROR(0x0700) AM_WRITE(rom1_out)
|
||||
AM_RANGE(0x0020, 0x002f) AM_MIRROR(0x0700) AM_READ(rom2_in)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( flicker_ram_ports, i4004_cpu_device::AS_RAM_PORTS, 8, flicker_state )
|
||||
AM_RANGE(0x00, 0x00) AM_WRITE(ram0_out)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static INPUT_PORTS_START( flicker )
|
||||
PORT_START("TEST")
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Door Slam") PORT_CODE(KEYCODE_HOME)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Door Slam") PORT_CODE(KEYCODE_HOME)
|
||||
PORT_BIT(0x001c, IP_ACTIVE_HIGH, IPT_UNKNOWN) // called "two coins", "three coins", "four coins" in patent, purpose unknown
|
||||
PORT_BIT(0x07e0, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_CUSTOM_MEMBER(DEVICE_SELF, flicker_state, coins_in, nullptr)
|
||||
PORT_BIT(0x0800, IP_ACTIVE_HIGH, IPT_TILT)
|
||||
PORT_BIT(0x1000, IP_ACTIVE_HIGH, IPT_START)
|
||||
PORT_BIT(0x8000, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test")
|
||||
PORT_BIT(0x1000, IP_ACTIVE_HIGH, IPT_START) PORT_NAME("Credit Button")
|
||||
PORT_BIT(0x6000, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
PORT_BIT(0x8000, IP_ACTIVE_HIGH, IPT_SERVICE1) PORT_NAME("Test")
|
||||
|
||||
// The coin slot would be connected to one of the lines via a wire jumper on a terminal strip
|
||||
PORT_START("COIN")
|
||||
// The coin slot would be connected to one of six lines via a wire jumper on a terminal strip
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_COIN1)
|
||||
PORT_DIPNAME( 0x07e0, 0x0020, DEF_STR( Coinage ) )
|
||||
PORT_DIPSETTING( 0x0020, DEF_STR( 1C_1C ) )
|
||||
PORT_DIPSETTING( 0x0040, DEF_STR( 1C_2C ) )
|
||||
PORT_DIPSETTING( 0x0080, DEF_STR( 1C_3C ) )
|
||||
PORT_DIPSETTING( 0x0100, DEF_STR( 1C_4C ) )
|
||||
PORT_DIPSETTING( 0x0200, DEF_STR( 1C_5C ) )
|
||||
PORT_DIPSETTING( 0x0400, DEF_STR( 1C_6C ) )
|
||||
PORT_CONFNAME(0x3f, 0x01, DEF_STR(Coinage))
|
||||
PORT_CONFSETTING( 0x01, DEF_STR(1C_1C))
|
||||
PORT_CONFSETTING( 0x02, DEF_STR(1C_2C))
|
||||
PORT_CONFSETTING( 0x04, DEF_STR(1C_3C))
|
||||
PORT_CONFSETTING( 0x08, DEF_STR(1C_4C))
|
||||
PORT_CONFSETTING( 0x10, DEF_STR(1C_5C))
|
||||
PORT_CONFSETTING( 0x20, DEF_STR(1C_6C))
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_COIN1)
|
||||
|
||||
PORT_START("SWITCH.0")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left Lane Target") PORT_CODE(KEYCODE_W)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("/B Target") PORT_CODE(KEYCODE_E)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left Lane 1000") PORT_CODE(KEYCODE_R)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("/A Target") PORT_CODE(KEYCODE_Y)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left Lane Target") PORT_CODE(KEYCODE_W)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"/B\" Target") PORT_CODE(KEYCODE_E)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left Lane 1000") PORT_CODE(KEYCODE_R)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"/A\" Target") PORT_CODE(KEYCODE_Y)
|
||||
|
||||
PORT_START("SWITCH.1")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right Lane Target") PORT_CODE(KEYCODE_U)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("/C Target") PORT_CODE(KEYCODE_I)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right Lane 1000") PORT_CODE(KEYCODE_O)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("/D Target") PORT_CODE(KEYCODE_A)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right Lane Target") PORT_CODE(KEYCODE_U)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"/C\" Target") PORT_CODE(KEYCODE_I)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right Lane 1000") PORT_CODE(KEYCODE_O)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"/D\" Target") PORT_CODE(KEYCODE_A)
|
||||
|
||||
PORT_START("SWITCH.2")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Spinner") PORT_CODE(KEYCODE_S)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Spinner") PORT_CODE(KEYCODE_S)
|
||||
PORT_BIT(0x000e, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
|
||||
PORT_START("SWITCH.3")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("10's Target") PORT_CODE(KEYCODE_D)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("100's Target") PORT_CODE(KEYCODE_F)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Pot Bumper") PORT_CODE(KEYCODE_G)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("3000 Hole") PORT_CODE(KEYCODE_H)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("10's Target") PORT_CODE(KEYCODE_D)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("100's Target") PORT_CODE(KEYCODE_F)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Pot Bumper") PORT_CODE(KEYCODE_G)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("3000 Hole") PORT_CODE(KEYCODE_H)
|
||||
|
||||
PORT_START("SWITCH.4")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("1000 Bonus") PORT_CODE(KEYCODE_J)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("500 Target") PORT_CODE(KEYCODE_K)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Out Hole") PORT_CODE(KEYCODE_X)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("1000 Bonus") PORT_CODE(KEYCODE_J)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("500 Targets") PORT_CODE(KEYCODE_K)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Out Hole") PORT_CODE(KEYCODE_X)
|
||||
|
||||
PORT_START("SWITCH.5")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left 500 Out") PORT_CODE(KEYCODE_L)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left Bumper") PORT_CODE(KEYCODE_Z)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right 500 Out") PORT_CODE(KEYCODE_C)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right Bumper") PORT_CODE(KEYCODE_V)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left 500 Out") PORT_CODE(KEYCODE_L)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Left Bumper") PORT_CODE(KEYCODE_Z)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right 500 Out") PORT_CODE(KEYCODE_C)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Right Bumper") PORT_CODE(KEYCODE_V)
|
||||
|
||||
PORT_START("SWITCH.6")
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("A Target") PORT_CODE(KEYCODE_B)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("B target") PORT_CODE(KEYCODE_N)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("C target") PORT_CODE(KEYCODE_M)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("D Target") PORT_CODE(KEYCODE_COMMA)
|
||||
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"A\" Target") PORT_CODE(KEYCODE_B)
|
||||
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"B\" Target") PORT_CODE(KEYCODE_N)
|
||||
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"C\" Target") PORT_CODE(KEYCODE_M)
|
||||
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("\"D\" Target") PORT_CODE(KEYCODE_COMMA)
|
||||
|
||||
// TODO: what are the other things in this matrix? FIVE-BALL, STRAIGHT, 15K-110K, etc.
|
||||
INPUT_PORTS_END
|
||||
|
||||
READ8_MEMBER( flicker_state::port02_r )
|
||||
|
||||
READ8_MEMBER(flicker_state::rom2_in)
|
||||
{
|
||||
if (offset < 7)
|
||||
return m_switch[offset]->read();
|
||||
else
|
||||
return 0;
|
||||
return (m_switch.size() > m_mux_col) ? m_switch[m_mux_col]->read() : 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( flicker_state::port00_w )
|
||||
|
||||
WRITE_LINE_MEMBER(flicker_state::cm_ram1_w)
|
||||
{
|
||||
static const uint8_t patterns[16] = { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x6f, 0, 0, 0, 0, 0, 0 };
|
||||
output().set_digit_value(offset, patterns[data]);
|
||||
}
|
||||
static constexpr uint8_t led_digits[16] = { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x6f, 0, 0, 0, 0, 0, 0 };
|
||||
static constexpr char const *const lamp_matrix[][4] = {
|
||||
{ nullptr, "lamp_credit_lamp", "lamp_flippers", "lamp_special" },
|
||||
{ "lamp_a_lamp", "lamp_b_lamp", "lamp_c_lamp", "lamp_d_lamp" },
|
||||
{ "lamp_not_a_lamp", "lamp_not_b_lamp", "lamp_not_c_lamp", "lamp_not_d_lamp" },
|
||||
{ "lamp_left_extra_ball", "lamp_double_bonus", "lamp_shoot_again", "lamp_right_extra_ball" },
|
||||
{ "lamp_00_100s", "lamp_100", "lamp_200", "lamp_300" },
|
||||
{ "lamp_400", "lamp_500", "lamp_600", "lamp_700" },
|
||||
{ "lamp_800", "lamp_900", nullptr, nullptr },
|
||||
{ "lamp_point_00", "lamp_1000", "lamp_2000", "lamp_3000" },
|
||||
{ "lamp_4000", "lamp_5000", "lamp_6000", "lamp_7000" },
|
||||
{ "lamp_dummy_zero", "lamp_game_over", "lamp_tilt", "lamp_same_player_shoots" },
|
||||
{ "lamp_1_up", "lamp_2_up", "lamp_one_player", "lamp_two_player" } };
|
||||
|
||||
WRITE8_MEMBER( flicker_state::port01_w )
|
||||
{
|
||||
uint16_t test_port = m_testport->read() & 0xf81e;
|
||||
uint16_t coin_port = m_coinport->read() & 0x07e0;
|
||||
|
||||
if (BIT(m_coinport->read(), 0) )
|
||||
test_port |= coin_port;
|
||||
|
||||
m_maincpu->set_input_line(I4004_TEST_LINE, BIT(test_port, offset));
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( flicker_state::port10_w )
|
||||
{
|
||||
/* Outputs depend on data:
|
||||
1 = tens chime
|
||||
2 = hundreds chime
|
||||
3 = thousands chime
|
||||
4 = left bumper
|
||||
5 = right bumper
|
||||
6 = pot bumper
|
||||
7 = out hole
|
||||
8 = 3000 hole
|
||||
9 = knocker
|
||||
A = coin counter
|
||||
B = coin acceptor
|
||||
|
||||
The coin outputs (A and B) don't activate
|
||||
|
||||
A large amount of data is continuously flowing through here, even when there is no
|
||||
sound to produce. We need to change this to just one pulse per actual sound. */
|
||||
|
||||
offset &= 0x0f;
|
||||
if (data != offset)
|
||||
if (!m_cm_ram1 && !state)
|
||||
{
|
||||
if (data != m_out_data)
|
||||
m_mux_col = m_ram0_output;
|
||||
output().set_digit_value(m_mux_col, led_digits[m_rom0_output]);
|
||||
if (ARRAY_LENGTH(lamp_matrix) > m_mux_col)
|
||||
{
|
||||
m_out_data = data;
|
||||
switch (data)
|
||||
{
|
||||
case 0x01:
|
||||
m_samples->start(1, 1);
|
||||
break;
|
||||
case 0x02:
|
||||
m_samples->start(2, 2);
|
||||
break;
|
||||
case 0x03:
|
||||
m_samples->start(3, 3);
|
||||
break;
|
||||
case 0x04:
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
m_samples->start(0, 0);
|
||||
break;
|
||||
case 0x07:
|
||||
case 0x08:
|
||||
m_samples->start(5, 5);
|
||||
break;
|
||||
case 0x09:
|
||||
m_samples->start(0, 6);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if (lamp_matrix[m_mux_col][0])
|
||||
output().set_value(lamp_matrix[m_mux_col][0], BIT(m_rom1_output, 0));
|
||||
if (lamp_matrix[m_mux_col][1])
|
||||
output().set_value(lamp_matrix[m_mux_col][1], BIT(m_rom1_output, 1));
|
||||
if (lamp_matrix[m_mux_col][2])
|
||||
output().set_value(lamp_matrix[m_mux_col][2], BIT(m_rom1_output, 2));
|
||||
if (lamp_matrix[m_mux_col][3])
|
||||
output().set_value(lamp_matrix[m_mux_col][3], BIT(m_rom1_output, 3));
|
||||
}
|
||||
if (0x0c == m_mux_col)
|
||||
{
|
||||
// TODO: BIT(m_rom1_output, 0) -> COIN ACC.
|
||||
}
|
||||
// TODO: these should be hooked up to input changed members as well
|
||||
m_maincpu->set_input_line(I4004_TEST_LINE, BIT(m_testport->read(), m_mux_col));
|
||||
}
|
||||
m_cm_ram1 = !state;
|
||||
}
|
||||
|
||||
|
||||
CUSTOM_INPUT_MEMBER(flicker_state::coins_in)
|
||||
{
|
||||
u8 const coins(m_coinport->read());
|
||||
return BIT(coins, 7) ? (coins & 0x3f) : 0;
|
||||
}
|
||||
|
||||
|
||||
WRITE_LINE_MEMBER(flicker_state::cm_ram2_w)
|
||||
{
|
||||
if (!m_cm_ram2 && !state && (m_relay_drive != m_ram0_output))
|
||||
{
|
||||
// The coin outputs (A and B) aren't used
|
||||
switch (m_relay_drive = m_ram0_output)
|
||||
{
|
||||
case 0x01: // 10 chime
|
||||
m_samples->start(1, 1);
|
||||
break;
|
||||
case 0x02: // 100 chime
|
||||
m_samples->start(2, 2);
|
||||
break;
|
||||
case 0x03: // 1000 chime
|
||||
m_samples->start(3, 3);
|
||||
break;
|
||||
case 0x04: // left bumper
|
||||
case 0x05: // right bumper
|
||||
case 0x06: // pot bumper
|
||||
m_samples->start(0, 0);
|
||||
break;
|
||||
case 0x07: // out hole
|
||||
case 0x08: // 3000 hole
|
||||
m_samples->start(5, 5);
|
||||
break;
|
||||
case 0x09: // door knocker
|
||||
m_samples->start(0, 6);
|
||||
break;
|
||||
case 0x0a: // coin counter
|
||||
logerror("coin counter\n");
|
||||
break;
|
||||
case 0x0b: // coin acceptor
|
||||
logerror("coin acceptor\n");
|
||||
break;
|
||||
default: // 0/C/D/E/F not connected
|
||||
break;
|
||||
}
|
||||
}
|
||||
m_cm_ram2 = !state;
|
||||
}
|
||||
|
||||
|
||||
static MACHINE_CONFIG_START( flicker )
|
||||
/* basic machine hardware */
|
||||
static MACHINE_CONFIG_START(flicker)
|
||||
// basic machine hardware
|
||||
MCFG_CPU_ADD("maincpu", I4004, XTAL_5MHz / 8)
|
||||
MCFG_CPU_DECRYPTED_OPCODES_MAP(flicker_rom)
|
||||
MCFG_CPU_DATA_MAP(flicker_map)
|
||||
MCFG_CPU_IO_MAP(flicker_io)
|
||||
MCFG_NVRAM_ADD_0FILL("nvram")
|
||||
MCFG_I4004_ROM_MAP(flicker_rom)
|
||||
MCFG_I4004_RAM_MEMORY_MAP(flicker_memory)
|
||||
MCFG_I4004_ROM_PORTS_MAP(flicker_rom_ports)
|
||||
MCFG_I4004_RAM_STATUS_MAP(flicker_status)
|
||||
MCFG_I4004_RAM_PORTS_MAP(flicker_ram_ports)
|
||||
MCFG_I4004_CM_RAM1_CB(WRITELINE(flicker_state, cm_ram1_w))
|
||||
MCFG_I4004_CM_RAM2_CB(WRITELINE(flicker_state, cm_ram2_w))
|
||||
|
||||
/* Video */
|
||||
MCFG_NVRAM_ADD_0FILL("memory")
|
||||
MCFG_NVRAM_ADD_0FILL("status")
|
||||
|
||||
// video
|
||||
MCFG_DEFAULT_LAYOUT(layout_flicker)
|
||||
|
||||
/* Sound */
|
||||
MCFG_FRAGMENT_ADD( genpin_audio )
|
||||
// sound
|
||||
MCFG_FRAGMENT_ADD(genpin_audio)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
ROM_START(flicker)
|
||||
ROM_REGION(0x10000, "maincpu", 0)
|
||||
ROM_REGION(0x0400, "maincpu", 0)
|
||||
ROM_LOAD("flicker.rom", 0x0000, 0x0400, CRC(c692e586) SHA1(5cabb28a074d18b589b5b8f700c57e1610071c68))
|
||||
ROM_END
|
||||
|
||||
// YEAR GAME PARENT MACHINE INPUT CLASS INIT ORIENTATION COMPANY DESCRIPTION FLAGS
|
||||
GAME(1974, flicker, 0, flicker, flicker, flicker_state, 0, ROT0, "Dave Nutting Associates / Bally", "Flicker (prototype)", MACHINE_MECHANICAL | MACHINE_NOT_WORKING )
|
||||
// YEAR GAME PARENT MACHINE INPUT CLASS INIT ORIENTATION COMPANY DESCRIPTION FLAGS
|
||||
GAME( 1974, flicker, 0, flicker, flicker, flicker_state, 0, ROT0, "Dave Nutting Associates / Bally", "Flicker (prototype)", MACHINE_MECHANICAL | MACHINE_NOT_WORKING )
|
||||
|
||||
@ -14,6 +14,8 @@
|
||||
#include "cpu/mcs40/mcs40.h"
|
||||
#include "machine/bankdev.h"
|
||||
|
||||
#include "intlc440.lh"
|
||||
|
||||
|
||||
namespace {
|
||||
|
||||
@ -24,11 +26,15 @@ public:
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_cpu(*this, "maincpu")
|
||||
, m_program_banks(*this, "prgbank")
|
||||
, m_io_banks(*this, "iobank")
|
||||
, m_rom_port_banks(*this, "rpbank")
|
||||
, m_ram_port_banks(*this, "mpbank")
|
||||
, m_bus(*this, "bus")
|
||||
, m_tty(*this, "tty")
|
||||
, m_ram(*this, "ram")
|
||||
, m_sw_mode(*this, "MODE")
|
||||
, m_sw_control(*this, "CONTROL")
|
||||
, m_sw_addr_data(*this, "ADDRDAT")
|
||||
, m_sw_passes(*this, "PASSES")
|
||||
{
|
||||
}
|
||||
|
||||
@ -45,6 +51,7 @@ public:
|
||||
DECLARE_WRITE8_MEMBER(ram0_out);
|
||||
DECLARE_WRITE8_MEMBER(ram1_out);
|
||||
|
||||
void bus_cycle(mcs40_cpu_device_base::phase step, u8 sync, u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(stp_ack);
|
||||
|
||||
// universal slot outputs
|
||||
@ -53,13 +60,20 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(bus_reset_4002);
|
||||
DECLARE_WRITE_LINE_MEMBER(bus_user_reset);
|
||||
|
||||
// edge-sensitive front-panel switches
|
||||
// front panel switches
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_stop);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_single_step);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_reset);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_mon);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_ram);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_prom);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_run);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_next_inst);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_decr);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_incr);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_load);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_cma_enable);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(sw_cma_write);
|
||||
|
||||
protected:
|
||||
virtual void driver_start() override;
|
||||
@ -82,7 +96,15 @@ private:
|
||||
BIT_SW_RESET,
|
||||
BIT_SW_MON,
|
||||
BIT_SW_RAM,
|
||||
BIT_SW_PROM
|
||||
BIT_SW_PROM,
|
||||
|
||||
BIT_SW_RUN = 0,
|
||||
BIT_SW_NEXT_INST,
|
||||
BIT_SW_DECR,
|
||||
BIT_SW_INCR,
|
||||
BIT_SW_LOAD,
|
||||
BIT_SW_CMA_ENABLE,
|
||||
BIT_SW_CMA_WRITE
|
||||
};
|
||||
enum : ioport_value
|
||||
{
|
||||
@ -91,22 +113,34 @@ private:
|
||||
MASK_SW_RESET = 1U << BIT_SW_RESET,
|
||||
MASK_SW_MON = 1U << BIT_SW_MON,
|
||||
MASK_SW_RAM = 1U << BIT_SW_RAM,
|
||||
MASK_SW_PROM = 1U << BIT_SW_PROM
|
||||
MASK_SW_PROM = 1U << BIT_SW_PROM,
|
||||
|
||||
MASK_SW_DECR = 1U << BIT_SW_DECR,
|
||||
MASK_SW_INCR = 1U << BIT_SW_INCR,
|
||||
MASK_SW_LOAD = 1U << BIT_SW_LOAD,
|
||||
MASK_SW_CMA_ENABLE = 1U << BIT_SW_CMA_ENABLE,
|
||||
MASK_SW_CMA_WRITE = 1U << BIT_SW_CMA_WRITE
|
||||
};
|
||||
|
||||
TIMER_CALLBACK_MEMBER(single_step_expired);
|
||||
TIMER_CALLBACK_MEMBER(reset_expired);
|
||||
|
||||
void trigger_reset();
|
||||
void reset_panel();
|
||||
void display_address(u16 value, u16 mask);
|
||||
void display_instruction(u8 value, u8 mask);
|
||||
void display_active_bank(u8 value);
|
||||
void display_execution(u8 value, u8 mask);
|
||||
void display_pointer(u8 value, u8 mask);
|
||||
|
||||
required_device<cpu_device> m_cpu;
|
||||
required_device<address_map_bank_device> m_program_banks, m_io_banks;
|
||||
required_device<mcs40_cpu_device_base> m_cpu;
|
||||
required_device<address_map_bank_device> m_program_banks, m_rom_port_banks, m_ram_port_banks;
|
||||
required_device<bus::intellec4::univ_bus_device> m_bus;
|
||||
required_device<rs232_port_device> m_tty;
|
||||
|
||||
required_shared_ptr<u8> m_ram;
|
||||
|
||||
required_ioport m_sw_mode;
|
||||
required_ioport m_sw_mode, m_sw_control, m_sw_addr_data, m_sw_passes;
|
||||
|
||||
emu_timer *m_single_step_timer = nullptr;
|
||||
emu_timer *m_reset_timer = nullptr;
|
||||
@ -116,9 +150,18 @@ private:
|
||||
bool m_ram_write = false;
|
||||
|
||||
// control board state
|
||||
bool m_stp_ack = false, m_single_step = false;
|
||||
bool m_stp_ack = false, m_single_step = false, m_cpu_reset = false;
|
||||
bool m_ff_mon = true, m_ff_ram = false, m_ff_prom = false;
|
||||
|
||||
// front panel state
|
||||
u16 m_latched_addr = 0U, m_display_addr = 0U;
|
||||
u8 m_display_instr = 0U, m_display_bank = 0U, m_display_exec = 0U, m_display_ptr = 0U;
|
||||
u8 m_pass_counter = 0U;
|
||||
bool m_panel_reset = false;
|
||||
bool m_next_inst = false, m_adr_cmp_latch = false, m_search_complete = false;
|
||||
bool m_src = false, m_pointer_valid = false;
|
||||
bool m_cma_enable = false, m_cma_write = false;
|
||||
|
||||
// current state of signals from bus
|
||||
bool m_bus_stop = false, m_bus_reset_4002 = false, m_bus_user_reset = false;
|
||||
|
||||
@ -126,6 +169,7 @@ private:
|
||||
bool m_sw_stop = false;
|
||||
bool m_sw_reset = false;
|
||||
bool m_sw_mon = false, m_sw_ram = false, m_sw_prom = false;
|
||||
bool m_sw_run = false;
|
||||
};
|
||||
|
||||
|
||||
@ -196,6 +240,83 @@ WRITE8_MEMBER(intellec4_40_state::ram1_out)
|
||||
m_tty->write_rts(BIT(~data, 0));
|
||||
}
|
||||
|
||||
void intellec4_40_state::bus_cycle(mcs40_cpu_device_base::phase step, u8 sync, u8 data)
|
||||
{
|
||||
switch (step)
|
||||
{
|
||||
case mcs40_cpu_device_base::phase::A1:
|
||||
if (m_cma_enable)
|
||||
{
|
||||
display_address(m_latched_addr, 0x0fffU);
|
||||
display_instruction(m_ram[m_latched_addr], 0xffU);
|
||||
}
|
||||
else if (!m_search_complete)
|
||||
{
|
||||
display_address(u16(data), 0x000fU);
|
||||
m_src = false;
|
||||
}
|
||||
if (m_cma_write)
|
||||
{
|
||||
m_ram[m_latched_addr] = u8(~m_sw_addr_data->read() & 0x00ffU);
|
||||
m_cma_write = false;
|
||||
}
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::A2:
|
||||
if (!m_search_complete && !m_cma_enable)
|
||||
display_address(u16(data) << 4, 0x00f0U);
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::A3:
|
||||
if (!m_search_complete && !m_cma_enable)
|
||||
{
|
||||
display_address(u16(data) << 8, 0x0f00U);
|
||||
display_active_bank(~m_cpu->get_cm_ram());
|
||||
}
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::M1:
|
||||
if (!m_search_complete && !m_cma_enable)
|
||||
display_instruction(data << 4, 0xf0U);
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::M2:
|
||||
if (!m_search_complete && !m_cma_enable)
|
||||
display_instruction(data, 0x0fU);
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::X1:
|
||||
// not connected to anything
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::X2:
|
||||
if (!m_search_complete && !m_cma_enable)
|
||||
{
|
||||
display_execution(data << 4, 0xf0U);
|
||||
m_src = BIT(~m_cpu->get_cm_rom(), 0);
|
||||
if (m_src)
|
||||
display_pointer(data << 4, 0xf0U);
|
||||
}
|
||||
break;
|
||||
case mcs40_cpu_device_base::phase::X3:
|
||||
if (m_search_complete != m_adr_cmp_latch)
|
||||
machine().output().set_value("led_status_search", m_search_complete = m_adr_cmp_latch);
|
||||
if (!m_search_complete && !m_cma_enable)
|
||||
{
|
||||
display_execution(data, 0x0fU);
|
||||
if (m_src)
|
||||
{
|
||||
display_pointer(data, 0x0fU);
|
||||
if (!m_panel_reset && !m_pointer_valid)
|
||||
machine().output().set_value("led_status_ptr_valid", m_pointer_valid = true);
|
||||
}
|
||||
}
|
||||
if (!m_panel_reset && !m_adr_cmp_latch)
|
||||
m_adr_cmp_latch = (m_latched_addr == m_display_addr) && !((m_pass_counter ^ m_sw_passes->read()) & 0x0fU);
|
||||
if (!m_search_complete && !m_panel_reset && !m_cma_enable && !m_sw_run && (m_latched_addr == m_display_addr))
|
||||
m_pass_counter = (m_pass_counter + 1U) & 0x0fU;
|
||||
if (m_adr_cmp_latch && !m_next_inst && !m_search_complete)
|
||||
machine().output().set_value("led_status_search", m_search_complete = true);
|
||||
if (!m_cpu_reset && !m_cma_enable && !m_sw_run)
|
||||
m_panel_reset = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(intellec4_40_state::stp_ack)
|
||||
{
|
||||
// resets the single-step monostable
|
||||
@ -287,7 +408,8 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_mon)
|
||||
if (!m_ff_mon)
|
||||
{
|
||||
m_program_banks->set_bank(BANK_PRG_MON);
|
||||
m_io_banks->set_bank(BANK_IO_MON);
|
||||
m_rom_port_banks->set_bank(BANK_IO_MON);
|
||||
m_ram_port_banks->set_bank(BANK_IO_MON);
|
||||
machine().output().set_value("led_mode_mon", m_ff_mon = true);
|
||||
}
|
||||
trigger_reset();
|
||||
@ -295,7 +417,8 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_mon)
|
||||
else
|
||||
{
|
||||
m_program_banks->set_bank(BANK_PRG_NONE);
|
||||
m_io_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_rom_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_ram_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
}
|
||||
if (m_ff_ram)
|
||||
machine().output().set_value("led_mode_ram", m_ff_ram = false);
|
||||
@ -314,7 +437,8 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_ram)
|
||||
if (!m_ff_ram)
|
||||
{
|
||||
m_program_banks->set_bank(BANK_PRG_RAM);
|
||||
m_io_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_rom_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_ram_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
machine().output().set_value("led_mode_ram", m_ff_ram = true);
|
||||
}
|
||||
trigger_reset();
|
||||
@ -322,7 +446,8 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_ram)
|
||||
else
|
||||
{
|
||||
m_program_banks->set_bank(BANK_PRG_NONE);
|
||||
m_io_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_rom_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_ram_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
}
|
||||
if (m_ff_mon)
|
||||
machine().output().set_value("led_mode_mon", m_ff_mon = false);
|
||||
@ -341,7 +466,8 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_prom)
|
||||
if (!m_ff_prom)
|
||||
{
|
||||
m_program_banks->set_bank(BANK_PRG_PROM);
|
||||
m_io_banks->set_bank(BANK_IO_PROM);
|
||||
m_rom_port_banks->set_bank(BANK_IO_PROM);
|
||||
m_ram_port_banks->set_bank(BANK_IO_PROM);
|
||||
machine().output().set_value("led_mode_prom", m_ff_prom = true);
|
||||
}
|
||||
trigger_reset();
|
||||
@ -349,7 +475,8 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_prom)
|
||||
else
|
||||
{
|
||||
m_program_banks->set_bank(BANK_PRG_NONE);
|
||||
m_io_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_rom_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
m_ram_port_banks->set_bank(BANK_IO_NEITHER);
|
||||
}
|
||||
if (m_ff_mon)
|
||||
machine().output().set_value("led_mode_mon", m_ff_mon = false);
|
||||
@ -359,6 +486,61 @@ INPUT_CHANGED_MEMBER(intellec4_40_state::sw_prom)
|
||||
m_sw_prom = !bool(newval);
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_run)
|
||||
{
|
||||
m_sw_run = !bool(newval);
|
||||
if (m_sw_run)
|
||||
reset_panel();
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_next_inst)
|
||||
{
|
||||
m_next_inst = !bool(newval);
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_decr)
|
||||
{
|
||||
// connected to a pulse generator circuit
|
||||
if (newval && !oldval)
|
||||
{
|
||||
m_latched_addr = (m_latched_addr - 1U) & 0x0fffU;
|
||||
reset_panel();
|
||||
}
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_incr)
|
||||
{
|
||||
// connected to a pulse generator circuit
|
||||
if (newval && !oldval)
|
||||
{
|
||||
m_latched_addr = (m_latched_addr + 1U) & 0x0fffU;
|
||||
reset_panel();
|
||||
}
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_load)
|
||||
{
|
||||
// connected to a pulse generator circuit
|
||||
if (newval && !oldval)
|
||||
{
|
||||
m_latched_addr = ~m_sw_addr_data->read() & 0x0fffU;
|
||||
reset_panel();
|
||||
}
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_cma_enable)
|
||||
{
|
||||
m_cma_enable = bool(newval);
|
||||
if (m_cma_enable)
|
||||
reset_panel();
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(intellec4_40_state::sw_cma_write)
|
||||
{
|
||||
if (newval && !oldval)
|
||||
m_cma_write = m_cma_enable;
|
||||
}
|
||||
|
||||
|
||||
void intellec4_40_state::driver_start()
|
||||
{
|
||||
@ -371,10 +553,27 @@ void intellec4_40_state::driver_start()
|
||||
|
||||
save_item(NAME(m_stp_ack));
|
||||
save_item(NAME(m_single_step));
|
||||
save_item(NAME(m_cpu_reset));
|
||||
save_item(NAME(m_ff_mon));
|
||||
save_item(NAME(m_ff_ram));
|
||||
save_item(NAME(m_ff_prom));
|
||||
|
||||
save_item(NAME(m_latched_addr));
|
||||
save_item(NAME(m_display_addr));
|
||||
save_item(NAME(m_display_instr));
|
||||
save_item(NAME(m_display_bank));
|
||||
save_item(NAME(m_display_exec));
|
||||
save_item(NAME(m_display_ptr));
|
||||
save_item(NAME(m_pass_counter));
|
||||
save_item(NAME(m_next_inst));
|
||||
save_item(NAME(m_panel_reset));
|
||||
save_item(NAME(m_adr_cmp_latch));
|
||||
save_item(NAME(m_search_complete));
|
||||
save_item(NAME(m_src));
|
||||
save_item(NAME(m_pointer_valid));
|
||||
save_item(NAME(m_cma_enable));
|
||||
save_item(NAME(m_cma_write));
|
||||
|
||||
save_item(NAME(m_bus_stop));
|
||||
save_item(NAME(m_bus_reset_4002));
|
||||
save_item(NAME(m_bus_user_reset));
|
||||
@ -383,6 +582,7 @@ void intellec4_40_state::driver_start()
|
||||
save_item(NAME(m_sw_reset));
|
||||
save_item(NAME(m_sw_mon));
|
||||
save_item(NAME(m_sw_ram));
|
||||
save_item(NAME(m_sw_run));
|
||||
|
||||
m_stp_ack = m_single_step = false;
|
||||
m_ff_mon = true;
|
||||
@ -392,15 +592,26 @@ void intellec4_40_state::driver_start()
|
||||
void intellec4_40_state::driver_reset()
|
||||
{
|
||||
// set stuff according to initial state of front panel
|
||||
ioport_value const sw_mode(m_sw_mode->read());
|
||||
m_sw_stop = BIT(~sw_mode, BIT_SW_STOP);
|
||||
m_sw_reset = BIT(~sw_mode, BIT_SW_RESET);
|
||||
m_sw_mon = BIT(~sw_mode, BIT_SW_MON);
|
||||
m_sw_ram = BIT(~sw_mode, BIT_SW_RAM);
|
||||
m_sw_prom = BIT(~sw_mode, BIT_SW_PROM);
|
||||
ioport_value const sw_mode(m_sw_mode->read()), sw_control(m_sw_control->read());
|
||||
m_sw_stop = BIT(~sw_mode, BIT_SW_STOP);
|
||||
m_sw_reset = BIT(~sw_mode, BIT_SW_RESET);
|
||||
m_sw_mon = BIT(~sw_mode, BIT_SW_MON);
|
||||
m_sw_ram = BIT(~sw_mode, BIT_SW_RAM);
|
||||
m_sw_prom = BIT(~sw_mode, BIT_SW_PROM);
|
||||
m_sw_run = BIT(~sw_control, BIT_SW_RUN);
|
||||
m_next_inst = BIT(~sw_control, BIT_SW_NEXT_INST);
|
||||
m_cma_enable = BIT( sw_control, BIT_SW_CMA_ENABLE);
|
||||
m_ff_mon = m_ff_mon && !m_sw_ram && !m_sw_prom;
|
||||
m_ff_ram = m_ff_ram && !m_sw_mon && !m_sw_prom;
|
||||
m_ff_prom = m_ff_prom && !m_sw_mon && !m_sw_ram;
|
||||
m_panel_reset = m_panel_reset || m_cma_enable || m_sw_run;
|
||||
if (m_panel_reset)
|
||||
{
|
||||
m_pass_counter = 0U;
|
||||
m_adr_cmp_latch = false;
|
||||
m_search_complete = m_search_complete && m_next_inst;
|
||||
m_pointer_valid = false;
|
||||
}
|
||||
|
||||
// ensure we're consistent with the state of the bus
|
||||
m_bus_stop = 0 == m_bus->stop_out();
|
||||
@ -408,16 +619,20 @@ void intellec4_40_state::driver_reset()
|
||||
m_bus_user_reset = 0 == m_bus->user_reset_out();
|
||||
|
||||
// ensure device inputs are all in the correct state
|
||||
m_cpu->set_input_line(INPUT_LINE_RESET, m_cpu_reset ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_cpu->set_input_line(I4040_TEST_LINE, m_bus->test_out() ? CLEAR_LINE : ASSERT_LINE);
|
||||
m_cpu->set_input_line(I4040_STP_LINE, ((m_sw_stop && !m_single_step) || m_bus_stop) ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_bus->test_in(1);
|
||||
m_bus->stop_in((m_sw_stop && !m_single_step) ? 0 : 1);
|
||||
m_bus->cpu_reset_in(m_cpu_reset ? 0 : 1);
|
||||
|
||||
// set front panel LEDs
|
||||
machine().output().set_value("led_status_run", !m_stp_ack);
|
||||
machine().output().set_value("led_mode_mon", m_ff_mon);
|
||||
machine().output().set_value("led_mode_ram", m_ff_ram);
|
||||
machine().output().set_value("led_mode_prom", m_ff_prom);
|
||||
machine().output().set_value("led_status_ptr_valid", m_pointer_valid);
|
||||
machine().output().set_value("led_status_run", !m_stp_ack);
|
||||
machine().output().set_value("led_status_search", m_search_complete);
|
||||
machine().output().set_value("led_mode_mon", m_ff_mon);
|
||||
machine().output().set_value("led_mode_ram", m_ff_ram);
|
||||
machine().output().set_value("led_mode_prom", m_ff_prom);
|
||||
}
|
||||
|
||||
|
||||
@ -434,9 +649,13 @@ TIMER_CALLBACK_MEMBER(intellec4_40_state::single_step_expired)
|
||||
|
||||
TIMER_CALLBACK_MEMBER(intellec4_40_state::reset_expired)
|
||||
{
|
||||
m_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
|
||||
m_bus->cpu_reset_in(1);
|
||||
// FIXME: can cause 4002 reset as well
|
||||
if (m_cpu_reset)
|
||||
{
|
||||
m_cpu_reset = false;
|
||||
m_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
|
||||
m_bus->cpu_reset_in(1);
|
||||
// FIXME: can cause 4002 reset as well
|
||||
}
|
||||
}
|
||||
|
||||
void intellec4_40_state::trigger_reset()
|
||||
@ -447,14 +666,143 @@ void intellec4_40_state::trigger_reset()
|
||||
// 9602 with Rx = 27kΩ, Cx = 0.1µF
|
||||
// K * Rx(kΩ) * Cx(pF) * (1 + (1 / Rx(kΩ))) = 0.34 * 27 * 100000 * (1 + (1 / 27)) = 952000ns
|
||||
m_reset_timer->adjust(attotime::from_usec(952));
|
||||
m_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
|
||||
m_bus->cpu_reset_in(0);
|
||||
// FIXME: can cause 4002 reset as well
|
||||
if (!m_cpu_reset)
|
||||
{
|
||||
m_cpu_reset = true;
|
||||
m_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
|
||||
m_bus->cpu_reset_in(0);
|
||||
reset_panel();
|
||||
// FIXME: can cause 4002 reset as well
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void intellec4_40_state::reset_panel()
|
||||
{
|
||||
if (!m_panel_reset)
|
||||
{
|
||||
m_pass_counter = 0U;
|
||||
m_panel_reset = true;
|
||||
m_adr_cmp_latch = false;
|
||||
if (m_search_complete && !m_next_inst)
|
||||
machine().output().set_value("led_status_search", m_search_complete = false);
|
||||
if (m_pointer_valid)
|
||||
machine().output().set_value("led_status_ptr_valid", m_pointer_valid = false);
|
||||
}
|
||||
}
|
||||
|
||||
ADDRESS_MAP_START(mod40_program_banks, AS_OPCODES, 8, intellec4_40_state)
|
||||
void intellec4_40_state::display_address(u16 value, u16 mask)
|
||||
{
|
||||
u16 const diff((value ^ m_display_addr) & mask);
|
||||
m_display_addr ^= diff;
|
||||
if (BIT(diff, 0))
|
||||
machine().output().set_value("led_address_a1_0", BIT(value, 0));
|
||||
if (BIT(diff, 1))
|
||||
machine().output().set_value("led_address_a1_1", BIT(value, 1));
|
||||
if (BIT(diff, 2))
|
||||
machine().output().set_value("led_address_a1_2", BIT(value, 2));
|
||||
if (BIT(diff, 3))
|
||||
machine().output().set_value("led_address_a1_3", BIT(value, 3));
|
||||
if (BIT(diff, 4))
|
||||
machine().output().set_value("led_address_a2_0", BIT(value, 4));
|
||||
if (BIT(diff, 5))
|
||||
machine().output().set_value("led_address_a2_1", BIT(value, 5));
|
||||
if (BIT(diff, 6))
|
||||
machine().output().set_value("led_address_a2_2", BIT(value, 6));
|
||||
if (BIT(diff, 7))
|
||||
machine().output().set_value("led_address_a2_3", BIT(value, 7));
|
||||
if (BIT(diff, 8))
|
||||
machine().output().set_value("led_address_a3_0", BIT(value, 8));
|
||||
if (BIT(diff, 9))
|
||||
machine().output().set_value("led_address_a3_1", BIT(value, 9));
|
||||
if (BIT(diff, 10))
|
||||
machine().output().set_value("led_address_a3_2", BIT(value, 10));
|
||||
if (BIT(diff, 11))
|
||||
machine().output().set_value("led_address_a3_3", BIT(value, 11));
|
||||
}
|
||||
|
||||
void intellec4_40_state::display_instruction(u8 value, u8 mask)
|
||||
{
|
||||
u16 const diff((value ^ m_display_instr) & mask);
|
||||
m_display_instr ^= diff;
|
||||
if (BIT(diff, 0))
|
||||
machine().output().set_value("led_instruction_m2_0", BIT(value, 0));
|
||||
if (BIT(diff, 1))
|
||||
machine().output().set_value("led_instruction_m2_1", BIT(value, 1));
|
||||
if (BIT(diff, 2))
|
||||
machine().output().set_value("led_instruction_m2_2", BIT(value, 2));
|
||||
if (BIT(diff, 3))
|
||||
machine().output().set_value("led_instruction_m2_3", BIT(value, 3));
|
||||
if (BIT(diff, 4))
|
||||
machine().output().set_value("led_instruction_m1_0", BIT(value, 4));
|
||||
if (BIT(diff, 5))
|
||||
machine().output().set_value("led_instruction_m1_1", BIT(value, 5));
|
||||
if (BIT(diff, 6))
|
||||
machine().output().set_value("led_instruction_m1_2", BIT(value, 6));
|
||||
if (BIT(diff, 7))
|
||||
machine().output().set_value("led_instruction_m1_3", BIT(value, 7));
|
||||
}
|
||||
|
||||
void intellec4_40_state::display_active_bank(u8 value)
|
||||
{
|
||||
u8 const diff((value ^ m_display_bank) & 0x0fU);
|
||||
m_display_bank ^= diff;
|
||||
if (BIT(diff, 0))
|
||||
machine().output().set_value("led_active_bank_0", BIT(value, 0));
|
||||
if (BIT(diff, 1))
|
||||
machine().output().set_value("led_active_bank_1", BIT(value, 1));
|
||||
if (BIT(diff, 2))
|
||||
machine().output().set_value("led_active_bank_2", BIT(value, 2));
|
||||
if (BIT(diff, 3))
|
||||
machine().output().set_value("led_active_bank_3", BIT(value, 3));
|
||||
}
|
||||
|
||||
void intellec4_40_state::display_execution(u8 value, u8 mask)
|
||||
{
|
||||
u16 const diff((value ^ m_display_exec) & mask);
|
||||
m_display_exec ^= diff;
|
||||
if (BIT(diff, 0))
|
||||
machine().output().set_value("led_execution_x3_0", BIT(value, 0));
|
||||
if (BIT(diff, 1))
|
||||
machine().output().set_value("led_execution_x3_1", BIT(value, 1));
|
||||
if (BIT(diff, 2))
|
||||
machine().output().set_value("led_execution_x3_2", BIT(value, 2));
|
||||
if (BIT(diff, 3))
|
||||
machine().output().set_value("led_execution_x3_3", BIT(value, 3));
|
||||
if (BIT(diff, 4))
|
||||
machine().output().set_value("led_execution_x2_0", BIT(value, 4));
|
||||
if (BIT(diff, 5))
|
||||
machine().output().set_value("led_execution_x2_1", BIT(value, 5));
|
||||
if (BIT(diff, 6))
|
||||
machine().output().set_value("led_execution_x2_2", BIT(value, 6));
|
||||
if (BIT(diff, 7))
|
||||
machine().output().set_value("led_execution_x2_3", BIT(value, 7));
|
||||
}
|
||||
|
||||
void intellec4_40_state::display_pointer(u8 value, u8 mask)
|
||||
{
|
||||
u16 const diff((value ^ m_display_ptr) & mask);
|
||||
m_display_ptr ^= diff;
|
||||
if (BIT(diff, 0))
|
||||
machine().output().set_value("led_last_ptr_x3_0", BIT(value, 0));
|
||||
if (BIT(diff, 1))
|
||||
machine().output().set_value("led_last_ptr_x3_1", BIT(value, 1));
|
||||
if (BIT(diff, 2))
|
||||
machine().output().set_value("led_last_ptr_x3_2", BIT(value, 2));
|
||||
if (BIT(diff, 3))
|
||||
machine().output().set_value("led_last_ptr_x3_3", BIT(value, 3));
|
||||
if (BIT(diff, 4))
|
||||
machine().output().set_value("led_last_ptr_x2_0", BIT(value, 4));
|
||||
if (BIT(diff, 5))
|
||||
machine().output().set_value("led_last_ptr_x2_1", BIT(value, 5));
|
||||
if (BIT(diff, 6))
|
||||
machine().output().set_value("led_last_ptr_x2_2", BIT(value, 6));
|
||||
if (BIT(diff, 7))
|
||||
machine().output().set_value("led_last_ptr_x2_3", BIT(value, 7));
|
||||
}
|
||||
|
||||
|
||||
ADDRESS_MAP_START(mod40_program_banks, mcs40_cpu_device_base::AS_ROM, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
|
||||
// 0x0000...0x0fff MON
|
||||
@ -468,57 +816,73 @@ ADDRESS_MAP_START(mod40_program_banks, AS_OPCODES, 8, intellec4_40_state)
|
||||
// 0x3000...0x3fff unmapped in case someone presses two mode switches at once
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START(mod40_io_banks, AS_PROGRAM, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_START(mod40_rom_port_banks, mcs40_cpu_device_base::AS_ROM_PORTS, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
|
||||
// 0x0000...0x0fff ROM ports - MON
|
||||
AM_RANGE(0x0000, 0x000f) AM_MIRROR(0x6700) AM_READ(rom0_in)
|
||||
AM_RANGE(0x00e0, 0x00ef) AM_MIRROR(0x6700) AM_READWRITE(rome_in, rome_out)
|
||||
AM_RANGE(0x00f0, 0x00ff) AM_MIRROR(0x6700) AM_READWRITE(romf_in, romf_out)
|
||||
// 0x0000...0x0fff MON
|
||||
AM_RANGE(0x0000, 0x000f) AM_MIRROR(0x3700) AM_READ(rom0_in)
|
||||
AM_RANGE(0x00e0, 0x00ef) AM_MIRROR(0x3700) AM_READWRITE(rome_in, rome_out)
|
||||
AM_RANGE(0x00f0, 0x00ff) AM_MIRROR(0x3700) AM_READWRITE(romf_in, romf_out)
|
||||
|
||||
// 0x1000...0x1fff RAM ports - MON
|
||||
AM_RANGE(0x1000, 0x103f) AM_MIRROR(0x6800) AM_WRITE(ram0_out)
|
||||
AM_RANGE(0x1040, 0x107f) AM_MIRROR(0x6800) AM_WRITE(ram1_out)
|
||||
// 0x1000...0x1fff neither
|
||||
|
||||
// 0x2000...0x2fff ROM ports - neither
|
||||
// 0x2000...0x2fff PROM
|
||||
|
||||
// 0x3000...0x3fff RAM ports - neither
|
||||
// 0x3000...0x3fff unused
|
||||
ADDRESS_MAP_END
|
||||
|
||||
// 0x4000...0x4fff ROM ports - PROM
|
||||
ADDRESS_MAP_START(mod40_ram_port_banks, mcs40_cpu_device_base::AS_RAM_PORTS, 8, intellec4_40_state)
|
||||
// 0x00...0x1f MON
|
||||
AM_RANGE(0x00, 0x00) AM_MIRROR(0x60) AM_WRITE(ram0_out)
|
||||
AM_RANGE(0x00, 0x01) AM_MIRROR(0x60) AM_WRITE(ram1_out)
|
||||
|
||||
// 0x5000...0x5fff RAM ports - PROM
|
||||
// 0x20...0x3f neither
|
||||
|
||||
// 0x6000...0x7fff unused
|
||||
// 0x40...0x5f PROM
|
||||
|
||||
// 0x60...0x7f unused
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
ADDRESS_MAP_START(mod40_program, AS_PROGRAM, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_START(mod40_rom, mcs40_cpu_device_base::AS_ROM, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
AM_RANGE(0x0000, 0x01ff) AM_READWRITE(pm_read, pm_write)
|
||||
AM_RANGE(0x0000, 0x0fff) AM_DEVICE("prgbank", address_map_bank_device, amap8)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START(mod40_data, AS_DATA, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_START(mod40_ram_memory, mcs40_cpu_device_base::AS_RAM_MEMORY, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
AM_RANGE(0x0000, 0x00ff) AM_RAM // 4 * 4002
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START(mod40_io, AS_IO, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_START(mod40_rom_ports, mcs40_cpu_device_base::AS_ROM_PORTS, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
AM_RANGE(0x0000, 0x1fff) AM_DEVICE("iobank", address_map_bank_device, amap8)
|
||||
AM_RANGE(0x0000, 0x0fff) AM_DEVICE("rpbank", address_map_bank_device, amap8)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START(mod40_opcodes, AS_OPCODES, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_START(mod40_ram_status, mcs40_cpu_device_base::AS_RAM_STATUS, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
AM_RANGE(0x0000, 0x0fff) AM_DEVICE("prgbank", address_map_bank_device, amap8)
|
||||
AM_RANGE(0x0000, 0x003f) AM_RAM // 4 * 4002
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START(mod40_ram_ports, mcs40_cpu_device_base::AS_RAM_PORTS, 8, intellec4_40_state)
|
||||
AM_RANGE(0x00, 0x1f) AM_DEVICE("mpbank", address_map_bank_device, amap8)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START(mod40_program_memory, mcs40_cpu_device_base::AS_PROGRAM_MEMORY, 8, intellec4_40_state)
|
||||
ADDRESS_MAP_UNMAP_LOW
|
||||
AM_RANGE(0x0000, 0x01ff) AM_READWRITE(pm_read, pm_write)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
MACHINE_CONFIG_START(intlc440)
|
||||
MCFG_CPU_ADD("maincpu", I4040, 5185000. / 7)
|
||||
MCFG_CPU_PROGRAM_MAP(mod40_program)
|
||||
MCFG_CPU_DATA_MAP(mod40_data)
|
||||
MCFG_CPU_IO_MAP(mod40_io)
|
||||
MCFG_CPU_DECRYPTED_OPCODES_MAP(mod40_opcodes)
|
||||
MCFG_I4040_ROM_MAP(mod40_rom)
|
||||
MCFG_I4040_RAM_MEMORY_MAP(mod40_ram_memory)
|
||||
MCFG_I4040_ROM_PORTS_MAP(mod40_rom_ports)
|
||||
MCFG_I4040_RAM_STATUS_MAP(mod40_ram_status)
|
||||
MCFG_I4040_RAM_PORTS_MAP(mod40_ram_ports)
|
||||
MCFG_I4040_PROGRAM_MEMORY_MAP(mod40_program_memory)
|
||||
MCFG_I4040_BUS_CYCLE_CB(FUNC(intellec4_40_state, bus_cycle));
|
||||
MCFG_I4040_SYNC_CB(DEVWRITELINE("bus", bus::intellec4::univ_bus_device, sync_in))
|
||||
MCFG_I4040_STP_ACK_CB(WRITELINE(intellec4_40_state, stp_ack))
|
||||
|
||||
@ -529,12 +893,19 @@ MACHINE_CONFIG_START(intlc440)
|
||||
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
|
||||
|
||||
MCFG_DEVICE_ADD("iobank", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(mod40_io_banks)
|
||||
MCFG_DEVICE_ADD("rpbank", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(mod40_rom_port_banks)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(15)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
|
||||
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
|
||||
|
||||
MCFG_DEVICE_ADD("mpbank", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(mod40_ram_port_banks)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(7)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x20)
|
||||
|
||||
MCFG_RS232_PORT_ADD("tty", default_rs232_devices, "terminal")
|
||||
|
||||
@ -556,17 +927,48 @@ MACHINE_CONFIG_START(intlc440)
|
||||
MCFG_INTELLEC4_UNIV_SLOT_ADD("bus", "j17", 518000. / 7, intellec4_univ_cards, nullptr)
|
||||
MCFG_INTELLEC4_UNIV_SLOT_ADD("bus", "j18", 518000. / 7, intellec4_univ_cards, nullptr)
|
||||
MCFG_INTELLEC4_UNIV_SLOT_ADD("bus", "j19", 518000. / 7, intellec4_univ_cards, nullptr)
|
||||
|
||||
MCFG_DEFAULT_LAYOUT(layout_intlc440)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
INPUT_PORTS_START(intlc440)
|
||||
PORT_START("MODE")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_TOGGLE PORT_NAME("STOP") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_stop, 0)
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("SINGLE STEP") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_single_step, 0)
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("RESET") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_reset, 0)
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("MON") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_mon, 0)
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("RAM") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_ram, 0)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_NAME("PROM") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_prom, 0)
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("STOP") PORT_CODE(KEYCODE_LEFT) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_stop, 0)
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("SINGLE STEP") PORT_CODE(KEYCODE_RIGHT) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_single_step, 0)
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_NAME("RESET") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_reset, 0)
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_NAME("MON") PORT_CODE(KEYCODE_1_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_mon, 0)
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_NAME("RAM") PORT_CODE(KEYCODE_2_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_ram, 0)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_NAME("PROM") PORT_CODE(KEYCODE_3_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_prom, 0)
|
||||
|
||||
PORT_START("CONTROL")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("RUN") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_run, 0)
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("NEXT INST") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_next_inst, 0)
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("DECR") PORT_CODE(KEYCODE_MINUS_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_decr, 0)
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("INCR") PORT_CODE(KEYCODE_PLUS_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_incr, 0)
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("LOAD") PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_load, 0)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("CMA ENABLE") PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_cma_enable, 0)
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("CMA WRITE") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, intellec4_40_state, sw_cma_write, 0)
|
||||
|
||||
PORT_START("ADDRDAT")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 0")
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 1")
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 2")
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 3")
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 4")
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 5")
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 6")
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 7")
|
||||
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 8")
|
||||
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 9")
|
||||
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 10")
|
||||
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("ADDRESS/DATA 11")
|
||||
|
||||
PORT_START("PASSES")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("PASSES 0")
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("PASSES 1")
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("PASSES 2")
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_TOGGLE PORT_NAME("PASSES 3")
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
@ -588,4 +990,4 @@ ROM_END
|
||||
} // anonymous namespace
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1974?, intlc440, 0, 0, intlc440, intlc440, intellec4_40_state, 0, "Intel", "INTELLEC 4/MOD40", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE )
|
||||
COMP( 1974?, intlc440, 0, 0, intlc440, intlc440, intellec4_40_state, 0, "Intel", "INTELLEC 4/MOD40", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_CLICKABLE_ARTWORK | MACHINE_SUPPORTS_SAVE )
|
||||
|
||||
865
src/mame/layout/intlc440.lay
Normal file
865
src/mame/layout/intlc440.lay
Normal file
@ -0,0 +1,865 @@
|
||||
<?xml version="1.0"?>
|
||||
<!--
|
||||
license:CC0
|
||||
copyright-holders:Vas Crabb
|
||||
Intel INTELLEC® 4/MOD 40 layout
|
||||
-->
|
||||
<mamelayout version="2">
|
||||
<element name="background">
|
||||
<rect><color red="0.20" green="0.16" blue="0.31" /></rect>
|
||||
</element>
|
||||
|
||||
<element name="led" defstate="0">
|
||||
<rect state="0"><color red="0.43" green="0.35" blue="0.39" /></rect>
|
||||
<rect state="1"><color red="1.0" green="0.18" blue="0.20" /></rect>
|
||||
</element>
|
||||
|
||||
<element name="switch" defstate="0">
|
||||
<rect state="0">
|
||||
<color red="1.0" green="0.97" blue="0.87" />
|
||||
<bounds left="0.0" top="0.0" right="1.0" bottom="0.15" />
|
||||
</rect>
|
||||
<rect state="0">
|
||||
<color red="0.88" green="0.83" blue="0.66" />
|
||||
<bounds left="0.0" top="0.15" right="1.0" bottom="0.5" />
|
||||
</rect>
|
||||
<rect state="0">
|
||||
<color red="0.94" green="0.90" blue="0.75" />
|
||||
<bounds left="0.0" top="0.5" right="1.0" bottom="1.0" />
|
||||
</rect>
|
||||
<rect state="1">
|
||||
<color red="0.94" green="0.90" blue="0.75" />
|
||||
<bounds left="0.0" top="0.0" right="1.0" bottom="0.5" />
|
||||
</rect>
|
||||
<rect state="1">
|
||||
<color red="1.0" green="0.97" blue="0.87" />
|
||||
<bounds left="0.0" top="0.5" right="1.0" bottom="0.9" />
|
||||
</rect>
|
||||
<rect state="1">
|
||||
<color red="0.76" green="0.70" blue="0.47" />
|
||||
<bounds left="0.0" top="0.9" right="1.0" bottom="1.0" />
|
||||
</rect>
|
||||
</element>
|
||||
|
||||
<element name="label_0"><text string="0"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_1"><text string="1"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_2"><text string="2"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_3"><text string="3"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_4"><text string="4"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_5"><text string="5"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_6"><text string="6"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_7"><text string="7"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_8"><text string="8"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_9"><text string="9"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_10"><text string="10"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_11"><text string="11"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_a1"><text string="A1"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_a2"><text string="A2"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_a3"><text string="A3"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_m1"><text string="M1"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_m2"><text string="M2"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_x2"><text string="X2"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_x3"><text string="X3"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_search"><text string="SEARCH"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_complete"><text string="COMPLETE"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_pointer"><text string="POINTER"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_valid"><text string="VALID"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_cm_ram"><text string="CM-RAM"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_mon"><text string="MON"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_ram"><text string="RAM"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_prom"><text string="PROM"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
|
||||
<element name="label_passes"><text string="PASSES"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_run"><text string="RUN"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_next"><text string="NEXT"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_inst"><text string="INST"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_decr"><text string="DECR"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_incr"><text string="INCR"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_load"><text string="LOAD"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_stop"><text string="STOP"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_single"><text string="SINGLE"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
<element name="label_step"><text string="STEP"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_write"><text string="WRITE"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_reset"><text string="RESET"><color red="1.0" green="1.0" blue="1.0" /></text></element>
|
||||
|
||||
<element name="label_address">
|
||||
<text string="ADDRESS" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_status">
|
||||
<text string="STATUS" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_instruction">
|
||||
<text string="INSTRUCTION" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_active_bank">
|
||||
<text string="ACTIVE BANK" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_mode">
|
||||
<text string="MODE" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_execution">
|
||||
<text string="EXECUTION" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_last_ptr">
|
||||
<text string="LAST RAM/ROM POINTER" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
|
||||
<element name="label_enable">
|
||||
<text string="ENABLE" align="2"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_disable">
|
||||
<text string="DISABLE" align="2"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
|
||||
<element name="label_addr_data">
|
||||
<text string="ADDRESS/DATA" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_mode_ctrl">
|
||||
<text string="MODE CONTROL" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_pass_counter">
|
||||
<text string="PASS COUNTER" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_search_ctrl">
|
||||
<text string="SEARCH ADDRESS CONTROL" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_cma">
|
||||
<text string="CMA" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
<element name="label_reset_ctrl">
|
||||
<text string="RESET CONTROL" align="1"><color red="1.0" green="1.0" blue="1.0" /></text>
|
||||
</element>
|
||||
|
||||
<view name="Terminal Below">
|
||||
<cpanel element="background"><bounds left="0" top="0" right="1000" bottom="400" /></cpanel>
|
||||
|
||||
<cpanel element="label_address"><bounds left="72" top="55" right="506" bottom="63" /></cpanel>
|
||||
<cpanel element="label_a3"><bounds left="81" top="63" right="185" bottom="70" /></cpanel>
|
||||
<cpanel element="label_a2"><bounds left="237" top="63" right="341" bottom="70" /></cpanel>
|
||||
<cpanel element="label_a1"><bounds left="393" top="63" right="497" bottom="70" /></cpanel>
|
||||
<cpanel element="label_11"><bounds left="81" top="71" right="92" bottom="78" /></cpanel>
|
||||
<cpanel element="label_10"><bounds left="112" top="71" right="123" bottom="78" /></cpanel>
|
||||
<cpanel element="label_9"><bounds left="143" top="71" right="154" bottom="78" /></cpanel>
|
||||
<cpanel element="label_8"><bounds left="174" top="71" right="185" bottom="78" /></cpanel>
|
||||
<cpanel element="label_7"><bounds left="237" top="71" right="248" bottom="78" /></cpanel>
|
||||
<cpanel element="label_6"><bounds left="268" top="71" right="279" bottom="78" /></cpanel>
|
||||
<cpanel element="label_5"><bounds left="299" top="71" right="310" bottom="78" /></cpanel>
|
||||
<cpanel element="label_4"><bounds left="330" top="71" right="341" bottom="78" /></cpanel>
|
||||
<cpanel element="label_3"><bounds left="393" top="71" right="404" bottom="78" /></cpanel>
|
||||
<cpanel element="label_2"><bounds left="424" top="71" right="435" bottom="78" /></cpanel>
|
||||
<cpanel element="label_1"><bounds left="455" top="71" right="466" bottom="78" /></cpanel>
|
||||
<cpanel element="label_0"><bounds left="486" top="71" right="497" bottom="78" /></cpanel>
|
||||
|
||||
<cpanel element="label_status"><bounds left="540" top="55" right="662" bottom="63" /></cpanel>
|
||||
<cpanel element="label_search"><bounds left="561" top="63" right="610" bottom="70" /></cpanel>
|
||||
<cpanel element="label_complete"><bounds left="561" top="71" right="610" bottom="78" /></cpanel>
|
||||
<cpanel element="label_pointer"><bounds left="623" top="63" right="672" bottom="70" /></cpanel>
|
||||
<cpanel element="label_valid"><bounds left="623" top="71" right="672" bottom="78" /></cpanel>
|
||||
<cpanel element="label_run"><bounds left="611" top="71" right="626" bottom="78" /></cpanel>
|
||||
|
||||
<cpanel element="label_instruction"><bounds left="72" top="104" right="350" bottom="112" /></cpanel>
|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
|
||||
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|
||||
</view>
|
||||
|
||||
<view name="Front Panel">
|
||||
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|
||||
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
|
||||
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||||
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||||
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||||
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|
||||
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
|
||||
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||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<cpanel name="led_address_a3_1" element="led">
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<cpanel name="led_active_bank_2" element="led">
|
||||
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||||
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|
||||
<cpanel name="led_active_bank_1" element="led">
|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
<cpanel name="led_execution_x2_3" element="led">
|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
<cpanel name="led_execution_x3_1" element="led">
|
||||
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||||
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||||
<cpanel name="led_execution_x3_0" element="led">
|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
</cpanel>
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||||
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||||
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|
||||
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||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0400">
|
||||
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||||
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||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0200">
|
||||
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||||
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||||
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|
||||
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||||
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||||
<bounds left="230" top="240" right="255" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0040">
|
||||
<bounds left="261" top="240" right="286" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0020">
|
||||
<bounds left="292" top="240" right="317" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0010">
|
||||
<bounds left="323" top="240" right="348" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0008">
|
||||
<bounds left="386" top="240" right="411" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0004">
|
||||
<bounds left="417" top="240" right="442" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0002">
|
||||
<bounds left="448" top="240" right="473" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="ADDRDAT" inputmask="0x0001">
|
||||
<bounds left="479" top="240" right="504" bottom="286" />
|
||||
</cpanel>
|
||||
|
||||
<cpanel element="switch" inputtag="MODE" inputmask="0x0008">
|
||||
<bounds left="573" top="240" right="598" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="MODE" inputmask="0x0010">
|
||||
<bounds left="604" top="240" right="629" bottom="286" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="MODE" inputmask="0x0020">
|
||||
<bounds left="635" top="240" right="660" bottom="286" />
|
||||
</cpanel>
|
||||
|
||||
<cpanel element="switch" inputtag="PASSES" inputmask="0x08">
|
||||
<bounds left="74" top="322" right="99" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="PASSES" inputmask="0x04">
|
||||
<bounds left="105" top="322" right="130" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="PASSES" inputmask="0x02">
|
||||
<bounds left="136" top="322" right="161" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="PASSES" inputmask="0x01">
|
||||
<bounds left="167" top="322" right="192" bottom="368" />
|
||||
</cpanel>
|
||||
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0001">
|
||||
<bounds left="230" top="322" right="255" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0002">
|
||||
<bounds left="261" top="322" right="286" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0004">
|
||||
<bounds left="292" top="322" right="317" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0008">
|
||||
<bounds left="323" top="322" right="348" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0010">
|
||||
<bounds left="354" top="322" right="379" bottom="368" />
|
||||
</cpanel>
|
||||
|
||||
<cpanel element="switch" inputtag="MODE" inputmask="0x0001">
|
||||
<bounds left="448" top="322" right="473" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="MODE" inputmask="0x0002">
|
||||
<bounds left="479" top="322" right="504" bottom="368" />
|
||||
</cpanel>
|
||||
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0020">
|
||||
<bounds left="573" top="322" right="598" bottom="368" />
|
||||
</cpanel>
|
||||
<cpanel element="switch" inputtag="CONTROL" inputmask="0x0040">
|
||||
<bounds left="604" top="322" right="629" bottom="368" />
|
||||
</cpanel>
|
||||
|
||||
<cpanel element="switch" inputtag="MODE" inputmask="0x0004">
|
||||
<bounds left="666" top="322" right="691" bottom="368" />
|
||||
</cpanel>
|
||||
</view>
|
||||
</mamelayout>
|
||||
Loading…
Reference in New Issue
Block a user