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srcclean (nw)

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This commit is contained in:
Vas Crabb 2017-03-26 12:57:49 +11:00
parent 770356315a
commit 6cb38b0771
99 changed files with 1050 additions and 1050 deletions
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162
hash/ibm5170.xml
View File

@ -2859,7 +2859,7 @@ Missing files come here
</dataarea>
</part>
</software>
<software name="scrlmous">
<description>Genius Scroll Mouse</description>
<year>2004</year>
@ -3760,86 +3760,86 @@ Missing files come here
<year>1989</year>
<publisher>Borland</publisher>
<info name="version" value="3.01" />
<part name="flop01" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk01.img" size="368640" crc="d1412b21" sha1="4fc367a229031dd3134100eece7bfb9b3b8dbd2d" offset="0" />
</dataarea>
</part>
<part name="flop02" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk02.img" size="368640" crc="56e083c3" sha1="aea7a20f9e22ab78d9377e3dce1ac5fdee83fbed" offset="0" />
</dataarea>
</part>
<part name="flop03" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk03.img" size="368640" crc="0bfcd167" sha1="b29c61e067d450090f611bf0f7ae58881124e984" offset="0" />
</dataarea>
</part>
<part name="flop04" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk04.img" size="368640" crc="cbed452b" sha1="0e6bf5519349297d377704bcd1e9568b12ad706d" offset="0" />
</dataarea>
</part>
<part name="flop05" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk05.img" size="368640" crc="43bf368f" sha1="0e59b71c067ad578a73ed8b9a9ad8fb52766efbd" offset="0" />
</dataarea>
</part>
<part name="flop06" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk06.img" size="368640" crc="d5314389" sha1="46ba14cb52f0c7f04753023eff77ccc8f40c3911" offset="0" />
</dataarea>
</part>
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<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk07.img" size="368640" crc="27f29554" sha1="150436b12138ef74b154b5080658ed97a7849cb0" offset="0" />
</dataarea>
</part>
<part name="flop08" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk08.img" size="368640" crc="19549090" sha1="6c16e114571422ce71c8ad8ef9f07c518724b506" offset="0" />
</dataarea>
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</dataarea>
</part>
<part name="flop10" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk10.img" size="368640" crc="385d1f10" sha1="0850e25d4d418822cccb1c6aefd3131bffe814ff" offset="0" />
</dataarea>
</part>
<part name="flop11" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk11.img" size="368640" crc="cee1c377" sha1="f9eea75e284c59f71f9adad6fa4da3287c451fec" offset="0" />
</dataarea>
</part>
<part name="flop12" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk12.img" size="368640" crc="7aa5fe5f" sha1="95238693de43a1f6a8062a0b09d920f6c39ea18b" offset="0" />
</dataarea>
</part>
<part name="flop13" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk13.img" size="368640" crc="159151e7" sha1="71082a91f55aebe8d0efa21cb8afedc3482131e9" offset="0" />
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</dataarea>
</part>
<part name="flop15" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk15.img" size="368640" crc="710bc39f" sha1="985a1ff252c17fe91aba5f40994dda853389c5d1" offset="0" />
</dataarea>
</part>
<part name="flop16" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk16.img" size="368640" crc="8941eb6a" sha1="ebe7bad7a92505664ec3a61aad4065dd6e72ca7a" offset="0" />
</dataarea>
</part>
<part name="flop01" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk01.img" size="368640" crc="d1412b21" sha1="4fc367a229031dd3134100eece7bfb9b3b8dbd2d" offset="0" />
</dataarea>
</part>
<part name="flop02" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk02.img" size="368640" crc="56e083c3" sha1="aea7a20f9e22ab78d9377e3dce1ac5fdee83fbed" offset="0" />
</dataarea>
</part>
<part name="flop03" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk03.img" size="368640" crc="0bfcd167" sha1="b29c61e067d450090f611bf0f7ae58881124e984" offset="0" />
</dataarea>
</part>
<part name="flop04" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk04.img" size="368640" crc="cbed452b" sha1="0e6bf5519349297d377704bcd1e9568b12ad706d" offset="0" />
</dataarea>
</part>
<part name="flop05" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk05.img" size="368640" crc="43bf368f" sha1="0e59b71c067ad578a73ed8b9a9ad8fb52766efbd" offset="0" />
</dataarea>
</part>
<part name="flop06" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk06.img" size="368640" crc="d5314389" sha1="46ba14cb52f0c7f04753023eff77ccc8f40c3911" offset="0" />
</dataarea>
</part>
<part name="flop07" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk07.img" size="368640" crc="27f29554" sha1="150436b12138ef74b154b5080658ed97a7849cb0" offset="0" />
</dataarea>
</part>
<part name="flop08" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk08.img" size="368640" crc="19549090" sha1="6c16e114571422ce71c8ad8ef9f07c518724b506" offset="0" />
</dataarea>
</part>
<part name="flop09" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk09.img" size="368640" crc="29cf72df" sha1="a019ddbb81baa4afbed94cea10f8cb63f64b1937" offset="0" />
</dataarea>
</part>
<part name="flop10" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk10.img" size="368640" crc="385d1f10" sha1="0850e25d4d418822cccb1c6aefd3131bffe814ff" offset="0" />
</dataarea>
</part>
<part name="flop11" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk11.img" size="368640" crc="cee1c377" sha1="f9eea75e284c59f71f9adad6fa4da3287c451fec" offset="0" />
</dataarea>
</part>
<part name="flop12" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk12.img" size="368640" crc="7aa5fe5f" sha1="95238693de43a1f6a8062a0b09d920f6c39ea18b" offset="0" />
</dataarea>
</part>
<part name="flop13" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk13.img" size="368640" crc="159151e7" sha1="71082a91f55aebe8d0efa21cb8afedc3482131e9" offset="0" />
</dataarea>
</part>
<part name="flop14" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk14.img" size="368640" crc="6df1d631" sha1="ba39fba55d21da98c294df456980724bbb83cc7a" offset="0" />
</dataarea>
</part>
<part name="flop15" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk15.img" size="368640" crc="710bc39f" sha1="985a1ff252c17fe91aba5f40994dda853389c5d1" offset="0" />
</dataarea>
</part>
<part name="flop16" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="borland_paradox_3.01_German_disk16.img" size="368640" crc="8941eb6a" sha1="ebe7bad7a92505664ec3a61aad4065dd6e72ca7a" offset="0" />
</dataarea>
</part>
</software>
<software name="bpdx40g">

12
src/devices/bus/hp_hil/hil_devices.h
View File

@ -10,13 +10,13 @@
#define __HP_HIL_DEVICES_H__
#define STR_KBD_HP_46020A "hp_46020a" // ITF Keyboard
#define STR_KBD_HP_46021A "hp_46021a" // ITF Keyboard
#define STR_KBD_HP_46030A "hp_46030a" // Vectra Keyboard
#define STR_KBD_HP_INTEGRAL "hp_ipc_kbd" // Integral Keyboard
#define STR_KBD_HP_46020A "hp_46020a" // ITF Keyboard
#define STR_KBD_HP_46021A "hp_46021a" // ITF Keyboard
#define STR_KBD_HP_46030A "hp_46030a" // Vectra Keyboard
#define STR_KBD_HP_INTEGRAL "hp_ipc_kbd" // Integral Keyboard
#define STR_MOUSE_HP_46060A "hp_46060a" // 2-button mouse
#define STR_MOUSE_HP_46060B "hp_46060b" // 3-button mouse
#define STR_MOUSE_HP_46060A "hp_46060a" // 2-button mouse
#define STR_MOUSE_HP_46060B "hp_46060b" // 3-button mouse
SLOT_INTERFACE_EXTERN(hp_hil_devices);

14
src/devices/bus/hp_hil/hlekbd.cpp
View File

@ -288,7 +288,7 @@ void hle_device_base::device_timer(emu_timer &timer, device_timer_id id, int par
void hle_device_base::hil_write(uint16_t data)
{
int frames = 0;
// printf("rx from mlc %04X (%s %02X)\n", data, BIT(data, 11) ? "command" : "data", data & 255);
// printf("rx from mlc %04X (%s %02X)\n", data, BIT(data, 11) ? "command" : "data", data & 255);
if (BIT(data, 11)) switch (data & 255)
{
@ -314,7 +314,7 @@ void hle_device_base::hil_write(uint16_t data)
case HPHIL_POL:
if (!m_fifo.empty())
{
m_hp_hil_mlc->hil_write(m_device_id16 | 0x40); // Keycode Set 1, no coordinate data
m_hp_hil_mlc->hil_write(m_device_id16 | 0x40); // Keycode Set 1, no coordinate data
frames = 1;
while (!m_fifo.empty())
{
@ -348,18 +348,18 @@ void hle_device_base::hil_write(uint16_t data)
if (!m_passthru)
m_hp_hil_mlc->hil_write(data);
// else
// m_next->hil_write(data);
// else
// m_next->hil_write(data);
}
void hle_device_base::transmit_byte(uint8_t byte)
{
if (!m_fifo.full()) {
// printf("queuing %02X\n", byte);
// printf("queuing %02X\n", byte);
m_fifo.enqueue(byte);
}
// else
// printf("queuing fail (fifo full)\n");
// else
// printf("queuing fail (fifo full)\n");
}
/*--------------------------------------------------

14
src/devices/bus/hp_hil/hp_hil.cpp
View File

@ -119,7 +119,7 @@ WRITE8_MEMBER(hp_hil_mlc_device::write)
{
case 0:
DBG_LOG(1,"Transmit", ("%scommand 0x%02x to device %d\n", !m_loop?"loopback ":"", data, m_w1 & 7));
if (m_loop & 2) // no devices on 2nd link loop
if (m_loop & 2) // no devices on 2nd link loop
return;
if (m_loop == 0)
{
@ -160,7 +160,7 @@ WRITE8_MEMBER(hp_hil_mlc_device::write)
m_w3 = data;
break;
case 32: // loopback switch: bit 0 = loop0, bit 1 = loop1
case 32: // loopback switch: bit 0 = loop0, bit 1 = loop1
m_loop = data;
break;
}
@ -170,7 +170,7 @@ READ8_MEMBER(hp_hil_mlc_device::read)
{
uint8_t data = 0;
switch (offset)
switch (offset)
{
case 0:
if (!m_fifo.empty())
@ -201,16 +201,16 @@ READ8_MEMBER(hp_hil_mlc_device::read)
void hp_hil_mlc_device::hil_write(uint16_t data)
{
DBG_LOG(1,"Receive", ("%s %04X fifo %s\n",
DBG_LOG(1,"Receive", ("%s %04X fifo %s\n",
BIT(data, 11)?"command":"data", data, m_fifo.full()?"full":(m_fifo.empty()?"empty":"ok")));
if (!m_fifo.full())
if (!m_fifo.full())
{
if (!BIT(data, 11))
if (!BIT(data, 11))
{
m_fifo.enqueue(data);
}
else if (!m_fifo.empty() || !(m_w2 & HPMLC_W2_IPF))
else if (!m_fifo.empty() || !(m_w2 & HPMLC_W2_IPF))
{
m_fifo.enqueue(data);
m_r3 |= HPMLC_R3_INT;

76
src/devices/bus/hp_hil/hp_hil.h
View File

@ -14,51 +14,51 @@
#include "emu.h"
#define HPMLC_R1_OB 0x10
#define HPMLC_R1_OB 0x10
#define HPMLC_W1_C 0x0800
#define HPMLC_W1_C 0x0800
#define HPMLC_R2_PERR 0x01
#define HPMLC_R2_FERR 0x02
#define HPMLC_R2_FOF 0x04
#define HPMLC_R2_PERR 0x01
#define HPMLC_R2_FERR 0x02
#define HPMLC_R2_FOF 0x04
#define HPMLC_W2_TEST 0x01
#define HPMLC_W2_IPF 0x04
#define HPMLC_W2_TEST 0x01
#define HPMLC_W2_IPF 0x04
#define HPMLC_R3_INT 0x01
#define HPMLC_R3_NMI 0x02
#define HPMLC_R3_LERR 0x04
#define HPMLC_R3_INT 0x01
#define HPMLC_R3_NMI 0x02
#define HPMLC_R3_LERR 0x04
#define HPMLC_W3_APE 0x02
#define HPMLC_W3_APE 0x02
// commands
#define HPHIL_IFC 0x00 // Interface Clear
#define HPHIL_EPT 0x01 // Enter Pass-Thru Mode
#define HPHIL_ELB 0x02 // Enter Loop-Back Mode
#define HPHIL_IDD 0x03 // Identify and Describe
#define HPHIL_DSR 0x04 // Device Soft Reset
#define HPHIL_PST 0x05 // Perform Self Test
#define HPHIL_RRG 0x06 // Read Register
#define HPHIL_WRG 0x07 // Write Register
#define HPHIL_ACF 0x08 // Auto Configure [08..0f]
#define HPHIL_POL 0x10 // Poll [10..1f]
#define HPHIL_RPL 0x20 // RePoll [20..2f]
#define HPHIL_RNM 0x30 // Report Name
#define HPHIL_RST 0x31 // Report Status
#define HPHIL_EXD 0x32 // Extended Describe
#define HPHIL_RSC 0x33 // Report Security Code
#define HPHIL_DKA 0x3D // Disable Keyswitch AutoRepeat
#define HPHIL_EK1 0x3E // Enable Keyswitch AutoRepeat 30cps
#define HPHIL_EK2 0x3F // Enable Keyswitch AutoRepeat 60cps
#define HPHIL_PR1 0x40 // Prompt 1..7 [40..46]
#define HPHIL_PRM 0x47 // Prompt (General Purpose)
#define HPHIL_AK1 0x48 // Acknowledge 1..7 [40..46]
#define HPHIL_ACK 0x4F // Acknowledge (General Purpose)
#define HPHIL_RIO 0xFA // Register I/O Error
#define HPHIL_SHR 0xFB // System Hard Reset
#define HPHIL_TER 0xFC // Transmission Error
#define HPHIL_CAE 0xFD // Configuration Address Error
#define HPHIL_DHR 0xFE // Device Hard Reset
#define HPHIL_IFC 0x00 // Interface Clear
#define HPHIL_EPT 0x01 // Enter Pass-Thru Mode
#define HPHIL_ELB 0x02 // Enter Loop-Back Mode
#define HPHIL_IDD 0x03 // Identify and Describe
#define HPHIL_DSR 0x04 // Device Soft Reset
#define HPHIL_PST 0x05 // Perform Self Test
#define HPHIL_RRG 0x06 // Read Register
#define HPHIL_WRG 0x07 // Write Register
#define HPHIL_ACF 0x08 // Auto Configure [08..0f]
#define HPHIL_POL 0x10 // Poll [10..1f]
#define HPHIL_RPL 0x20 // RePoll [20..2f]
#define HPHIL_RNM 0x30 // Report Name
#define HPHIL_RST 0x31 // Report Status
#define HPHIL_EXD 0x32 // Extended Describe
#define HPHIL_RSC 0x33 // Report Security Code
#define HPHIL_DKA 0x3D // Disable Keyswitch AutoRepeat
#define HPHIL_EK1 0x3E // Enable Keyswitch AutoRepeat 30cps
#define HPHIL_EK2 0x3F // Enable Keyswitch AutoRepeat 60cps
#define HPHIL_PR1 0x40 // Prompt 1..7 [40..46]
#define HPHIL_PRM 0x47 // Prompt (General Purpose)
#define HPHIL_AK1 0x48 // Acknowledge 1..7 [40..46]
#define HPHIL_ACK 0x4F // Acknowledge (General Purpose)
#define HPHIL_RIO 0xFA // Register I/O Error
#define HPHIL_SHR 0xFB // System Hard Reset
#define HPHIL_TER 0xFC // Transmission Error
#define HPHIL_CAE 0xFD // Configuration Address Error
#define HPHIL_DHR 0xFE // Device Hard Reset
/*
* init sequnce (p. 4-13)

2
src/devices/bus/isa/mc1502_fdc.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Electronika MC 1502 FDC device
Electronika MC 1502 FDC device
**********************************************************************/

2
src/devices/bus/isa/mc1502_fdc.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Electronika MC 1502 FDC device
Electronika MC 1502 FDC device
**********************************************************************/

2
src/devices/bus/isa/mc1502_rom.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
MC-1502 ROM cartridge device
MC-1502 ROM cartridge device
**********************************************************************/

2
src/devices/bus/isa/mc1502_rom.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
MC-1502 ROM cartridge device
MC-1502 ROM cartridge device
**********************************************************************/

2
src/devices/bus/isa/p1_fdc.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 FDC device (model B504)
Poisk-1 FDC device (model B504)
**********************************************************************/

2
src/devices/bus/isa/p1_fdc.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 FDC device (model B504)
Poisk-1 FDC device (model B504)
**********************************************************************/

2
src/devices/bus/isa/p1_hdc.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 HDC device (model B942)
Poisk-1 HDC device (model B942)
**********************************************************************/

2
src/devices/bus/isa/p1_hdc.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 HDC device (model B942)
Poisk-1 HDC device (model B942)
**********************************************************************/

2
src/devices/bus/isa/p1_rom.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 ROM cartridge device
Poisk-1 ROM cartridge device
**********************************************************************/

2
src/devices/bus/isa/p1_rom.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 ROM cartridge device
Poisk-1 ROM cartridge device
**********************************************************************/

10
src/devices/bus/isa/p1_sound.cpp
View File

@ -2,12 +2,12 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 sound card. DAC, ADC, MIDI in/out and 6 music channels.
Poisk-1 sound card. DAC, ADC, MIDI in/out and 6 music channels.
Memory-mapped, uses IRQ3 and IRQ7, no DMA.
Memory-mapped, uses IRQ3 and IRQ7, no DMA.
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
**********************************************************************/
@ -141,7 +141,7 @@ READ8_MEMBER(p1_sound_device::adc_r)
WRITE8_MEMBER(p1_sound_device::dac_w)
{
// logerror("DAC write: %02x <- %02x\n", offset>>1, data);
// logerror("DAC write: %02x <- %02x\n", offset>>1, data);
m_dac_data[offset >> 1] = data;
m_isa->irq7_w(CLEAR_LINE);
}

6
src/devices/bus/isa/p1_sound.h
View File

@ -2,10 +2,10 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Poisk-1 sound card
Poisk-1 sound card
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
**********************************************************************/

4
src/devices/bus/nes/subor.cpp
View File

@ -146,7 +146,7 @@ void nes_subor2_device::pcb_reset()
and studying VirtuaNESEx. The latter makes the
read at 0x5300 return 0x8F, perhaps as a form
of copy protection?
There are two revisions of Type 2 that are
currently known;
@ -322,4 +322,4 @@ WRITE8_MEMBER(nes_subor2_device::write_l)
update_banks();
break;
}
}
}

2
src/devices/bus/nes/subor.h
View File

@ -75,4 +75,4 @@ extern const device_type NES_SUBOR0;
extern const device_type NES_SUBOR1;
extern const device_type NES_SUBOR2;
#endif /* MAME_BUS_NES_SUBOR_H */
#endif /* MAME_BUS_NES_SUBOR_H */

4
src/devices/bus/nes/zemina.cpp
View File

@ -65,12 +65,12 @@ void nes_zemina_device::pcb_reset()
-------------------------------------------------*/
/*-------------------------------------------------
Zemina board emulation
Currently, this board is only known to be used
by one game: Magic Kid GooGoo.
Info from kevtris at NESDev, who dumped the game:
wiki.nesdev.com/w/index.php/INES_Mapper_190

2
src/devices/bus/nes/zemina.h
View File

@ -28,4 +28,4 @@ public:
// device type definition
extern const device_type NES_ZEMINA;
#endif /* MAME_BUS_NES_ZEMINA_H */
#endif /* MAME_BUS_NES_ZEMINA_H */

2
src/devices/bus/ti8x/bitsocket.h
View File

@ -52,4 +52,4 @@ private:
} } // namespace bus::ti8x
#endif // MAME_DEVICES_BUS_TI8X_BITSOCKET_H
#endif // MAME_DEVICES_BUS_TI8X_BITSOCKET_H

2
src/devices/bus/ti8x/graphlinkhle.h
View File

@ -63,4 +63,4 @@ private:
} } // namespace bus::ti8x
#endif // MAME_DEVICES_BUS_TI8X_GRAPHLINKHLE_H
#endif // MAME_DEVICES_BUS_TI8X_GRAPHLINKHLE_H

2
src/devices/cpu/drccache.cpp
View File

@ -243,7 +243,7 @@ void drc_cache::request_oob_codegen(drc_oob_delegate callback, void *param1, voi
oob_handler *oob = (oob_handler *)alloc(sizeof(*oob));
assert(oob != nullptr);
new (oob) oob_handler();
// fill it in
oob->m_callback = callback;
oob->m_param1 = param1;

2
src/devices/cpu/m6502/n2a03.h
View File

@ -74,7 +74,7 @@ private:
/* These are the official XTAL values and clock rates used by Nintendo for
manufacturing throughout the production of the 2A03. PALC_APU_CLOCK is
the clock rate devised by UMC(?) for PAL Famicom clone hardware. */
the clock rate devised by UMC(?) for PAL Famicom clone hardware. */
#define N2A03_NTSC_XTAL XTAL_21_4772MHz
#define N2A03_PAL_XTAL XTAL_26_601712MHz

10
src/devices/cpu/mb86233/mb86233d.cpp
View File

@ -10,7 +10,7 @@
0 1 2 3 4 5 6 7 8 9 a b c d e f
0 b0 b1 x0 x1 x2 i0 i1 i2 sp pag vsm dmc c0 c1 pc -
1 a ah al b bh bl c ch cl d dh dl p ph pl sft
Second register bank:
0 1 2 3 4 5 6 7 8 9 a b c d e f
2 <register file>
@ -69,7 +69,7 @@
1011 11.c 0110 1110 .... .... .... .... iret
Top 3 bits = instruction group, except when it isn't.
*/
@ -161,7 +161,7 @@ static std::string memory(uint32_t reg, bool x1)
else
util::stream_format(stream, "x0");
}
if(reg & 0x10) {
if((0x10 - (reg & 0xf)) < 10)
util::stream_format(stream, "-%d", 0x10 - (reg & 0xf));
@ -334,7 +334,7 @@ static unsigned dasm_mb86233(std::ostream &stream, uint32_t opcode )
default:
util::stream_format(stream, "mov {%d} %s, %s", op, memory(r1, false), memory(r2, true));
break;
}
}
break;
}
@ -398,7 +398,7 @@ static unsigned dasm_mb86233(std::ostream &stream, uint32_t opcode )
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
util::stream_format(stream, "ldi #0x%x, %s", opcode & 0xffffff, regnames[(opcode >> 24) & 0x3f]); break;
break;
case 0x2f: case 0x3f: {
uint32_t cond = ( opcode >> 20 ) & 0x1f;
uint32_t subtype = ( opcode >> 17 ) & 7;

18
src/devices/cpu/mips/mips3.cpp
View File

@ -983,7 +983,7 @@ inline bool mips3_device::RBYTE(offs_t address, uint32_t *result)
*result = (*m_memory.read_byte)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1022,7 +1022,7 @@ inline bool mips3_device::RHALF(offs_t address, uint32_t *result)
*result = (*m_memory.read_word)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1061,7 +1061,7 @@ inline bool mips3_device::RWORD(offs_t address, uint32_t *result)
*result = (*m_memory.read_dword)(*m_program, address);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1100,7 +1100,7 @@ inline bool mips3_device::RWORD_MASKED(offs_t address, uint32_t *result, uint32_
*result = (*m_memory.read_dword_masked)(*m_program, address, mem_mask);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1157,7 +1157,7 @@ inline bool mips3_device::RDOUBLE_MASKED(offs_t address, uint64_t *result, uint6
*result = (*m_memory.read_qword_masked)(*m_program, address, mem_mask);
return true;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_READ_ALLOWED)
{
@ -1186,7 +1186,7 @@ inline void mips3_device::WBYTE(offs_t address, uint8_t data)
(*m_memory.write_byte)(*m_program, address, data);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1265,7 +1265,7 @@ inline void mips3_device::WWORD(offs_t address, uint32_t data)
(*m_memory.write_dword)(*m_program, address, data);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1305,7 +1305,7 @@ inline void mips3_device::WWORD_MASKED(offs_t address, uint32_t data, uint32_t m
(*m_memory.write_dword_masked)(*m_program, address, data, mem_mask);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{
@ -1365,7 +1365,7 @@ inline void mips3_device::WDOUBLE_MASKED(offs_t address, uint64_t data, uint64_t
(*m_memory.write_qword_masked)(*m_program, address, data, mem_mask);
return;
}
const uint32_t tlbval = vtlb_table()[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED)
{

132
src/devices/cpu/mips/mips3drc.cpp
View File

@ -840,68 +840,68 @@ void mips3_device::static_generate_memory_accessor(int mode, int size, int iswri
UML_LABEL(block, addrok); // addrok:
}
/* TX4925 on-board peripherals pass-through */
if (m_flavor == MIPS3_TYPE_TX4925)
{
int addrok;
UML_AND(block, I3, I0, 0xffff0000); // and i3, i0, 0xffff0000
UML_CMP(block, I3, 0xff1f0000); // cmp i3, 0xff1f0000
UML_JMPc(block, COND_NZ, addrok = label++);
switch (size)
{
case 1:
if (iswrite)
UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte
else
UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte
break;
case 2:
if (iswrite)
UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word
else
UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word
break;
case 4:
if (iswrite)
{
if (!ismasked)
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword
else
UML_WRITEM(block, I0, I1, I2, SIZE_DWORD, SPACE_PROGRAM); // writem i0,i1,i2,program_dword
}
else
{
if (!ismasked)
UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword
else
UML_READM(block, I0, I0, I2, SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword
}
break;
case 8:
if (iswrite)
{
if (!ismasked)
UML_DWRITE(block, I0, I1, SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword
else
UML_DWRITEM(block, I0, I1, I2, SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i1,i2,program_qword
}
else
{
if (!ismasked)
UML_DREAD(block, I0, I0, SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword
else
UML_DREADM(block, I0, I0, I2, SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword
}
break;
}
UML_RET(block);
UML_LABEL(block, addrok);
}
/* TX4925 on-board peripherals pass-through */
if (m_flavor == MIPS3_TYPE_TX4925)
{
int addrok;
UML_AND(block, I3, I0, 0xffff0000); // and i3, i0, 0xffff0000
UML_CMP(block, I3, 0xff1f0000); // cmp i3, 0xff1f0000
UML_JMPc(block, COND_NZ, addrok = label++);
switch (size)
{
case 1:
if (iswrite)
UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte
else
UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte
break;
case 2:
if (iswrite)
UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word
else
UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word
break;
case 4:
if (iswrite)
{
if (!ismasked)
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword
else
UML_WRITEM(block, I0, I1, I2, SIZE_DWORD, SPACE_PROGRAM); // writem i0,i1,i2,program_dword
}
else
{
if (!ismasked)
UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword
else
UML_READM(block, I0, I0, I2, SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword
}
break;
case 8:
if (iswrite)
{
if (!ismasked)
UML_DWRITE(block, I0, I1, SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword
else
UML_DWRITEM(block, I0, I1, I2, SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i1,i2,program_qword
}
else
{
if (!ismasked)
UML_DREAD(block, I0, I0, SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword
else
UML_DREADM(block, I0, I0, I2, SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword
}
break;
}
UML_RET(block);
UML_LABEL(block, addrok);
}
/* general case: assume paging and perform a translation */
UML_SHR(block, I3, I0, 12); // shr i3,i0,12
@ -1165,8 +1165,8 @@ void mips3_device::generate_checksum_block(drcuml_block *block, compiler_state *
UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword
if (seqhead->delay.first() != nullptr
&& !(seqhead->delay.first()->flags & OPFLAG_VIRTUAL_NOOP)
&& seqhead->physpc != seqhead->delay.first()->physpc)
&& !(seqhead->delay.first()->flags & OPFLAG_VIRTUAL_NOOP)
&& seqhead->physpc != seqhead->delay.first()->physpc)
{
base = m_direct->read_ptr(seqhead->delay.first()->physpc);
assert(base != nullptr);
@ -1208,8 +1208,8 @@ void mips3_device::generate_checksum_block(drcuml_block *block, compiler_state *
sum += curdesc->opptr.l[0];
if (curdesc->delay.first() != nullptr
&& !(curdesc->delay.first()->flags & OPFLAG_VIRTUAL_NOOP)
&& (curdesc == seqlast || (curdesc->next() != nullptr && curdesc->next()->physpc != curdesc->delay.first()->physpc)))
&& !(curdesc->delay.first()->flags & OPFLAG_VIRTUAL_NOOP)
&& (curdesc == seqlast || (curdesc->next() != nullptr && curdesc->next()->physpc != curdesc->delay.first()->physpc)))
{
base = m_direct->read_ptr(curdesc->delay.first()->physpc);
assert(base != nullptr);

2
src/devices/cpu/upd7725/upd7725.h
View File

@ -195,7 +195,7 @@ private:
// m_irq_firing: if an irq has fired; 0 = not fired or has already finished firing
// 1 = next opcode is the first half of int firing 'NOP+push pc'
// 2 = next opcode is the second half of int firing 'JMP 0100'
int m_irq_firing;
int m_irq_firing;
address_space *m_program, *m_data;
direct_read_data *m_direct;

20
src/devices/cpu/z180/z180.cpp
View File

@ -1573,12 +1573,12 @@ int z180_device::z180_dma0(int max_cycles)
offs_t sar0 = 65536 * IO_SAR0B + 256 * IO_SAR0H + IO_SAR0L;
offs_t dar0 = 65536 * IO_DAR0B + 256 * IO_DAR0H + IO_DAR0L;
int bcr0 = 256 * IO_BCR0H + IO_BCR0L;
if (bcr0 == 0)
if (bcr0 == 0)
{
bcr0 = 0x10000;
}
int count = (IO_DMODE & Z180_DMODE_MMOD) ? bcr0 : 1;
int cycles = 0;
@ -1710,12 +1710,12 @@ int z180_device::z180_dma1()
offs_t mar1 = 65536 * IO_MAR1B + 256 * IO_MAR1H + IO_MAR1L;
offs_t iar1 = 256 * IO_IAR1H + IO_IAR1L;
int bcr1 = 256 * IO_BCR1H + IO_BCR1L;
if (bcr1 == 0)
if (bcr1 == 0)
{
bcr1 = 0x10000;
}
int cycles = 0;
if ((m_iol & Z180_DREQ1) == 0)
@ -2391,7 +2391,7 @@ again:
else
{
do
{
{
curcycles = check_interrupts();
m_icount -= curcycles;
handle_io_timers(curcycles);
@ -2413,7 +2413,7 @@ again:
m_icount -= curcycles;
handle_io_timers(curcycles);
/* if channel 0 was started in burst mode, go recheck the mode */
if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
(IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
@ -2434,7 +2434,7 @@ again:
curcycles = z180_dma1();
m_icount -= curcycles;
handle_io_timers(curcycles);
/* If DMA is done break out to the faster loop */
if ((IO_DSTAT & Z180_DSTAT_DME) != Z180_DSTAT_DME)
break;
@ -2449,7 +2449,7 @@ again:
/* If DMA is started go to check the mode */
if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
goto again;
curcycles = check_interrupts();
m_icount -= curcycles;
handle_io_timers(curcycles);

30
src/devices/machine/6821pia.cpp
View File

@ -1111,7 +1111,7 @@ WRITE_LINE_MEMBER( pia6821_device::cb2_w )
bool pia6821_device::cb2_output()
{
m_out_cb2_needs_pulled = false;
return m_out_cb2;
}
@ -1130,17 +1130,17 @@ bool pia6821_device::cb2_output_z()
// control byte wrappers
//-------------------------------------------------
bool pia6821_device::irq1_enabled(uint8_t c) { return bool((c >> 0) & 0x01); }
bool pia6821_device::c1_low_to_high(uint8_t c) { return bool((c >> 1) & 0x01); }
bool pia6821_device::c1_high_to_low(uint8_t c) { return !bool((c >> 1) & 0x01); }
bool pia6821_device::output_selected(uint8_t c) { return bool((c >> 2) & 0x01); }
bool pia6821_device::irq2_enabled(uint8_t c) { return bool((c >> 3) & 0x01); }
bool pia6821_device::strobe_e_reset(uint8_t c) { return bool((c >> 3) & 0x01); }
bool pia6821_device::strobe_c1_reset(uint8_t c) { return !bool((c >> 3) & 0x01); }
bool pia6821_device::c2_set(uint8_t c) { return bool((c >> 3) & 0x01); }
bool pia6821_device::c2_low_to_high(uint8_t c) { return bool((c >> 4) & 0x01); }
bool pia6821_device::c2_high_to_low(uint8_t c) { return !bool((c >> 4) & 0x01); }
bool pia6821_device::c2_set_mode(uint8_t c) { return bool((c >> 4) & 0x01); }
bool pia6821_device::c2_strobe_mode(uint8_t c) { return !bool((c >> 4) & 0x01); }
bool pia6821_device::c2_output(uint8_t c) { return bool((c >> 5) & 0x01); }
bool pia6821_device::c2_input(uint8_t c) { return !bool((c >> 5) & 0x01); }
bool pia6821_device::irq1_enabled(uint8_t c) { return bool((c >> 0) & 0x01); }
bool pia6821_device::c1_low_to_high(uint8_t c) { return bool((c >> 1) & 0x01); }
bool pia6821_device::c1_high_to_low(uint8_t c) { return !bool((c >> 1) & 0x01); }
bool pia6821_device::output_selected(uint8_t c) { return bool((c >> 2) & 0x01); }
bool pia6821_device::irq2_enabled(uint8_t c) { return bool((c >> 3) & 0x01); }
bool pia6821_device::strobe_e_reset(uint8_t c) { return bool((c >> 3) & 0x01); }
bool pia6821_device::strobe_c1_reset(uint8_t c) { return !bool((c >> 3) & 0x01); }
bool pia6821_device::c2_set(uint8_t c) { return bool((c >> 3) & 0x01); }
bool pia6821_device::c2_low_to_high(uint8_t c) { return bool((c >> 4) & 0x01); }
bool pia6821_device::c2_high_to_low(uint8_t c) { return !bool((c >> 4) & 0x01); }
bool pia6821_device::c2_set_mode(uint8_t c) { return bool((c >> 4) & 0x01); }
bool pia6821_device::c2_strobe_mode(uint8_t c) { return !bool((c >> 4) & 0x01); }
bool pia6821_device::c2_output(uint8_t c) { return bool((c >> 5) & 0x01); }
bool pia6821_device::c2_input(uint8_t c) { return !bool((c >> 5) & 0x01); }

56
src/devices/machine/ie15.cpp
View File

@ -2,12 +2,12 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
15IE-00-013 Terminal
15IE-00-013 Terminal
A serial (RS232 or current loop) green-screen terminal, mostly VT52
compatible (no Hold Screen mode and no graphics character set).
A serial (RS232 or current loop) green-screen terminal, mostly VT52
compatible (no Hold Screen mode and no graphics character set).
Alternate character set (selected by SO/SI chars) is Cyrillic.
Alternate character set (selected by SO/SI chars) is Cyrillic.
****************************************************************************/
@ -416,32 +416,32 @@ void ie15_device::device_reset()
}
/*
Usable raster is 800 x 275 pixels (80 x 25 characters). 24 lines are
available to the user and 25th (topmost) line is the status line.
Status line, if enabled, displays current serial port speed, 16 setup
bits, and clock. There is no NVRAM, so setup bits are always 0 after
reset and clock starts counting at 0 XXX.
Usable raster is 800 x 275 pixels (80 x 25 characters). 24 lines are
available to the user and 25th (topmost) line is the status line.
Status line, if enabled, displays current serial port speed, 16 setup
bits, and clock. There is no NVRAM, so setup bits are always 0 after
reset and clock starts counting at 0 XXX.
No character attributes are available, but in 'display controls' mode
control characters stored in memory are shown as blinking chars.
No character attributes are available, but in 'display controls' mode
control characters stored in memory are shown as blinking chars.
Character cell is 10 x 11; character generator provides 7 x 8 of that.
3 extra horizontal pixels are always blank. Blinking cursor may be
displayed on 3 extra scan lines.
Character cell is 10 x 11; character generator provides 7 x 8 of that.
3 extra horizontal pixels are always blank. Blinking cursor may be
displayed on 3 extra scan lines.
On each scan line, video board draws 80 characters from any location
in video memory; this is used by firmware to provide instant scroll
and cursor, which is a character with code 0x7F stored in off-screen
memory.
On each scan line, video board draws 80 characters from any location
in video memory; this is used by firmware to provide instant scroll
and cursor, which is a character with code 0x7F stored in off-screen
memory.
Video board output is controlled by
- control flag 0 "disable video": 0 == disable
- control flag 1 "cursor": 0 == if this scan line is one of extra 3,
enable video every 5 frames.
- control flag 3 "status line": 0 == current scan line is part of status line
- keyboard mode 'RED' ('display controls'): if character code is
less than 0x20 and RED is set, enable video every 5 frames; if RED is
unset, disable video.
Video board output is controlled by
- control flag 0 "disable video": 0 == disable
- control flag 1 "cursor": 0 == if this scan line is one of extra 3,
enable video every 5 frames.
- control flag 3 "status line": 0 == current scan line is part of status line
- keyboard mode 'RED' ('display controls'): if character code is
less than 0x20 and RED is set, enable video every 5 frames; if RED is
unset, disable video.
*/
void ie15_device::draw_scanline(uint32_t *p, uint16_t offset, uint8_t scanline)
@ -506,9 +506,9 @@ void ie15_device::update_leds()
}
/*
VBlank is active for 3 topmost on-screen rows and 1 at the bottom; however, control flag 3
VBlank is active for 3 topmost on-screen rows and 1 at the bottom; however, control flag 3
overrides VBlank,
allowing status line to be switched on and off.
allowing status line to be switched on and off.
*/
void ie15_device::scanline_callback()
{

2
src/devices/machine/mm5740.cpp
View File

@ -73,7 +73,7 @@ uint32_t mm5740_device::calc_effective_clock_key_debounce(uint32_t capacitance)
void mm5740_device::device_start()
{
// resolve callbacks
for(int i = 0; i < 9; i++)
for(int i = 0; i < 9; i++)
{
m_read_x[i].resolve_safe(0x3ff);
}

56
src/devices/machine/mm5740.h
View File

@ -5,27 +5,27 @@
MM5740 Keyboard Encoder emulation
**********************************************************************
_____ _____
B3 1 |* \_/ | 40 B4
Vll 2 | | 39 B9
Clock 3 | | 38 B2
X9 4 | | 37 B1
X8 5 | | 36 B8
X7 6 | | 35 B7
X6 7 | | 34 B6
X5 8 | | 33 B5
X4 9 | | 32 Vss
X3 10 | MM5740 | 31 Y9
X2 11 | | 30 Y8
X1 12 | | 29 Y7
_____ _____
B3 1 |* \_/ | 40 B4
Vll 2 | | 39 B9
Clock 3 | | 38 B2
X9 4 | | 37 B1
X8 5 | | 36 B8
X7 6 | | 35 B7
X6 7 | | 34 B6
X5 8 | | 33 B5
X4 9 | | 32 Vss
X3 10 | MM5740 | 31 Y9
X2 11 | | 30 Y8
X1 12 | | 29 Y7
Data Strobe Output 13 | | 28 Y6
Data Strobe Control 14 | | 27 Y5
Output Enable 15 | | 26 Y4
Repeat 16 | | 25 Y3
Output Enable 15 | | 26 Y4
Repeat 16 | | 25 Y3
Key Bounce Mask 17 | | 24 Y2
Vgg 18 | | 23 Y1
Control 19 | | 22 Y0
Shift Lock I/O 20 |_____________| 21 Shift
Vgg 18 | | 23 Y1
Control 19 | | 22 Y0
Shift Lock I/O 20 |_____________| 21 Shift
Name Pin No. Function
----------------------------------------------------------------------
@ -33,7 +33,7 @@ Name Pin No. Function
X1-X9 4-12 Output - Drives the key switch matrix.
Y1-Y10 22-31 Inputs - connect to the X drive lines with
the key switch matrix.
the key switch matrix.
B1-B9 1,33-40 Tri-stated data outputs.
@ -44,10 +44,10 @@ Data Strobe Control 14 Input to control data strobe output pulse width
Output Enable 15 Input to control the chip's TRI-STATE output
Repeat 16 Each cycle of this signal will issue
a new data strobe for the pressed key.
a new data strobe for the pressed key.
Key-Bounce Mask 17 Use capacitor on this chip to provide
key debouncing
key debouncing
Shift 21 Shift key pressed
@ -55,9 +55,9 @@ Control 19 Control key pressed
Shift Lock I/O 20 Togglable input to signify shift (NOT caps) lock.
Clock 3 A TTL compatible clock signal
Clock 3 A TTL compatible clock signal
Vss 32 +5.0V
Vss 32 +5.0V
Vll 2 Ground
@ -67,10 +67,10 @@ Vgg 18 -12V
**********************************************************************/
/* TODO:
Support Key-bounce mask
Support Repeat function
Support shift lock
Support additional internal ROMs
Support Key-bounce mask
Support Repeat function
Support shift lock
Support additional internal ROMs
*/
#pragma once
@ -111,7 +111,7 @@ public:
// public interface
uint16_t b_r();
template<typename Object> static devcb_base &set_x_cb(device_t &device, Object &&object, uint8_t i)
template<typename Object> static devcb_base &set_x_cb(device_t &device, Object &&object, uint8_t i)
{
assert(i<9); return downcast<mm5740_device &>(device).m_read_x[i].set_callback(std::forward<Object>(object));
}

4
src/devices/machine/tms1024.cpp
View File

@ -81,7 +81,7 @@ READ8_MEMBER(tms1024_device::read_h)
// read selected port data
if (m_s != 0)
m_h = (m_read_port[m_s-1])((offs_t)(m_s-1)) & 0xf;
// high-impedance otherwise
}
@ -103,7 +103,7 @@ WRITE_LINE_MEMBER(tms1024_device::write_std)
{
if (m_s != 0)
(m_write_port[m_s-1])((offs_t)(m_s-1), m_h);
else
{
// reset all ports

208
src/devices/machine/z80sio.cpp
View File

@ -147,7 +147,7 @@ z80sio_device::z80sio_device(const machine_config &mconfig, device_type type, co
m_out_txdrqa_cb(*this),
m_out_rxdrqb_cb(*this),
m_out_txdrqb_cb(*this),
m_variant(variant),
m_variant(variant),
m_cputag("maincpu")
{
for (auto & elem : m_int_state)
@ -273,10 +273,10 @@ int z80sio_device::z80daisy_irq_state()
//-------------------------------------------------
int z80sio_device::z80daisy_irq_ack()
{
// default irq vector is -1 for 68000 but 0 for z80 for example...
int ret = owner()->subdevice<cpu_device>(m_cputag)->default_irq_vector();
// default irq vector is -1 for 68000 but 0 for z80 for example...
int ret = owner()->subdevice<cpu_device>(m_cputag)->default_irq_vector();
LOGINT("%s %s \n",tag(), FUNCNAME);
LOGINT("%s %s \n",tag(), FUNCNAME);
// loop over all interrupt sources
for (auto & elem : m_int_state)
{
@ -286,16 +286,16 @@ int z80sio_device::z80daisy_irq_ack()
elem = Z80_DAISY_IEO; // Set IUS bit (called IEO in z80 daisy lingo)
m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING;
LOGINT(" - Found an INT request, ");
LOGINT("returning RR2: %02x\n", m_chanB->m_rr2 );
LOGINT("returning RR2: %02x\n", m_chanB->m_rr2 );
check_interrupts();
return m_chanB->m_rr2;
return m_chanB->m_rr2;
}
}
ret = m_chanB->m_rr2;
ret = m_chanB->m_rr2;
LOGINT(" - failed to find an interrupt to ack, returning default IRQ vector: %02x\n", ret );
logerror("z80sio_irq_ack: failed to find an interrupt to ack!\n");
return ret;
return ret;
}
@ -307,10 +307,10 @@ void z80sio_device::z80daisy_irq_reti()
LOGINT("%s %s \n",tag(), FUNCNAME);
if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
{
LOGINT(" - I8274 and UPD7201 lacks RETI detection, no action taken\n");
return;
}
{
LOGINT(" - I8274 and UPD7201 lacks RETI detection, no action taken\n");
return;
}
// loop over all interrupt sources
for (auto & elem : m_int_state)
@ -356,45 +356,45 @@ void z80sio_device::reset_interrupts()
int z80sio_device::get_interrupt_prio(int index, int type)
{
int prio_level = -1;
int priority = -1;
int prio_level = -1;
int priority = -1;
if ((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
if ((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
{
/* These CPU variants use Bit 2 of WR2 of Channnel A to determine the priority Hi to Lo:
0: RxA TxA RxB TxB ExtA ExtB
1: RxA RxB TxA TxB ExtA ExtB */
switch(type)
{
case z80sio_channel::INT_RECEIVE:
case z80sio_channel::INT_SPECIAL: prio_level = z80sio_channel::INT_RCV_SPC_PRI_LVL; break; // 0
case z80sio_channel::INT_TRANSMIT: prio_level = z80sio_channel::INT_TRANSMIT_PRI_LVL; break; // 1
case z80sio_channel::INT_EXTERNAL: prio_level = z80sio_channel::INT_EXTERNAL_PRI_LVL; break; // 2
default:
logerror("Bad interrupt source being prioritized!");
return -1;
}
// Assume that the PRIORITY bit is set
priority = (prio_level * 2) + index;
/* These CPU variants use Bit 2 of WR2 of Channnel A to determine the priority Hi to Lo:
0: RxA TxA RxB TxB ExtA ExtB
1: RxA RxB TxA TxB ExtA ExtB */
switch(type)
{
case z80sio_channel::INT_RECEIVE:
case z80sio_channel::INT_SPECIAL: prio_level = z80sio_channel::INT_RCV_SPC_PRI_LVL; break; // 0
case z80sio_channel::INT_TRANSMIT: prio_level = z80sio_channel::INT_TRANSMIT_PRI_LVL; break; // 1
case z80sio_channel::INT_EXTERNAL: prio_level = z80sio_channel::INT_EXTERNAL_PRI_LVL; break; // 2
default:
logerror("Bad interrupt source being prioritized!");
return -1;
}
// Assume that the PRIORITY bit is set
priority = (prio_level * 2) + index;
// Check if it actually was cleared
// Check if it actually was cleared
if ( (m_chanA->m_wr2 & z80sio_channel::WR2_PRIORITY) == 0)
{
// Adjust priority if needed, only affects TxA and RxB
// Adjust priority if needed, only affects TxA and RxB
if (index == CHANNEL_A && type == z80sio_channel::INT_TRANSMIT )
priority--;
priority--;
else if (index == CHANNEL_B && type == z80sio_channel::INT_RECEIVE )
priority++;
priority++;
}
}
else // Plain old z80sio
{
}
else // Plain old z80sio
{
priority = (index << 2) | type;
}
return priority;
}
return priority;
}
/*
/*
8274: "RR2 contains the vector which gets modified to indicate the source of interrupt. However, the state of
the vector does not change if no new interrupts are generated. The contents of RR2 are only changed when
a new interrupt is generated. In order to get the correct information, RR2 must be read only after an
@ -403,7 +403,7 @@ int z80sio_device::get_interrupt_prio(int index, int type)
*/
uint8_t z80sio_device::modify_vector(int index, int type)
{
uint8_t vector = m_chanB->m_wr2;
uint8_t vector = m_chanB->m_wr2;
if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
{
if (m_chanB->m_wr1 & z80sio_channel::WR1_STATUS_VECTOR)
@ -427,7 +427,7 @@ uint8_t z80sio_device::modify_vector(int index, int type)
vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (type << 1);
}
}
return vector;
return vector;
}
//-------------------------------------------------
@ -436,11 +436,11 @@ uint8_t z80sio_device::modify_vector(int index, int type)
void z80sio_device::trigger_interrupt(int index, int type)
{
uint8_t priority = get_interrupt_prio(index, type);
uint8_t vector = modify_vector(index, type);
uint8_t vector = modify_vector(index, type);
LOGINT("%s %s Chan:%c Type:%s\n", tag(), FUNCNAME, 'A' + index, std::array<char const *, 4>
{{"INT_TRANSMIT", "INT_EXTERNAL", "INT_RECEIVE", "INT_SPECIAL"}}[type]);
LOGINT(" - Priority:%02x Vector:%02x\n", priority, vector);
{{"INT_TRANSMIT", "INT_EXTERNAL", "INT_RECEIVE", "INT_SPECIAL"}}[type]);
LOGINT(" - Priority:%02x Vector:%02x\n", priority, vector);
// update vector register
m_chanB->m_rr2 = vector;
@ -464,9 +464,9 @@ int z80sio_device::m1_r()
{
LOGINT("%s %s \n",FUNCNAME, tag());
if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
return 0;
else
return z80daisy_irq_ack();
return 0;
else
return z80daisy_irq_ack();
}
@ -773,7 +773,7 @@ int z80sio_channel::get_clock_mode()
return clocks;
}
/*
/*
From "uPD7201/7201A MULTI PROTOCOL SERIAL COMMUNICATION CONTROLLER" by NEC:
"RTSA (Request to Send A): The state of the RTS bit (01 of the CR5 register) controls this pin. If
the RTS bit is reset in the asynchronous mode, a high level will not be output on the RTS pin until
@ -898,14 +898,14 @@ uint8_t z80sio_channel::do_sioreg_rr1()
highest priority interrupting condition at the time of the read. If
no interrupts are pending, the vector is modified with V3 = 0, V2 = 1, and
V1 = 1. This register is read only through Channel B."
Intel 8274 datasheet: "RR2 - Channel B: Interrupt Vector - Contains the interrupt
vector programmed in into WR2. If the status affects vector mode is selected (WR1:D2),
it containes the modified vector for the highest priority interrupt pending.
If no interrupts are pending the variable bits in the vector are set to one."
NEC upd7201 MPSC2 Technical Manual: "When the MPSC2 is used in vectored mode, the
contents of this register are placed on the bus during the appropriate portion of
contents of this register are placed on the bus during the appropriate portion of
interrupt acknowledge sequence. You can read the value of CR2B at any time.
This is particularly useful in determining the cause of an interrup when using the
MPSC2 in Non-vectored mode."
@ -916,36 +916,36 @@ uint8_t z80sio_channel::do_sioreg_rr2()
// channel B only, channel A returns 0
if (m_index == z80sio_device::CHANNEL_A) return 0;
LOGINT(" - Channel B so we might need to update the vector modification\n");
LOGINT(" - Channel B so we might need to update the vector modification\n");
// Assume the unmodified vector
m_rr2 = m_uart->m_chanB->m_wr2;
if((m_variant == z80sio_device::TYPE_I8274) || (m_variant == z80sio_device::TYPE_UPD7201))
{
int i = 0;
LOGINT(" - 8274 or 7201 requires special care\n");
if((m_variant == z80sio_device::TYPE_I8274) || (m_variant == z80sio_device::TYPE_UPD7201))
{
int i = 0;
LOGINT(" - 8274 or 7201 requires special care\n");
// loop over all interrupt sources
for (auto & elem : m_uart->m_int_state)
{
// find the first channel with an interrupt requested
if (elem & Z80_DAISY_INT)
{
LOGINT(" - Checking an INT source %d\n", i);
m_rr2 = m_uart->modify_vector((m_uart->m_int_source[i] >> 8) & 1, m_uart->m_int_source[i] & 3);
LOGINT(" - Found an INT request to ack while reading RR2\n");
elem = Z80_DAISY_IEO; // Set IUS bit (called IEO in z80 daisy lingo)
m_uart->check_interrupts();
break;
}
// loop over all interrupt sources
for (auto & elem : m_uart->m_int_state)
{
// find the first channel with an interrupt requested
if (elem & Z80_DAISY_INT)
{
LOGINT(" - Checking an INT source %d\n", i);
m_rr2 = m_uart->modify_vector((m_uart->m_int_source[i] >> 8) & 1, m_uart->m_int_source[i] & 3);
LOGINT(" - Found an INT request to ack while reading RR2\n");
elem = Z80_DAISY_IEO; // Set IUS bit (called IEO in z80 daisy lingo)
m_uart->check_interrupts();
break;
}
i++;
}
// If no pending interrupt were found set variable bits to ones.
if (i >= 6)
{
m_rr2 |= 0x1F;
m_uart->m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING;
}
// If no pending interrupt were found set variable bits to ones.
if (i >= 6)
{
m_rr2 |= 0x1F;
m_uart->m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING;
}
}
return m_rr2;
}
@ -1031,8 +1031,8 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
if (m_sync) m_rr0 |= RR0_SYNC_HUNT;
if (m_cts) m_rr0 |= RR0_CTS;
// Clear any pending External interrupt
m_uart->m_int_state[m_index == z80sio_device::CHANNEL_A ? 4 : 5] = 0;
// Clear any pending External interrupt
m_uart->m_int_state[m_index == z80sio_device::CHANNEL_A ? 4 : 5] = 0;
LOGINT("%s %s Ch:%c : Reset External/Status Interrupt\n", FUNCNAME, tag(), 'A' + m_index);
break;
@ -1049,16 +1049,16 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
case WR0_RESET_TX_INT:
// reset transmitter interrupt pending
{
uint8_t priority = 3; // Assume TxB
// Check if it is TxA
if (m_index == z80sio_device::CHANNEL_A)
{
// Check if priority bit is cleared
priority = (m_uart->m_chanA->m_wr2 & z80sio_channel::WR2_PRIORITY) == 0 ? 1 : 2;
}
m_uart->m_int_state[priority] = 0;
LOGINT("%s %s Ch:%c : Reset TX Interrupt, priority:%d\n", FUNCNAME, tag(), 'A' + m_index, priority);
}
uint8_t priority = 3; // Assume TxB
// Check if it is TxA
if (m_index == z80sio_device::CHANNEL_A)
{
// Check if priority bit is cleared
priority = (m_uart->m_chanA->m_wr2 & z80sio_channel::WR2_PRIORITY) == 0 ? 1 : 2;
}
m_uart->m_int_state[priority] = 0;
LOGINT("%s %s Ch:%c : Reset TX Interrupt, priority:%d\n", FUNCNAME, tag(), 'A' + m_index, priority);
}
m_uart->check_interrupts();
LOGCMD("%s %s Ch:%c : Reset Transmitter Interrupt Pending\n", FUNCNAME, tag(), 'A' + m_index);
break;
@ -1069,23 +1069,23 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
break;
case WR0_RETURN_FROM_INT:
LOGINT("%s %s Ch:%c : Return from interrupt\n", FUNCNAME, tag(), 'A' + m_index);
{
int found = 0;
// loop over all interrupt sources
for (auto & elem : m_uart->m_int_state)
{
// find the first channel with an interrupt requested
if (elem & (Z80_DAISY_IEO))
{
// clear the IEO state and update the IRQs
elem &= ~(Z80_DAISY_IEO);
m_uart->check_interrupts();
found = 1;
break;
}
}
LOGINT(" - %s\n", found == 0 ? "failed to find an interrupt to clear IEO on!" : "cleared IEO");
}
{
int found = 0;
// loop over all interrupt sources
for (auto & elem : m_uart->m_int_state)
{
// find the first channel with an interrupt requested
if (elem & (Z80_DAISY_IEO))
{
// clear the IEO state and update the IRQs
elem &= ~(Z80_DAISY_IEO);
m_uart->check_interrupts();
found = 1;
break;
}
}
LOGINT(" - %s\n", found == 0 ? "failed to find an interrupt to clear IEO on!" : "cleared IEO");
}
break;
default:
LOG("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK);

50
src/devices/machine/z80sio.h
View File

@ -193,11 +193,11 @@ public:
int m_txc;
// Register state
// read registers enum
// read registers enum
uint8_t m_rr0; // REG_RR0_STATUS
uint8_t m_rr1; // REG_RR1_SPEC_RCV_COND
uint8_t m_rr2; // REG_RR2_INTERRUPT_VECT
// write registers enum
// write registers enum
uint8_t m_wr0; // REG_WR0_COMMAND_REGPT
uint8_t m_wr1; // REG_WR1_INT_DMA_ENABLE
uint8_t m_wr2; // REG_WR2_INT_VECTOR
@ -220,9 +220,9 @@ protected:
enum
{
INT_RCV_SPC_PRI_LVL = 0,
INT_TRANSMIT_PRI_LVL = 1,
INT_EXTERNAL_PRI_LVL = 2
INT_RCV_SPC_PRI_LVL = 0,
INT_TRANSMIT_PRI_LVL = 1,
INT_EXTERNAL_PRI_LVL = 2
};
// Read registers
@ -278,20 +278,20 @@ protected:
enum
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38,
WR0_NULL = 0x00,
WR0_SEND_ABORT = 0x08,
WR0_RESET_EXT_STATUS = 0x10,
WR0_CHANNEL_RESET = 0x18,
WR0_ENABLE_INT_NEXT_RX = 0x20,
WR0_RESET_TX_INT = 0x28,
WR0_ERROR_RESET = 0x30,
WR0_RETURN_FROM_INT = 0x38,
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38,
WR0_NULL = 0x00,
WR0_SEND_ABORT = 0x08,
WR0_RESET_EXT_STATUS = 0x10,
WR0_CHANNEL_RESET = 0x18,
WR0_ENABLE_INT_NEXT_RX = 0x20,
WR0_RESET_TX_INT = 0x28,
WR0_ERROR_RESET = 0x30,
WR0_RETURN_FROM_INT = 0x38,
WR0_CRC_RESET_CODE_MASK = 0xc0,
WR0_CRC_RESET_NULL = 0x00,
WR0_CRC_RESET_RX = 0x40,
WR0_CRC_RESET_TX = 0x80,
WR0_CRC_RESET_NULL = 0x00,
WR0_CRC_RESET_RX = 0x40,
WR0_CRC_RESET_TX = 0x80,
WR0_CRC_RESET_TX_UNDERRUN = 0xc0
};
@ -448,10 +448,10 @@ public:
static void static_set_cputag(device_t &device, const char *tag)
{
z80sio_device &dev = downcast<z80sio_device &>(device);
dev.m_cputag = tag;
}
static void configure_channels(device_t &device, int rxa, int txa, int rxb, int txb)
dev.m_cputag = tag;
}
static void configure_channels(device_t &device, int rxa, int txa, int rxb, int txb)
{
z80sio_device &dev = downcast<z80sio_device &>(device);
dev.m_rxca = rxa;
@ -506,12 +506,12 @@ protected:
// internal interrupt management
void check_interrupts();
void reset_interrupts();
int get_interrupt_prio(int index, int type);
uint8_t modify_vector(int index, int type);
int get_interrupt_prio(int index, int type);
uint8_t modify_vector(int index, int type);
void trigger_interrupt(int index, int state);
int get_channel_index(z80sio_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
// CPU types that has slightly different behaviour
// CPU types that has slightly different behaviour
enum
{
TYPE_Z80SIO = 0x001,

2
src/devices/sound/tms5110r.hxx
View File

@ -408,7 +408,7 @@ static const struct tms5100_coeffs T0280D_0281D_coeff =
an unvoiced frame follows a silent one (which in turn followed a
voiced frame), the k5-k10 parameters are not zeroed as they should be,
producing a loud noise.
This bug is fixed correctly on the tms52xx chips.
This bug is fixed correctly on the tms52xx chips.
*/
static const struct tms5100_coeffs T0280F_2801A_coeff =
{

2
src/devices/sound/tms5220.h
View File

@ -83,7 +83,7 @@ public:
go active or inactive at slightly different times by separate write_line
writes, which causes the chip to incorrectly reset itself on the 99/8,
where the writes are supposed to happen simultaneously;
/RS is bit 1, /WS is bit 0
/RS is bit 1, /WS is bit 0
Note this is a hack and probably can be removed later, once the 'real'
line handlers above defer by at least 4 clock cycles before taking effect */
DECLARE_WRITE8_MEMBER( data_w );

8
src/devices/video/hlcd0538.cpp
View File

@ -73,18 +73,18 @@ void hlcd0538_device::device_start()
WRITE_LINE_MEMBER(hlcd0538_device::write_clk)
{
state = (state) ? 1 : 0;
// clock in data on falling edge
if (!state && m_clk)
m_shift = (m_shift << 1 | m_data) & u64(0x3ffffffff);
m_clk = state;
}
WRITE_LINE_MEMBER(hlcd0538_device::write_lcd)
{
state = (state) ? 1 : 0;
// transfer to latches on rising edge
if (state && !m_lcd)
{
@ -93,7 +93,7 @@ WRITE_LINE_MEMBER(hlcd0538_device::write_lcd)
}
m_lcd = state;
// interrupt output follows lcd input
m_write_interrupt(state);
}

62
src/devices/video/hp1ll3.cpp
View File

@ -3,32 +3,32 @@
/*
HP 1LL3-0005 GPU emulation.
Used by HP Integral PC, possibly other HP products.
Used by HP Integral PC, possibly other HP products.
On IPC, memory is 4 16Kx4bit DRAM chips = 32KB total (16K words),
but firmware probes memory size and can work with 128KB memory.
Undocumented "_desktop" mode requires this.
On IPC, memory is 4 16Kx4bit DRAM chips = 32KB total (16K words),
but firmware probes memory size and can work with 128KB memory.
Undocumented "_desktop" mode requires this.
Capabilities:
- up to 1024x1024 px on screen
- lines
- rectangles
- area fill with user-defined pattern
- 16x16 user-defined proportional font, with automatic cursor
- 16x16 user-defined sprite for mouse cursor (not a sprite layer)
- windows with blitter (copy, fill and scroll) and clipping
Capabilities:
- up to 1024x1024 px on screen
- lines
- rectangles
- area fill with user-defined pattern
- 16x16 user-defined proportional font, with automatic cursor
- 16x16 user-defined sprite for mouse cursor (not a sprite layer)
- windows with blitter (copy, fill and scroll) and clipping
To do:
. proper cursor and mouse pointers [cursor can be offset from the pen location]
+ variable width fonts [?? placed relative to current window]
+ basic lines
- patterned lines
. bit blits & scroll
. meaning of WRRR bits
. meaning of CONF data [+ autoconfiguration]
- interrupt generation
- realistic timing?
- &c.
To do:
. proper cursor and mouse pointers [cursor can be offset from the pen location]
+ variable width fonts [?? placed relative to current window]
+ basic lines
- patterned lines
. bit blits & scroll
. meaning of WRRR bits
. meaning of CONF data [+ autoconfiguration]
- interrupt generation
- realistic timing?
- &c.
*/
#include "emu.h"
@ -54,7 +54,7 @@
} while (0)
#define HPGPU_VRAM_SIZE 16384 // *4 // experiment
#define HPGPU_VRAM_SIZE 16384 // *4 // experiment
#define HPGPU_HORZ_TOTAL 512
#define HPGPU_VERT_TOTAL 256
@ -96,7 +96,7 @@ void hp1ll3_device::device_start()
m_cursor.allocate(16, 16);
m_sprite.allocate(16, 16);
m_videoram = std::make_unique<uint16_t[]>(HPGPU_VRAM_SIZE*2); // x2 size to make WRWIN/RDWIN easier
m_videoram = std::make_unique<uint16_t[]>(HPGPU_VRAM_SIZE*2); // x2 size to make WRWIN/RDWIN easier
}
void hp1ll3_device::device_reset()
@ -397,14 +397,14 @@ uint32_t hp1ll3_device::screen_update(screen_device &screen, bitmap_ind16 &bitma
//-------------------------------------------------
/*
* offset 0: CSR
* offset 0: CSR
*
* bit 0 gpu is busy
* bit 1 data is ready
* bit 3 vert blank time
* bit 7 out of window
* bit 0 gpu is busy
* bit 1 data is ready
* bit 3 vert blank time
* bit 7 out of window
*
* offset 2: data
* offset 2: data
*/
READ8_MEMBER( hp1ll3_device::read )

124
src/devices/video/hp1ll3.h
View File

@ -30,76 +30,76 @@
* 3 -- ???
* 4 -- write 1 word of data, then command, then read X words of data, then write NOP
*/
#define NOP 0 // type 0
#define CONF 2 // type 3, configure GPU (screen size, timings...). 11 words of data.
#define DISVID 3 // type 0, disable video
#define ENVID 4 // type 0, enable video
#define WRMEM 7 // type 4, write GPU memory at offset, terminate by NOP
#define RDMEM 8 // type 4, read GPU memory from offset, terminate by NOP
#define WRSAD 9 // type 1, set screen area start address
#define WRORG 10 // type 1, set ???
#define WRDAD 11 // type 1, set data area start address (16x16 area fill, sprite and cursor)
#define WRRR 12 // type 1, set replacement rule (rasterop)
#define MOVEP 13 // type 2, move pointer
#define IMOVEP 14
#define DRAWP 15 // type 2, draw line
#define IDRAWP 16
#define RDP 17
#define WRUDL 18 // type 1, set user-defined line pattern (16-bit)
#define WRWINSIZ 19 // type 2, set ???
#define WRWINORG 20 // type 2, set ???
#define COPY 21 // type 2
#define FILL 22 // type 1, fill area
#define FRAME 23 // type _, draw rectangle
#define SCROLUP 24 // type 2
#define SCROLDN 25 // type 2
#define SCROLLF 26 // type 2
#define SCROLRT 27 // type 2
#define RDWIN 28 // type 1
#define WRWIN 29 // type 1
#define RDWINPARM 30
#define CR 31
#define CRLFx 32
#define LABEL 36 // type 1, draw text
#define ENSP 38 // type 0, enable sprite
#define DISSP 39 // type 0, disable sprite
#define MOVESP 40 // type 2, move sprite
#define IMOVESP 41
#define RDSP 42
#define DRAWPX 43 // type _, draw single pixel
#define WRFAD 44 // type 1, set font area start address
#define ENCURS 45 // type 0
#define DISCURS 46 // type 0
#define ID 63
#define NOP 0 // type 0
#define CONF 2 // type 3, configure GPU (screen size, timings...). 11 words of data.
#define DISVID 3 // type 0, disable video
#define ENVID 4 // type 0, enable video
#define WRMEM 7 // type 4, write GPU memory at offset, terminate by NOP
#define RDMEM 8 // type 4, read GPU memory from offset, terminate by NOP
#define WRSAD 9 // type 1, set screen area start address
#define WRORG 10 // type 1, set ???
#define WRDAD 11 // type 1, set data area start address (16x16 area fill, sprite and cursor)
#define WRRR 12 // type 1, set replacement rule (rasterop)
#define MOVEP 13 // type 2, move pointer
#define IMOVEP 14
#define DRAWP 15 // type 2, draw line
#define IDRAWP 16
#define RDP 17
#define WRUDL 18 // type 1, set user-defined line pattern (16-bit)
#define WRWINSIZ 19 // type 2, set ???
#define WRWINORG 20 // type 2, set ???
#define COPY 21 // type 2
#define FILL 22 // type 1, fill area
#define FRAME 23 // type _, draw rectangle
#define SCROLUP 24 // type 2
#define SCROLDN 25 // type 2
#define SCROLLF 26 // type 2
#define SCROLRT 27 // type 2
#define RDWIN 28 // type 1
#define WRWIN 29 // type 1
#define RDWINPARM 30
#define CR 31
#define CRLFx 32
#define LABEL 36 // type 1, draw text
#define ENSP 38 // type 0, enable sprite
#define DISSP 39 // type 0, disable sprite
#define MOVESP 40 // type 2, move sprite
#define IMOVESP 41
#define RDSP 42
#define DRAWPX 43 // type _, draw single pixel
#define WRFAD 44 // type 1, set font area start address
#define ENCURS 45 // type 0
#define DISCURS 46 // type 0
#define ID 63
/*
* Replacement Rules (rops). sources:
* Replacement Rules (rops). sources:
*
* - NetBSD's diofbvar.h (definitions for Topcat chip)
* - pdf/hp/9000_300/specs/A-5958-4362-9_Series_300_Display_Color_Card_Theory_of_Operation_Oct85.pdf
* refers to TOPCAT documentation p/n A-1FH2-2001-7 (not online)
*/
#define RR_FORCE_ZERO 0x0
#define RR_CLEAR RR_FORCE_ZERO
#define RR_AND 0x1
#define RR_AND_NOT_OLD 0x2
#define RR_NEW 0x3
#define RR_COPY RR_NEW
#define RR_AND_NOT_NEW 0x4
#define RR_OLD 0x5
#define RR_XOR 0x6
#define RR_OR 0x7
#define RR_NOR 0x8
#define RR_XNOR 0x9
#define RR_NOT_OLD 0xa
#define RR_INVERT RR_NOT_OLD
#define RR_OR_NOT_OLD 0xb
#define RR_NOT_NEW 0xc
#define RR_COPYINVERTED RR_NOT_NEW
#define RR_OR_NOT_NEW 0xd
#define RR_NAND 0xe
#define RR_FORCE_ONE 0xf
#define RR_FORCE_ZERO 0x0
#define RR_CLEAR RR_FORCE_ZERO
#define RR_AND 0x1
#define RR_AND_NOT_OLD 0x2
#define RR_NEW 0x3
#define RR_COPY RR_NEW
#define RR_AND_NOT_NEW 0x4
#define RR_OLD 0x5
#define RR_XOR 0x6
#define RR_OR 0x7
#define RR_NOR 0x8
#define RR_XNOR 0x9
#define RR_NOT_OLD 0xa
#define RR_INVERT RR_NOT_OLD
#define RR_OR_NOT_OLD 0xb
#define RR_NOT_NEW 0xc
#define RR_COPYINVERTED RR_NOT_NEW
#define RR_OR_NOT_NEW 0xd
#define RR_NAND 0xe
#define RR_FORCE_ONE 0xf
#define WS 16 // bits in a word

2
src/devices/video/pc_vga.cpp
View File

@ -331,7 +331,7 @@ void vga_device::device_start()
save_item(NAME(vga.gc.memory_map_sel));
save_item(NAME(vga.gc.host_oe));
save_item(NAME(vga.gc.chain_oe));
save_item(NAME(vga.attribute.index));
save_item(NAME(vga.attribute.data));
save_item(NAME(vga.attribute.state));

2
src/emu/debug/debugcpu.cpp
View File

@ -981,7 +981,7 @@ u64 debugger_cpu::expression_read_memory(void *param, const char *name, expressi
if (!with_se) {
auto dis = m_machine.disable_side_effect();
return read_memory(space, space.address_to_byte(address), size, false);
} else
} else
return read_memory(space, space.address_to_byte(address), size, false);
}
break;

2
src/emu/drivers/xtal.h
View File

@ -142,7 +142,7 @@ enum
XTAL_13_4952MHz = 13495200, /* Used on Shadow Force pcb and maybe other Technos pcbs? */
XTAL_14MHz = 14000000,
XTAL_14_112MHz = 14112000, /* Timex/Sinclair TS2068 */
XTAL_14_3MHz = 14300000, /* Agat-7 */
XTAL_14_3MHz = 14300000, /* Agat-7 */
XTAL_14_314MHz = 14314000, /* Taito TTL Board */
XTAL_14_31818MHz = 14318181, /* Extremely common, used on 100's of PCBs (4x NTSC subcarrier) */
XTAL_14_705882MHz = 14705882, /* Aleck64 */

2
src/emu/http.cpp
View File

@ -202,7 +202,7 @@ void http_manager::update()
m_server->clear();
for (auto handler : m_handlers)
{
{
m_server->on_get(handler.first, [handler](auto response, auto request)
{
std::tuple<std::string,int, std::string> output = handler.second(request->path);

4
src/emu/main.cpp
View File

@ -14,8 +14,8 @@ Controls execution of the core MAME system.
machine_manager::machine_manager(emu_options& options, osd_interface& osd)
: m_osd(osd),
m_options(options),
m_machine(nullptr)
{
m_machine(nullptr)
{
}
void machine_manager::start_http_server()

2
src/emu/main.h
View File

@ -90,7 +90,7 @@ public:
virtual void ui_initialize(running_machine& machine) { }
virtual void update_machine() { }
http_manager *http() { return m_http.get(); }
void start_http_server();

2
src/emu/softlist_dev.h
View File

@ -160,7 +160,7 @@ public:
static software_list_device *find_by_name(const machine_config &mconfig, const std::string &name);
static void display_matches(const machine_config &config, const char *interface, const std::string &name);
static device_image_interface *find_mountable_image(const machine_config &mconfig, const software_part &part, std::function<bool (const device_image_interface &)> filter);
static device_image_interface *find_mountable_image(const machine_config &mconfig, const software_part &part);
static device_image_interface *find_mountable_image(const machine_config &mconfig, const software_part &part);
protected:
// device-level overrides

2
src/frontend/mame/clifront.cpp
View File

@ -231,7 +231,7 @@ void cli_frontend::start_execution(mame_machine_manager *manager, std::vector<st
manager->start_http_server();
manager->start_luaengine();
if (!option_errors.empty())
osd_printf_error("Error in command line:\n%s\n", strtrimspace(option_errors).c_str());

2
src/frontend/mame/mame.h
View File

@ -51,7 +51,7 @@ public:
virtual ui_manager* create_ui(running_machine& machine) override;
virtual void create_custom(running_machine& machine) override;
virtual void load_cheatfiles(running_machine& machine) override;
virtual void ui_initialize(running_machine& machine) override;

16
src/frontend/mame/mameopts.cpp
View File

@ -212,8 +212,8 @@ void mame_options::parse_slot_devices(emu_options &options, std::function<void(e
//-------------------------------------------------
// reevaluate_slot_options - based on recent changes
// in what images are mounted, give drivers a chance
// to specify new default slot options
// in what images are mounted, give drivers a chance
// to specify new default slot options
//-------------------------------------------------
bool mame_options::reevaluate_slot_options(emu_options &options)
@ -272,7 +272,7 @@ bool mame_options::parse_command_line(emu_options &options, std::vector<std::str
if (!options.parse_command_line(args, OPTION_PRIORITY_CMDLINE, error_string))
return false;
// identify any options as a result of softlists
// identify any options as a result of softlists
auto softlist_opts = evaluate_initial_softlist_options(options);
// assemble a "value specifier" that will be used to specify options set up as a consequence
@ -401,13 +401,13 @@ std::map<std::string, std::string> mame_options::evaluate_initial_softlist_optio
}
// identify other shared features specified as '<<slot name>>_default'
//
//
// example from SMS:
//
// <software name = "alexbmx">
// ...
// <sharedfeat name = "ctrl1_default" value = "paddle" />
// </software>
// <software name = "alexbmx">
// ...
// <sharedfeat name = "ctrl1_default" value = "paddle" />
// </software>
for (const feature_list_item &fi : swinfo->shared_info())
{
const std::string default_suffix = "_default";

2
src/frontend/mame/ui/slotopt.cpp
View File

@ -159,7 +159,7 @@ void menu_slot_devices::populate(float &customtop, float &custombottom)
// does this slot have any selectable options?
bool has_selectable_options = slot.has_selectable_options();
// name this option
// name this option
std::string opt_name("------");
const device_slot_option *option = slot_get_current_option(slot);
if (option)

4
src/lib/formats/asst128_dsk.cpp
View File

@ -2,9 +2,9 @@
// copyright-holders:Olivier Galibert
/*********************************************************************
formats/asst128_dsk.c
formats/asst128_dsk.c
asst128 format
asst128 format
*********************************************************************/

4
src/lib/formats/asst128_dsk.h
View File

@ -2,9 +2,9 @@
// copyright-holders:Olivier Galibert
/*********************************************************************
formats/asst128_dsk.h
formats/asst128_dsk.h
asst128 format
asst128 format
*********************************************************************/

4
src/lib/formats/hp_ipc_dsk.cpp
View File

@ -2,9 +2,9 @@
// copyright-holders:Sergey Svishchev
/*********************************************************************
formats/hp_ipc_dsk.c
formats/hp_ipc_dsk.c
HP Integral PC format
HP Integral PC format
*********************************************************************/

4
src/lib/formats/hp_ipc_dsk.h
View File

@ -2,9 +2,9 @@
// copyright-holders:Sergey Svishchev
/*********************************************************************
formats/hp_ipc_dsk.h
formats/hp_ipc_dsk.h
hp_ipc format
hp_ipc format
*********************************************************************/

2
src/lib/formats/jfd_dsk.cpp
View File

@ -339,7 +339,7 @@ bool jfd_format::load(io_generic *io, uint32_t form_factor, floppy_image *image)
}
}
}
if (discop3)
{
generate_track_from_levels(track / 2, track % 2, track_data, 0, image);

2
src/lib/netlist/nl_lists.h
View File

@ -25,7 +25,7 @@
// timed queue
// ----------------------------------------------------------------------------------------
#define USE_HEAP (0)
#define USE_HEAP (0)
namespace netlist
{

4
src/lib/util/options.cpp
View File

@ -482,8 +482,8 @@ bool core_options::parse_ini_file(util::core_file &inifile, int priority, int ig
//-------------------------------------------------
// pluck_from_command_line - finds a specific
// value from within a command line
// pluck_from_command_line - finds a specific
// value from within a command line
//-------------------------------------------------
bool core_options::pluck_from_command_line(std::vector<std::string> &args, const std::string &optionname, std::string &result)

22
src/mame/drivers/a7150.cpp
View File

@ -141,10 +141,10 @@ WRITE8_MEMBER(a7150_state::ppi_c_w)
// b7
}
#define KGS_ST_OBF 0x01
#define KGS_ST_IBF 0x02
#define KGS_ST_INT 0x04
#define KGS_ST_ERR 0x80
#define KGS_ST_OBF 0x01
#define KGS_ST_IBF 0x02
#define KGS_ST_INT 0x04
#define KGS_ST_ERR 0x80
READ8_MEMBER(a7150_state::kgs_host_r)
{
@ -256,7 +256,7 @@ WRITE8_MEMBER(a7150_state::a7150_kgs_w)
{
case 0:
m_kgs_ctrl &= ~(KGS_ST_ERR | KGS_ST_INT);
// m_pic8259->ir1_w(CLEAR_LINE);
// m_pic8259->ir1_w(CLEAR_LINE);
break;
case 1:
@ -281,7 +281,7 @@ static ADDRESS_MAP_START(a7150_mem, AS_PROGRAM, 16, a7150_state)
ADDRESS_MAP_END
static ADDRESS_MAP_START(a7150_io, AS_IO, 16, a7150_state)
ADDRESS_MAP_UNMAP_HIGH
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x004a, 0x004b) AM_DEVWRITE8("isbc_215g", isbc_215g_device, write, 0x00ff) // KES board
AM_RANGE(0x00c0, 0x00c3) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0x00ff)
AM_RANGE(0x00c8, 0x00cf) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0x00ff)
@ -422,8 +422,8 @@ static MACHINE_CONFIG_START( a7150, a7150_state )
// IFSP port on processor card
MCFG_DEVICE_ADD("ppi8255", I8255, 0)
// MCFG_I8255_IN_PORTA_CB(DEVREAD8("cent_status_in", input_buffer_device, read))
// MCFG_I8255_OUT_PORTB_CB(DEVWRITE8("cent_data_out", output_latch_device, write))
// MCFG_I8255_IN_PORTA_CB(DEVREAD8("cent_status_in", input_buffer_device, read))
// MCFG_I8255_OUT_PORTB_CB(DEVWRITE8("cent_data_out", output_latch_device, write))
MCFG_I8255_OUT_PORTC_CB(WRITE8(a7150_state, ppi_c_w))
MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
@ -475,7 +475,7 @@ static MACHINE_CONFIG_START( a7150, a7150_state )
MCFG_Z80SIO_OUT_RTSA_CB(DEVWRITELINE(RS232_A_TAG, rs232_port_device, write_rts))
MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE(RS232_B_TAG, rs232_port_device, write_txd))
MCFG_Z80SIO_OUT_DTRB_CB(WRITELINE(a7150_state, kgs_iml_w))
// MCFG_Z80SIO_OUT_RTSB_CB(WRITELINE(a7150_state, kgs_ifss_loopback_w))
// MCFG_Z80SIO_OUT_RTSB_CB(WRITELINE(a7150_state, kgs_ifss_loopback_w))
// V.24 port (graphics tablet)
MCFG_RS232_PORT_ADD(RS232_A_TAG, default_rs232_devices, nullptr)
@ -502,8 +502,8 @@ ROM_START( a7150 )
ROM_REGION( 0x10000, "user2", ROMREGION_ERASEFF )
// ROM from A7100
ROM_LOAD( "KGS7070-152.bin", 0x0000, 0x2000, CRC(403f4235) SHA1(d07ccd40f8b600651d513f588bcf1ea4f15ed094))
// ROM_LOAD( "KGS7070-153.rom", 0x0000, 0x2000, CRC(a72fe820) SHA1(4b77ab2b59ea8c3632986847ff359df26b16196b))
// ROM_LOAD( "KGS7070-154.rom", 0x0000, 0x2000, CRC(2995ade0) SHA1(62516f2e1cb62698445f80fd823d39a1a78a7807))
// ROM_LOAD( "KGS7070-153.rom", 0x0000, 0x2000, CRC(a72fe820) SHA1(4b77ab2b59ea8c3632986847ff359df26b16196b))
// ROM_LOAD( "KGS7070-154.rom", 0x0000, 0x2000, CRC(2995ade0) SHA1(62516f2e1cb62698445f80fd823d39a1a78a7807))
ROM_END
/* Driver */

2
src/mame/drivers/abc80.cpp
View File

@ -407,7 +407,7 @@ void abc80_state::device_timer(emu_timer &timer, device_timer_id id, int param,
{
case TIMER_ID_SCANLINE:
draw_scanline(m_bitmap, m_screen->vpos());
m_pio_astb = !m_pio_astb;
m_pio->strobe_a(m_pio_astb);

36
src/mame/drivers/agat.cpp
View File

@ -3,17 +3,17 @@
/***************************************************************************
agat.c
Skeleton driver for Agat series of Soviet Apple II non-clones
Skeleton driver for Agat series of Soviet Apple II non-clones
These are similar to Apple II (same bus architecture, keyboard and
floppy interface), but video controller is completely different.
These are similar to Apple II (same bus architecture, keyboard and
floppy interface), but video controller is completely different.
To do:
- native keyboards (at least two variants)
- 840K floppy controller (MFM encoding, but track layout is unique)
- agat7: 64K and 128K onboard memory configurations
- agat9
- 3rd party slot devices
To do:
- native keyboards (at least two variants)
- 840K floppy controller (MFM encoding, but track layout is unique)
- agat7: 64K and 128K onboard memory configurations
- agat9
- 3rd party slot devices
************************************************************************/
@ -485,7 +485,7 @@ WRITE8_MEMBER(agat7_state::c100_w)
READ8_MEMBER(agat7_state::c800_r)
{
// logerror("%s: c800_r %04X (slot %d) == %02X\n", machine().describe_context(), offset+0xc800, m_cnxx_slot, 0);
// logerror("%s: c800_r %04X (slot %d) == %02X\n", machine().describe_context(), offset+0xc800, m_cnxx_slot, 0);
if (offset == 0x7ff)
{
@ -507,7 +507,7 @@ READ8_MEMBER(agat7_state::c800_r)
WRITE8_MEMBER(agat7_state::c800_w)
{
// logerror("%s: c800_w %04X <- %02X\n", machine().describe_context(), offset+0xc800, data);
// logerror("%s: c800_w %04X <- %02X\n", machine().describe_context(), offset+0xc800, data);
if (offset == 0x7ff)
{
@ -551,7 +551,7 @@ uint8_t agat7_state::read_floatingbus()
}
/***************************************************************************
ADDRESS MAP
ADDRESS MAP
***************************************************************************/
/* onboard memory banking on Agat-7 */
@ -599,8 +599,8 @@ READ8_MEMBER(agat7_state::agat7_ram_r)
WRITE8_MEMBER(agat7_state::agat7_ram_w)
{
// if (offset > 0x7fff)
// logerror("%s: ram %04X (bank %d slot %d) <- %02X\n", machine().describe_context(), offset, m_agat7_membank, m_agat7_ram_slot, data);
// if (offset > 0x7fff)
// logerror("%s: ram %04X (bank %d slot %d) <- %02X\n", machine().describe_context(), offset, m_agat7_membank, m_agat7_ram_slot, data);
if (offset < 32768)
{
@ -1014,7 +1014,7 @@ static MACHINE_CONFIG_START( agat7, agat7_state )
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("32K")
// MCFG_RAM_EXTRA_OPTIONS("64K,128K")
// MCFG_RAM_EXTRA_OPTIONS("64K,128K")
MCFG_RAM_DEFAULT_VALUE(0x00)
/* sound hardware */
@ -1078,11 +1078,11 @@ ROM_START( agat7 )
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
ROM_DEFAULT_BIOS("v1")
ROM_SYSTEM_BIOS( 0, "v1", "Version 1" ) // original?
ROM_SYSTEM_BIOS( 0, "v1", "Version 1" ) // original?
ROMX_LOAD( "monitor7.rom", 0x3800, 0x0800, CRC(071fda0b) SHA1(6089d46b7addc4e2ae096b2cf81124681bd2b27a), ROM_BIOS(1))
ROM_SYSTEM_BIOS( 1, "v2", "Version 2" ) // modded by author of agatcomp.ru
ROM_SYSTEM_BIOS( 1, "v2", "Version 2" ) // modded by author of agatcomp.ru
ROMX_LOAD( "agat_pzu.bin", 0x3800, 0x0800, CRC(c605163d) SHA1(b30fd1b264a347a9de69bb9e3105483254994d06), ROM_BIOS(2))
ROM_SYSTEM_BIOS( 2, "debug", "Debug" ) // written by author of agatcomp.ru
ROM_SYSTEM_BIOS( 2, "debug", "Debug" ) // written by author of agatcomp.ru
ROMX_LOAD( "debug-sysmon7.bin", 0x3800, 0x0800, CRC(d26f18a4) SHA1(2862c13a82e2f4dfc757aa2eeab11fe71c570c12), ROM_BIOS(3))
// 140KB floppy controller

18
src/mame/drivers/apple2e.cpp
View File

@ -1961,35 +1961,35 @@ READ8_MEMBER(apple2e_state::c100_int_bank_r) { return read_int_rom(space, 0x410
WRITE8_MEMBER(apple2e_state::c100_w) { write_slot_rom(space, 1, offset, data); }
READ8_MEMBER(apple2e_state::c300_r) { return read_slot_rom(space, 3, offset); }
READ8_MEMBER(apple2e_state::c300_int_r)
{
READ8_MEMBER(apple2e_state::c300_int_r)
{
if (!m_slotc3rom)
{
m_intc8rom = true;
update_slotrom_banks();
}
return read_int_rom(space, 0x300, offset);
return read_int_rom(space, 0x300, offset);
}
READ8_MEMBER(apple2e_state::c300_int_bank_r)
{
READ8_MEMBER(apple2e_state::c300_int_bank_r)
{
if (!m_slotc3rom)
{
m_intc8rom = true;
update_slotrom_banks();
}
return read_int_rom(space, 0x4300, offset);
return read_int_rom(space, 0x4300, offset);
}
WRITE8_MEMBER(apple2e_state::c300_w)
{
WRITE8_MEMBER(apple2e_state::c300_w)
{
if (!m_slotc3rom)
{
m_intc8rom = true;
update_slotrom_banks();
}
write_slot_rom(space, 3, offset, data);
write_slot_rom(space, 3, offset, data);
}
READ8_MEMBER(apple2e_state::c400_r) { return read_slot_rom(space, 4, offset); }
READ8_MEMBER(apple2e_state::c400_int_r)

32
src/mame/drivers/aristmk5.cpp
View File

@ -5,12 +5,12 @@
Aristocrat MK5 / MKV hardware
possibly 'Acorn Archimedes on a chip' hardware
Current significant issues:
- Games run twice as fast as they should, music is double speed etc.
There are threads that say when running in VGA mode an original AA
will play music etc. at half the expected speed, so it is likely
that the way the timers work differs in this mode (25hz instead of 50?)
- Games lock up after 50 spins
Current significant issues:
- Games run twice as fast as they should, music is double speed etc.
There are threads that say when running in VGA mode an original AA
will play music etc. at half the expected speed, so it is likely
that the way the timers work differs in this mode (25hz instead of 50?)
- Games lock up after 50 spins
Note: ARM250 mapping is not identical to plain AA
@ -1453,7 +1453,7 @@ static INPUT_PORTS_START(wamazona)
PORT_BIT(0x00000020, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_D) PORT_NAME("Bet 2 Credits")
PORT_BIT(0x00000040, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_S) PORT_NAME("Bet 1 Credit / Red")
PORT_BIT(0x00000400, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_E) PORT_NAME("Diamond")
PORT_BIT(0x00000800, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00000800, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00001000, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_T) PORT_NAME("Club")
INPUT_PORTS_END
@ -1468,7 +1468,7 @@ static INPUT_PORTS_START(sbuk2)
PORT_BIT(0x00000040, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_S) PORT_NAME("Bet 1 Credit / Red")
PORT_BIT(0x00000200, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00000400, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00000800, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00000800, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00001000, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x00002000, IP_ACTIVE_HIGH, IPT_UNUSED)
INPUT_PORTS_END
@ -3572,7 +3572,7 @@ ROM_START( kgbirda5 )
ROM_LOAD32_WORD( "0200024v.u11", 0x000002, 0x80000, CRC(52791ad8) SHA1(6e4cf553b355f03ef69ef3c4e2816bbd0cbe6599) )
ROM_LOAD32_WORD( "0200024v.u8", 0x100000, 0x80000, CRC(c0477ae3) SHA1(5005944b8b28553dd959192d614be7f1b6228a30) )
ROM_LOAD32_WORD( "0200024v.u12", 0x100002, 0x80000, CRC(df176c5a) SHA1(dcaecdefb7c880b9425a6445dbed969968fe3d1c) )
ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASE00 ) /* ARM Code */
ROM_REGION( 0x200000, "vram", ROMREGION_ERASE00 )
ROM_REGION( 0x20000*4, "sram", ROMREGION_ERASE00 )
@ -5306,11 +5306,11 @@ ROM_END
ROM_START( swhr2 )
ARISTOCRAT_MK5_BIOS
/*
Checksum code found at 0x000b68
0x000000-0x05b507 is the Checksummed Range (excluding 0x000020-0x000027 where Checksum is stored)
Expected Checksum 0x757b4b7c
Calculated Checksum 0x757b4b7c (OK)
0x05b508-0x0c43af is the non-Checksummed range (unusual endpoint)
Checksum code found at 0x000b68
0x000000-0x05b507 is the Checksummed Range (excluding 0x000020-0x000027 where Checksum is stored)
Expected Checksum 0x757b4b7c
Calculated Checksum 0x757b4b7c (OK)
0x05b508-0x0c43af is the non-Checksummed range (unusual endpoint)
*/
ROM_REGION( 0x400000, "game_prg", ROMREGION_ERASEFF )
ROM_LOAD32_WORD( "0200465v.u7", 0x000000, 0x80000, CRC(23350042) SHA1(fd839a4835358057a5ee1fcaf716f2443461352d) )
@ -5491,7 +5491,7 @@ ROM_START( toutango )
ROM_LOAD32_WORD( "0100782v.u13", 0x200002, 0x80000, CRC(f8a67a69) SHA1(b1a28047cb4572ae15359c30f71cafa4bd70658c) )
ROM_LOAD32_WORD( "0100782v.u10", 0x300000, 0x80000, CRC(e6528de7) SHA1(b3aa1937f0b673ba2cfa68acc7cb540ebefc66d4) )
ROM_LOAD32_WORD( "0100782v.u14", 0x300002, 0x80000, CRC(69f2acde) SHA1(cda52548e675a06677a2d9fee89b33f9abb96f64) )
ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASE00 ) /* ARM Code */
ROM_REGION( 0x200000, "vram", ROMREGION_ERASE00 )
ROM_REGION( 0x20000*4, "sram", ROMREGION_ERASE00 )
@ -6079,7 +6079,7 @@ GAMEL( 1997, pengpayb, pengpay, aristmk5, swhr2, aristmk5_state, aristm
GAMEL( 1995, pengpayc, pengpay, aristmk5, wcougar, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Penguin Pays (0100113V, NSW/ACT)", MACHINE_FLAGS, layout_wcougar ) // 586, A - 12/10/95
GAMEL( 1997, pengpayu, pengpay, aristmk5_usa, aristmk5_usa, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Penguin Pays (BHI0417-03, US)", MACHINE_FLAGS, layout_aristmk5_us ) // 586/7(b), B - 14/07/97
GAMEL( 2001, pengpuck, pengpay, aristmk5_usa, pengpuck, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Penguin Pays - Penguin Pucks (EHG1257, US)", MACHINE_FLAGS, layout_pengpuck ) // MV4122/1, C - 19/01/01
GAMEL( 1998, petshop, aristmk5, aristmk5, petshop, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Pet Shop (0100731V, NSW/ACT)", MACHINE_FLAGS, layout_petshop ) // 618/1, A - 17/04/98
GAMEL( 1998, petshop, aristmk5, aristmk5, petshop, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Pet Shop (0100731V, NSW/ACT)", MACHINE_FLAGS, layout_petshop ) // 618/1, A - 17/04/98
GAMEL( 1995, phantpay, aristmk5, aristmk5, swhr2, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Phantom Pays (0500005V, NSW/ACT)", MACHINE_FLAGS, layout_swhr2 ) // 570/1, E - 12/09/95
GAMEL( 1998, penpir, aristmk5, aristmk5, kgalah, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Penguin Pirate (0100674V, NSW/ACT)", MACHINE_FLAGS, layout_kgalah ) // 619/1, A - 31/03/98
GAMEL( 1998, penpira, penpir, aristmk5, snowcat, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Penguin Pirate (0200578V, NSW/ACT)", MACHINE_FLAGS, layout_snowcat ) // 619, A - 27/02/98

90
src/mame/drivers/bitgraph.cpp
View File

@ -2,40 +2,40 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
BBN BitGraph -- monochrome, raster graphics (768x1024), serial terminal.
BBN BitGraph -- monochrome, raster graphics (768x1024), serial terminal.
Apparently had at least four hardware revisions, A-D, but which ROM
revisions support which hardware is unclear. A Versabus slot, and
various hardware and software options are mentioned in the docs. Best
guesses follow.
Apparently had at least four hardware revisions, A-D, but which ROM
revisions support which hardware is unclear. A Versabus slot, and
various hardware and software options are mentioned in the docs. Best
guesses follow.
Onboard hardware (common to all revisions) is
- 32K ROM
- 128K RAM (includes frame buffer)
- 3 serial ports, each driven by 6850 ACIA
- some kind of baud rate generator, possibly COM8016
- sync serial port, driven by 6854 but apparently never supported by ROM
- 682x PIA
- AY-3-891x PSG
- ER2055 EAROM
- DEC VT100 keyboard interface
Onboard hardware (common to all revisions) is
- 32K ROM
- 128K RAM (includes frame buffer)
- 3 serial ports, each driven by 6850 ACIA
- some kind of baud rate generator, possibly COM8016
- sync serial port, driven by 6854 but apparently never supported by ROM
- 682x PIA
- AY-3-891x PSG
- ER2055 EAROM
- DEC VT100 keyboard interface
Rev A has additional 4th serial port for mouse (not supported by ROM 1.25).
Rev A has 40 hz realtime clock, the rest use 1040 hz.
Rev A-C use AY-3-8912 (with one external PIO port, to connect the EAROM).
Rev D uses AY-3-8913 (no external ports; EAROM is wired to TBD).
Rev B-D have onboard 8035 to talk to parallel printer and mouse.
Rev B-D have more memory (at least up to 512K).
Rev A has additional 4th serial port for mouse (not supported by ROM 1.25).
Rev A has 40 hz realtime clock, the rest use 1040 hz.
Rev A-C use AY-3-8912 (with one external PIO port, to connect the EAROM).
Rev D uses AY-3-8913 (no external ports; EAROM is wired to TBD).
Rev B-D have onboard 8035 to talk to parallel printer and mouse.
Rev B-D have more memory (at least up to 512K).
ROM 1.25 doesn't support mouse, setup mode, pixel data upload and autowrap.
ROM 1.25 doesn't support mouse, setup mode, pixel data upload and autowrap.
Missing/incorrect emulation:
Bidirectional keyboard interface (to drive LEDs and speaker).
8035.
EAROM.
1.25 only -- clksync() is dummied out -- causes watchdog resets.
Selectable memory size.
Video enable/reverse video switch.
Missing/incorrect emulation:
Bidirectional keyboard interface (to drive LEDs and speaker).
8035.
EAROM.
1.25 only -- clksync() is dummied out -- causes watchdog resets.
Selectable memory size.
Video enable/reverse video switch.
****************************************************************************/
@ -192,7 +192,7 @@ static ADDRESS_MAP_START(bitgraphb_mem, AS_PROGRAM, 16, bitgraph_state)
AM_RANGE(0x010020, 0x010027) AM_READWRITE8(adlc_r, adlc_w, 0xff00)
AM_RANGE(0x010028, 0x01002f) AM_READWRITE8(pia_r, pia_w, 0xff00) // EAROM, PSG
AM_RANGE(0x010030, 0x010031) AM_WRITE(baud_write)
// AM_RANGE(0x010030, 0x010037) AM_READ8(ppu_read, 0x00ff)
// AM_RANGE(0x010030, 0x010037) AM_READ8(ppu_read, 0x00ff)
AM_RANGE(0x010038, 0x01003f) AM_WRITE8(ppu_write, 0x00ff)
AM_RANGE(0x380000, 0x3fffff) AM_RAM
ADDRESS_MAP_END
@ -247,14 +247,14 @@ WRITE8_MEMBER(bitgraph_state::pia_pa_w)
}
/*
B0 O: BC1 to noisemaker.
B1 O: BDIR to noisemaker.
B2 O: Clock for EAROM.
B3 O: CS1 for EAROM.
B4 O: Enable HDLC Xmt interrupt.
B5 O: Enable HDLC Rcv interrupt.
B6 O: Clear Clock interrupt. Must write a 0 [clear interrupt], then a 1.
B7 I: EVEN field ??
B0 O: BC1 to noisemaker.
B1 O: BDIR to noisemaker.
B2 O: Clock for EAROM.
B3 O: CS1 for EAROM.
B4 O: Enable HDLC Xmt interrupt.
B5 O: Enable HDLC Rcv interrupt.
B6 O: Clear Clock interrupt. Must write a 0 [clear interrupt], then a 1.
B7 I: EVEN field ??
*/
READ8_MEMBER(bitgraph_state::pia_pb_r)
{
@ -423,18 +423,18 @@ WRITE8_MEMBER(bitgraph_state::ppu_write)
#ifdef UNUSED_FUNCTION
static ADDRESS_MAP_START(ppu_io, AS_IO, 8, bitgraph_state)
// AM_RANGE(0x00, 0x00) AM_READ(ppu_irq)
// AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1)
// AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(ppu_t0_r)
// AM_RANGE(0x00, 0x00) AM_READ(ppu_irq)
// AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1)
// AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(ppu_t0_r)
AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("i8243", i8243_device, i8243_prog_w)
ADDRESS_MAP_END
#endif
/*
p4 O: Centronics data 3..0
p5 O: Centronics data 7..4
p6 O: Centronics control
p7 I: Centronics status
p4 O: Centronics data 3..0
p5 O: Centronics data 7..4
p6 O: Centronics control
p7 I: Centronics status
*/
WRITE8_MEMBER(bitgraph_state::ppu_i8243_w)
{

4
src/mame/drivers/cc40.cpp
View File

@ -304,7 +304,7 @@ READ8_MEMBER(cc40_state::bankswitch_r)
WRITE8_MEMBER(cc40_state::bankswitch_w)
{
data &= 0x0f;
// d0-d1: system rom bankswitch
membank("sysbank")->set_entry(data & 3);
@ -330,7 +330,7 @@ void cc40_state::update_clock_divider()
WRITE8_MEMBER(cc40_state::clock_control_w)
{
data &= 0x0f;
// d0-d2: clock divider
// d3: enable clock divider always
// other bits: unused?

4
src/mame/drivers/cxgz80.cpp
View File

@ -72,7 +72,7 @@ public:
u16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
u32 m_display_cache[0x20]; // (internal use)
u8 m_display_decay[0x20][0x20]; // (internal use)
TIMER_DEVICE_CALLBACK_MEMBER(display_decay_tick);
void display_update();
void set_display_size(int maxx, int maxy);
@ -260,7 +260,7 @@ WRITE8_MEMBER(cxgz80_state::ch2001_leds_w)
// 74ls273 Q1-Q4: 74ls145 A-D
// 74ls145 0-9: input mux/led select
m_inp_mux = 1 << (data & 0xf) & 0x3ff;
// 74ls273 Q5-Q8: MC14028 A-D
// MC14028 Q0-Q7: led data, Q8,Q9: N/C
u8 led_data = 1 << (data >> 4 & 0xf) & 0xff;

104
src/mame/drivers/dvk_ksm.cpp
View File

@ -2,60 +2,60 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
KSM (Kontroller Simvolnogo Monitora = Character Display Controller),
a single-board replacement for standalone 15IE-00-013 terminal (ie15.c)
in later-model DVK desktops.
KSM (Kontroller Simvolnogo Monitora = Character Display Controller),
a single-board replacement for standalone 15IE-00-013 terminal (ie15.c)
in later-model DVK desktops.
MPI (Q-Bus clone) board, consumes only power from the bus.
Interfaces with MS7004 (DEC LK201 workalike) keyboard and monochrome CRT.
MPI (Q-Bus clone) board, consumes only power from the bus.
Interfaces with MS7004 (DEC LK201 workalike) keyboard and monochrome CRT.
Hardware revisions (XXX verify everything):
- 7.102.076 -- has DIP switches, SRAM at 0x2000, model name "KSM"
- 7.102.228 -- no DIP switches, ?? SRAM at 0x2100, model name "KSM-01"
Hardware revisions (XXX verify everything):
- 7.102.076 -- has DIP switches, SRAM at 0x2000, model name "KSM"
- 7.102.228 -- no DIP switches, ?? SRAM at 0x2100, model name "KSM-01"
Two sets of dumps exist:
- one puts SRAM at 0x2000, which is where technical manual puts it,
but chargen has 1 missing pixel in 'G' character.
- another puts SRAM at 0x2100, but has no missing pixel.
Merge them for now into one (SRAM at 0x2000 and no missing pixel).
Two sets of dumps exist:
- one puts SRAM at 0x2000, which is where technical manual puts it,
but chargen has 1 missing pixel in 'G' character.
- another puts SRAM at 0x2100, but has no missing pixel.
Merge them for now into one (SRAM at 0x2000 and no missing pixel).
Emulates a VT52 without copier (ESC Z response is ESC / M), with
Hold Screen mode and Graphics character set (but it is unique and
mapped to a different range -- 100..137).
Emulates a VT52 without copier (ESC Z response is ESC / M), with
Hold Screen mode and Graphics character set (but it is unique and
mapped to a different range -- 100..137).
F4 + 0..9 on numeric keypad = setup mode. 0 changes serial port speed,
1..9 toggle one of mode bits:
F4 + 0..9 on numeric keypad = setup mode. 0 changes serial port speed,
1..9 toggle one of mode bits:
1 XON/XOFF 0: Off 1: On
2 Character set 0: N0/N1 2: N2
3 Auto LF 0: Off 1: On
4 Auto repeat 0: On 1: Off
5 Auto wraparound 0: On 1: Off
6 Interpret controls 0: Interpret 1: Display
7 Parity check 0: Off 1: On
8 Parity bits 0: None 1: Even
9 Stop bits
1 XON/XOFF 0: Off 1: On
2 Character set 0: N0/N1 2: N2
3 Auto LF 0: Off 1: On
4 Auto repeat 0: On 1: Off
5 Auto wraparound 0: On 1: Off
6 Interpret controls 0: Interpret 1: Display
7 Parity check 0: Off 1: On
8 Parity bits 0: None 1: Even
9 Stop bits
N0/N1 charset has regular ASCII in C0 page and Cyrillic in C1 page,
switching between them via SI/SO. N2 charset has uppercase Cyrillic
chars in place of lowercase Latin ones.
N0/N1 charset has regular ASCII in C0 page and Cyrillic in C1 page,
switching between them via SI/SO. N2 charset has uppercase Cyrillic
chars in place of lowercase Latin ones.
ESC toggles Cyrillic/Latin mode (depends in the host's terminal driver)
F1 toggles Hold Screen mode (also depends in the host's terminal driver)
F9 resets terminal (clears memory).
F20 toggles on/off-line mode.
ESC toggles Cyrillic/Latin mode (depends in the host's terminal driver)
F1 toggles Hold Screen mode (also depends in the host's terminal driver)
F9 resets terminal (clears memory).
F20 toggles on/off-line mode.
Terminfo description:
Terminfo description:
ksm|DVK KSM,
am, bw, dch1=\EP, ich1=\EQ,
acsc=hRiTjXkClJmFnNqUtEuPv\174wKxW.M\054Q\055S\053\136~_{@}Z0\177,
use=vt52,
am, bw, dch1=\EP, ich1=\EQ,
acsc=hRiTjXkClJmFnNqUtEuPv\174wKxW.M\054Q\055S\053\136~_{@}Z0\177,
use=vt52,
To do:
- verify if pixel stretching is done by hw
- verify details of hw revisions (memory map, DIP presence...)
- baud rate selection
To do:
- verify if pixel stretching is done by hw
- verify details of hw revisions (memory map, DIP presence...)
- baud rate selection
****************************************************************************/
@ -241,19 +241,19 @@ WRITE_LINE_MEMBER(ksm_state::write_line_clock)
}
/*
Raster size is 28x11 scan lines.
XXX VBlank is active for 2 topmost on-screen rows and 1 at the bottom.
Raster size is 28x11 scan lines.
XXX VBlank is active for 2 topmost on-screen rows and 1 at the bottom.
Usable raster is 800 x 275 pixels (80 x 25 characters). 24 lines are
available to the user and 25th (topmost) line is the status line.
Status line displays current serial port speed and 9 setup bits.
Usable raster is 800 x 275 pixels (80 x 25 characters). 24 lines are
available to the user and 25th (topmost) line is the status line.
Status line displays current serial port speed and 9 setup bits.
No character attributes are available, but in 'display controls' mode
control characters stored in memory are shown as blinking chars.
No character attributes are available, but in 'display controls' mode
control characters stored in memory are shown as blinking chars.
Character cell is 10 x 11; character generator provides 7 x 8 of that.
3 extra horizontal pixels are always XXX blank. Blinking XXX cursor may be
displayed on 3 extra scan lines.
Character cell is 10 x 11; character generator provides 7 x 8 of that.
3 extra horizontal pixels are always XXX blank. Blinking XXX cursor may be
displayed on 3 extra scan lines.
*/
uint32_t ksm_state::draw_scanline(uint16_t *p, uint16_t offset, uint8_t scanline)

4
src/mame/drivers/ec184x.cpp
View File

@ -2,9 +2,9 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
drivers/ec184x.c
drivers/ec184x.c
Driver file for EC-184x series
Driver file for EC-184x series
***************************************************************************/

38
src/mame/drivers/eurocom2.cpp
View File

@ -343,8 +343,8 @@ static ADDRESS_MAP_START(waveterm_map, AS_PROGRAM, 8, waveterm_state)
AM_RANGE(0xfd00, 0xfd03) AM_DEVREADWRITE("pia3", pia6821_device, read, write)
AM_RANGE(0xfd08, 0xfd0f) AM_DEVREADWRITE("ptm", ptm6840_device, read, write)
AM_RANGE(0xfd10, 0xfd17) AM_UNMAP
AM_RANGE(0xfd18, 0xfd18) AM_READ(waveterm_adc) // AD558 ADC
// AM_RANGE(0xfd20, 0xfd20) AM_READ(waveterm_dac) // ZN432 DAC ??
AM_RANGE(0xfd18, 0xfd18) AM_READ(waveterm_adc) // AD558 ADC
// AM_RANGE(0xfd20, 0xfd20) AM_READ(waveterm_dac) // ZN432 DAC ??
ADDRESS_MAP_END
static INPUT_PORTS_START(eurocom2)
@ -441,18 +441,18 @@ static MACHINE_CONFIG_START( eurocom2, eurocom2_state )
MCFG_GENERIC_KEYBOARD_CB(WRITE8(eurocom2_state, kbd_put))
MCFG_DEVICE_ADD("pia1", PIA6821, 0)
MCFG_PIA_READCA1_HANDLER(READLINE(eurocom2_state, pia1_ca1_r)) // keyboard strobe
MCFG_PIA_READCA2_HANDLER(READLINE(eurocom2_state, pia1_ca2_r)) // SST output Q14
MCFG_PIA_READCB1_HANDLER(READLINE(eurocom2_state, pia1_cb1_r)) // SST output Q6
MCFG_PIA_CB2_HANDLER(WRITELINE(eurocom2_state, pia1_cb2_w)) // SST reset input
MCFG_PIA_READCA1_HANDLER(READLINE(eurocom2_state, pia1_ca1_r)) // keyboard strobe
MCFG_PIA_READCA2_HANDLER(READLINE(eurocom2_state, pia1_ca2_r)) // SST output Q14
MCFG_PIA_READCB1_HANDLER(READLINE(eurocom2_state, pia1_cb1_r)) // SST output Q6
MCFG_PIA_CB2_HANDLER(WRITELINE(eurocom2_state, pia1_cb2_w)) // SST reset input
MCFG_PIA_READPA_HANDLER(READ8(eurocom2_state, kbd_get))
// MCFG_PIA_READPB_HANDLER(READ8(eurocom2_state, kbd_get))
// MCFG_PIA_IRQA_HANDLER(INPUTLINE("maincpu", M6809_IRQ_LINE))
// MCFG_PIA_IRQB_HANDLER(INPUTLINE("maincpu", M6809_IRQ_LINE))
// MCFG_PIA_READPB_HANDLER(READ8(eurocom2_state, kbd_get))
// MCFG_PIA_IRQA_HANDLER(INPUTLINE("maincpu", M6809_IRQ_LINE))
// MCFG_PIA_IRQB_HANDLER(INPUTLINE("maincpu", M6809_IRQ_LINE))
MCFG_DEVICE_ADD("pia2", PIA6821, 0)
// MCFG_PIA_IRQA_HANDLER(INPUTLINE("maincpu", M6809_FIRQ_LINE))
// MCFG_PIA_IRQB_HANDLER(INPUTLINE("maincpu", M6809_FIRQ_LINE))
// MCFG_PIA_IRQA_HANDLER(INPUTLINE("maincpu", M6809_FIRQ_LINE))
// MCFG_PIA_IRQB_HANDLER(INPUTLINE("maincpu", M6809_FIRQ_LINE))
MCFG_DEVICE_ADD("acia", ACIA6850, 0)
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE ("rs232", rs232_port_device, write_txd))
@ -462,11 +462,11 @@ static MACHINE_CONFIG_START( eurocom2, eurocom2_state )
MCFG_RS232_CTS_HANDLER(DEVWRITELINE ("acia", acia6850_device, write_cts))
MCFG_FD1793_ADD("fdc", XTAL_2MHz/2)
// MCFG_WD_FDC_INTRQ_CALLBACK(INPUTLINE("maincpu", M6809_IRQ_LINE))
// MCFG_WD_FDC_INTRQ_CALLBACK(INPUTLINE("maincpu", M6809_IRQ_LINE))
MCFG_FLOPPY_DRIVE_ADD("fdc:0", eurocom_floppies, "525qd", eurocom2_state::floppy_formats)
// MCFG_FLOPPY_DRIVE_SOUND(true)
// MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", eurocom_floppies, "525qd", eurocom2_state::floppy_formats)
// MCFG_FLOPPY_DRIVE_SOUND(true)
// MCFG_FLOPPY_DRIVE_SOUND(true)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED_CLASS(waveterm, eurocom2, waveterm_state)
@ -481,13 +481,13 @@ static MACHINE_CONFIG_DERIVED_CLASS(waveterm, eurocom2, waveterm_state)
// ports A(in/out), B(out), CA1(in), CA2(in), and CB2(out) = interface to PPG bus via DIL socket on WTI board
// CB1 -- front panel "End" button
MCFG_DEVICE_ADD("pia3", PIA6821, 0)
// MCFG_PIA_READPA_HANDLER(READ8(waveterm_state, pia3_pa_r))
// MCFG_PIA_WRITEPA_HANDLER(WRITE8(waveterm_state, pia3_pa_w))
// MCFG_PIA_READPA_HANDLER(READ8(waveterm_state, pia3_pa_r))
// MCFG_PIA_WRITEPA_HANDLER(WRITE8(waveterm_state, pia3_pa_w))
MCFG_PIA_WRITEPB_HANDLER(WRITE8(waveterm_state, pia3_pb_w))
// MCFG_PIA_READCA1_HANDLER(READLINE(waveterm_state, pia3_ca1_r))
// MCFG_PIA_READCA2_HANDLER(READLINE(waveterm_state, pia3_ca2_r))
// MCFG_PIA_READCA1_HANDLER(READLINE(waveterm_state, pia3_ca1_r))
// MCFG_PIA_READCA2_HANDLER(READLINE(waveterm_state, pia3_ca2_r))
MCFG_PIA_READCB1_HANDLER(IOPORT("FP"))
// MCFG_PIA_CB2_HANDLER(WRITELINE(waveterm_state, pia3_cb2_w))
// MCFG_PIA_CB2_HANDLER(WRITELINE(waveterm_state, pia3_cb2_w))
MCFG_DEVICE_ADD("ptm", PTM6840, 0)

4
src/mame/drivers/fidel6502.cpp
View File

@ -493,7 +493,7 @@ public:
DECLARE_WRITE8_MEMBER(fdesdis_lcd_w);
DECLARE_READ8_MEMBER(fdesdis_input_r);
DECLARE_DRIVER_INIT(fdesdis);
// Phantom
DECLARE_MACHINE_RESET(fphantom);
DECLARE_DRIVER_INIT(fphantom);
@ -1008,7 +1008,7 @@ WRITE8_MEMBER(fidel6502_state::chesster_control_w)
WRITE8_MEMBER(fidel6502_state::kishon_control_w)
{
chesster_control_w(space, offset, data);
// 2 more bankswitch bits: 74259(2) Q2 to A17, Q0 to A18
membank("bank1")->set_entry((m_led_select >> 2 & 3) | (m_speech_bank >> 1 & 4) | (m_speech_bank << 1 & 8) | (m_speech_bank << 4 & 0x10));
}

28
src/mame/drivers/h19.cpp
View File

@ -2,22 +2,22 @@
// copyright-holders:Robbbert, Mark Garlanger
/***************************************************************************
Heathkit H19
Heathkit H19
A smart terminal designed and manufactured by Heath Company.
A smart terminal designed and manufactured by Heath Company.
The keyboard consists of a 9x10 matrix connected to a MM5740AAC/N
mask-programmed keyboard controller. The output of this passes
through a rom.
The keyboard consists of a 9x10 matrix connected to a MM5740AAC/N
mask-programmed keyboard controller. The output of this passes
through a rom.
Input can also come from the serial port (a 8250).
Either device will signal an interrupt to the CPU when a key
is pressed/data is received.
Input can also come from the serial port (a 8250).
Either device will signal an interrupt to the CPU when a key
is pressed/data is received.
TODO:
- speed up emulation
- update SW401 baud rate options for Watz ROM
- update SW401 & SW402 definitions for Super-19 ROM
TODO:
- speed up emulation
- update SW401 baud rate options for Watz ROM
- update SW401 & SW402 definitions for Super-19 ROM
****************************************************************************/
/***************************************************************************
@ -176,7 +176,7 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( h19 )
PORT_START("MODIFIERS")
// bit 0 connects to B8 of MM5740 - low if either shift key is
// bit 0 connects to B8 of MM5740 - low if either shift key is
// bit 7 is low if a key is pressed
PORT_BIT(0x002, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CapsLock") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
PORT_BIT(0x004, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Break") PORT_CODE(KEYCODE_PAUSE)
@ -530,7 +530,7 @@ static MACHINE_CONFIG_START( h19, h19_state )
MCFG_MC6845_ADD("crtc", MC6845, "screen", MC6845_CLOCK)
MCFG_MC6845_SHOW_BORDER_AREA(true)
MCFG_MC6845_CHAR_WIDTH(8)
MCFG_MC6845_CHAR_WIDTH(8)
MCFG_MC6845_UPDATE_ROW_CB(h19_state, crtc_update_row)
MCFG_MC6845_OUT_VSYNC_CB(INPUTLINE("maincpu", INPUT_LINE_NMI)) // frame pulse

8
src/mame/drivers/hh_pic16.cpp
View File

@ -431,7 +431,7 @@ void pabball_state::prepare_display()
u16 sel = m_c & 0xf;
if (sel & 8) sel &= 9;
sel = 1 << sel;
// CD4028 9 is 7seg
set_display_segmask(0x200, 0xff);
display_matrix(8, 10, m_b, sel);
@ -448,10 +448,10 @@ WRITE8_MEMBER(pabball_state::write_c)
{
// C2: RTCC pin
m_maincpu->set_input_line(PIC16C5x_RTCC, data >> 2 & 1);
// C7: speaker out
m_speaker->level_w(data >> 7 & 1);
// C0-C3: CD4028 A-D
m_c = data;
prepare_display();
@ -1535,7 +1535,7 @@ WRITE8_MEMBER(us2pfball_state::write_c)
{
// C7: speaker out
m_speaker->level_w(data >> 7 & 1);
// C0-C6: digit segments
m_c = data;
prepare_display();

4
src/mame/drivers/hh_tms1k.cpp
View File

@ -1628,7 +1628,7 @@ MACHINE_CONFIG_END
Coleco Quiz Wiz Challenger
* TMS1000NLL M32001-N2 (die label 1000E, M32001)
* 4 7seg LEDs, 17 other LEDs, 1-bit sound
This is a 4-player version of Quiz Wiz, a multiple choice quiz game.
According to the manual, Quiz Wiz cartridges are compatible with it.
The question books are needed to play, as well as optional game pieces.
@ -2435,7 +2435,7 @@ MACHINE_CONFIG_END
CONIC 102-001, led PCB: CONIC 100-003 REV A itac
* TMS1000NLL MP0908 (die label 1000B, MP0908)
* 2 7seg LEDs, 30 other LEDs, 1-bit sound
This is a peg solitaire game, with random start position.
known releases:

240
src/mame/drivers/hp9845.cpp
View File

@ -78,7 +78,7 @@
Timing and pixel size for real 98750A are slightly different between
alpha and graphics raster (dual raster):
alpha graphics
alpha graphics
------------------------------------------------------
Matrix: 720x375 560x455
Clock frequency: 20.85 MHz 20.85 MHz
@ -95,7 +95,7 @@
hold up to 30 rows with full size characters plus some lines for one row with
cropped characters:
98770A 98780A
98770A 98780A
------------------------------------------------------
Matrix: 720x455 720x455
Clock frequency: 29.7984 MHz 28.224 MHz
@ -109,8 +109,8 @@
*/
// Base address of video buffer
#define VIDEO_BUFFER_BASE_LOW 0x16000 // for 98770A and 98780A
#define VIDEO_BUFFER_BASE_HIGH 0x17000 // for 98750A
#define VIDEO_BUFFER_BASE_LOW 0x16000 // for 98770A and 98780A
#define VIDEO_BUFFER_BASE_HIGH 0x17000 // for 98750A
// For test "B" of alpha video to succeed this must be < 234
// Basically "B" test is designed to intentionally prevent line buffer to be filled so that display is blanked
@ -129,7 +129,7 @@
#define VIDEO_HTOTAL (VIDEO_CHAR_WIDTH * VIDEO_CHAR_TOTAL)
#define VIDEO_VTOTAL (VIDEO_CHAR_HEIGHT * VIDEO_ROWS_TOTAL)
#define VIDEO_ACTIVE_SCANLINES (VIDEO_CHAR_HEIGHT * VIDEO_CHAR_ROWS)
#define VIDEO_TOT_HPIXELS (VIDEO_CHAR_WIDTH * VIDEO_CHAR_COLUMNS)
#define VIDEO_TOT_HPIXELS (VIDEO_CHAR_WIDTH * VIDEO_CHAR_COLUMNS)
// Constants of graphic video
// Pixel clock is 20.8494 MHz (the same as alpha video)
@ -151,35 +151,35 @@
// Constants of 98770A video
// HBEND & VBEND probably are not really 0
#define VIDEO_770_PIXEL_CLOCK 29798400
#define VIDEO_770_HTOTAL 1024
#define VIDEO_770_HBEND 0
#define VIDEO_770_HBSTART (VIDEO_CHAR_COLUMNS * VIDEO_CHAR_WIDTH)
#define VIDEO_770_VTOTAL 485
#define VIDEO_770_VBEND 0
#define VIDEO_770_VBSTART (VIDEO_770_VBEND + GVIDEO_VPIXELS)
#define VIDEO_770_ALPHA_L_LIM 80 // Left-side limit of alpha-only horizontal part
#define VIDEO_770_ALPHA_R_LIM 640 // Right-side limit of alpha-only horizontal part
#define VIDEO_770_PIXEL_CLOCK 29798400
#define VIDEO_770_HTOTAL 1024
#define VIDEO_770_HBEND 0
#define VIDEO_770_HBSTART (VIDEO_CHAR_COLUMNS * VIDEO_CHAR_WIDTH)
#define VIDEO_770_VTOTAL 485
#define VIDEO_770_VBEND 0
#define VIDEO_770_VBSTART (VIDEO_770_VBEND + GVIDEO_VPIXELS)
#define VIDEO_770_ALPHA_L_LIM 80 // Left-side limit of alpha-only horizontal part
#define VIDEO_770_ALPHA_R_LIM 640 // Right-side limit of alpha-only horizontal part
#define I_GR 0xb0 // graphics intensity
#define I_AL 0xd0 // alpha intensity
#define I_CU 0xf0 // graphics cursor intensity
#define I_LP 0xff // light pen cursor intensity
#define I_GR 0xb0 // graphics intensity
#define I_AL 0xd0 // alpha intensity
#define I_CU 0xf0 // graphics cursor intensity
#define I_LP 0xff // light pen cursor intensity
// Palette indexes (for monochromatic screens)
#define PEN_BLACK 0 // Black
#define PEN_GRAPHIC 1 // Graphics
#define PEN_ALPHA 2 // Text
#define PEN_CURSOR 3 // Graphic cursor
#define PEN_LP 4 // Light pen cursor
#define PEN_BLACK 0 // Black
#define PEN_GRAPHIC 1 // Graphics
#define PEN_ALPHA 2 // Text
#define PEN_CURSOR 3 // Graphic cursor
#define PEN_LP 4 // Light pen cursor
// Light pen constants
constexpr unsigned LP_FOV = 9; // Field of view
constexpr unsigned LP_XOFFSET = 5; // x-offset of LP (due to delay in hit recognition)
constexpr unsigned LP_FOV = 9; // Field of view
constexpr unsigned LP_XOFFSET = 5; // x-offset of LP (due to delay in hit recognition)
// Peripheral Addresses (PA)
#define IO_SLOT_FIRST_PA 1
#define IO_SLOT_LAST_PA 12
#define IO_SLOT_FIRST_PA 1
#define IO_SLOT_LAST_PA 12
#define T15_PA 15
#define KEY_SCAN_OSCILLATOR 327680
@ -754,10 +754,10 @@ void hp9845b_state::machine_start()
m_graphic_mem.resize(GVIDEO_MEM_SIZE);
// initialize palette
m_palette->set_pen_color(PEN_BLACK , 0x00, 0x00, 0x00); // black
m_palette->set_pen_color(PEN_GRAPHIC, 0x00, I_GR, 0x00); // graphics
m_palette->set_pen_color(PEN_ALPHA , 0x00, I_AL, 0x00); // alpha
m_palette->set_pen_color(PEN_CURSOR , 0x00, I_CU, 0x00); // graphics cursor
m_palette->set_pen_color(PEN_BLACK , 0x00, 0x00, 0x00); // black
m_palette->set_pen_color(PEN_GRAPHIC, 0x00, I_GR, 0x00); // graphics
m_palette->set_pen_color(PEN_ALPHA , 0x00, I_AL, 0x00); // alpha
m_palette->set_pen_color(PEN_CURSOR , 0x00, I_CU, 0x00); // graphics cursor
}
void hp9845b_state::machine_reset()
@ -789,7 +789,7 @@ READ16_MEMBER(hp9845b_state::graphic_r)
if (m_gv_dma_en) {
BIT_SET(res, 6);
}
BIT_SET(res, 5); // ID
BIT_SET(res, 5); // ID
break;
case 2:
@ -1487,7 +1487,7 @@ void hp9845ct_state::draw_line(unsigned x0 , unsigned y0 , unsigned x1 , unsigne
x = x0;
y = y0;
dx = abs((int) (x1 - x));
sx = x < x1 ? 1 : -1; // actually always 1 because of normalization
sx = x < x1 ? 1 : -1; // actually always 1 because of normalization
dy = abs((int) (y1 - y));
sy = y < y1 ? 1 : -1;
err = (dx > dy ? dx : -dy) / 2;
@ -1682,7 +1682,7 @@ uint16_t hp9845ct_state::lp_r4_r(void)
void hp9845ct_state::lp_r5_w(uint16_t data)
{
m_gv_lp_reg_cnt = data & 7;
m_gv_lp_en = (data & 0x700) == 0x400; // enables writes on R4 to set LP data (actually FB bit), also enables LP command processing and LP IRQs
m_gv_lp_en = (data & 0x700) == 0x400; // enables writes on R4 to set LP data (actually FB bit), also enables LP command processing and LP IRQs
m_gv_lp_int_en = (data & 0x500) == 0x400;
m_gv_lp_selftest = m_gv_lp_en && m_gv_lp_reg_cnt == 7;
update_graphic_bits();
@ -1727,7 +1727,7 @@ void hp9845ct_state::compute_lp_data(void)
uint16_t xleft = 0;
uint16_t yleft = 0;
uint16_t ylo = 0;
uint16_t xp = m_gv_lp_x; // light gun pointer
uint16_t xp = m_gv_lp_x; // light gun pointer
uint16_t yp = m_gv_lp_y;
int yc = get_lp_cursor_y_top() + 24;
@ -1735,10 +1735,10 @@ void hp9845ct_state::compute_lp_data(void)
constexpr int offset = 57 - VIDEO_770_ALPHA_L_LIM;
xwindow[ 0 ] = xwindow[ 1 ] = xwindow[ 2 ] = true;
ywindow[ 0 ] = ywindow[ 1 ] = ywindow[ 2 ] = true;
yhi = m_gv_lp_cursor_y + 16; // YHI
xleft = m_gv_lp_cursor_x + offset; // XLEFT
yhi = m_gv_lp_cursor_y + 16; // YHI
xleft = m_gv_lp_cursor_x + offset; // XLEFT
yleft = yhi;
ylo = m_gv_lp_cursor_y + 32; // YLO
ylo = m_gv_lp_cursor_y + 32; // YLO
} else {
// Hit in a cursor-only part.
bool yhi_hit = false;
@ -1799,9 +1799,9 @@ void hp9845ct_state::compute_lp_data(void)
ywindow[ 1 ] = yleft == yc;
ywindow[ 2 ] = yleft == yc && ylo >= yleft;
}
m_gv_next_lp_data[ 0 ] = ~yhi & 0x1ff; // YHI
m_gv_next_lp_data[ 1 ] = ~xleft & 0x3ff; // XLEFT
m_gv_next_lp_data[ 2 ] = ~ylo & 0x1ff; // YLO
m_gv_next_lp_data[ 0 ] = ~yhi & 0x1ff; // YHI
m_gv_next_lp_data[ 1 ] = ~xleft & 0x3ff; // XLEFT
m_gv_next_lp_data[ 2 ] = ~ylo & 0x1ff; // YLO
if (!xwindow[ 0 ]) {
BIT_SET(m_gv_next_lp_data[ 0 ], 13);
@ -1924,34 +1924,34 @@ void hp9845c_state::machine_start()
// initialize palette
// graphics colors
m_palette->set_pen_color(0, 0x00, 0x00, 0x00); // black
m_palette->set_pen_color(1, I_GR, 0x00, 0x00); // red
m_palette->set_pen_color(2, 0x00, I_GR, 0x00); // green
m_palette->set_pen_color(3, I_GR, I_GR, 0x00); // yellow
m_palette->set_pen_color(4, 0x00, 0x00, I_GR); // blue
m_palette->set_pen_color(5, I_GR, 0x00, I_GR); // magenta
m_palette->set_pen_color(6, 0x00, I_GR, I_GR); // cyan
m_palette->set_pen_color(7, I_GR, I_GR, I_GR); // white
m_palette->set_pen_color(0, 0x00, 0x00, 0x00); // black
m_palette->set_pen_color(1, I_GR, 0x00, 0x00); // red
m_palette->set_pen_color(2, 0x00, I_GR, 0x00); // green
m_palette->set_pen_color(3, I_GR, I_GR, 0x00); // yellow
m_palette->set_pen_color(4, 0x00, 0x00, I_GR); // blue
m_palette->set_pen_color(5, I_GR, 0x00, I_GR); // magenta
m_palette->set_pen_color(6, 0x00, I_GR, I_GR); // cyan
m_palette->set_pen_color(7, I_GR, I_GR, I_GR); // white
// alpha colors
m_palette->set_pen_color(8, 0x00, 0x00, 0x00); // black
m_palette->set_pen_color(9, I_AL, 0x00, 0x00); // red
m_palette->set_pen_color(10, 0x00, I_AL, 0x00); // green
m_palette->set_pen_color(11, I_AL, I_AL, 0x00); // yellow
m_palette->set_pen_color(12, 0x00, 0x00, I_AL); // blue
m_palette->set_pen_color(13, I_AL, 0x00, I_AL); // magenta
m_palette->set_pen_color(14, 0x00, I_AL, I_AL); // cyan
m_palette->set_pen_color(15, I_AL, I_AL, I_AL); // white
m_palette->set_pen_color(8, 0x00, 0x00, 0x00); // black
m_palette->set_pen_color(9, I_AL, 0x00, 0x00); // red
m_palette->set_pen_color(10, 0x00, I_AL, 0x00); // green
m_palette->set_pen_color(11, I_AL, I_AL, 0x00); // yellow
m_palette->set_pen_color(12, 0x00, 0x00, I_AL); // blue
m_palette->set_pen_color(13, I_AL, 0x00, I_AL); // magenta
m_palette->set_pen_color(14, 0x00, I_AL, I_AL); // cyan
m_palette->set_pen_color(15, I_AL, I_AL, I_AL); // white
// cursor colors
m_palette->set_pen_color(16, 0x80, 0x80, 0x80); // grey
m_palette->set_pen_color(17, I_CU, 0x00, 0x00); // red
m_palette->set_pen_color(18, 0x00, I_CU, 0x00); // green
m_palette->set_pen_color(19, I_CU, I_CU, 0x00); // yellow
m_palette->set_pen_color(20, 0x00, 0x00, I_CU); // blue
m_palette->set_pen_color(21, I_CU, 0x00, I_CU); // magenta
m_palette->set_pen_color(22, 0x00, I_CU, I_CU); // cyan
m_palette->set_pen_color(23, I_CU, I_CU, I_CU); // white
m_palette->set_pen_color(16, 0x80, 0x80, 0x80); // grey
m_palette->set_pen_color(17, I_CU, 0x00, 0x00); // red
m_palette->set_pen_color(18, 0x00, I_CU, 0x00); // green
m_palette->set_pen_color(19, I_CU, I_CU, 0x00); // yellow
m_palette->set_pen_color(20, 0x00, 0x00, I_CU); // blue
m_palette->set_pen_color(21, I_CU, 0x00, I_CU); // magenta
m_palette->set_pen_color(22, 0x00, I_CU, I_CU); // cyan
m_palette->set_pen_color(23, I_CU, I_CU, I_CU); // white
}
void hp9845c_state::machine_reset()
@ -1993,13 +1993,13 @@ READ16_MEMBER(hp9845c_state::graphic_r)
BIT_SET(res, 6);
}
if (m_gv_lp_status && m_gv_lp_int_en) {
BIT_SET(res, 0); // Lightpen service request
BIT_SET(res, 0); // Lightpen service request
}
if (m_gv_sk_status) {
BIT_SET(res, 1); // Softkey service request
BIT_SET(res, 1); // Softkey service request
m_gv_sk_status = false;
}
BIT_SET(res, 11); // ID
BIT_SET(res, 11); // ID
update_graphic_bits();
break;
@ -2042,12 +2042,12 @@ WRITE16_MEMBER(hp9845c_state::graphic_w)
m_gv_cmd = (uint8_t)(data & 0xf);
m_gv_dma_en = BIT(data , 6) != 0;
m_gv_int_en = BIT(data , 7) != 0;
m_gv_gr_en = BIT(data , 8); // enables graphics controller & vector generator command processing and IRQs
m_gv_sk_en = BIT(data , 9); // enables reads on R4 to return SK keycode, also enables SK IRQs
m_gv_opt_en = BIT(data , 11); // not really used
m_gv_dsa_en = BIT(data , 12); // for factory use only (unknown)
m_gv_gr_en = BIT(data , 8); // enables graphics controller & vector generator command processing and IRQs
m_gv_sk_en = BIT(data , 9); // enables reads on R4 to return SK keycode, also enables SK IRQs
m_gv_opt_en = BIT(data , 11); // not really used
m_gv_dsa_en = BIT(data , 12); // for factory use only (unknown)
if (BIT(data, 5)) {
m_gv_fsm_state = GV_STAT_RESET; // command/reset state machine
m_gv_fsm_state = GV_STAT_RESET; // command/reset state machine
}
advance_gv_fsm(false , false);
lp_r5_w(data);
@ -2344,7 +2344,7 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
// read words command
check_io_counter_restore();
LOG(("read words, last = %x\n", m_gv_last_cmd));
m_gv_fsm_state = GV_STAT_WAIT_MEM_0; // -> read stream
m_gv_fsm_state = GV_STAT_WAIT_MEM_0; // -> read stream
m_gv_last_cmd = m_gv_cmd;
} else if (ds) {
if ((m_gv_cmd == 0x0) || (m_gv_cmd == 0x2)) {
@ -2352,10 +2352,10 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
check_io_counter_restore();
if (m_gv_cmd == 0x2) LOG(("clear/set words, last = %x\n", m_gv_last_cmd));
else LOG(("write words, last = %x\n", m_gv_last_cmd));
m_gv_fsm_state = GV_STAT_WAIT_TRIG_1; // -> write stream
m_gv_fsm_state = GV_STAT_WAIT_TRIG_1; // -> write stream
} else {
// any other command
m_gv_fsm_state = GV_STAT_WAIT_TRIG_0; // -> wait for trigger
m_gv_fsm_state = GV_STAT_WAIT_TRIG_0; // -> wait for trigger
}
m_gv_last_cmd = m_gv_cmd;
} else {
@ -2367,25 +2367,25 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
// process data on R4 or R6
if (act_trig) {
switch (m_gv_cmd) {
case 0x8: // load X I/O address
m_gv_word_x_position = ~m_gv_data_w & 0x3f; // 0..34
case 0x8: // load X I/O address
m_gv_word_x_position = ~m_gv_data_w & 0x3f; // 0..34
LOG(("load X I/O adress = %04x\n", m_gv_word_x_position));
m_gv_io_counter = get_gv_mem_addr(m_gv_word_x_position , m_gv_word_y_position);
m_gv_plane = 0;
m_gv_plane_wrap = false;
break;
case 0x9: // load Y I/O address
m_gv_word_y_position = ~m_gv_data_w & 0x1ff; // 0..454
case 0x9: // load Y I/O address
m_gv_word_y_position = ~m_gv_data_w & 0x1ff; // 0..454
LOG(("load Y I/O adress = %04x\n", m_gv_word_y_position));
m_gv_io_counter = get_gv_mem_addr(m_gv_word_x_position , m_gv_word_y_position);
m_gv_plane = 0;
m_gv_plane_wrap = false;
break;
case 0xa: // load memory control
case 0xa: // load memory control
m_gv_memory_control = m_gv_data_w & 0x7f;
LOG(("load memory control = %04x\n", m_gv_memory_control));
break;
case 0xb: // set line type/area fill
case 0xb: // set line type/area fill
m_gv_line_type_area_fill = m_gv_data_w & 0x1ff;
if (BIT(m_gv_line_type_area_fill, 4)) {
m_gv_line_type_mask = m_line_type[ m_gv_line_type_area_fill & 0x7 ];
@ -2393,21 +2393,21 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
}
LOG(("set line type = %04x\n", m_gv_line_type_area_fill));
break;
case 0xc: // load color mask
case 0xc: // load color mask
m_gv_music_memory = m_gv_data_w & 0x1ff;
LOG(("load color mask = %04x\n", m_gv_music_memory));
break;
case 0xd: // load end points
case 0xd: // load end points
m_gv_ypt = ~m_gv_data_w & 0x1ff;
LOG(("load end points y = %d\n", m_gv_ypt));
break;
case 0xe: // Y cursor position & color
case 0xe: // Y cursor position & color
m_gv_cursor_color = ~m_gv_data_w & 0x7;
m_gv_cursor_y = 1073 - (m_gv_data_w >> 6);
if (m_gv_cursor_fs) m_gv_cursor_y -= 8;
LOG(("Y cursor position = %d, color = %d\n", m_gv_cursor_y, m_gv_cursor_color));
break;
case 0xf: // X cursor position & type
case 0xf: // X cursor position & type
m_gv_cursor_fs = BIT(m_gv_data_w, 0);
m_gv_cursor_gc = BIT(m_gv_data_w, 1) || m_gv_cursor_fs;
m_gv_cursor_x = ((m_gv_data_w >> 6) & 0x3ff) - 42;
@ -2419,10 +2419,10 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
logerror("unknown 98770A command = %d, parm = 0x%04x\n", m_gv_cmd, m_gv_data_w);
}
if (m_gv_cmd == 0xd) {
m_gv_fsm_state = GV_STAT_WAIT_DS_2; // -> get second data word
m_gv_fsm_state = GV_STAT_WAIT_DS_2; // -> get second data word
} else {
get_out = true;
m_gv_fsm_state = GV_STAT_WAIT_DS_0; // -> done
m_gv_fsm_state = GV_STAT_WAIT_DS_0; // -> done
}
} else {
get_out = true;
@ -2437,7 +2437,7 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
m_gv_data_r = m_graphic_mem[ m_gv_plane ][ m_gv_io_counter ];
LOG(("read words @%04x = %04x, plane #%d\n" , m_gv_io_counter , m_gv_data_r, m_gv_plane + 1));
advance_io_counter();
m_gv_fsm_state = GV_STAT_WAIT_DS_1; // -> proceed with read stream
m_gv_fsm_state = GV_STAT_WAIT_DS_1; // -> proceed with read stream
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
@ -2448,7 +2448,7 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
// wait for data word to be read
if (ds) {
// -- next word
m_gv_fsm_state = GV_STAT_WAIT_MEM_0; // -> process data word
m_gv_fsm_state = GV_STAT_WAIT_MEM_0; // -> process data word
} else {
// -- done
get_out = true;
@ -2459,7 +2459,7 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
// wait for data word to be written
if (ds) {
// -- next word
m_gv_fsm_state = GV_STAT_WAIT_TRIG_1; // -> process data word
m_gv_fsm_state = GV_STAT_WAIT_TRIG_1; // -> process data word
} else {
// done
get_out = true;
@ -2475,20 +2475,20 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
if (BIT(m_gv_data_w, 10)) {
// draw vector
LOG(("load end points x = %d (draw)\n", m_gv_xpt));
m_gv_fsm_state = GV_STAT_WAIT_MEM_2; // -> proceed with draw vector
m_gv_fsm_state = GV_STAT_WAIT_MEM_2; // -> proceed with draw vector
} else {
LOG(("load end points x = %d (move)\n", m_gv_xpt));
m_gv_last_xpt = m_gv_xpt;
m_gv_last_ypt = m_gv_ypt;
m_gv_fsm_state = GV_STAT_WAIT_DS_0; // -> proceed with next word pair
m_gv_fsm_state = GV_STAT_WAIT_DS_0; // -> proceed with next word pair
}
} else if (m_gv_cmd == 0x2) {
// clear/set words command
m_gv_data_w = BIT(m_gv_memory_control, m_gv_plane + 3) ? 0xffff : 0;
m_gv_fsm_state = GV_STAT_WAIT_MEM_1; // -> proceed with next word
m_gv_fsm_state = GV_STAT_WAIT_MEM_1; // -> proceed with next word
} else if (m_gv_cmd == 0x0) {
// write words command
m_gv_fsm_state = GV_STAT_WAIT_MEM_1; // -> proceed with next word
m_gv_fsm_state = GV_STAT_WAIT_MEM_1; // -> proceed with next word
}
} else {
// done
@ -2506,7 +2506,7 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
m_graphic_mem[ m_gv_plane ][ m_gv_io_counter ] = m_gv_data_w;
}
advance_io_counter();
m_gv_fsm_state = GV_STAT_WAIT_DS_2; // -> proceed with write stream
m_gv_fsm_state = GV_STAT_WAIT_DS_2; // -> proceed with write stream
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
@ -2544,7 +2544,7 @@ void hp9845c_state::advance_gv_fsm(bool ds , bool trigger)
}
m_gv_last_xpt = m_gv_xpt;
m_gv_last_ypt = m_gv_ypt;
m_gv_fsm_state = GV_STAT_WAIT_DS_0; // -> proceed with next word pair
m_gv_fsm_state = GV_STAT_WAIT_DS_0; // -> proceed with next word pair
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
@ -2594,31 +2594,31 @@ static MACHINE_CONFIG_START( hp9835a, hp9845_state )
MACHINE_CONFIG_END
/*
Global memory map in blocks of 32 kwords / 64 kbytes each:
Global memory map in blocks of 32 kwords / 64 kbytes each:
block 0: 0x000000 - 0x007fff (LPU RAM)
block 1: 0x008000 - 0x00ffff (PPU RAM, only 0x00c000 - 0x00ffff used)
block 2: 0x010000 - 0x017fff (unused)
block 3: 0x018000 - 0x01ffff (LPU system ROM)
block 4: 0x020000 - 0x027fff (LPU RAM)
block 5: 0x028000 - 0x02ffff (PPU system ROM)
block 6: 0x030000 - 0x037fff (LPU RAM)
block 7: 0x038000 - 0x03ffff (LPU option ROM)
block 10: 0x040000 - 0x047fff (LPU RAM)
block 11: 0x048000 - 0x04ffff (PPU option ROM)
block 12: 0x050000 - 0x057fff (LPU RAM)
block 13: 0x058000 - 0x05ffff (LPU option ROM)
block 14: 0x060000 - 0x067fff (LPU RAM)
block 15: 0x068000 - 0x06ffff (PPU option ROM)
block 16: 0x070000 - 0x077fff (LPU RAM)
block 17: 0x078000 - 0x07ffff (unused)
block 0: 0x000000 - 0x007fff (LPU RAM)
block 1: 0x008000 - 0x00ffff (PPU RAM, only 0x00c000 - 0x00ffff used)
block 2: 0x010000 - 0x017fff (unused)
block 3: 0x018000 - 0x01ffff (LPU system ROM)
block 4: 0x020000 - 0x027fff (LPU RAM)
block 5: 0x028000 - 0x02ffff (PPU system ROM)
block 6: 0x030000 - 0x037fff (LPU RAM)
block 7: 0x038000 - 0x03ffff (LPU option ROM)
block 10: 0x040000 - 0x047fff (LPU RAM)
block 11: 0x048000 - 0x04ffff (PPU option ROM)
block 12: 0x050000 - 0x057fff (LPU RAM)
block 13: 0x058000 - 0x05ffff (LPU option ROM)
block 14: 0x060000 - 0x067fff (LPU RAM)
block 15: 0x068000 - 0x06ffff (PPU option ROM)
block 16: 0x070000 - 0x077fff (LPU RAM)
block 17: 0x078000 - 0x07ffff (unused)
notes:
- all block numbers are octal
- blocks 20 to 76 are reserved for 512 kbyte RAM boards (p/n 09845-66590)
- block 45 is reserved for the Test ROM
- memory addresses are continuous (for convenience, the mapping below uses block numbers as
address part above 0xffff, so there are gaps between 0x8000 and 0xffff which are masked out).
notes:
- all block numbers are octal
- blocks 20 to 76 are reserved for 512 kbyte RAM boards (p/n 09845-66590)
- block 45 is reserved for the Test ROM
- memory addresses are continuous (for convenience, the mapping below uses block numbers as
address part above 0xffff, so there are gaps between 0x8000 and 0xffff which are masked out).
- all LPU RAM is dynamically mapped at machine start according to -ramsize option
*/

68
src/mame/drivers/hp_ipc.cpp
View File

@ -306,43 +306,43 @@ Useful links etc.
bitsavers://pdf/hp/integral/00095-90126_Integral_Personal_Computer_Service_Jan86.pdf
bitsavers://pdf/hp/hp-hil/45918A-90001_HP-HIL_Technical_Reference_Manual_Jan86.pdf
HP-HIL MLC, SLC datasheets
HP-HIL MLC, SLC datasheets
bitsavers://pdf/sony/floppy/Sony_OA-D32_Microfloppy_Service_Nov83.pdf
OA-D32W
OA-D32W
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1983-01.pdf
HP-IL issue
HP-IL issue
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1985-10.pdf
IPC issue
IPC issue
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-06.pdf
HP-HIL article
HP-HIL article
http://www.hpmuseum.net/pdf/ComputerNews_1985_Jan15_37pages_OCR.pdf
introducing the IPC
introducing the IPC
http://www.hpmuseum.net/pdf/ComputerFocus_1985_Nov_25pages_OCR.pdf
SysV upgrade
SysV upgrade
http://www.hpmuseum.net/pdf/InformationSystemsAndManufacturingNews_81pages_Jun1-86_OCR.pdf
EPROM/ROM modules
EPROM/ROM modules
http://www.hpmuseum.net/pdf/HPChannels_1986_11_37pages_Nov86_OCR.pdf
SW Eng ROM and serial option for it
SW Eng ROM and serial option for it
http://www.coho.org/~pete/downloads/IPC/burst/Freeware/IPC_Driver_Writers_Disc/hp-ux.5.0.0
kernel namelist
kernel namelist
http://www.hpmuseum.net/display_item.php?hw=122
overview, manuals, software
overview, manuals, software
http://www.ambry.com/hp-computer-model/9807A.html
replacement parts
replacement parts
http://www.brouhaha.com/~eric/hpcalc/chips/
chip part numbers
chip part numbers
Software to look for
@ -473,20 +473,20 @@ static ADDRESS_MAP_START(hp_ipc_mem_inner, AS_PROGRAM, 16, hp_ipc_state)
AM_RANGE(0x1E40000, 0x1E4002F) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
// supervisor mode
AM_RANGE(0x0000000, 0x007FFFF) AM_ROM AM_REGION("maincpu", 0) // Internal ROM (operating system PCA)
AM_RANGE(0x0080000, 0x00FFFFF) AM_UNMAP // Internal ROM (option ROM PCA)
AM_RANGE(0x0100000, 0x04FFFFF) AM_UNMAP // External ROM modules
AM_RANGE(0x0000000, 0x007FFFF) AM_ROM AM_REGION("maincpu", 0) // Internal ROM (operating system PCA)
AM_RANGE(0x0080000, 0x00FFFFF) AM_UNMAP // Internal ROM (option ROM PCA)
AM_RANGE(0x0100000, 0x04FFFFF) AM_UNMAP // External ROM modules
AM_RANGE(0x0600000, 0x060FFFF) AM_READWRITE(mmu_r, mmu_w)
AM_RANGE(0x0610000, 0x0610007) AM_READWRITE8(floppy_id_r, floppy_id_w, 0x00ff)
AM_RANGE(0x0610008, 0x061000F) AM_DEVREADWRITE8("fdc", wd2797_t, read, write, 0x00ff)
AM_RANGE(0x0620000, 0x062000F) AM_DEVREADWRITE8("gpu", hp1ll3_device, read, write, 0x00ff)
AM_RANGE(0x0630000, 0x063FFFF) AM_NOP // AM_DEVREADWRITE8(TMS9914_TAG, tms9914_device, read, write, 0x00ff)
AM_RANGE(0x0630000, 0x063FFFF) AM_NOP // AM_DEVREADWRITE8(TMS9914_TAG, tms9914_device, read, write, 0x00ff)
AM_RANGE(0x0640000, 0x064002F) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
AM_RANGE(0x0650000, 0x065FFFF) AM_NOP // HP-IL Printer (optional; ROM sets _desktop to 0 if not mapped) -- sys/lpint.h
AM_RANGE(0x0660000, 0x06600FF) AM_DEVREADWRITE8("mlc", hp_hil_mlc_device, read, write, 0x00ff) // 'caravan', scrn/caravan.h
AM_RANGE(0x0670000, 0x067FFFF) AM_NOP // Speaker (NatSemi COP 452)
AM_RANGE(0x0680000, 0x068FFFF) AM_NOP // 'SIMON (98628) fast HP-IB card' -- sys/simon.h
AM_RANGE(0x0700000, 0x07FFFFF) AM_UNMAP // External I/O
AM_RANGE(0x0650000, 0x065FFFF) AM_NOP // HP-IL Printer (optional; ROM sets _desktop to 0 if not mapped) -- sys/lpint.h
AM_RANGE(0x0660000, 0x06600FF) AM_DEVREADWRITE8("mlc", hp_hil_mlc_device, read, write, 0x00ff) // 'caravan', scrn/caravan.h
AM_RANGE(0x0670000, 0x067FFFF) AM_NOP // Speaker (NatSemi COP 452)
AM_RANGE(0x0680000, 0x068FFFF) AM_NOP // 'SIMON (98628) fast HP-IB card' -- sys/simon.h
AM_RANGE(0x0700000, 0x07FFFFF) AM_UNMAP // External I/O
AM_RANGE(0x0800000, 0x0FFFFFF) AM_READWRITE(ram_r, ram_w)
// bus error handler
@ -699,15 +699,15 @@ static SLOT_INTERFACE_START( hp_ipc_floppies )
SLOT_INTERFACE_END
/*
* IRQ levels (page 5-4)
* IRQ levels (page 5-4)
*
* 7 Soft reset from keyboard, non-maskable
* 6 Real-time clock or NBIR3 (ext. I/O)
* 5 Disc Drive or NBIR2
* 4 GPU or NBIR1
* 3 HP-IB, printer, or NBIR0
* 2 HP-HIL devices (keyboard, mouse)
* 1 Real-time clock
* 7 Soft reset from keyboard, non-maskable
* 6 Real-time clock or NBIR3 (ext. I/O)
* 5 Disc Drive or NBIR2
* 4 GPU or NBIR1
* 3 HP-IB, printer, or NBIR0
* 2 HP-HIL devices (keyboard, mouse)
* 1 Real-time clock
*/
static MACHINE_CONFIG_START(hp_ipc, hp_ipc_state)
MCFG_CPU_ADD("maincpu", M68000, XTAL_15_92MHz / 2)
@ -726,8 +726,8 @@ static MACHINE_CONFIG_START(hp_ipc, hp_ipc_state)
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::amber())
MCFG_SCREEN_UPDATE_DEVICE("gpu", hp1ll3_device, screen_update)
MCFG_SCREEN_RAW_PARAMS(XTAL_6MHz * 2, 720, 0, 512, 278, 0, 256)
// when _desktop == 0:
// MCFG_SCREEN_RAW_PARAMS(XTAL_6MHz * 2, 720, 0, 640, 480, 0, 400)
// when _desktop == 0:
// MCFG_SCREEN_RAW_PARAMS(XTAL_6MHz * 2, 720, 0, 640, 480, 0, 400)
MCFG_SCREEN_VBLANK_CALLBACK(DEVWRITELINE("mlc", hp_hil_mlc_device, ap_w)) // XXX actually it's driven by 555 (U59)
MCFG_DEFAULT_LAYOUT(layout_lcd)
@ -735,7 +735,7 @@ static MACHINE_CONFIG_START(hp_ipc, hp_ipc_state)
MCFG_PALETTE_ADD_MONOCHROME("palette")
MCFG_HP1LL3_ADD("gpu")
// MCFG_HP1LL3_IRQ_CALLBACK(WRITELINE(hp_ipc_state, irq_4))
// MCFG_HP1LL3_IRQ_CALLBACK(WRITELINE(hp_ipc_state, irq_4))
MCFG_VIDEO_SET_SCREEN("screen")
// XXX actual clock is 1MHz; remove this workaround (and change 2000 to 100 in hp_ipc_dsk.cpp)
@ -748,7 +748,7 @@ static MACHINE_CONFIG_START(hp_ipc, hp_ipc_state)
MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz)
MCFG_MM58167_IRQ_CALLBACK(WRITELINE(hp_ipc_state, irq_1))
// MCFG_MM58167_STANDBY_IRQ_CALLBACK(WRITELINE(hp_ipc_state, irq_6))
// MCFG_MM58167_STANDBY_IRQ_CALLBACK(WRITELINE(hp_ipc_state, irq_6))
MCFG_DEVICE_ADD("mlc", HP_HIL_MLC, XTAL_15_92MHz/2)
MCFG_HP_HIL_INT_CALLBACK(WRITELINE(hp_ipc_state, irq_2))

20
src/mame/drivers/isbc.cpp
View File

@ -51,7 +51,7 @@ public:
required_device<cpu_device> m_maincpu;
optional_device<i8251_device> m_uart8251;
// optional_device<i8274_device> m_uart8274;
// optional_device<i8274_device> m_uart8274;
optional_device<i8274N_device> m_uart8274;
required_device<pic8259_device> m_pic_0;
optional_device<pic8259_device> m_pic_1;
@ -64,7 +64,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(isbc86_tmr2_w);
DECLARE_WRITE_LINE_MEMBER(isbc286_tmr2_w);
// DECLARE_WRITE_LINE_MEMBER(isbc_uart8274_irq);
// DECLARE_WRITE_LINE_MEMBER(isbc_uart8274_irq);
DECLARE_READ8_MEMBER(get_slave_ack);
DECLARE_WRITE8_MEMBER(ppi_c_w);
DECLARE_WRITE8_MEMBER(upperen_w);
@ -168,7 +168,7 @@ static ADDRESS_MAP_START(isbc2861_mem, AS_PROGRAM, 16, isbc_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000, 0xdffff) AM_RAM
AM_RANGE(0xe0000, 0xfffff) AM_READWRITE(bioslo_r, bioslo_w) AM_SHARE("biosram")
// AM_RANGE(0x100000, 0x1fffff) AM_RAM // FIXME: XENIX doesn't like this, IRMX is okay with it
// AM_RANGE(0x100000, 0x1fffff) AM_RAM // FIXME: XENIX doesn't like this, IRMX is okay with it
AM_RANGE(0xff0000, 0xffffff) AM_ROM AM_REGION("user1",0)
ADDRESS_MAP_END
@ -361,7 +361,7 @@ static MACHINE_CONFIG_START( isbc286, isbc_state )
MCFG_PIT8253_CLK0(XTAL_22_1184MHz/18)
MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic_0", pic8259_device, ir0_w))
MCFG_PIT8253_CLK1(XTAL_22_1184MHz/18)
// MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("uart8274", z80dart_device, rxtxcb_w))
// MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("uart8274", z80dart_device, rxtxcb_w))
MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("uart8274", i8274N_device, rxtxcb_w))
MCFG_PIT8253_CLK2(XTAL_22_1184MHz/18)
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(isbc_state, isbc286_tmr2_w))
@ -396,7 +396,7 @@ static MACHINE_CONFIG_START( isbc286, isbc_state )
MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_txd))
MCFG_Z80SIO_OUT_DTRB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_dtr))
MCFG_Z80SIO_OUT_RTSB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_rts))
// MCFG_Z80SIO_OUT_INT_CB(WRITELINE(isbc_state, isbc_uart8274_irq))
// MCFG_Z80SIO_OUT_INT_CB(WRITELINE(isbc_state, isbc_uart8274_irq))
MCFG_Z80SIO_OUT_INT_CB(DEVWRITELINE("pic_0", pic8259_device, ir6_w))
#endif
@ -481,13 +481,13 @@ ROM_END
* :uart8274 B Reg 00 <- 18 - Channel reset command
* :uart8274 B Reg 04 <- 44 - x16 clock, 1 stop bit, no parity
* :uart8274 B Reg 05 <- ea - Tx Enabled, Transmitter Bits/Character 8, Send Break 0, RTS=0, DTR=0
* :uart8274 B Reg 03 <- c1 - Rx 8 bits, No Auto Enables, Rx Enabled,
* :uart8274 B Reg 03 <- c1 - Rx 8 bits, No Auto Enables, Rx Enabled,
* :uart8274 B Reg 00 <- 18 - Channel reset command
* :uart8274 B Reg 04 <- 4e - x16 clock, 2 stop bit, even parity but parity disabled
* :uart8274 B Reg 05 <- ea - Tx Enabled, Tx 8 bits, Send Break 0, RTS=0, DTR=0
* :uart8274 B Reg 03 <- c1 - Rx Enabled, Rx 8 bits, No Auto Enables
* :uart8274 B Reg 07 <- 00 - Hi SYNC bits
* :uart8274 B Reg 07 <- 00 - Hi SYNC bits
* :uart8274 B Reg 06 <- 00 - Lo SYNC bits
* :uart8274 A Reg 02 <- 04 - RTSB selected, non vectored mode, 85-1 mode selected, A over B interleaved int prios
* :uart8274 B Reg 02 <- 26 - interrupt vector 26
@ -497,7 +497,7 @@ ROM_END
* :uart8274 B Reg 00 <- 18 - Channel reset command
* :uart8274 B Reg 04 <- 44 - x16 clock, 1 stop bit, no parity
* :uart8274 B Reg 05 <- ea - Tx Enabled, Tx 8 bits, Send Break 0, RTS=0, DTR=0
* :uart8274 B Reg 03 <- c1 - Rx Enabled, Rx 8 bits, No Auto Enables
* :uart8274 B Reg 03 <- c1 - Rx Enabled, Rx 8 bits, No Auto Enables
* :uart8274 B Reg 00 <- 28 - Reset Transmitter Interrupt Pending
* :uart8274 B Reg 00 <- 28 - Reset Transmitter Interrupt Pending
* :uart8274 B Reg 00 <- 28 - Reset Transmitter Interrupt Pending
@ -507,7 +507,7 @@ ROM_END
* :uart8274 A Reg 04 <- 4e - x16 clock, 2 stop bit, even parity but parity disabled
* :uart8274 A Reg 05 <- ea - Tx Enabled, Tx 8 bits, Send Break 0, RTS=0, DTR=0
* :uart8274 A Reg 03 <- c1 - Rx Enabled, Rx 8 bits, No Auto Enables
* :uart8274 A Reg 07 <- 00 - Hi SYNC bits
* :uart8274 A Reg 07 <- 00 - Hi SYNC bits
* :uart8274 A Reg 06 <- 00 - Lo SYNC bits
* :uart8274 A Reg 02 <- 04 - RTSB selected, non vectored mode, 85-1 mode selected, A over B interleaved int prios
* :uart8274 B Reg 02 <- 26 - interrupt vector 26
@ -520,7 +520,7 @@ ROM_END
* :uart8274 A Reg 04 <- 4e - x16 clock, 2 stop bit, even parity but parity disabled
* :uart8274 A Reg 05 <- ea - Tx Enabled, Tx 8 bits, Send Break 0, RTS=0, DTR=0
* :uart8274 A Reg 03 <- c1 - Rx Enabled, Rx 8 bits, No Auto Enables
* :uart8274 A Reg 07 <- 00 - Hi SYNC bits
* :uart8274 A Reg 07 <- 00 - Hi SYNC bits
* :uart8274 A Reg 06 <- 00 - Lo SYNC bits
* :uart8274 A Reg 02 <- 04 - RTSB selected, non vectored mode, 85-1 mode selected, A over B interleaved int prios
* :uart8274 B Reg 02 <- 26 - interrupt vector 26

14
src/mame/drivers/iskr103x.cpp
View File

@ -2,15 +2,15 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
drivers/iskr103x.c
drivers/iskr103x.c
Driver file for Iskra-1030, 1031
Driver file for Iskra-1030, 1031
TODO
- fix cyrillic chargen upload for CGA and MDA
- replace DIP switch definition
- keyboard test is not passing (code 301)
- hard disk is connected but untested
TODO
- fix cyrillic chargen upload for CGA and MDA
- replace DIP switch definition
- keyboard test is not passing (code 301)
- hard disk is connected but untested
***************************************************************************/

2
src/mame/drivers/karnov.cpp
View File

@ -849,7 +849,7 @@ static MACHINE_CONFIG_START( karnov, karnov_state )
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( karnovjbl, karnov )
/* X-TALs:
/* X-TALs:
Top board next to #9 is 20.000 MHz
Top board next to the microcontroller is 6.000 MHz
Bottom board next to the ribbon cable is 12.000 MHz*/

14
src/mame/drivers/mc1502.cpp
View File

@ -2,9 +2,9 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
drivers/mc1502.c
drivers/mc1502.c
Driver file for Elektronika MS 1502
Driver file for Elektronika MS 1502
***************************************************************************/
@ -196,10 +196,10 @@ MACHINE_START_MEMBER(mc1502_state, mc1502)
DBG_LOG(0, "init", ("machine_start()\n"));
/*
Keyboard polling circuit holds IRQ1 high until a key is
pressed, then it starts a timer that pulses IRQ1 low each
40ms (check) for 20ms (check) until all keys are released.
Last pulse causes BIOS to write a 'break' scancode into port 60h.
Keyboard polling circuit holds IRQ1 high until a key is
pressed, then it starts a timer that pulses IRQ1 low each
40ms (check) for 20ms (check) until all keys are released.
Last pulse causes BIOS to write a 'break' scancode into port 60h.
*/
m_pic8259->ir1_w(1);
memset(&m_kbd, 0, sizeof(m_kbd));
@ -318,7 +318,7 @@ static MACHINE_CONFIG_START( mc1502, mc1502_state )
MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_MOTOR_ENABLED | CASSETTE_SPEAKER_ENABLED)
MCFG_SOFTWARE_LIST_ADD("flop_list","mc1502_flop")
// MCFG_SOFTWARE_LIST_ADD("cass_list","mc1502_cass")
// MCFG_SOFTWARE_LIST_ADD("cass_list","mc1502_cass")
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("608K") /* 96 base + 512 on expansion card */

6
src/mame/drivers/naomi.cpp
View File

@ -2719,7 +2719,7 @@ static MACHINE_CONFIG_START( naomi_base, naomi_state )
MCFG_EEPROM_SERIAL_93C46_ADD("main_eeprom")
MCFG_EEPROM_SERIAL_DEFAULT_VALUE(0)
// clock was measured using GPIO (13.499Mhz) and UART (13.260MHz) access
// IO ports access may have latency so actual CPU core clock can be higher, possible OSC3 14.7456MHz
MCFG_MIE_ADD("mie", 13500000, "maple_dc", 0, nullptr, nullptr, nullptr, ":MIE.3", nullptr, ":MIE.5", nullptr, nullptr)
@ -6681,8 +6681,8 @@ ROM_START( kick4csh )
// LED6,7 - 7seg LEDs
// BT1 - Panasonic CR2032 battery
ROM_REGION(0x220000, "hopper_board", 0)
ROM_LOAD( "fpr-24150.ic6", 0x0000000, 0x200000, CRC(3845c34c) SHA1(027b17bac64482ee152773d5fab30fcbc6e2bcb7) ) // SH4 code
ROM_LOAD( "6372a.ic3", 0x0200000, 0x020000, CRC(f30839ad) SHA1(ea1a32c4da1ed9745300bcdd7964a7c0964e3221) ) // FPGA config
ROM_LOAD( "fpr-24150.ic6", 0x0000000, 0x200000, CRC(3845c34c) SHA1(027b17bac64482ee152773d5fab30fcbc6e2bcb7) ) // SH4 code
ROM_LOAD( "6372a.ic3", 0x0200000, 0x020000, CRC(f30839ad) SHA1(ea1a32c4da1ed9745300bcdd7964a7c0964e3221) ) // FPGA config
// 840-0140 2004 317-0397-COM Naomi
ROM_PARAMETER( ":rom_board:key", "820857c9" )

6
src/mame/drivers/novag6502.cpp
View File

@ -348,7 +348,7 @@ void novag6502_state::cforte_prepare_display()
{
// 3 led rows
display_matrix(8, 3, m_led_data, m_led_select, false);
// lcd panel (mostly handled in cforte_lcd_output_w)
set_display_segmask(0x3ff0, 0xff);
set_display_size(8, 3+13);
@ -368,10 +368,10 @@ WRITE64_MEMBER(novag6502_state::cforte_lcd_output_w)
m_display_state[dig+3] = 0;
for (int i = 0; i < 4; i++)
m_display_state[dig+3] |= ((rowdata[i] >> (2*dig) & 3) << (2*i));
m_display_state[dig+3] = BITSWAP8(m_display_state[dig+3],7,2,0,4,6,5,3,1);
}
cforte_prepare_display();
}

8
src/mame/drivers/phoenix.cpp
View File

@ -777,7 +777,7 @@ main PCB is marked: "PH2"
main PCB is labeled: "03814367" and "280402" and "N 132073"
ROMs PCB is marked: "PH1"
On top of main PCB there is a small piggyback PCB. it is a replacement for MN6221 Melody-Alarm Generator - sound. There are 3 PROMs (dumped) and a few 74xx logics.
This board was in a cocktail table cabinet manufactured by Model Racing and labeled "Thunderbird".
This board was in a cocktail table cabinet manufactured by Model Racing and labeled "Thunderbird".
*/
ROM_START( phoenixc2 ) // verified main and ROMs PCBs and 2 PROMs
@ -1158,7 +1158,7 @@ ROM_START( avefenixl )
ROM_END
/*
PCB is marked: "003 LATO A" on component side and "003 LATO B" on solder side. (In Italian "lato" means "side")
PCB is marked: "003 LATO A" on component side and "003 LATO B" on solder side. (In Italian "lato" means "side")
*/
ROM_START( griffon ) // verified single PCB, single PROM
@ -1570,7 +1570,7 @@ GAME( 1981, phoenixass, phoenix, phoenix, phoenix, driver_device, 0,
GAME( 1980, avefenix, phoenix, phoenix, phoenix, driver_device, 0, ROT90, "bootleg (Video Game)", "Ave Fenix (Electrogame, Spanish bootleg of Phoenix)", MACHINE_SUPPORTS_SAVE ) // Electrogame (Barcelona) made the dedicated cabinet and is likely the real manufacturer, ingame shows 'Video Game'
GAME( 1980, avefenixrf, phoenix, phoenix, phoenix, driver_device, 0, ROT90, "bootleg (Recreativos Franco S.A.)", "Ave Fenix (Recreativos Franco, Spanish bootleg of Phoenix)", MACHINE_SUPPORTS_SAVE )
GAME( 1980, avefenixl, phoenix, phoenix, phoenix, driver_device, 0, ROT90, "bootleg (Laguna)", "Ave Fenix (Laguna, Spanish bootleg of Phoenix)", MACHINE_SUPPORTS_SAVE )
/*** Pleiads (& clones) ***/
GAME( 1981, pleiads, 0, pleiads, pleiads, driver_device, 0, ROT90, "Tehkan", "Pleiads (Tehkan)", MACHINE_IMPERFECT_COLORS )
GAME( 1981, pleiadsb2, pleiads, pleiads, pleiads, driver_device, 0, ROT90, "bootleg (ESG)", "Pleiads (bootleg set 2)", MACHINE_SUPPORTS_SAVE )
@ -1580,6 +1580,6 @@ GAME( 1981, pleiadsi, pleiads, pleiads, pleiadce, driver_device, 0,
GAME( 1981, pleiadsn, pleiads, phoenix, pleiadce, driver_device, 0, ROT90, "Niemer S.A.", "Pleiads (Niemer S.A.)", MACHINE_IMPERFECT_COLORS ) // possibly licensed, but some of the roms match the bootlegs
GAME( 1981, pleiadss, pleiads, phoenix, pleiadce, driver_device, 0, ROT90, "bootleg", "Pleiads (Spanish bootleg)", MACHINE_SUPPORTS_SAVE ) // colours match PCB (but are ugly)
GAME( 1981, capitol, pleiads, phoenix, capitol, driver_device, 0, ROT90, "bootleg? (Universal Video Spiel)", "Capitol", MACHINE_IMPERFECT_COLORS )
/*** Others ***/
GAME( 1982, survival, 0, survival, survival, driver_device, 0, ROT90, "Rock-Ola", "Survival", MACHINE_IMPERFECT_COLORS )

28
src/mame/drivers/poisk1.cpp
View File

@ -2,22 +2,22 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
drivers/poisk1.c
drivers/poisk1.c
Driver file for Poisk-1
Driver file for Poisk-1
to do:
- cassette i/o and softlist
- verify palette
- monochrome output
- trap: does memory always get written or it's up to NMI ISR to complete writes?
- keyboard layout for earliest revision (v89r0)
to do:
- cassette i/o and softlist
- verify palette
- monochrome output
- trap: does memory always get written or it's up to NMI ISR to complete writes?
- keyboard layout for earliest revision (v89r0)
slot devices:
- hard disk controllers
- network cards
- joystick, mouse, serial, parallel ports
- sound card
slot devices:
- hard disk controllers
- network cards
- joystick, mouse, serial, parallel ports
- sound card
***************************************************************************/
@ -247,7 +247,7 @@ WRITE8_MEMBER(p1_state::p1_ppi2_porta_w)
/*
06Ah Dxx 6 Enable/Disable color burst (?)
7 Enable/Disable D7H/D7L
7 Enable/Disable D7H/D7L
*/
WRITE8_MEMBER(p1_state::p1_ppi_portc_w)

6
src/mame/drivers/popper.cpp
View File

@ -245,8 +245,8 @@ static const res_net_decode_info popper_decode_info =
static const res_net_info popper_net_info =
{
RES_NET_VCC_5V | RES_NET_VBIAS_5V | RES_NET_VIN_TTL_OUT,
{
{ RES_NET_AMP_NONE, 0, 0, 3, { 1000, 470, 220 } },
{
{ RES_NET_AMP_NONE, 0, 0, 3, { 1000, 470, 220 } },
{ RES_NET_AMP_NONE, 0, 0, 3, { 1000, 470, 220 } },
{ RES_NET_AMP_NONE, 0, 0, 2, { 470, 220, 0 } }
}
@ -389,7 +389,7 @@ WRITE8_MEMBER( popper_state::ay1_w )
WRITE8_MEMBER( popper_state::nmi_control_w )
{
// logerror("nmi_control_w: %02x\n", data);
// logerror("nmi_control_w: %02x\n", data);
m_nmi_enable = data & 1;
}

2
src/mame/drivers/sderby.cpp
View File

@ -876,7 +876,7 @@ ROM_START( shinygld )
ROM_LOAD( "22.u145", 0x080000, 0x20000, CRC(113ccf81) SHA1(c2192e81a4be38911c971e1593b902f92d9a02d5) ) // 27C1001
/* Dumper's note: Board carries five PLDs : one GAL22V10 near the 68000 CPU (which most likely acts as main address decoder),
three PALCE22V10H (two are near the GFX ROMs, probably for enabling them), one PALCE16V8H.*/
three PALCE22V10H (two are near the GFX ROMs, probably for enabling them), one PALCE16V8H.*/
ROM_REGION( 0x1000, "plds", 0)
ROM_LOAD( "gal22v10.bin", 0x0400, 0x02e5, NO_DUMP ) // soldered
ROM_LOAD( "palce22v10_1.bin", 0x2dd, 0x2dd, NO_DUMP ) // soldered

4
src/mame/drivers/segas32.cpp
View File

@ -5337,14 +5337,14 @@ void segas32_state::init_arescue(int m_hasdsp)
uint8_t *dspsrc = (uint8_t *)memregion("dsp")->base();
uint32_t *dspprg = (uint32_t *)memregion("dspprg")->base();
uint16_t *dspdata = (uint16_t *)memregion("dspdata")->base();
// copy DSP program
for (int i = 0; i < 0x2000; i+= 4)
{
*dspprg = dspsrc[0+i]<<24 | dspsrc[1+i]<<16 | dspsrc[2+i]<<8;
dspprg++;
}
// copy DSP data
for (int i = 0; i < 0x800; i+= 2)
{

2
src/mame/drivers/seta2.cpp
View File

@ -397,7 +397,7 @@ static ADDRESS_MAP_START( penbros_map, AS_PROGRAM, 16, seta2_state )
AM_RANGE(0x500302, 0x500303) AM_READ_PORT("DSW2") // DSW 2
AM_RANGE(0x500300, 0x50030f) AM_WRITE(sound_bank_w) // Samples Banks
ADDRESS_MAP_END
static ADDRESS_MAP_START( penbrosk_map, AS_PROGRAM, 16, seta2_state )
AM_IMPORT_FROM(penbros_base_map)
AM_RANGE(0x508300, 0x508301) AM_READ_PORT("DSW1") // DSW 1

2
src/mame/drivers/stargame.cpp
View File

@ -51,7 +51,7 @@ ROM_START(spcship)
ROM_REGION(0x4000, "maincpu", 0)
ROM_LOAD("sss-1g.bin", 0x0000, 0x4000, CRC(119a3064) SHA1(d915ecf44279a9e16a50a723eb9523afec1fb380))
ROM_REGION(0x4000, "audiocpu", 0)
ROM_LOAD("sss-1a0.bin", 0x0000, 0x4000, CRC(eae78e63) SHA1(9fa3587ae3ee6f674bb16102680e70069e9d275e))
ROM_LOAD("sss-1a0.bin", 0x0000, 0x4000, CRC(eae78e63) SHA1(9fa3587ae3ee6f674bb16102680e70069e9d275e))
ROM_END

4
src/mame/drivers/tosh1000.cpp
View File

@ -30,7 +30,7 @@
Useful links:
- board photo: http://s8.hostingkartinok.com/uploads/images/2016/05/579e9d152bc772d9c16bc8ac611eb97f.jpg
- manuals: http://www.minuszerodegrees.net/manuals/Toshiba/Toshiba.htm
- manuals: http://www.minuszerodegrees.net/manuals/Toshiba/Toshiba.htm
***************************************************************************/
@ -126,7 +126,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( tosh1000_io, AS_IO, 8, tosh1000_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0x00ff) AM_DEVICE("mb", ibm5160_mb_device, map)
AM_RANGE(0x00c8, 0x00c8) AM_WRITE(romdos_bank_w) // ROM-DOS page select [p. B-15]
AM_RANGE(0x00c8, 0x00c8) AM_WRITE(romdos_bank_w) // ROM-DOS page select [p. B-15]
AM_RANGE(0x02c0, 0x02df) AM_DEVREADWRITE("rtc", rp5c01_device, read, write)
ADDRESS_MAP_END

2
src/mame/drivers/vg5k.cpp
View File

@ -202,7 +202,7 @@ static INPUT_PORTS_START( vg5k )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_NAME("CTRL ACCENT") PORT_CHAR(UCHAR_SHIFT_2)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_NAME("CTRL ACCENT") PORT_CHAR(UCHAR_SHIFT_2)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_INSERT) PORT_NAME("INSC INSL") PORT_CHAR(UCHAR_MAMEKEY(INSERT))
PORT_START("ROW2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F2) PORT_NAME("RUN STOP") PORT_CHAR(UCHAR_MAMEKEY(F2)) PORT_CHAR(UCHAR_MAMEKEY(PAUSE))

50
src/mame/drivers/vp101.cpp
View File

@ -12,7 +12,7 @@
AC97 audio with custom DMA frontend which streams 8 stereo channels
PIC18c442 protection chip (not readable) on VP101 only (VP100 is unprotected?)
1 MB of VRAM at main RAM offset 0x07400000
1 MB of VRAM at main RAM offset 0x07400000
****************************************************************************/
@ -36,20 +36,20 @@ public:
virtual void machine_reset() override;
virtual void machine_start() override;
DECLARE_READ32_MEMBER(tty_ready_r);
DECLARE_WRITE32_MEMBER(tty_w);
DECLARE_READ32_MEMBER(test_r) { return 0xffffffff; }
DECLARE_READ32_MEMBER(pic_r);
DECLARE_WRITE32_MEMBER(pic_w);
DECLARE_WRITE32_MEMBER(dmaaddr_w);
DECLARE_WRITE_LINE_MEMBER(dmarq_w);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
protected:
@ -78,7 +78,7 @@ void vp10x_state::machine_start()
m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
m_maincpu->add_fastram(0x00000000, 0x07ffffff, false, m_mainram);
}
WRITE32_MEMBER(vp10x_state::dmaaddr_w)
{
m_dma_ptr = (data & 0x07ffffff);
@ -89,18 +89,18 @@ WRITE_LINE_MEMBER(vp10x_state::dmarq_w)
if (state != m_dmarq_state)
{
m_dmarq_state = state;
if (state)
{
uint16_t *RAMbase = (uint16_t *)&m_mainram[0];
uint16_t *RAM = &RAMbase[m_dma_ptr>>1];
uint16_t *RAM = &RAMbase[m_dma_ptr>>1];
m_ata->write_dmack(ASSERT_LINE);
m_ata->write_dmack(ASSERT_LINE);
while (m_dmarq_state)
{
*RAM++ = m_ata->read_dma();
m_dma_ptr += 2; // pointer must advance
m_dma_ptr += 2; // pointer must advance
}
m_ata->write_dmack(CLEAR_LINE);
@ -108,7 +108,7 @@ WRITE_LINE_MEMBER(vp10x_state::dmarq_w)
}
}
READ32_MEMBER(vp10x_state::pic_r)
READ32_MEMBER(vp10x_state::pic_r)
{
static const uint8_t vers[5] = { 0x00, 0x01, 0x00, 0x00, 0x00 };
static const uint8_t serial[10] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a };
@ -118,15 +118,15 @@ READ32_MEMBER(vp10x_state::pic_r)
{
case 0x20:
return vers[pic_state++];
case 0x21:
case 0x22:
return serial[pic_state++];
case 0x23: // this is the same for jnero and specfrce. great security!
case 0x23: // this is the same for jnero and specfrce. great security!
return magic[pic_state++];
}
return 0;
}
@ -165,7 +165,7 @@ uint32_t vp10x_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap,
*line++ = word;
}
}
return 0;
}
@ -189,13 +189,13 @@ static ADDRESS_MAP_START( main_map, AS_PROGRAM, 32, vp10x_state )
AM_RANGE(0x1c400000, 0x1c400003) AM_WRITE(tty_w) // boot ROM code uses this one
AM_RANGE(0x1c400014, 0x1c400017) AM_READ(tty_ready_r)
AM_RANGE(0x1ca0000c, 0x1ca0000f) AM_READ_PORT("IN0")
AM_RANGE(0x1ca00010, 0x1ca00013) AM_READ(test_r) // bits here cause various test mode stuff
AM_RANGE(0x1ca00010, 0x1ca00013) AM_READ(test_r) // bits here cause various test mode stuff
AM_RANGE(0x1cf00000, 0x1cf00003) AM_NOP AM_READNOP
AM_RANGE(0x1d000030, 0x1d000033) AM_WRITE(dmaaddr_w) // ATA DMA destination address
AM_RANGE(0x1d000030, 0x1d000033) AM_WRITE(dmaaddr_w) // ATA DMA destination address
AM_RANGE(0x1d000040, 0x1d00005f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff)
AM_RANGE(0x1d000060, 0x1d00007f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0x0000ffff)
AM_RANGE(0x1f200000, 0x1f200003) AM_READWRITE(pic_r, pic_w)
AM_RANGE(0x1f807000, 0x1f807fff) AM_RAM AM_SHARE("nvram")
AM_RANGE(0x1f807000, 0x1f807fff) AM_RAM AM_SHARE("nvram")
AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("maincpu", 0)
ADDRESS_MAP_END
@ -205,7 +205,7 @@ static INPUT_PORTS_START( vp101 )
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0xfffffff0, IP_ACTIVE_HIGH, IPT_UNKNOWN )
INPUT_PORTS_END
@ -223,10 +223,10 @@ static MACHINE_CONFIG_START( vp101, vp10x_state )
MCFG_SCREEN_UPDATE_DRIVER(vp10x_state, screen_update)
MCFG_SCREEN_SIZE(320, 240)
MCFG_SCREEN_VISIBLE_AREA(0, 319, 0, 239)
MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", nullptr, false)
MCFG_ATA_INTERFACE_DMARQ_HANDLER(WRITELINE(vp10x_state, dmarq_w))
MCFG_NVRAM_ADD_0FILL("nvram")
MACHINE_CONFIG_END

2
src/mame/includes/gridlee.h
View File

@ -14,7 +14,7 @@
#define GRIDLEE_MASTER_CLOCK (20000000)
#define GRIDLEE_CPU_CLOCK (GRIDLEE_MASTER_CLOCK / 16)
#define GRIDLEE_PIXEL_CLOCK (GRIDLEE_MASTER_CLOCK / 4)
#define GRIDLEE_PIXEL_CLOCK (GRIDLEE_MASTER_CLOCK / 4)
#define GRIDLEE_HTOTAL (0x140)
#define GRIDLEE_HBEND (0x000)
#define GRIDLEE_HBSTART (0x100)

2
src/mame/includes/marineb.h
View File

@ -55,4 +55,4 @@ public:
INTERRUPT_GEN_MEMBER(marineb_vblank_irq);
INTERRUPT_GEN_MEMBER(wanted_vblank_irq);
void set_tilemap_scrolly( int cols );
};
};

6
src/mame/mame.lst
View File

@ -12107,8 +12107,8 @@ promutrvc // (c) 1985 Enerdyne Technologies Inc
strvmstr // (c) 1986 Enerdyne Technologies Inc
@source:eurocom2.cpp
eurocom2 //
waveterm //
eurocom2 //
waveterm //
@source:europc.cpp
europc // 1988 Schneider Euro PC (CGA or Hercules)
@ -36942,7 +36942,7 @@ voyager // (c) 2002 Team Play, Inc.
@source:vp101.cpp
jnero // (c) 2004 ICE/Play Mechanix
specfrce // (c) 2002 ICE/Play Mechanix
zoofari // (c) 2006 ICE/Play Mechanix
zoofari // (c) 2006 ICE/Play Mechanix
@source:vpoker.cpp
5acespkr // (c) 198?

2
src/mame/video/abc80.cpp
View File

@ -157,7 +157,7 @@ void abc80_state::draw_scanline(bitmap_rgb32 &bitmap, int y)
void abc80_state::video_start()
{
m_screen->register_screen_bitmap(m_bitmap);
// start timers
m_scanline_timer = timer_alloc(TIMER_ID_SCANLINE);
m_scanline_timer->adjust(m_screen->time_until_pos(0, ABC80_HBEND), 0, m_screen->scan_period());

16
src/mame/video/agat7.cpp
View File

@ -6,14 +6,14 @@
Implementation of Agat-7 onboard video.
5 video modes:
- 32x32 color text
- 64x32 mono text with reverse video
- 64x64 color graphics
- 128x128 color graphics
- 256x256 mono graphics
5 video modes:
- 32x32 color text
- 64x32 mono text with reverse video
- 64x64 color graphics
- 128x128 color graphics
- 256x256 mono graphics
Character generator ROM could have 128 or 256 chars.
Character generator ROM could have 128 or 256 chars.
C7xx: video mode select
@ -75,7 +75,7 @@ agat7video_device::agat7video_device(const machine_config &mconfig, const char *
void agat7video_device::device_start()
{
// save_item(NAME(m_video_mode));
// save_item(NAME(m_video_mode));
save_item(NAME(m_start_address));
}

14
src/mame/video/gime.cpp
View File

@ -624,15 +624,15 @@ uint8_t gime_base_device::read(offs_t offset)
switch(offset & 0xF0)
{
case 0x00:
data = read_gime_register(offset); // $FF90 - $FF9F
data = read_gime_register(offset); // $FF90 - $FF9F
break;
case 0x10:
data = read_mmu_register(offset); // $FFA0 - $FFAF
data = read_mmu_register(offset); // $FFA0 - $FFAF
break;
case 0x20:
data = read_palette_register(offset); // $FFB0 - $FFBF
data = read_palette_register(offset); // $FFB0 - $FFBF
break;
default:
@ -733,20 +733,20 @@ void gime_base_device::write(offs_t offset, uint8_t data)
switch(offset & 0xF0)
{
case 0x00:
write_gime_register(offset & 0x0F, data); // $FF90 - $FF9F
write_gime_register(offset & 0x0F, data); // $FF90 - $FF9F
break;
case 0x10:
write_mmu_register(offset & 0x0F, data); // $FFA0 - $FFAF
write_mmu_register(offset & 0x0F, data); // $FFA0 - $FFAF
break;
case 0x20:
write_palette_register(offset & 0x0F, data & 0x3F); // $FFB0 - $FFBF
write_palette_register(offset & 0x0F, data & 0x3F); // $FFB0 - $FFBF
break;
case 0x30:
case 0x40:
write_sam_register(offset - 0x30); // $FFC0 - $FFDF
write_sam_register(offset - 0x30); // $FFC0 - $FFDF
break;
}
}