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F8 documentation correction and improvement (nw)

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This commit is contained in:
AJR 2018-08-09 12:16:17 -04:00
parent 2123d4bc64
commit 6cfd636c60
2 changed files with 21 additions and 5 deletions
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21
src/devices/cpu/f8/f8.cpp
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@ -7,6 +7,27 @@
* This work is based on Frank Palazzolo's F8 emulation in a standalone
* Fairchild Channel F emulator and the 'Fairchild F3850 CPU' data sheets.
*
* The 3850 CPU itself does not include the address bus, pointer registers
* or an interrupt controller. Those functions are provided by at least one
* of the following devices:
*
* - 3851 Program Storage Unit (PSU)
* - 3852 Dynamic Memory Interface (DMI)
* - 3853 Static Memory Interface (SMI)
* - 3856 Program Storage Unit (PSU)
* - 3861 Peripheral Input/Output (PIO)
* - 3871 Peripheral Input/Output (PIO)
*
* Of these support devices, the 3851 PSU includes 1024 bytes of mask ROM,
* and the 3856 PSU includes 2048 bytes of mask ROM; addressing for the PSU
* is also determined by mask option. The 3853 SMI may be used with external
* program ROMs.
*
* The PSU does not have DC0 and DC1, only DC0; as a result, it does not
* respond to the main CPU's DC0/DC1 swap instruction. This may lead to two
* devices responding to the same DC0 address and attempting to place their
* bytes on the data bus simultaneously!
*
*****************************************************************************/
#include "emu.h"

5
src/devices/machine/f3853.cpp
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@ -10,11 +10,6 @@
Based on a datasheet obtained from www.freetradezone.com
The SMI does not have DC0 and DC1, only DC0; as a result, it does
not respond to the main CPU's DC0/DC1 swap instruction. This may
lead to two devices responding to the same DC0 address and
attempting to place their bytes on the data bus simultaneously!
8-bit shift register:
Feedback in0 = !((out3 ^ out4) ^ (out5 ^ out7))
Interrupts are at 0xfe