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Don't use safe_pc[base] when you already have a

Browse Source 
resolved device_state_interface. Added redundant
methods to device_state_interface to generate
errors when this is done.
This commit is contained in:
Aaron Giles 2012-09-11 15:16:43 +00:00
parent 1df58104fe
commit 6d8c3c9f2d
29 changed files with 184 additions and 179 deletions
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2
src/emu/cpu/m6502/opsce02.h
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@ -291,7 +291,7 @@
t1=RDOPARG(); \ t1=RDOPARG(); \
t2=RDOPARG(); \ t2=RDOPARG(); \
t3=RDOPARG(); \ t3=RDOPARG(); \
logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", cpustate->device->safe_pc(),t1,t2,t3); logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", cpustate->device->pc(),t1,t2,t3);
/* 65ce02 ****************************************************** /* 65ce02 ******************************************************
* BBR Branch if bit is reset * BBR Branch if bit is reset

2
src/emu/cpu/tlcs90/tlcs90.c
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@ -1967,7 +1967,7 @@ static CPU_EXECUTE( t90 )
break; break;
default: default:
fatalerror("%04x: unimplemented opcode, op=%02x\n",device->safe_pc(),cpustate->op); fatalerror("%04x: unimplemented opcode, op=%02x\n",device->pc(),cpustate->op);
} }
if ( cpustate->op != EI ) if ( cpustate->op != EI )

2
src/emu/cpu/tms34010/34010gfx.c
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@ -84,7 +84,7 @@ static int apply_window(tms34010_state *tms, const char *inst_name,int srcbpp, U
int diff, cycles = 3; int diff, cycles = 3;
if (WINDOW_CHECKING(tms) == 2) if (WINDOW_CHECKING(tms) == 2)
logerror("%08x: %s apply_window window mode %d not supported!\n", tms->device->safe_pc(), inst_name, WINDOW_CHECKING(tms)); logerror("%08x: %s apply_window window mode %d not supported!\n", tms->device->pc(), inst_name, WINDOW_CHECKING(tms));
CLR_V(tms); CLR_V(tms);
if (WINDOW_CHECKING(tms) == 1) if (WINDOW_CHECKING(tms) == 1)

5
src/emu/distate.h
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@ -162,6 +162,11 @@ public:
// state setters // state setters
void set_state(int index, UINT64 value); void set_state(int index, UINT64 value);
void set_state_string(int index, const char *string); void set_state_string(int index, const char *string);
// deliberately ambiguous functions; if you have the state interface
// just use pc() and pcbase() directly
offs_t safe_pc() { return pc(); }
offs_t safe_pcbase() { return pcbase(); }
public: // protected eventually public: // protected eventually

2
src/mame/drivers/cyclemb.c
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@ -430,7 +430,7 @@ READ8_MEMBER( cyclemb_state::skydest_i8741_0_r )
//printf("%04x\n",m_maincpu->safe_pc()); //printf("%04x\n",m_maincpu->safe_pc());
/* TODO: internal state of this */ /* TODO: internal state of this */
if(m_maincpu->safe_pc() == m_dsw_pc_hack) if(m_maincpu->pc() == m_dsw_pc_hack)
m_mcu[0].rxd = (ioport("DSW1")->read() & 0x1f) << 2; m_mcu[0].rxd = (ioport("DSW1")->read() & 0x1f) << 2;
else if(m_mcu[0].rst) else if(m_mcu[0].rst)
{ {

2
src/mame/drivers/eolithsp.c
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@ -117,7 +117,7 @@ CUSTOM_INPUT_MEMBER(eolith_state::eolith_speedup_getvblank)
// StealSee doesn't use interrupts, just the vblank // StealSee doesn't use interrupts, just the vblank
CUSTOM_INPUT_MEMBER(eolith_state::stealsee_speedup_getvblank) CUSTOM_INPUT_MEMBER(eolith_state::stealsee_speedup_getvblank)
{ {
int pc = m_maincpu->safe_pc(); int pc = m_maincpu->pc();
if (pc==0x400081ec) if (pc==0x400081ec)
if(!eolith_vblank) if(!eolith_vblank)

14
src/mess/audio/mea8000.c
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@ -556,12 +556,12 @@ READ8_DEVICE_HANDLER ( mea8000_r )
case 1: case 1:
/* ready to accept next frame */ /* ready to accept next frame */
#if 0 #if 0
LOG(( "$%04x %f: mea8000_r ready=%i\n", device->machine().firstcpu ->safe_pcbase( ), machine.time().as_double(), mea8000_accept_byte( mea8000 ) )); LOG(( "$%04x %f: mea8000_r ready=%i\n", device->machine().firstcpu->pcbase( ), machine.time().as_double(), mea8000_accept_byte( mea8000 ) ));
#endif #endif
return mea8000_accept_byte(mea8000) << 7; return mea8000_accept_byte(mea8000) << 7;
default: default:
logerror( "$%04x mea8000_r invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset ); logerror( "$%04x mea8000_r invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
} }
return 0; return 0;
} }
@ -577,19 +577,19 @@ WRITE8_DEVICE_HANDLER ( mea8000_w )
{ {
/* got pitch byte before first frame */ /* got pitch byte before first frame */
mea8000->pitch = 2 * data; mea8000->pitch = 2 * data;
LOG(( "$%04x %f: mea8000_w pitch %i\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mea8000->pitch )); LOG(( "$%04x %f: mea8000_w pitch %i\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mea8000->pitch ));
mea8000->state = MEA8000_WAIT_FIRST; mea8000->state = MEA8000_WAIT_FIRST;
mea8000->bufpos = 0; mea8000->bufpos = 0;
} }
else if (mea8000->bufpos == 4) else if (mea8000->bufpos == 4)
{ {
/* overflow */ /* overflow */
LOG(( "$%04x %f: mea8000_w data overflow %02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data )); LOG(( "$%04x %f: mea8000_w data overflow %02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data ));
} }
else else
{ {
/* enqueue frame byte */ /* enqueue frame byte */
LOG(( "$%04x %f: mea8000_w data %02X in frame pos %i\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), LOG(( "$%04x %f: mea8000_w data %02X in frame pos %i\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(),
data, mea8000->bufpos )); data, mea8000->bufpos ));
mea8000->buf[mea8000->bufpos] = data; mea8000->buf[mea8000->bufpos] = data;
mea8000->bufpos++; mea8000->bufpos++;
@ -623,7 +623,7 @@ WRITE8_DEVICE_HANDLER ( mea8000_w )
mea8000_stop_frame(device->machine(), mea8000); mea8000_stop_frame(device->machine(), mea8000);
LOG(( "$%04x %f: mea8000_w command %02X stop=%i cont=%i roe=%i\n", LOG(( "$%04x %f: mea8000_w command %02X stop=%i cont=%i roe=%i\n",
device->machine().firstcpu->safe_pcbase(), device->machine().time().as_double(), data, device->machine().firstcpu->pcbase(), device->machine().time().as_double(), data,
stop, mea8000->cont, mea8000->roe )); stop, mea8000->cont, mea8000->roe ));
mea8000_update_req(device); mea8000_update_req(device);
@ -631,7 +631,7 @@ WRITE8_DEVICE_HANDLER ( mea8000_w )
} }
default: default:
logerror( "$%04x mea8000_w invalid write offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset ); logerror( "$%04x mea8000_w invalid write offset %i\n", device->machine().firstcpu->pcbase( ), offset );
} }
} }

6
src/mess/devices/sonydriv.c
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@ -271,7 +271,7 @@ int sony_read_status(device_t *device)
if (LOG_SONY_EXTRA) if (LOG_SONY_EXTRA)
{ {
printf("sony.status(): action=%x pc=0x%08x%s\n", printf("sony.status(): action=%x pc=0x%08x%s\n",
action, (int) device->machine().firstcpu->safe_pc(), sony.floppy_enable ? "" : " (no drive enabled)"); action, (int) device->machine().firstcpu->pc(), sony.floppy_enable ? "" : " (no drive enabled)");
} }
if ((! sony_enable2()) && sony.floppy_enable) if ((! sony_enable2()) && sony.floppy_enable)
@ -333,7 +333,7 @@ int sony_read_status(device_t *device)
} }
break; break;
case 0x0a: /* At track 0: 0=track zero 1=not track zero */ case 0x0a: /* At track 0: 0=track zero 1=not track zero */
logerror("sony.status(): reading Track 0 pc=0x%08x\n", (int) device->machine().firstcpu->safe_pc()); logerror("sony.status(): reading Track 0 pc=0x%08x\n", (int) device->machine().firstcpu->pc());
if (cur_image) if (cur_image)
result = floppy_tk00_r(&cur_image->device()); result = floppy_tk00_r(&cur_image->device());
else else
@ -407,7 +407,7 @@ static void sony_doaction(device_t *device)
if (LOG_SONY) if (LOG_SONY)
{ {
logerror("sony_doaction(): action=%d pc=0x%08x%s\n", logerror("sony_doaction(): action=%d pc=0x%08x%s\n",
action, (int) device->machine().firstcpu->safe_pc(), (sony.floppy_enable) ? "" : " (MOTOR OFF)"); action, (int) device->machine().firstcpu->pc(), (sony.floppy_enable) ? "" : " (MOTOR OFF)");
} }
if (sony.floppy_enable) if (sony.floppy_enable)

6
src/mess/drivers/camplynx.c
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@ -121,7 +121,7 @@ WRITE8_MEMBER( camplynx_state::lynx48k_bank_w )
if (data & 4) if (data & 4)
membank("bank1")->set_entry(2); membank("bank1")->set_entry(2);
else else
logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->safe_pc(), data); logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->pc(), data);
} }
WRITE8_MEMBER( camplynx_state::lynx128k_bank_w ) WRITE8_MEMBER( camplynx_state::lynx128k_bank_w )
@ -157,7 +157,7 @@ WRITE8_MEMBER( camplynx_state::lynx128k_bank_w )
membank("bank8")->set_base(base + 0x2e000); membank("bank8")->set_base(base + 0x2e000);
} }
else else
logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->safe_pc(), data); logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->pc(), data);
/* Set write banks */ /* Set write banks */
bank = data & 0xd0; bank = data & 0xd0;
@ -186,7 +186,7 @@ WRITE8_MEMBER( camplynx_state::lynx128k_bank_w )
membank("bank18")->set_base(base + 0x2e000); membank("bank18")->set_base(base + 0x2e000);
} }
else else
logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->safe_pc(), data); logerror("%04X: Cannot understand bankswitch command %X\n",m_maincpu->pc(), data);
} }
static ADDRESS_MAP_START( lynx48k_mem, AS_PROGRAM, 8, camplynx_state ) static ADDRESS_MAP_START( lynx48k_mem, AS_PROGRAM, 8, camplynx_state )

2
src/mess/drivers/cxhumax.c
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@ -150,7 +150,7 @@ READ32_MEMBER( cxhumax_state::cx_scratch_r )
UINT32 data = m_scratch_reg; UINT32 data = m_scratch_reg;
verboselog( machine(), 9, "(SCRATCH) %08X -> %08X\n", 0xE0400024 + (offset << 2), data); verboselog( machine(), 9, "(SCRATCH) %08X -> %08X\n", 0xE0400024 + (offset << 2), data);
if((m_maincpu->safe_pc()==0xF0003BB8) || (m_maincpu->safe_pc()==0x01003724) || (m_maincpu->safe_pc()==0x00005d8c)) { // HDCI-2000 if((m_maincpu->pc()==0xF0003BB8) || (m_maincpu->pc()==0x01003724) || (m_maincpu->pc()==0x00005d8c)) { // HDCI-2000
//we're in disabled debug_printf //we're in disabled debug_printf
unsigned char* buf = (unsigned char *)alloca(200); unsigned char* buf = (unsigned char *)alloca(200);
unsigned char temp; unsigned char temp;

4
src/mess/drivers/gp2x.c
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@ -250,7 +250,7 @@ READ32_MEMBER( gp2x_state::nand_r )
break; break;
default: default:
logerror("NAND: read unk command %x (PC %x)\n", m_nand_cmd, m_maincpu->safe_pc()); logerror("NAND: read unk command %x (PC %x)\n", m_nand_cmd, m_maincpu->pc());
break; break;
} }
} }
@ -266,7 +266,7 @@ WRITE32_MEMBER( gp2x_state::nand_w )
{ {
case 4: // command case 4: // command
m_nand_cmd = data; m_nand_cmd = data;
// printf("NAND: command %x (PC %x0)\n", data, m_maincpu->safe_pc()); // printf("NAND: command %x (PC %x0)\n", data, m_maincpu->pc());
m_nand_stage = 0; m_nand_stage = 0;
m_nand_subword_stage = 0; m_nand_subword_stage = 0;
break; break;

2
src/mess/drivers/next.c
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@ -529,7 +529,7 @@ void next_state::dma_do_ctrl_w(int slot, UINT8 data)
data & DMA_INITBUFTURBO ? " initbufturbo" : ""); data & DMA_INITBUFTURBO ? " initbufturbo" : "");
#endif #endif
if(data & DMA_SETENABLE) if(data & DMA_SETENABLE)
logerror("dma enable %s %s %08x (%08x)\n", name, data & DMA_SETREAD ? "read" : "write", (dma_slots[slot].limit-dma_slots[slot].start) & 0x7fffffff, maincpu->safe_pc()); logerror("dma enable %s %s %08x (%08x)\n", name, data & DMA_SETREAD ? "read" : "write", (dma_slots[slot].limit-dma_slots[slot].start) & 0x7fffffff, maincpu->pc());
dma_slot &ds = dma_slots[slot]; dma_slot &ds = dma_slots[slot];
if(data & (DMA_RESET|DMA_INITBUF|DMA_INITBUFTURBO)) { if(data & (DMA_RESET|DMA_INITBUF|DMA_INITBUFTURBO)) {

6
src/mess/drivers/pasogo.c
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@ -177,7 +177,7 @@ READ8_MEMBER( pasogo_state::vg230_io_r )
} }
if (log) if (log)
logerror("%.5x vg230 %02x read %.2x\n",(int) m_maincpu->safe_pc(),vg230->index,data); logerror("%.5x vg230 %02x read %.2x\n",(int) m_maincpu->pc(),vg230->index,data);
// data=machine.root_device().memregion("maincpu")->base()[0x4000+offset]; // data=machine.root_device().memregion("maincpu")->base()[0x4000+offset];
} }
else else
@ -221,7 +221,7 @@ WRITE8_MEMBER( pasogo_state::vg230_io_w )
} }
if (log) if (log)
logerror("%.5x vg230 %02x write %.2x\n",(int)m_maincpu->safe_pc(),vg230->index,data); logerror("%.5x vg230 %02x write %.2x\n",(int)m_maincpu->pc(),vg230->index,data);
} }
else else
vg230->index=data; vg230->index=data;
@ -288,7 +288,7 @@ WRITE8_MEMBER( pasogo_state::ems_w )
ems->mapper[ems->index].address=(ems->mapper[ems->index].data[0]<<14)|((ems->mapper[ems->index].data[1]&0xf)<<22); ems->mapper[ems->index].address=(ems->mapper[ems->index].data[0]<<14)|((ems->mapper[ems->index].data[1]&0xf)<<22);
ems->mapper[ems->index].on=ems->mapper[ems->index].data[1]&0x80; ems->mapper[ems->index].on=ems->mapper[ems->index].data[1]&0x80;
ems->mapper[ems->index].type=(ems->mapper[ems->index].data[1]&0x70)>>4; ems->mapper[ems->index].type=(ems->mapper[ems->index].data[1]&0x70)>>4;
logerror("%.5x ems mapper %d(%05x)on:%d type:%d address:%07x\n",(int)m_maincpu->safe_pc(),ems->index, ems->data<<12, logerror("%.5x ems mapper %d(%05x)on:%d type:%d address:%07x\n",(int)m_maincpu->pc(),ems->index, ems->data<<12,
ems->mapper[ems->index].on, ems->mapper[ems->index].type, ems->mapper[ems->index].address ); ems->mapper[ems->index].on, ems->mapper[ems->index].type, ems->mapper[ems->index].address );
switch (ems->mapper[ems->index].type) switch (ems->mapper[ems->index].type)

4
src/mess/drivers/pasopia7.c
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@ -615,7 +615,7 @@ READ8_MEMBER( pasopia7_state::pasopia7_io_r )
return pasopia7_fdc_r(space, offset & 7); return pasopia7_fdc_r(space, offset & 7);
else else
{ {
logerror("(PC=%06x) Read i/o address %02x\n",m_maincpu->safe_pc(),io_port); logerror("(PC=%06x) Read i/o address %02x\n",m_maincpu->pc(),io_port);
} }
return 0xff; return 0xff;
@ -672,7 +672,7 @@ WRITE8_MEMBER( pasopia7_state::pasopia7_io_w )
pasopia7_fdc_w(space, offset & 7, data); pasopia7_fdc_w(space, offset & 7, data);
else else
{ {
logerror("(PC=%06x) Write i/o address %02x = %02x\n",m_maincpu->safe_pc(),offset,data); logerror("(PC=%06x) Write i/o address %02x = %02x\n",m_maincpu->pc(),offset,data);
} }
} }

2
src/mess/drivers/vboy.c
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@ -793,7 +793,7 @@ READ16_MEMBER( vboy_state::vip_r )
case 0x42: //XPCTRL case 0x42: //XPCTRL
return m_vip_regs.XPCTRL; return m_vip_regs.XPCTRL;
case 0x44: //VER case 0x44: //VER
printf("%08x read VER\n",m_maincpu->safe_pc()); printf("%08x read VER\n",m_maincpu->pc());
return m_vip_regs.VER; return m_vip_regs.VER;
case 0x48: //SPT0 case 0x48: //SPT0
return m_vip_regs.SPT[0]; return m_vip_regs.SPT[0];

4
src/mess/machine/apple2.c
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@ -1450,12 +1450,12 @@ READ8_MEMBER ( apple2_state::apple2_c05x_r )
if (offset == 0xa) // RAM if (offset == 0xa) // RAM
{ {
apple2_setvar(space.machine(), VAR_TK2000RAM, ~0); apple2_setvar(space.machine(), VAR_TK2000RAM, ~0);
printf("TK2000: RAM (PC %x)\n", m_maincpu->safe_pc()); printf("TK2000: RAM (PC %x)\n", m_maincpu->pc());
} }
else if (offset == 0xb) // ROM else if (offset == 0xb) // ROM
{ {
apple2_setvar(space.machine(), 0, ~VAR_TK2000RAM); apple2_setvar(space.machine(), 0, ~VAR_TK2000RAM);
printf("TK2000: ROM (PC %x)\n", m_maincpu->safe_pc()); printf("TK2000: ROM (PC %x)\n", m_maincpu->pc());
} }
} }

4
src/mess/machine/coco.c
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@ -261,8 +261,8 @@ UINT8 coco_state::floating_bus_read(void)
address_space *program = m_maincpu->space(AS_PROGRAM); address_space *program = m_maincpu->space(AS_PROGRAM);
// get the previous and current PC // get the previous and current PC
UINT16 prev_pc = m_maincpu->safe_pcbase(); UINT16 prev_pc = m_maincpu->pcbase();
UINT16 pc = m_maincpu->safe_pc(); UINT16 pc = m_maincpu->pc();
// get the byte; and skip over header bytes // get the byte; and skip over header bytes
byte = program->read_byte(prev_pc); byte = program->read_byte(prev_pc);

132
src/mess/machine/compis.c
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@ -550,7 +550,7 @@ void compis_state::handle_eoi(int data)
case 0x0d: m_i186.intr.in_service &= ~0x20; break; case 0x0d: m_i186.intr.in_service &= ~0x20; break;
case 0x0e: m_i186.intr.in_service &= ~0x40; break; case 0x0e: m_i186.intr.in_service &= ~0x40; break;
case 0x0f: m_i186.intr.in_service &= ~0x80; break; case 0x0f: m_i186.intr.in_service &= ~0x80; break;
default: logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", m_maincpu->safe_pc(), data & 0x1f); default: logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", m_maincpu->pc(), data & 0x1f);
} }
if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", machine().time().as_double(), data & 0x1f); if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", machine().time().as_double(), data & 0x1f);
} }
@ -718,7 +718,7 @@ void compis_state::internal_timer_update(int which, int new_count, int new_maxA,
diff = new_control ^ t->control; diff = new_control ^ t->control;
if (diff & 0x001c) if (diff & 0x001c)
logerror("%05X:ERROR! -unsupported timer mode %04X\n", logerror("%05X:ERROR! -unsupported timer mode %04X\n",
m_maincpu->safe_pc(), new_control); m_maincpu->pc(), new_control);
/* if we have real changes, update things */ /* if we have real changes, update things */
if (diff != 0) if (diff != 0)
@ -820,7 +820,7 @@ void compis_state::update_dma_control(int which, int new_control)
diff = new_control ^ d->control; diff = new_control ^ d->control;
if (diff & 0x6811) if (diff & 0x6811)
logerror("%05X:ERROR! - unsupported DMA mode %04X\n", logerror("%05X:ERROR! - unsupported DMA mode %04X\n",
m_maincpu->safe_pc(), new_control); m_maincpu->pc(), new_control);
/* if we're going live, set a timer */ /* if we're going live, set a timer */
if ((diff & 0x0002) && (new_control & 0x0002)) if ((diff & 0x0002) && (new_control & 0x0002))
@ -877,21 +877,21 @@ READ16_MEMBER( compis_state::compis_i186_internal_port_r )
switch (offset) switch (offset)
{ {
case 0x11: case 0x11:
logerror("%05X:ERROR - read from 80186 EOI\n", m_maincpu->safe_pc()); logerror("%05X:ERROR - read from 80186 EOI\n", m_maincpu->pc());
break; break;
case 0x12: case 0x12:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", m_maincpu->pc());
if (m_i186.intr.poll_status & 0x8000) if (m_i186.intr.poll_status & 0x8000)
int_callback(machine().device("maincpu"), 0); int_callback(machine().device("maincpu"), 0);
return m_i186.intr.poll_status; return m_i186.intr.poll_status;
case 0x13: case 0x13:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", m_maincpu->pc());
return m_i186.intr.poll_status; return m_i186.intr.poll_status;
case 0x14: case 0x14:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", m_maincpu->pc());
temp = (m_i186.intr.timer >> 3) & 0x01; temp = (m_i186.intr.timer >> 3) & 0x01;
temp |= (m_i186.intr.dma[0] >> 1) & 0x04; temp |= (m_i186.intr.dma[0] >> 1) & 0x04;
temp |= (m_i186.intr.dma[1] >> 0) & 0x08; temp |= (m_i186.intr.dma[1] >> 0) & 0x08;
@ -902,56 +902,56 @@ READ16_MEMBER( compis_state::compis_i186_internal_port_r )
return temp; return temp;
case 0x15: case 0x15:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", m_maincpu->pc());
return m_i186.intr.priority_mask; return m_i186.intr.priority_mask;
case 0x16: case 0x16:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", m_maincpu->pc());
return m_i186.intr.in_service; return m_i186.intr.in_service;
case 0x17: case 0x17:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", m_maincpu->pc());
temp = m_i186.intr.request & ~0x0001; temp = m_i186.intr.request & ~0x0001;
if (m_i186.intr.status & 0x0007) if (m_i186.intr.status & 0x0007)
temp |= 1; temp |= 1;
return temp; return temp;
case 0x18: case 0x18:
if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", m_maincpu->pc());
return m_i186.intr.status; return m_i186.intr.status;
case 0x19: case 0x19:
if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", m_maincpu->pc());
return m_i186.intr.timer; return m_i186.intr.timer;
case 0x1a: case 0x1a:
if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", m_maincpu->pc());
return m_i186.intr.dma[0]; return m_i186.intr.dma[0];
case 0x1b: case 0x1b:
if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", m_maincpu->pc());
return m_i186.intr.dma[1]; return m_i186.intr.dma[1];
case 0x1c: case 0x1c:
if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", m_maincpu->pc());
return m_i186.intr.ext[0]; return m_i186.intr.ext[0];
case 0x1d: case 0x1d:
if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", m_maincpu->pc());
return m_i186.intr.ext[1]; return m_i186.intr.ext[1];
case 0x1e: case 0x1e:
if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", m_maincpu->pc());
return m_i186.intr.ext[2]; return m_i186.intr.ext[2];
case 0x1f: case 0x1f:
if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", m_maincpu->pc());
return m_i186.intr.ext[3]; return m_i186.intr.ext[3];
case 0x28: case 0x28:
case 0x2c: case 0x2c:
case 0x30: case 0x30:
if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", m_maincpu->safe_pc(), (offset - 0x28) / 4); if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", m_maincpu->pc(), (offset - 0x28) / 4);
which = (offset - 0x28) / 4; which = (offset - 0x28) / 4;
if (!(offset & 1)) if (!(offset & 1))
internal_timer_sync(which); internal_timer_sync(which);
@ -960,87 +960,87 @@ READ16_MEMBER( compis_state::compis_i186_internal_port_r )
case 0x29: case 0x29:
case 0x2d: case 0x2d:
case 0x31: case 0x31:
if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", m_maincpu->safe_pc(), (offset - 0x29) / 4); if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", m_maincpu->pc(), (offset - 0x29) / 4);
which = (offset - 0x29) / 4; which = (offset - 0x29) / 4;
return m_i186.timer[which].maxA; return m_i186.timer[which].maxA;
case 0x2a: case 0x2a:
case 0x2e: case 0x2e:
logerror("%05X:read 80186 Timer %d max B\n", m_maincpu->safe_pc(), (offset - 0x2a) / 4); logerror("%05X:read 80186 Timer %d max B\n", m_maincpu->pc(), (offset - 0x2a) / 4);
which = (offset - 0x2a) / 4; which = (offset - 0x2a) / 4;
return m_i186.timer[which].maxB; return m_i186.timer[which].maxB;
case 0x2b: case 0x2b:
case 0x2f: case 0x2f:
case 0x33: case 0x33:
if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", m_maincpu->safe_pc(), (offset - 0x2b) / 4); if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", m_maincpu->pc(), (offset - 0x2b) / 4);
which = (offset - 0x2b) / 4; which = (offset - 0x2b) / 4;
return m_i186.timer[which].control; return m_i186.timer[which].control;
case 0x50: case 0x50:
if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", m_maincpu->pc());
return m_i186.mem.upper; return m_i186.mem.upper;
case 0x51: case 0x51:
if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", m_maincpu->pc());
return m_i186.mem.lower; return m_i186.mem.lower;
case 0x52: case 0x52:
if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", m_maincpu->pc());
return m_i186.mem.peripheral; return m_i186.mem.peripheral;
case 0x53: case 0x53:
if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", m_maincpu->pc());
return m_i186.mem.middle; return m_i186.mem.middle;
case 0x54: case 0x54:
if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", m_maincpu->safe_pc()); if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", m_maincpu->pc());
return m_i186.mem.middle_size; return m_i186.mem.middle_size;
case 0x60: case 0x60:
case 0x68: case 0x68:
if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", m_maincpu->safe_pc(), (offset - 0x60) / 8); if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", m_maincpu->pc(), (offset - 0x60) / 8);
which = (offset - 0x60) / 8; which = (offset - 0x60) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
return m_i186.dma[which].source; return m_i186.dma[which].source;
case 0x61: case 0x61:
case 0x69: case 0x69:
if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", m_maincpu->safe_pc(), (offset - 0x61) / 8); if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", m_maincpu->pc(), (offset - 0x61) / 8);
which = (offset - 0x61) / 8; which = (offset - 0x61) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
return m_i186.dma[which].source >> 16; return m_i186.dma[which].source >> 16;
case 0x62: case 0x62:
case 0x6a: case 0x6a:
if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", m_maincpu->safe_pc(), (offset - 0x62) / 8); if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", m_maincpu->pc(), (offset - 0x62) / 8);
which = (offset - 0x62) / 8; which = (offset - 0x62) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
return m_i186.dma[which].dest; return m_i186.dma[which].dest;
case 0x63: case 0x63:
case 0x6b: case 0x6b:
if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", m_maincpu->safe_pc(), (offset - 0x63) / 8); if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", m_maincpu->pc(), (offset - 0x63) / 8);
which = (offset - 0x63) / 8; which = (offset - 0x63) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
return m_i186.dma[which].dest >> 16; return m_i186.dma[which].dest >> 16;
case 0x64: case 0x64:
case 0x6c: case 0x6c:
if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", m_maincpu->safe_pc(), (offset - 0x64) / 8); if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", m_maincpu->pc(), (offset - 0x64) / 8);
which = (offset - 0x64) / 8; which = (offset - 0x64) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
return m_i186.dma[which].count; return m_i186.dma[which].count;
case 0x65: case 0x65:
case 0x6d: case 0x6d:
if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", m_maincpu->safe_pc(), (offset - 0x65) / 8); if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", m_maincpu->pc(), (offset - 0x65) / 8);
which = (offset - 0x65) / 8; which = (offset - 0x65) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
return m_i186.dma[which].control; return m_i186.dma[which].control;
default: default:
logerror("%05X:read 80186 port %02X\n", m_maincpu->safe_pc(), offset); logerror("%05X:read 80186 port %02X\n", m_maincpu->pc(), offset);
break; break;
} }
return 0x00; return 0x00;
@ -1061,21 +1061,21 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
switch (offset) switch (offset)
{ {
case 0x11: case 0x11:
if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", m_maincpu->pc(), data16);
handle_eoi(0x8000); handle_eoi(0x8000);
update_interrupt_state(machine()); update_interrupt_state(machine());
break; break;
case 0x12: case 0x12:
logerror("%05X:ERROR - write to 80186 interrupt poll = %04X\n", m_maincpu->safe_pc(), data16); logerror("%05X:ERROR - write to 80186 interrupt poll = %04X\n", m_maincpu->pc(), data16);
break; break;
case 0x13: case 0x13:
logerror("%05X:ERROR - write to 80186 interrupt poll status = %04X\n", m_maincpu->safe_pc(), data16); logerror("%05X:ERROR - write to 80186 interrupt poll status = %04X\n", m_maincpu->pc(), data16);
break; break;
case 0x14: case 0x14:
if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.timer = (m_i186.intr.timer & ~0x08) | ((data16 << 3) & 0x08); m_i186.intr.timer = (m_i186.intr.timer & ~0x08) | ((data16 << 3) & 0x08);
m_i186.intr.dma[0] = (m_i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08); m_i186.intr.dma[0] = (m_i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08);
m_i186.intr.dma[1] = (m_i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08); m_i186.intr.dma[1] = (m_i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08);
@ -1087,68 +1087,68 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
break; break;
case 0x15: case 0x15:
if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.priority_mask = data16 & 0x0007; m_i186.intr.priority_mask = data16 & 0x0007;
update_interrupt_state(machine()); update_interrupt_state(machine());
break; break;
case 0x16: case 0x16:
if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.in_service = data16 & 0x00ff; m_i186.intr.in_service = data16 & 0x00ff;
update_interrupt_state(machine()); update_interrupt_state(machine());
break; break;
case 0x17: case 0x17:
if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.request = (m_i186.intr.request & ~0x00c0) | (data16 & 0x00c0); m_i186.intr.request = (m_i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
update_interrupt_state(machine()); update_interrupt_state(machine());
break; break;
case 0x18: case 0x18:
if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.status = (m_i186.intr.status & ~0x8007) | (data16 & 0x8007); m_i186.intr.status = (m_i186.intr.status & ~0x8007) | (data16 & 0x8007);
update_interrupt_state(machine()); update_interrupt_state(machine());
break; break;
case 0x19: case 0x19:
if (LOG_PORTS) logerror("%05X:80186 timer interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 timer interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.timer = data16 & 0x000f; m_i186.intr.timer = data16 & 0x000f;
break; break;
case 0x1a: case 0x1a:
if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.dma[0] = data16 & 0x000f; m_i186.intr.dma[0] = data16 & 0x000f;
break; break;
case 0x1b: case 0x1b:
if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.dma[1] = data16 & 0x000f; m_i186.intr.dma[1] = data16 & 0x000f;
break; break;
case 0x1c: case 0x1c:
if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.ext[0] = data16 & 0x007f; m_i186.intr.ext[0] = data16 & 0x007f;
break; break;
case 0x1d: case 0x1d:
if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.ext[1] = data16 & 0x007f; m_i186.intr.ext[1] = data16 & 0x007f;
break; break;
case 0x1e: case 0x1e:
if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.ext[2] = data16 & 0x001f; m_i186.intr.ext[2] = data16 & 0x001f;
break; break;
case 0x1f: case 0x1f:
if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", m_maincpu->pc(), data16);
m_i186.intr.ext[3] = data16 & 0x001f; m_i186.intr.ext[3] = data16 & 0x001f;
break; break;
case 0x28: case 0x28:
case 0x2c: case 0x2c:
case 0x30: case 0x30:
if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", m_maincpu->safe_pc(), (offset - 0x28) / 4, data16); if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", m_maincpu->pc(), (offset - 0x28) / 4, data16);
which = (offset - 0x28) / 4; which = (offset - 0x28) / 4;
internal_timer_update(which, data16, -1, -1, -1); internal_timer_update(which, data16, -1, -1, -1);
break; break;
@ -1156,14 +1156,14 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x29: case 0x29:
case 0x2d: case 0x2d:
case 0x31: case 0x31:
if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", m_maincpu->safe_pc(), (offset - 0x29) / 4, data16); if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", m_maincpu->pc(), (offset - 0x29) / 4, data16);
which = (offset - 0x29) / 4; which = (offset - 0x29) / 4;
internal_timer_update(which, -1, data16, -1, -1); internal_timer_update(which, -1, data16, -1, -1);
break; break;
case 0x2a: case 0x2a:
case 0x2e: case 0x2e:
if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", m_maincpu->safe_pc(), (offset - 0x2a) / 4, data16); if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", m_maincpu->pc(), (offset - 0x2a) / 4, data16);
which = (offset - 0x2a) / 4; which = (offset - 0x2a) / 4;
internal_timer_update(which, -1, -1, data16, -1); internal_timer_update(which, -1, -1, data16, -1);
break; break;
@ -1171,33 +1171,33 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x2b: case 0x2b:
case 0x2f: case 0x2f:
case 0x33: case 0x33:
if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", m_maincpu->safe_pc(), (offset - 0x2b) / 4, data16); if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", m_maincpu->pc(), (offset - 0x2b) / 4, data16);
which = (offset - 0x2b) / 4; which = (offset - 0x2b) / 4;
internal_timer_update(which, -1, -1, -1, data16); internal_timer_update(which, -1, -1, -1, data16);
break; break;
case 0x50: case 0x50:
if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", m_maincpu->pc(), data16);
m_i186.mem.upper = data16 | 0xc038; m_i186.mem.upper = data16 | 0xc038;
break; break;
case 0x51: case 0x51:
if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", m_maincpu->pc(), data16);
m_i186.mem.lower = (data16 & 0x3fff) | 0x0038; //printf("%X\n",m_i186.mem.lower); m_i186.mem.lower = (data16 & 0x3fff) | 0x0038; //printf("%X\n",m_i186.mem.lower);
break; break;
case 0x52: case 0x52:
if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", m_maincpu->pc(), data16);
m_i186.mem.peripheral = data16 | 0x0038; m_i186.mem.peripheral = data16 | 0x0038;
break; break;
case 0x53: case 0x53:
if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", m_maincpu->pc(), data16);
m_i186.mem.middle = data16 | 0x01f8; m_i186.mem.middle = data16 | 0x01f8;
break; break;
case 0x54: case 0x54:
if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", m_maincpu->pc(), data16);
m_i186.mem.middle_size = data16 | 0x8038; m_i186.mem.middle_size = data16 | 0x8038;
temp = (m_i186.mem.peripheral & 0xffc0) << 4; temp = (m_i186.mem.peripheral & 0xffc0) << 4;
@ -1221,7 +1221,7 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x60: case 0x60:
case 0x68: case 0x68:
if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", m_maincpu->safe_pc(), (offset - 0x60) / 8, data16); if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", m_maincpu->pc(), (offset - 0x60) / 8, data16);
which = (offset - 0x60) / 8; which = (offset - 0x60) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
m_i186.dma[which].source = (m_i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff); m_i186.dma[which].source = (m_i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff);
@ -1229,7 +1229,7 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x61: case 0x61:
case 0x69: case 0x69:
if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", m_maincpu->safe_pc(), (offset - 0x61) / 8, data16); if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", m_maincpu->pc(), (offset - 0x61) / 8, data16);
which = (offset - 0x61) / 8; which = (offset - 0x61) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
m_i186.dma[which].source = (m_i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000); m_i186.dma[which].source = (m_i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000);
@ -1237,7 +1237,7 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x62: case 0x62:
case 0x6a: case 0x6a:
if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", m_maincpu->safe_pc(), (offset - 0x62) / 8, data16); if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", m_maincpu->pc(), (offset - 0x62) / 8, data16);
which = (offset - 0x62) / 8; which = (offset - 0x62) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff); m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff);
@ -1245,7 +1245,7 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x63: case 0x63:
case 0x6b: case 0x6b:
if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", m_maincpu->safe_pc(), (offset - 0x63) / 8, data16); if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", m_maincpu->pc(), (offset - 0x63) / 8, data16);
which = (offset - 0x63) / 8; which = (offset - 0x63) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000); m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000);
@ -1253,7 +1253,7 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x64: case 0x64:
case 0x6c: case 0x6c:
if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", m_maincpu->safe_pc(), (offset - 0x64) / 8, data16); if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", m_maincpu->pc(), (offset - 0x64) / 8, data16);
which = (offset - 0x64) / 8; which = (offset - 0x64) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
m_i186.dma[which].count = data16; m_i186.dma[which].count = data16;
@ -1261,14 +1261,14 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
case 0x65: case 0x65:
case 0x6d: case 0x6d:
if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", m_maincpu->safe_pc(), (offset - 0x65) / 8, data16); if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", m_maincpu->pc(), (offset - 0x65) / 8, data16);
which = (offset - 0x65) / 8; which = (offset - 0x65) / 8;
// stream_update(dma_stream, 0); // stream_update(dma_stream, 0);
update_dma_control(which, data16); update_dma_control(which, data16);
break; break;
case 0x7f: case 0x7f:
if (LOG_PORTS) logerror("%05X:80186 relocation register = %04X\n", m_maincpu->safe_pc(), data16); if (LOG_PORTS) logerror("%05X:80186 relocation register = %04X\n", m_maincpu->pc(), data16);
/* we assume here there that this doesn't happen too often */ /* we assume here there that this doesn't happen too often */
/* plus, we can't really remove the old memory range, so we also assume that it's */ /* plus, we can't really remove the old memory range, so we also assume that it's */
@ -1289,7 +1289,7 @@ WRITE16_MEMBER( compis_state::compis_i186_internal_port_w )
break; break;
default: default:
logerror("%05X:80186 port %02X = %04X\n", m_maincpu->safe_pc(), offset, data16); logerror("%05X:80186 port %02X = %04X\n", m_maincpu->pc(), offset, data16);
break; break;
} }
} }

2
src/mess/machine/gamecom.c
View File

@ -329,7 +329,7 @@ WRITE8_MEMBER( gamecom_state::gamecom_internal_w )
case SM8521_55: case SM8521_56: case SM8521_57: case SM8521_58: case SM8521_55: case SM8521_56: case SM8521_57: case SM8521_58:
case SM8521_59: case SM8521_5A: case SM8521_5B: case SM8521_5C: case SM8521_59: case SM8521_5A: case SM8521_5B: case SM8521_5C:
case SM8521_5D: case SM8521_5D:
logerror( "%X: Write to reserved address (0x%02X). Value written: 0x%02X\n", m_maincpu->safe_pc(), offset, data ); logerror( "%X: Write to reserved address (0x%02X). Value written: 0x%02X\n", m_maincpu->pc(), offset, data );
break; break;
} }
m_p_ram[offset] = data; m_p_ram[offset] = data;

4
src/mess/machine/isa_hdc.c
View File

@ -796,7 +796,7 @@ static READ8_DEVICE_HANDLER(pc_HDC_r )
} }
if (LOG_HDC_CALL) if (LOG_HDC_CALL)
logerror("pc_HDC_r(): pc=%06X offs=%d result=0x%02x\n", device->machine().firstcpu->safe_pc(), offset, data); logerror("pc_HDC_r(): pc=%06X offs=%d result=0x%02x\n", device->machine().firstcpu->pc(), offset, data);
return data; return data;
} }
@ -805,7 +805,7 @@ static WRITE8_DEVICE_HANDLER( pc_HDC_w )
{ {
isa8_hdc_device *hdc = downcast<isa8_hdc_device *>(device); isa8_hdc_device *hdc = downcast<isa8_hdc_device *>(device);
if (LOG_HDC_CALL) if (LOG_HDC_CALL)
logerror("pc_HDC_w(): pc=%06X offs=%d data=0x%02x\n", device->machine().firstcpu->safe_pc(), offset, data); logerror("pc_HDC_w(): pc=%06X offs=%d data=0x%02x\n", device->machine().firstcpu->pc(), offset, data);
switch( offset ) switch( offset )
{ {

10
src/mess/machine/mac.c
View File

@ -1158,7 +1158,7 @@ READ16_MEMBER ( mac_state::mac_iwm_r )
result = applefdc_r(fdc, (offset >> 8)); result = applefdc_r(fdc, (offset >> 8));
if (LOG_MAC_IWM) if (LOG_MAC_IWM)
printf("mac_iwm_r: offset=0x%08x mem_mask %04x = %02x (PC %x)\n", offset, mem_mask, result, m_maincpu->safe_pc()); printf("mac_iwm_r: offset=0x%08x mem_mask %04x = %02x (PC %x)\n", offset, mem_mask, result, m_maincpu->pc());
return (result << 8) | result; return (result << 8) | result;
} }
@ -1168,7 +1168,7 @@ WRITE16_MEMBER ( mac_state::mac_iwm_w )
device_t *fdc = space.machine().device("fdc"); device_t *fdc = space.machine().device("fdc");
if (LOG_MAC_IWM) if (LOG_MAC_IWM)
printf("mac_iwm_w: offset=0x%08x data=0x%04x mask %04x (PC=%x)\n", offset, data, mem_mask, m_maincpu->safe_pc()); printf("mac_iwm_w: offset=0x%08x data=0x%04x mask %04x (PC=%x)\n", offset, data, mem_mask, m_maincpu->pc());
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
applefdc_w(fdc, (offset >> 8), data & 0xff); applefdc_w(fdc, (offset >> 8), data & 0xff);
@ -1534,7 +1534,7 @@ static WRITE8_DEVICE_HANDLER(mac_via_out_b)
else if (ADB_IS_EGRET) else if (ADB_IS_EGRET)
{ {
#if LOG_ADB #if LOG_ADB
printf("68K: New Egret state: SS %d VF %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->safe_pc()); printf("68K: New Egret state: SS %d VF %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->pc());
#endif #endif
mac->m_egret->set_via_full((data&0x10) ? 1 : 0); mac->m_egret->set_via_full((data&0x10) ? 1 : 0);
mac->m_egret->set_sys_session((data&0x20) ? 1 : 0); mac->m_egret->set_sys_session((data&0x20) ? 1 : 0);
@ -1542,7 +1542,7 @@ static WRITE8_DEVICE_HANDLER(mac_via_out_b)
else if (ADB_IS_CUDA) else if (ADB_IS_CUDA)
{ {
#if LOG_ADB #if LOG_ADB
printf("68K: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->safe_pc()); printf("68K: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->pc());
#endif #endif
mac->m_cuda->set_byteack((data&0x10) ? 1 : 0); mac->m_cuda->set_byteack((data&0x10) ? 1 : 0);
mac->m_cuda->set_tip((data&0x20) ? 1 : 0); mac->m_cuda->set_tip((data&0x20) ? 1 : 0);
@ -2012,7 +2012,7 @@ DIRECT_UPDATE_MEMBER(mac_state::overlay_opbaseoverride)
READ32_MEMBER(mac_state::mac_read_id) READ32_MEMBER(mac_state::mac_read_id)
{ {
// printf("Mac read ID reg @ PC=%x\n", m_maincpu->safe_pc()); // printf("Mac read ID reg @ PC=%x\n", m_maincpu->pc());
switch (m_model) switch (m_model)
{ {

16
src/mess/machine/macpci.c
View File

@ -53,7 +53,7 @@ static READ8_DEVICE_HANDLER(mac_via_in_a)
{ {
// macpci_state *mac = device->machine().driver_data<macpci_state>(); // macpci_state *mac = device->machine().driver_data<macpci_state>();
// printf("VIA1 IN_A (PC %x)\n", mac->m_maincpu->safe_pc()); // printf("VIA1 IN_A (PC %x)\n", mac->m_maincpu->pc());
return 0x80; return 0x80;
} }
@ -65,7 +65,7 @@ static READ8_DEVICE_HANDLER(mac_via_in_b)
val |= mac->m_cuda->get_treq()<<3; val |= mac->m_cuda->get_treq()<<3;
// printf("VIA1 IN B = %02x (PC %x)\n", val, mac->m_maincpu->safe_pc()); // printf("VIA1 IN B = %02x (PC %x)\n", val, mac->m_maincpu->pc());
return val; return val;
} }
@ -74,17 +74,17 @@ static WRITE8_DEVICE_HANDLER(mac_via_out_a)
{ {
// macpci_state *mac = device->machine().driver_data<macpci_state>(); // macpci_state *mac = device->machine().driver_data<macpci_state>();
// printf("VIA1 OUT A: %02x (PC %x)\n", data, mac->m_maincpu->safe_pc()); // printf("VIA1 OUT A: %02x (PC %x)\n", data, mac->m_maincpu->pc());
} }
static WRITE8_DEVICE_HANDLER(mac_via_out_b) static WRITE8_DEVICE_HANDLER(mac_via_out_b)
{ {
macpci_state *mac = device->machine().driver_data<macpci_state>(); macpci_state *mac = device->machine().driver_data<macpci_state>();
// printf("VIA1 OUT B: %02x (PC %x)\n", data, mac->m_maincpu->safe_pc()); // printf("VIA1 OUT B: %02x (PC %x)\n", data, mac->m_maincpu->pc());
#if LOG_ADB #if LOG_ADB
printf("PPC: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->safe_pc()); printf("PPC: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, mac->m_maincpu->pc());
#endif #endif
mac->m_cuda->set_byteack((data&0x10) ? 1 : 0); mac->m_cuda->set_byteack((data&0x10) ? 1 : 0);
mac->m_cuda->set_tip((data&0x20) ? 1 : 0); mac->m_cuda->set_tip((data&0x20) ? 1 : 0);
@ -98,7 +98,7 @@ READ16_MEMBER ( macpci_state::mac_via_r )
offset &= 0x0f; offset &= 0x0f;
if (LOG_VIA) if (LOG_VIA)
printf("mac_via_r: offset=0x%02x (PC=%x)\n", offset, m_maincpu->safe_pc()); printf("mac_via_r: offset=0x%02x (PC=%x)\n", offset, m_maincpu->pc());
data = m_via1->read(space, offset); data = m_via1->read(space, offset);
device_adjust_icount(m_maincpu, m_via_cycles); device_adjust_icount(m_maincpu, m_via_cycles);
@ -112,7 +112,7 @@ WRITE16_MEMBER ( macpci_state::mac_via_w )
offset &= 0x0f; offset &= 0x0f;
if (LOG_VIA) if (LOG_VIA)
printf("mac_via_w: offset=0x%02x data=0x%08x (PC=%x)\n", offset, data, m_maincpu->safe_pc()); printf("mac_via_w: offset=0x%02x data=0x%08x (PC=%x)\n", offset, data, m_maincpu->pc());
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
m_via1->write(space, offset, data & 0xff); m_via1->write(space, offset, data & 0xff);
@ -181,7 +181,7 @@ MAC_DRIVER_INIT(pippin, PCIMODEL_MAC_PIPPIN)
READ32_MEMBER(macpci_state::mac_read_id) READ32_MEMBER(macpci_state::mac_read_id)
{ {
printf("Mac read ID reg @ PC=%x\n", m_maincpu->safe_pc()); printf("Mac read ID reg @ PC=%x\n", m_maincpu->pc());
switch (m_model) switch (m_model)
{ {

40
src/mess/machine/mc6843.c
View File

@ -427,7 +427,7 @@ READ8_DEVICE_HANDLER ( mc6843_r )
int cmd = mc6843->CMR & 0x0f; int cmd = mc6843->CMR & 0x0f;
LOG(( "%f $%04x mc6843_r: data input cmd=%s(%i), pos=%i/%i, GCR=%i, ", LOG(( "%f $%04x mc6843_r: data input cmd=%s(%i), pos=%i/%i, GCR=%i, ",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
mc6843_cmd[cmd], cmd, mc6843->data_idx, mc6843_cmd[cmd], cmd, mc6843->data_idx,
mc6843->data_size, mc6843->GCR )); mc6843->data_size, mc6843->GCR ));
@ -480,7 +480,7 @@ READ8_DEVICE_HANDLER ( mc6843_r )
{ {
/* XXX TODO: other read modes */ /* XXX TODO: other read modes */
data = mc6843->data[0]; data = mc6843->data[0];
logerror( "$%04x mc6843 read in unsupported command mode %i\n", device->machine().firstcpu ->safe_pcbase( ), cmd ); logerror( "$%04x mc6843 read in unsupported command mode %i\n", device->machine().firstcpu->pcbase( ), cmd );
} }
LOG(( "data=%02X\n", data )); LOG(( "data=%02X\n", data ));
@ -491,14 +491,14 @@ READ8_DEVICE_HANDLER ( mc6843_r )
case 1: /* Current-Track Address Register (CTAR) */ case 1: /* Current-Track Address Register (CTAR) */
data = mc6843->CTAR; data = mc6843->CTAR;
LOG(( "%f $%04x mc6843_r: read CTAR %i (actual=%i)\n", LOG(( "%f $%04x mc6843_r: read CTAR %i (actual=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
floppy_drive_get_current_track( mc6843_floppy_image( device ) ) )); floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
break; break;
case 2: /* Interrupt Status Register (ISR) */ case 2: /* Interrupt Status Register (ISR) */
data = mc6843->ISR; data = mc6843->ISR;
LOG(( "%f $%04x mc6843_r: read ISR %02X: cmd=%scomplete settle=%scomplete sense-rq=%i STRB=%i\n", LOG(( "%f $%04x mc6843_r: read ISR %02X: cmd=%scomplete settle=%scomplete sense-rq=%i STRB=%i\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
(data & 1) ? "" : "not-" , (data & 2) ? "" : "not-", (data & 1) ? "" : "not-" , (data & 2) ? "" : "not-",
(data >> 2) & 1, (data >> 3) & 1 )); (data >> 2) & 1, (data >> 3) & 1 ));
@ -524,7 +524,7 @@ READ8_DEVICE_HANDLER ( mc6843_r )
data = mc6843->STRA; data = mc6843->STRA;
LOG(( "%f $%04x mc6843_r: read STRA %02X: data-rq=%i del-dta=%i ready=%i t0=%i wp=%i trk-dif=%i idx=%i busy=%i\n", LOG(( "%f $%04x mc6843_r: read STRA %02X: data-rq=%i del-dta=%i ready=%i t0=%i wp=%i trk-dif=%i idx=%i busy=%i\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
data & 1, (data >> 1) & 1, (data >> 2) & 1, (data >> 3) & 1, data & 1, (data >> 1) & 1, (data >> 2) & 1, (data >> 3) & 1,
(data >> 4) & 1, (data >> 5) & 1, (data >> 6) & 1, (data >> 7) & 1 )); (data >> 4) & 1, (data >> 5) & 1, (data >> 6) & 1, (data >> 7) & 1 ));
break; break;
@ -533,7 +533,7 @@ READ8_DEVICE_HANDLER ( mc6843_r )
case 4: /* Status Register B (STRB) */ case 4: /* Status Register B (STRB) */
data = mc6843->STRB; data = mc6843->STRB;
LOG(( "%f $%04x mc6843_r: read STRB %02X: data-err=%i CRC-err=%i dta--mrk-err=%i sect-mrk-err=%i seek-err=%i fi=%i wr-err=%i hard-err=%i\n", LOG(( "%f $%04x mc6843_r: read STRB %02X: data-err=%i CRC-err=%i dta--mrk-err=%i sect-mrk-err=%i seek-err=%i fi=%i wr-err=%i hard-err=%i\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
data & 1, (data >> 1) & 1, (data >> 2) & 1, (data >> 3) & 1, data & 1, (data >> 1) & 1, (data >> 2) & 1, (data >> 3) & 1,
(data >> 4) & 1, (data >> 5) & 1, (data >> 6) & 1, (data >> 7) & 1 )); (data >> 4) & 1, (data >> 5) & 1, (data >> 6) & 1, (data >> 7) & 1 ));
@ -545,12 +545,12 @@ READ8_DEVICE_HANDLER ( mc6843_r )
case 7: /* Logical-Track Address Register (LTAR) */ case 7: /* Logical-Track Address Register (LTAR) */
data = mc6843->LTAR; data = mc6843->LTAR;
LOG(( "%f $%04x mc6843_r: read LTAR %i (actual=%i)\n", LOG(( "%f $%04x mc6843_r: read LTAR %i (actual=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
floppy_drive_get_current_track( mc6843_floppy_image( device ) ) )); floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
break; break;
default: default:
logerror( "$%04x mc6843 invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset ); logerror( "$%04x mc6843 invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
} }
return data; return data;
@ -567,7 +567,7 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
int FWF = (mc6843->CMR >> 4) & 1; int FWF = (mc6843->CMR >> 4) & 1;
LOG(( "%f $%04x mc6843_w: data output cmd=%s(%i), pos=%i/%i, GCR=%i, data=%02X\n", LOG(( "%f $%04x mc6843_w: data output cmd=%s(%i), pos=%i/%i, GCR=%i, data=%02X\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
mc6843_cmd[cmd], cmd, mc6843->data_idx, mc6843_cmd[cmd], cmd, mc6843->data_idx,
mc6843->data_size, mc6843->GCR, data )); mc6843->data_size, mc6843->GCR, data ));
@ -584,7 +584,7 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
/* end of sector write */ /* end of sector write */
device_t* img = mc6843_floppy_image( device ); device_t* img = mc6843_floppy_image( device );
LOG(( "%f $%04x mc6843_w: write sector %i\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->data_id )); LOG(( "%f $%04x mc6843_w: write sector %i\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->data_id ));
floppy_drive_write_sector_data( floppy_drive_write_sector_data(
img, mc6843->side, mc6843->data_id, img, mc6843->side, mc6843->data_id,
@ -648,7 +648,7 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
UINT8 track = mc6843->data[1]; UINT8 track = mc6843->data[1];
UINT8 sector = mc6843->data[3]; UINT8 sector = mc6843->data[3];
UINT8 filler = 0xe5; /* standard Thomson filler */ UINT8 filler = 0xe5; /* standard Thomson filler */
LOG(( "%f $%04x mc6843_w: address id detected track=%i sector=%i\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), track, sector)); LOG(( "%f $%04x mc6843_w: address id detected track=%i sector=%i\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), track, sector));
floppy_drive_format_sector( img, mc6843->side, sector, track, 0, sector, 0, filler ); floppy_drive_format_sector( img, mc6843->side, sector, track, 0, sector, 0, filler );
} }
else else
@ -670,7 +670,7 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
else else
{ {
/* XXX TODO: other write modes */ /* XXX TODO: other write modes */
logerror( "$%04x mc6843 write %02X in unsupported command mode %i (FWF=%i)\n", device->machine().firstcpu ->safe_pcbase( ), data, cmd, FWF ); logerror( "$%04x mc6843 write %02X in unsupported command mode %i (FWF=%i)\n", device->machine().firstcpu->pcbase( ), data, cmd, FWF );
} }
break; break;
} }
@ -678,7 +678,7 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
case 1: /* Current-Track Address Register (CTAR) */ case 1: /* Current-Track Address Register (CTAR) */
mc6843->CTAR = data & 0x7f; mc6843->CTAR = data & 0x7f;
LOG(( "%f $%04x mc6843_w: set CTAR to %i %02X (actual=%i) \n", LOG(( "%f $%04x mc6843_w: set CTAR to %i %02X (actual=%i) \n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->CTAR, data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->CTAR, data,
floppy_drive_get_current_track( mc6843_floppy_image( device ) ) )); floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
break; break;
@ -687,7 +687,7 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
int cmd = data & 15; int cmd = data & 15;
LOG(( "%f $%04x mc6843_w: set CMR to $%02X: cmd=%s(%i) FWF=%i DMA=%i ISR3-intr=%i fun-intr=%i\n", LOG(( "%f $%04x mc6843_w: set CMR to $%02X: cmd=%s(%i) FWF=%i DMA=%i ISR3-intr=%i fun-intr=%i\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
data, mc6843_cmd[cmd], cmd, (data >> 4) & 1, (data >> 5) & 1, data, mc6843_cmd[cmd], cmd, (data >> 4) & 1, (data >> 5) & 1,
(data >> 6) & 1, (data >> 7) & 1 )); (data >> 6) & 1, (data >> 7) & 1 ));
@ -734,36 +734,36 @@ WRITE8_DEVICE_HANDLER ( mc6843_w )
/* assume CLK freq = 1MHz (IBM 3740 compatibility) */ /* assume CLK freq = 1MHz (IBM 3740 compatibility) */
LOG(( "%f $%04x mc6843_w: set SUR to $%02X: head settling time=%fms, track-to-track seek time=%f\n", LOG(( "%f $%04x mc6843_w: set SUR to $%02X: head settling time=%fms, track-to-track seek time=%f\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), device->machine().firstcpu->pcbase( ),
data, 4.096 * (data & 15), 1.024 * ((data >> 4) & 15) )); data, 4.096 * (data & 15), 1.024 * ((data >> 4) & 15) ));
break; break;
case 4: /* Sector Address Register (SAR) */ case 4: /* Sector Address Register (SAR) */
mc6843->SAR = data & 0x1f; mc6843->SAR = data & 0x1f;
LOG(( "%f $%04x mc6843_w: set SAR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->SAR, data )); LOG(( "%f $%04x mc6843_w: set SAR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->SAR, data ));
break; break;
case 5: /* General Count Register (GCR) */ case 5: /* General Count Register (GCR) */
mc6843->GCR = data & 0x7f; mc6843->GCR = data & 0x7f;
LOG(( "%f $%04x mc6843_w: set GCR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->GCR, data )); LOG(( "%f $%04x mc6843_w: set GCR to %i (%02X)\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->GCR, data ));
break; break;
case 6: /* CRC Control Register (CCR) */ case 6: /* CRC Control Register (CCR) */
mc6843->CCR = data & 3; mc6843->CCR = data & 3;
LOG(( "%f $%04x mc6843_w: set CCR to %02X: CRC=%s shift=%i\n", LOG(( "%f $%04x mc6843_w: set CCR to %02X: CRC=%s shift=%i\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data,
(data & 1) ? "enabled" : "disabled", (data >> 1) & 1 )); (data & 1) ? "enabled" : "disabled", (data >> 1) & 1 ));
break; break;
case 7: /* Logical-Track Address Register (LTAR) */ case 7: /* Logical-Track Address Register (LTAR) */
mc6843->LTAR = data & 0x7f; mc6843->LTAR = data & 0x7f;
LOG(( "%f $%04x mc6843_w: set LTAR to %i %02X (actual=%i)\n", LOG(( "%f $%04x mc6843_w: set LTAR to %i %02X (actual=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6843->LTAR, data, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6843->LTAR, data,
floppy_drive_get_current_track( mc6843_floppy_image( device ) ) )); floppy_drive_get_current_track( mc6843_floppy_image( device ) ) ));
break; break;
default: default:
logerror( "$%04x mc6843 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), offset, data ); logerror( "$%04x mc6843 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu->pcbase( ), offset, data );
} }
} }

36
src/mess/machine/mc6846.c
View File

@ -267,7 +267,7 @@ READ8_DEVICE_HANDLER ( mc6846_r )
case 0: case 0:
case 4: case 4:
LOG (( "$%04x %f: mc6846 CSR read $%02X intr=%i (timer=%i, cp1=%i, cp2=%i)\n", LOG (( "$%04x %f: mc6846 CSR read $%02X intr=%i (timer=%i, cp1=%i, cp2=%i)\n",
device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), device->machine().time().as_double(),
mc6846->csr, (mc6846->csr >> 7) & 1, mc6846->csr, (mc6846->csr >> 7) & 1,
mc6846->csr & 1, (mc6846->csr >> 1) & 1, (mc6846->csr >> 2) & 1 )); mc6846->csr & 1, (mc6846->csr >> 1) & 1, (mc6846->csr >> 2) & 1 ));
mc6846->csr0_to_be_cleared = mc6846->csr & 1; mc6846->csr0_to_be_cleared = mc6846->csr & 1;
@ -276,15 +276,15 @@ READ8_DEVICE_HANDLER ( mc6846_r )
return mc6846->csr; return mc6846->csr;
case 1: case 1:
LOG (( "$%04x %f: mc6846 PCR read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->pcr )); LOG (( "$%04x %f: mc6846 PCR read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->pcr ));
return mc6846->pcr; return mc6846->pcr;
case 2: case 2:
LOG (( "$%04x %f: mc6846 DDR read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->ddr )); LOG (( "$%04x %f: mc6846 DDR read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->ddr ));
return mc6846->ddr; return mc6846->ddr;
case 3: case 3:
LOG (( "$%04x %f: mc6846 PORT read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), PORT )); LOG (( "$%04x %f: mc6846 PORT read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), PORT ));
if ( ! (mc6846->pcr & 0x80) ) if ( ! (mc6846->pcr & 0x80) )
{ {
if ( mc6846->csr1_to_be_cleared ) if ( mc6846->csr1_to_be_cleared )
@ -298,11 +298,11 @@ READ8_DEVICE_HANDLER ( mc6846_r )
return PORT; return PORT;
case 5: case 5:
LOG (( "$%04x %f: mc6846 TCR read $%02X\n",device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->tcr )); LOG (( "$%04x %f: mc6846 TCR read $%02X\n",device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->tcr ));
return mc6846->tcr; return mc6846->tcr;
case 6: case 6:
LOG (( "$%04x %f: mc6846 COUNTER hi read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) >> 8 )); LOG (( "$%04x %f: mc6846 COUNTER hi read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) >> 8 ));
if ( mc6846->csr0_to_be_cleared ) if ( mc6846->csr0_to_be_cleared )
{ {
mc6846->csr &= ~1; mc6846->csr &= ~1;
@ -312,7 +312,7 @@ READ8_DEVICE_HANDLER ( mc6846_r )
return mc6846_counter( device ) >> 8; return mc6846_counter( device ) >> 8;
case 7: case 7:
LOG (( "$%04x %f: mc6846 COUNTER low read $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) & 0xff )); LOG (( "$%04x %f: mc6846 COUNTER low read $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846_counter( device ) & 0xff ));
if ( mc6846->csr0_to_be_cleared ) if ( mc6846->csr0_to_be_cleared )
{ {
mc6846->csr &= ~1; mc6846->csr &= ~1;
@ -322,7 +322,7 @@ READ8_DEVICE_HANDLER ( mc6846_r )
return mc6846_counter( device ) & 0xff; return mc6846_counter( device ) & 0xff;
default: default:
logerror( "$%04x mc6846 invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset ); logerror( "$%04x mc6846 invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
} }
return 0; return 0;
} }
@ -353,7 +353,7 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
"latcged,pos-edge", "latcged,pos-edge,intr" "latcged,pos-edge", "latcged,pos-edge,intr"
}; };
LOG (( "$%04x %f: mc6846 PCR write $%02X reset=%i cp2=%s cp1=%s\n", LOG (( "$%04x %f: mc6846 PCR write $%02X reset=%i cp2=%s cp1=%s\n",
device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data, device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data,
(data >> 7) & 1, cp2[ (data >> 3) & 7 ], cp1[ data & 7 ] )); (data >> 7) & 1, cp2[ (data >> 3) & 7 ], cp1[ data & 7 ] ));
} }
@ -366,7 +366,7 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
mc6846_update_irq( device ); mc6846_update_irq( device );
} }
if ( data & 4 ) if ( data & 4 )
logerror( "$%04x mc6846 CP1 latching not implemented\n", device->machine().firstcpu ->safe_pcbase( ) ); logerror( "$%04x mc6846 CP1 latching not implemented\n", device->machine().firstcpu->pcbase( ) );
if (data & 0x20) if (data & 0x20)
{ {
if (data & 0x10) if (data & 0x10)
@ -376,12 +376,12 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
mc6846->iface->out_cp2_func( device, 0, mc6846->cp2_cpu ); mc6846->iface->out_cp2_func( device, 0, mc6846->cp2_cpu );
} }
else else
logerror( "$%04x mc6846 acknowledge not implemented\n", device->machine().firstcpu ->safe_pcbase( ) ); logerror( "$%04x mc6846 acknowledge not implemented\n", device->machine().firstcpu->pcbase( ) );
} }
break; break;
case 2: case 2:
LOG (( "$%04x %f: mc6846 DDR write $%02X\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data )); LOG (( "$%04x %f: mc6846 DDR write $%02X\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data ));
if ( ! (mc6846->pcr & 0x80) ) if ( ! (mc6846->pcr & 0x80) )
{ {
mc6846->ddr = data; mc6846->ddr = data;
@ -391,7 +391,7 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
break; break;
case 3: case 3:
LOG (( "$%04x %f: mc6846 PORT write $%02X (mask=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data,mc6846->ddr )); LOG (( "$%04x %f: mc6846 PORT write $%02X (mask=$%02X)\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data,mc6846->ddr ));
if ( ! (mc6846->pcr & 0x80) ) if ( ! (mc6846->pcr & 0x80) )
{ {
mc6846->pdr = data; mc6846->pdr = data;
@ -400,12 +400,12 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
if ( mc6846->csr1_to_be_cleared && (mc6846->csr & 2) ) if ( mc6846->csr1_to_be_cleared && (mc6846->csr & 2) )
{ {
mc6846->csr &= ~2; mc6846->csr &= ~2;
LOG (( "$%04x %f: mc6846 CP1 intr reset\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double() )); LOG (( "$%04x %f: mc6846 CP1 intr reset\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double() ));
} }
if ( mc6846->csr2_to_be_cleared && (mc6846->csr & 4) ) if ( mc6846->csr2_to_be_cleared && (mc6846->csr & 4) )
{ {
mc6846->csr &= ~4; mc6846->csr &= ~4;
LOG (( "$%04x %f: mc6846 CP2 intr reset\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double() )); LOG (( "$%04x %f: mc6846 CP2 intr reset\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double() ));
} }
mc6846->csr1_to_be_cleared = 0; mc6846->csr1_to_be_cleared = 0;
mc6846->csr2_to_be_cleared = 0; mc6846->csr2_to_be_cleared = 0;
@ -421,7 +421,7 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
"freq-cmp", "freq-cmp", "pulse-cmp", "pulse-cmp" "freq-cmp", "freq-cmp", "pulse-cmp", "pulse-cmp"
}; };
LOG (( "$%04x %f: mc6846 TCR write $%02X reset=%i clock=%s scale=%i mode=%s out=%s\n", LOG (( "$%04x %f: mc6846 TCR write $%02X reset=%i clock=%s scale=%i mode=%s out=%s\n",
device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), data, device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), data,
(data >> 7) & 1, (data & 0x40) ? "extern" : "sys", (data >> 7) & 1, (data & 0x40) ? "extern" : "sys",
(data & 0x40) ? 1 : 8, mode[ (data >> 1) & 7 ], (data & 0x40) ? 1 : 8, mode[ (data >> 1) & 7 ],
(data & 1) ? "enabled" : "0" )); (data & 1) ? "enabled" : "0" ));
@ -455,7 +455,7 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
case 7: case 7:
mc6846->latch = ( ((UINT16) mc6846->time_MSB) << 8 ) + data; mc6846->latch = ( ((UINT16) mc6846->time_MSB) << 8 ) + data;
LOG (( "$%04x %f: mc6846 COUNT write %i\n", device->machine().firstcpu ->safe_pcbase( ), device->machine().time().as_double(), mc6846->latch )); LOG (( "$%04x %f: mc6846 COUNT write %i\n", device->machine().firstcpu->pcbase( ), device->machine().time().as_double(), mc6846->latch ));
if (!(mc6846->tcr & 0x38)) if (!(mc6846->tcr & 0x38))
{ {
/* timer initialization */ /* timer initialization */
@ -471,7 +471,7 @@ WRITE8_DEVICE_HANDLER ( mc6846_w )
break; break;
default: default:
logerror( "$%04x mc6846 invalid write offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset ); logerror( "$%04x mc6846 invalid write offset %i\n", device->machine().firstcpu->pcbase( ), offset );
} }
} }

30
src/mess/machine/mc6854.c
View File

@ -808,7 +808,7 @@ READ8_DEVICE_HANDLER ( mc6854_r )
case 0: /* status register 1 */ case 0: /* status register 1 */
mc6854_update_sr1( mc6854 ); mc6854_update_sr1( mc6854 );
LOG(( "%f $%04x mc6854_r: get SR1=$%02X (rda=%i,s2rq=%i,fd=%i,cts=%i,tu=%i,tdra=%i,irq=%i)\n", LOG(( "%f $%04x mc6854_r: get SR1=$%02X (rda=%i,s2rq=%i,fd=%i,cts=%i,tu=%i,tdra=%i,irq=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->sr1, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->sr1,
( mc6854->sr1 & RDA) ? 1 : 0, ( mc6854->sr1 & S2RQ) ? 1 : 0, ( mc6854->sr1 & RDA) ? 1 : 0, ( mc6854->sr1 & S2RQ) ? 1 : 0,
( mc6854->sr1 & FD ) ? 1 : 0, ( mc6854->sr1 & CTS ) ? 1 : 0, ( mc6854->sr1 & FD ) ? 1 : 0, ( mc6854->sr1 & CTS ) ? 1 : 0,
( mc6854->sr1 & TU ) ? 1 : 0, ( mc6854->sr1 & TDRA) ? 1 : 0, ( mc6854->sr1 & TU ) ? 1 : 0, ( mc6854->sr1 & TDRA) ? 1 : 0,
@ -818,7 +818,7 @@ READ8_DEVICE_HANDLER ( mc6854_r )
case 1: /* status register 2 */ case 1: /* status register 2 */
mc6854_update_sr2( mc6854 ); mc6854_update_sr2( mc6854 );
LOG(( "%f $%04x mc6854_r: get SR2=$%02X (ap=%i,fv=%i,ridle=%i,rabt=%i,err=%i,dcd=%i,ovrn=%i,rda2=%i)\n", LOG(( "%f $%04x mc6854_r: get SR2=$%02X (ap=%i,fv=%i,ridle=%i,rabt=%i,err=%i,dcd=%i,ovrn=%i,rda2=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->sr2, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->sr2,
( mc6854->sr2 & AP ) ? 1 : 0, ( mc6854->sr2 & FV ) ? 1 : 0, ( mc6854->sr2 & AP ) ? 1 : 0, ( mc6854->sr2 & FV ) ? 1 : 0,
( mc6854->sr2 & RIDLE) ? 1 : 0, ( mc6854->sr2 & RABT) ? 1 : 0, ( mc6854->sr2 & RIDLE) ? 1 : 0, ( mc6854->sr2 & RABT) ? 1 : 0,
( mc6854->sr2 & ERR ) ? 1 : 0, ( mc6854->sr2 & DCD ) ? 1 : 0, ( mc6854->sr2 & ERR ) ? 1 : 0, ( mc6854->sr2 & DCD ) ? 1 : 0,
@ -830,12 +830,12 @@ READ8_DEVICE_HANDLER ( mc6854_r )
{ {
UINT8 data = mc6854_rfifo_pop( device ); UINT8 data = mc6854_rfifo_pop( device );
LOG(( "%f $%04x mc6854_r: get data $%02X\n", LOG(( "%f $%04x mc6854_r: get data $%02X\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data )); device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data ));
return data; return data;
} }
default: default:
logerror( "$%04x mc6854 invalid read offset %i\n", device->machine().firstcpu ->safe_pcbase( ), offset ); logerror( "$%04x mc6854 invalid read offset %i\n", device->machine().firstcpu->pcbase( ), offset );
} }
return 0; return 0;
} }
@ -851,7 +851,7 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
case 0: /* control register 1 */ case 0: /* control register 1 */
mc6854->cr1 = data; mc6854->cr1 = data;
LOG(( "%f $%04x mc6854_w: set CR1=$%02X (ac=%i,irq=%c%c,%sreset=%c%c)\n", LOG(( "%f $%04x mc6854_w: set CR1=$%02X (ac=%i,irq=%c%c,%sreset=%c%c)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr1, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr1,
AC ? 1 : 0, AC ? 1 : 0,
RIE ? 'r' : '-', TIE ? 't' : '-', RIE ? 'r' : '-', TIE ? 't' : '-',
DISCONTINUE ? "discontinue," : "", DISCONTINUE ? "discontinue," : "",
@ -859,7 +859,7 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
)); ));
if ( mc6854->cr1 & 0xc ) if ( mc6854->cr1 & 0xc )
logerror( "$%04x mc6854 DMA not handled (CR1=$%02X)\n", logerror( "$%04x mc6854 DMA not handled (CR1=$%02X)\n",
device->machine().firstcpu ->safe_pcbase( ), mc6854->cr1 ); device->machine().firstcpu->pcbase( ), mc6854->cr1 );
if ( DISCONTINUE ) if ( DISCONTINUE )
{ {
/* abort receive FIFO but keeps shift register & synchro */ /* abort receive FIFO but keeps shift register & synchro */
@ -888,15 +888,15 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
/* control register 3 */ /* control register 3 */
mc6854->cr3 = data; mc6854->cr3 = data;
LOG(( "%f $%04x mc6854_w: set CR3=$%02X (lcf=%i,aex=%i,idl=%i,fdse=%i,loop=%i,tst=%i,dtr=%i)\n", LOG(( "%f $%04x mc6854_w: set CR3=$%02X (lcf=%i,aex=%i,idl=%i,fdse=%i,loop=%i,tst=%i,dtr=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr3, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr3,
LCF ? (CEX ? 16 : 8) : 0, AEX ? 1 : 0, LCF ? (CEX ? 16 : 8) : 0, AEX ? 1 : 0,
IDL0 ? 0 : 1, FDSE ? 1 : 0, LOOP ? 1 : 0, IDL0 ? 0 : 1, FDSE ? 1 : 0, LOOP ? 1 : 0,
TST ? 1 : 0, DTR ? 1 : 0 TST ? 1 : 0, DTR ? 1 : 0
)); ));
if ( LOOP ) if ( LOOP )
logerror( "$%04x mc6854 loop mode not handled (CR3=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), mc6854->cr3 ); logerror( "$%04x mc6854 loop mode not handled (CR3=$%02X)\n", device->machine().firstcpu->pcbase( ), mc6854->cr3 );
if ( TST ) if ( TST )
logerror( "$%04x mc6854 test mode not handled (CR3=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), mc6854->cr3 ); logerror( "$%04x mc6854 test mode not handled (CR3=$%02X)\n", device->machine().firstcpu->pcbase( ), mc6854->cr3 );
mc6854->out_dtr_func( DTR ? 1 : 0 ); mc6854->out_dtr_func( DTR ? 1 : 0 );
@ -906,13 +906,13 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
/* control register 2 */ /* control register 2 */
mc6854->cr2 = data; mc6854->cr2 = data;
LOG(( "%f $%04x mc6854_w: set CR2=$%02X (pse=%i,bytes=%i,fmidle=%i,%s,tlast=%i,clr=%c%c,rts=%i)\n", LOG(( "%f $%04x mc6854_w: set CR2=$%02X (pse=%i,bytes=%i,fmidle=%i,%s,tlast=%i,clr=%c%c,rts=%i)\n",
device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr2, device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr2,
PSE ? 1 : 0, TWOBYTES ? 2 : 1, FMIDLE ? 1 : 0, PSE ? 1 : 0, TWOBYTES ? 2 : 1, FMIDLE ? 1 : 0,
FCTDRA ? "fc" : "tdra", TLAST ? 1 : 0, FCTDRA ? "fc" : "tdra", TLAST ? 1 : 0,
data & 0x20 ? 'r' : '-', data & 0x40 ? 't' : '-', data & 0x20 ? 'r' : '-', data & 0x40 ? 't' : '-',
RTS ? 1 : 0 )); RTS ? 1 : 0 ));
if ( PSE ) if ( PSE )
logerror( "$%04x mc6854 status prioritization not handled (CR2=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), mc6854->cr2 ); logerror( "$%04x mc6854 status prioritization not handled (CR2=$%02X)\n", device->machine().firstcpu->pcbase( ), mc6854->cr2 );
if ( TLAST ) if ( TLAST )
mc6854_tfifo_terminate( device ); mc6854_tfifo_terminate( device );
if ( data & 0x20 ) if ( data & 0x20 )
@ -936,7 +936,7 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
break; break;
case 2: /* transmitter data: continue data */ case 2: /* transmitter data: continue data */
LOG(( "%f $%04xmc6854_w: push data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data )); LOG(( "%f $%04xmc6854_w: push data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data ));
mc6854_tfifo_push( device, data ); mc6854_tfifo_push( device, data );
break; break;
@ -945,7 +945,7 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
{ {
/* control register 4 */ /* control register 4 */
mc6854->cr4 = data; mc6854->cr4 = data;
LOG(( "%f $%04x mc6854_w: set CR4=$%02X (interframe=%i,tlen=%i,rlen=%i,%s%s)\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), mc6854->cr4, LOG(( "%f $%04x mc6854_w: set CR4=$%02X (interframe=%i,tlen=%i,rlen=%i,%s%s)\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), mc6854->cr4,
TWOINTER ? 2 : 1, TWOINTER ? 2 : 1,
TWL, RWL, TWL, RWL,
ABT ? ( ABTEX ? "abort-ext," : "abort,") : "", ABT ? ( ABTEX ? "abort-ext," : "abort,") : "",
@ -960,14 +960,14 @@ WRITE8_DEVICE_HANDLER ( mc6854_w )
else else
{ {
/* transmitter data: last data */ /* transmitter data: last data */
LOG(( "%f $%04x mc6854_w: push last-data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu ->safe_pcbase( ), data )); LOG(( "%f $%04x mc6854_w: push last-data=$%02X\n", device->machine().time().as_double(), device->machine().firstcpu->pcbase( ), data ));
mc6854_tfifo_push( device, data ); mc6854_tfifo_push( device, data );
mc6854_tfifo_terminate( device ); mc6854_tfifo_terminate( device );
} }
break; break;
default: default:
logerror( "$%04x mc6854 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu ->safe_pcbase( ), offset, data ); logerror( "$%04x mc6854 invalid write offset %i (data=$%02X)\n", device->machine().firstcpu->pcbase( ), offset, data );
} }
} }

4
src/mess/machine/mos6530.c
View File

@ -227,7 +227,7 @@ WRITE8_DEVICE_HANDLER( mos6530_w )
if (!port->out_port_func.isnull()) if (!port->out_port_func.isnull())
port->out_port_func(0, data); port->out_port_func(0, data);
else else
logerror("6530MIOT chip %s: Port %c is being written to but has no handler. PC: %08X - %02X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->safe_pc(), data); logerror("6530MIOT chip %s: Port %c is being written to but has no handler. PC: %08X - %02X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->pc(), data);
} }
} }
} }
@ -289,7 +289,7 @@ READ8_DEVICE_HANDLER( mos6530_r )
port->in = port->in_port_func(0); port->in = port->in_port_func(0);
} }
else else
logerror("6530MIOT chip %s: Port %c is being read but has no handler. PC: %08X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->safe_pc()); logerror("6530MIOT chip %s: Port %c is being read but has no handler. PC: %08X\n", device->tag(), 'A' + (offset & 1), device->machine().firstcpu->pc());
/* apply the DDR to the result */ /* apply the DDR to the result */
val = (out & port->ddr) | (port->in & ~port->ddr); val = (out & port->ddr) | (port->in & ~port->ddr);

6
src/mess/machine/ncr5380.c
View File

@ -237,7 +237,7 @@ UINT8 ncr5380_device::ncr5380_read_reg(UINT32 offset)
} }
if (VERBOSE) if (VERBOSE)
logerror("NCR5380: read %s (reg %d) = %02x [PC=%x]\n", rnames[reg], reg, rv, machine().firstcpu->safe_pc()); logerror("NCR5380: read %s (reg %d) = %02x [PC=%x]\n", rnames[reg], reg, rv, machine().firstcpu->pc());
return rv; return rv;
} }
@ -247,7 +247,7 @@ void ncr5380_device::ncr5380_write_reg(UINT32 offset, UINT8 data)
int reg = offset & 7; int reg = offset & 7;
if (VERBOSE) if (VERBOSE)
logerror("NCR5380: %02x to %s (reg %d) [PC=%x]\n", data, wnames[reg], reg, machine().firstcpu->safe_pc()); logerror("NCR5380: %02x to %s (reg %d) [PC=%x]\n", data, wnames[reg], reg, machine().firstcpu->pc());
switch( reg ) switch( reg )
{ {
@ -334,7 +334,7 @@ void ncr5380_device::ncr5380_write_reg(UINT32 offset, UINT8 data)
if (get_cmd_len(m_5380_Command[0]) == m_cmd_ptr) if (get_cmd_len(m_5380_Command[0]) == m_cmd_ptr)
{ {
if (VERBOSE) if (VERBOSE)
logerror("NCR5380: Command (to ID %d): %x %x %x %x %x %x %x %x %x %x (PC %x)\n", m_last_id, m_5380_Command[0], m_5380_Command[1], m_5380_Command[2], m_5380_Command[3], m_5380_Command[4], m_5380_Command[5], m_5380_Command[6], m_5380_Command[7], m_5380_Command[8], m_5380_Command[9], machine().firstcpu->safe_pc()); logerror("NCR5380: Command (to ID %d): %x %x %x %x %x %x %x %x %x %x (PC %x)\n", m_last_id, m_5380_Command[0], m_5380_Command[1], m_5380_Command[2], m_5380_Command[3], m_5380_Command[4], m_5380_Command[5], m_5380_Command[6], m_5380_Command[7], m_5380_Command[8], m_5380_Command[9], machine().firstcpu->pc());
m_scsi_devices[m_last_id]->SetCommand(&m_5380_Command[0], 16); m_scsi_devices[m_last_id]->SetCommand(&m_5380_Command[0], 16);
m_scsi_devices[m_last_id]->ExecCommand(&m_d_limit); m_scsi_devices[m_last_id]->ExecCommand(&m_d_limit);

12
src/mess/machine/pokemini.c
View File

@ -409,7 +409,7 @@ WRITE8_DEVICE_HANDLER( pokemini_hwreg_w )
case 0x02: /* CPU related? case 0x02: /* CPU related?
Bit 0-7 R/W Unknown Bit 0-7 R/W Unknown
*/ */
logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data ); logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
break; break;
case 0x08: /* Seconds-timer control case 0x08: /* Seconds-timer control
Bit 0 R/W Timer enable Bit 0 R/W Timer enable
@ -441,7 +441,7 @@ WRITE8_DEVICE_HANDLER( pokemini_hwreg_w )
Bit 5 R Battery status: 0 - battery OK, 1 - battery low Bit 5 R Battery status: 0 - battery OK, 1 - battery low
Bit 6-7 Unused Bit 6-7 Unused
*/ */
logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data ); logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
break; break;
case 0x18: /* Timer 1 pre-scale + enable case 0x18: /* Timer 1 pre-scale + enable
Bit 0-2 R/W low timer 1 prescaler select Bit 0-2 R/W low timer 1 prescaler select
@ -956,7 +956,7 @@ WRITE8_DEVICE_HANDLER( pokemini_hwreg_w )
*/ */
case 0x35: /* Timer 1 sound-pivot (high, unused) case 0x35: /* Timer 1 sound-pivot (high, unused)
*/ */
logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data ); logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
break; break;
case 0x36: /* Timer 1 counter (low), read only case 0x36: /* Timer 1 counter (low), read only
*/ */
@ -1035,7 +1035,7 @@ WRITE8_DEVICE_HANDLER( pokemini_hwreg_w )
*/ */
case 0x3D: /* Timer 2 sound-pivot (high, unused) case 0x3D: /* Timer 2 sound-pivot (high, unused)
*/ */
logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data ); logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
break; break;
case 0x3E: /* Timer 2 counter (low), read only case 0x3E: /* Timer 2 counter (low), read only
Bit 0-7 R/W Timer 2 counter value bit 0-7 Bit 0-7 R/W Timer 2 counter value bit 0-7
@ -1300,7 +1300,7 @@ WRITE8_DEVICE_HANDLER( pokemini_hwreg_w )
Map size 2: 0x00 to 0x60 Map size 2: 0x00 to 0x60
Bit 7 Unused Bit 7 Unused
*/ */
logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data ); logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
break; break;
case 0x87: /* Sprite tile data memory offset (low) case 0x87: /* Sprite tile data memory offset (low)
Bit 0-5 Always "0" Bit 0-5 Always "0"
@ -1341,7 +1341,7 @@ WRITE8_DEVICE_HANDLER( pokemini_hwreg_w )
// lcd_data_w( data ); // lcd_data_w( data );
break; break;
default: default:
logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu ->safe_pc( ), offset, data ); logerror( "%0X: Write to unknown hardware address: %02X, %02X\n", device->machine().firstcpu->pc( ), offset, data );
break; break;
} }
state->m_pm_reg[offset] = data; state->m_pm_reg[offset] = data;

2
src/mess/video/crtc_ega.c
View File

@ -80,7 +80,7 @@ READ8_MEMBER( crtc_ega_device::register_r )
WRITE8_MEMBER( crtc_ega_device::register_w ) WRITE8_MEMBER( crtc_ega_device::register_w )
{ {
if (LOG) logerror("CRTC_EGA PC %04x: reg 0x%02x = 0x%02x\n", machine().firstcpu->safe_pc(), m_register_address_latch, data); if (LOG) logerror("CRTC_EGA PC %04x: reg 0x%02x = 0x%02x\n", machine().firstcpu->pc(), m_register_address_latch, data);
switch (m_register_address_latch) switch (m_register_address_latch)
{ {