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Disable SOUND_DEBUG for non-debug builds, and srcclean

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This commit is contained in:
Vas Crabb 2020-09-27 11:00:56 +10:00
parent 7dad0f4f58
commit 6e807013c5
70 changed files with 596 additions and 592 deletions
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2
hash/fmtowns_cd.xml
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@ -9692,7 +9692,7 @@ User/save disks that can be created from the game itself are not included.
<info name="usage" value="Requires 2 MB RAM"/>
<part name="flop1" interface="floppy_3_5">
<dataarea name="flop" size="1261568">
<!--
<!--
This image has been reconstructed manually by creating empty files with the names that the game expects and re-initializing them with the in-game option.
It's enough to make the game work, but it should be replaced with an actual dump of the original disk.
-->

2
plugins/cheat/init.lua
View File

@ -944,7 +944,7 @@ function cheat.startplugin()
end
end
end
return intf
return intf
end
function ce.list()

2
scripts/src/netlist.lua
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@ -32,7 +32,7 @@ project "netlist"
}
includedirs {
-- MAME_DIR .. "src/lib",
-- MAME_DIR .. "src/lib",
MAME_DIR .. "src/lib/netlist",
}

2
src/devices/cpu/unsp/unspdasm_extended.cpp
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@ -147,7 +147,7 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of
uint8_t rb = (ximm & 0x000f) >> 0;
uint8_t size = (ximm & 0x7000) >> 12;
uint8_t rx = (ximm & 0x0e00) >> 9;
if (size == 0) size = 8;
int start = (rx + 1)&7;

2
src/devices/machine/alpha_8921.h
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@ -2,7 +2,7 @@
// copyright-holders:cam900
/***************************************************************************
Alpha denshi ALPHA-8921 emulation
Alpha denshi ALPHA-8921 emulation
***************************************************************************/

2
src/devices/machine/bl_handhelds_menucontrol.h
View File

@ -33,7 +33,7 @@ private:
// internal state
uint16_t m_menupos;
// command handling
uint8_t m_clockstate;
uint8_t m_datashifterpos;

418
src/devices/machine/cs8900a.cpp
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@ -4,11 +4,11 @@
/*************************************************************************
CS8900A ethernet controller implementation
CS8900A ethernet controller implementation
by Rhett Aultman <roadriverrail@gmail.com>
ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/)
VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de>
by Rhett Aultman <roadriverrail@gmail.com>
ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/)
VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de>
**************************************************************************/
@ -20,17 +20,17 @@
DEFINE_DEVICE_TYPE(CS8900A, cs8900a_device, "cs8900a", "CS8900A Crystal LAN 10Base-T Ethernet MAC")
/* warn illegal behaviour */
#define CS8900_DEBUG_WARN_REG (1 << 1U) /* warn about invalid register accesses */
#define CS8900_DEBUG_WARN_RXTX (1 << 2U) /* warn about invalid rx or tx conditions */
#define CS8900_DEBUG_WARN_REG (1 << 1U) /* warn about invalid register accesses */
#define CS8900_DEBUG_WARN_RXTX (1 << 2U) /* warn about invalid rx or tx conditions */
#define CS8900_DEBUG (1 << 3U) /* enable to see port reads */
#define CS8900_DEBUG (1 << 3U) /* enable to see port reads */
#define CS8900_DEBUG_INIT (1 << 4U)
#define CS8900_DEBUG_LOAD (1 << 5U) /* enable to see port reads */
#define CS8900_DEBUG_STORE (1 << 6U) /* enable to see port writes */
#define CS8900_DEBUG_REGISTERS (1 << 7U) /* enable to see CS8900a register I/O */
#define CS8900_DEBUG_RXTX_STATE (1 << 8U) /* enable to see tranceiver state changes */
#define CS8900_DEBUG_RXTX_DATA (1 << 9U) /* enable to see data in/out flow */
#define CS8900_DEBUG_FRAMES (1 << 10U) /* enable to see arch frame send/recv */
#define CS8900_DEBUG_LOAD (1 << 5U) /* enable to see port reads */
#define CS8900_DEBUG_STORE (1 << 6U) /* enable to see port writes */
#define CS8900_DEBUG_REGISTERS (1 << 7U) /* enable to see CS8900a register I/O */
#define CS8900_DEBUG_RXTX_STATE (1 << 8U) /* enable to see tranceiver state changes */
#define CS8900_DEBUG_RXTX_DATA (1 << 9U) /* enable to see data in/out flow */
#define CS8900_DEBUG_FRAMES (1 << 10U) /* enable to see arch frame send/recv */
/** #define CS8900_DEBUG_IGNORE_RXEVENT 1 **/ /* enable to ignore RXEVENT in DEBUG_REGISTERS */
#define VERBOSE 0
@ -41,57 +41,57 @@ DEFINE_DEVICE_TYPE(CS8900A, cs8900a_device, "cs8900a", "CS8900A Crystal LAN 10Ba
/* CS8900 registers */
/* these are the 8 16-bit-ports for "I/O space configuration"
(see 4.10 on page 75 of cs8900a-4.pdf, the cs8900a data sheet)
/* these are the 8 16-bit-ports for "I/O space configuration"
(see 4.10 on page 75 of cs8900a-4.pdf, the cs8900a data sheet)
REMARK: The code operatoes the cs8900a in IO space configuration, as
it generates I/OW and I/OR signals.
REMARK: The code operatoes the cs8900a in IO space configuration, as
it generates I/OW and I/OR signals.
*/
/*
RW: RXTXDATA = DE00/DE01
RW: RXTXDATA2 = DE02/DE03 (for 32-bit-operation)
-W: TXCMD = DE04/DE05 (TxCMD, Transmit Command) mapped to PP + 0144 (Reg. 9, Sec. 4.4, page 46)
-W: TXLENGTH = DE06/DE07 (TxLenght, Transmit Length) mapped to PP + 0146
R-: INTSTQUEUE = DE08/DE09 (Interrupt Status Queue) mapped to PP + 0120 (ISQ, Sec. 5.1, page 78)
RW: PP_PTR = DE0A/DE0B (PacketPage Pointer) (see. page 75p: Read -011.---- ----.----)
RW: PP_DATA0 = DE0C/DE0D (PacketPage Data (Port 0))
RW: PP_DATA1 = DE0E/DE0F (PacketPage Data (Port 1)) (for 32 bit only)
RW: RXTXDATA = DE00/DE01
RW: RXTXDATA2 = DE02/DE03 (for 32-bit-operation)
-W: TXCMD = DE04/DE05 (TxCMD, Transmit Command) mapped to PP + 0144 (Reg. 9, Sec. 4.4, page 46)
-W: TXLENGTH = DE06/DE07 (TxLenght, Transmit Length) mapped to PP + 0146
R-: INTSTQUEUE = DE08/DE09 (Interrupt Status Queue) mapped to PP + 0120 (ISQ, Sec. 5.1, page 78)
RW: PP_PTR = DE0A/DE0B (PacketPage Pointer) (see. page 75p: Read -011.---- ----.----)
RW: PP_DATA0 = DE0C/DE0D (PacketPage Data (Port 0))
RW: PP_DATA1 = DE0E/DE0F (PacketPage Data (Port 1)) (for 32 bit only)
*/
enum io_space_conf_regs_e : u8 {
CS8900_ADDR_RXTXDATA = 0x00, /* RW */
CS8900_ADDR_RXTXDATA2 = 0x02, /* RW 32 bit only! */
CS8900_ADDR_TXCMD = 0x04, /* -W Maps to PP+0144 */
CS8900_ADDR_TXLENGTH = 0x06, /* -W Maps to PP+0146 */
CS8900_ADDR_INTSTQUEUE = 0x08, /* R- Interrupt status queue, maps to PP + 0120 */
CS8900_ADDR_PP_PTR = 0x0a, /* RW PacketPage Pointer */
CS8900_ADDR_PP_DATA = 0x0c, /* RW PacketPage Data, Port 0 */
CS8900_ADDR_PP_DATA2 = 0x0e /* RW PacketPage Data, Port 1 - 32 bit only */
CS8900_ADDR_RXTXDATA = 0x00, /* RW */
CS8900_ADDR_RXTXDATA2 = 0x02, /* RW 32 bit only! */
CS8900_ADDR_TXCMD = 0x04, /* -W Maps to PP+0144 */
CS8900_ADDR_TXLENGTH = 0x06, /* -W Maps to PP+0146 */
CS8900_ADDR_INTSTQUEUE = 0x08, /* R- Interrupt status queue, maps to PP + 0120 */
CS8900_ADDR_PP_PTR = 0x0a, /* RW PacketPage Pointer */
CS8900_ADDR_PP_DATA = 0x0c, /* RW PacketPage Data, Port 0 */
CS8900_ADDR_PP_DATA2 = 0x0e /* RW PacketPage Data, Port 1 - 32 bit only */
};
/* Makros for reading and writing the visible register: */
#define GET_CS8900_8(_xxx_) \
(assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \
cs8900_ioregs[_xxx_] \
#define GET_CS8900_8(_xxx_) \
(assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \
cs8900_ioregs[_xxx_] \
)
#define SET_CS8900_8(_xxx_, _val_) \
do { \
assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \
cs8900_ioregs[_xxx_] = (_val_) & 0xff; \
#define SET_CS8900_8(_xxx_, _val_) \
do { \
assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \
cs8900_ioregs[_xxx_] = (_val_) & 0xff; \
} while (0)
#define GET_CS8900_16(_xxx_) \
(assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \
cs8900_ioregs[_xxx_] | (cs8900_ioregs[_xxx_ + 1] << 8) \
#define GET_CS8900_16(_xxx_) \
(assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \
cs8900_ioregs[_xxx_] | (cs8900_ioregs[_xxx_ + 1] << 8) \
)
#define SET_CS8900_16(_xxx_, _val_) \
do { \
assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \
cs8900_ioregs[_xxx_] = (_val_) & 0xff; \
cs8900_ioregs[_xxx_ + 1] = (_val_ >> 8) & 0xff; \
#define SET_CS8900_16(_xxx_, _val_) \
do { \
assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \
cs8900_ioregs[_xxx_] = (_val_) & 0xff; \
cs8900_ioregs[_xxx_ + 1] = (_val_ >> 8) & 0xff; \
} while (0)
/* The PacketPage register */
@ -99,106 +99,106 @@ enum io_space_conf_regs_e : u8 {
/* Macros for reading and writing the PacketPage register: */
#define GET_PP_8(_xxx_) \
(assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \
cs8900_packetpage[_xxx_] \
#define GET_PP_8(_xxx_) \
(assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \
cs8900_packetpage[_xxx_] \
)
#define GET_PP_16(_xxx_) \
(assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \
assert((_xxx_ & 1) == 0), \
((u16)cs8900_packetpage[_xxx_]) \
|((u16)cs8900_packetpage[_xxx_ + 1] << 8) \
#define GET_PP_16(_xxx_) \
(assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \
assert((_xxx_ & 1) == 0), \
((u16)cs8900_packetpage[_xxx_]) \
|((u16)cs8900_packetpage[_xxx_ + 1] << 8) \
)
#define GET_PP_32(_xxx_) \
(assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \
assert((_xxx_ & 3) == 0), \
(((u32)cs8900_packetpage[_xxx_])) \
|(((u32)cs8900_packetpage[_xxx_ + 1]) << 8) \
|(((u32)cs8900_packetpage[_xxx_ + 2]) << 16) \
|(((u32)cs8900_packetpage[_xxx_ + 3]) << 24) \
#define GET_PP_32(_xxx_) \
(assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \
assert((_xxx_ & 3) == 0), \
(((u32)cs8900_packetpage[_xxx_])) \
|(((u32)cs8900_packetpage[_xxx_ + 1]) << 8) \
|(((u32)cs8900_packetpage[_xxx_ + 2]) << 16) \
|(((u32)cs8900_packetpage[_xxx_ + 3]) << 24) \
)
#define SET_PP_8(_xxx_, _val_) \
do { \
assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \
cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \
#define SET_PP_8(_xxx_, _val_) \
do { \
assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \
cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \
} while (0)
#define SET_PP_16(_xxx_, _val_) \
do { \
assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \
assert((_xxx_ & 1) == 0), \
cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \
cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \
#define SET_PP_16(_xxx_, _val_) \
do { \
assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \
assert((_xxx_ & 1) == 0), \
cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \
cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \
} while (0)
#define SET_PP_32(_xxx_, _val_) \
do { \
assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \
assert((_xxx_ & 3) == 0), \
cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \
cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \
cs8900_packetpage[_xxx_ + 2] = (_val_ >> 16) & 0xFF; \
cs8900_packetpage[_xxx_ + 3] = (_val_ >> 24) & 0xFF; \
#define SET_PP_32(_xxx_, _val_) \
do { \
assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \
assert((_xxx_ & 3) == 0), \
cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \
cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \
cs8900_packetpage[_xxx_ + 2] = (_val_ >> 16) & 0xFF; \
cs8900_packetpage[_xxx_ + 3] = (_val_ >> 24) & 0xFF; \
} while (0)
enum packetpage_regs_e : u16 {
/* The packetpage register: see p. 39f */
CS8900_PP_ADDR_PRODUCTID = 0x0000, /* R- - 4.3., p. 41 */
CS8900_PP_ADDR_IOBASE = 0x0020, /* i RW - 4.3., p. 41 - 4.7., p. 72 */
CS8900_PP_ADDR_INTNO = 0x0022, /* i RW - 3.2., p. 17 - 4.3., p. 41 */
CS8900_PP_ADDR_DMA_CHAN = 0x0024, /* i RW - 3.2., p. 17 - 4.3., p. 41 */
CS8900_PP_ADDR_DMA_SOF = 0x0026, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */
CS8900_PP_ADDR_DMA_FC = 0x0028, /* ? R- - 4.3., p. 41, "Receive DMA" */
CS8900_PP_ADDR_RXDMA_BC = 0x002a, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */
CS8900_PP_ADDR_MEMBASE = 0x002c, /* i RW - 4.3., p. 41 - 4.9., p. 73 */
CS8900_PP_ADDR_BPROM_BASE = 0x0030, /* i RW - 3.6., p. 24 - 4.3., p. 41 */
CS8900_PP_ADDR_BPROM_MASK = 0x0034, /* i RW - 3.6., p. 24 - 4.3., p. 41 */
CS8900_PP_ADDR_PRODUCTID = 0x0000, /* R- - 4.3., p. 41 */
CS8900_PP_ADDR_IOBASE = 0x0020, /* i RW - 4.3., p. 41 - 4.7., p. 72 */
CS8900_PP_ADDR_INTNO = 0x0022, /* i RW - 3.2., p. 17 - 4.3., p. 41 */
CS8900_PP_ADDR_DMA_CHAN = 0x0024, /* i RW - 3.2., p. 17 - 4.3., p. 41 */
CS8900_PP_ADDR_DMA_SOF = 0x0026, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */
CS8900_PP_ADDR_DMA_FC = 0x0028, /* ? R- - 4.3., p. 41, "Receive DMA" */
CS8900_PP_ADDR_RXDMA_BC = 0x002a, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */
CS8900_PP_ADDR_MEMBASE = 0x002c, /* i RW - 4.3., p. 41 - 4.9., p. 73 */
CS8900_PP_ADDR_BPROM_BASE = 0x0030, /* i RW - 3.6., p. 24 - 4.3., p. 41 */
CS8900_PP_ADDR_BPROM_MASK = 0x0034, /* i RW - 3.6., p. 24 - 4.3., p. 41 */
/* 0x0038 - 0x003F: reserved */
CS8900_PP_ADDR_EEPROM_CMD = 0x0040, /* i RW - 3.5., p. 23 - 4.3., p. 41 */
CS8900_PP_ADDR_EEPROM_DATA = 0x0042, /* i RW - 3.5., p. 23 - 4.3., p. 41 */
CS8900_PP_ADDR_EEPROM_CMD = 0x0040, /* i RW - 3.5., p. 23 - 4.3., p. 41 */
CS8900_PP_ADDR_EEPROM_DATA = 0x0042, /* i RW - 3.5., p. 23 - 4.3., p. 41 */
/* 0x0044 - 0x004F: reserved */
CS8900_PP_ADDR_REC_FRAME_BC = 0x0050, /* RW - 4.3., p. 41 - 5.2.9., p. 86 */
CS8900_PP_ADDR_REC_FRAME_BC = 0x0050, /* RW - 4.3., p. 41 - 5.2.9., p. 86 */
/* 0x0052 - 0x00FF: reserved */
CS8900_PP_ADDR_CONF_CTRL = 0x0100, /* - RW - 4.4., p. 46; see below */
CS8900_PP_ADDR_STATUS_EVENT = 0x0120, /* - R- - 4.4., p. 46; see below */
CS8900_PP_ADDR_CONF_CTRL = 0x0100, /* - RW - 4.4., p. 46; see below */
CS8900_PP_ADDR_STATUS_EVENT = 0x0120, /* - R- - 4.4., p. 46; see below */
/* 0x0140 - 0x0143: reserved */
CS8900_PP_ADDR_TXCMD = 0x0144, /* # -W - 4.5., p. 70 - 5.7., p. 98 */
CS8900_PP_ADDR_TXLENGTH = 0x0146, /* # -W - 4.5., p. 70 - 5.7., p. 98 */
CS8900_PP_ADDR_TXCMD = 0x0144, /* # -W - 4.5., p. 70 - 5.7., p. 98 */
CS8900_PP_ADDR_TXLENGTH = 0x0146, /* # -W - 4.5., p. 70 - 5.7., p. 98 */
/* 0x0148 - 0x014F: reserved */
CS8900_PP_ADDR_LOG_ADDR_FILTER = 0x0150, /* RW - 4.6., p. 71 - 5.3., p. 86 */
CS8900_PP_ADDR_MAC_ADDR = 0x0158, /* # RW - 4.6., p. 71 - 5.3., p. 86 */
CS8900_PP_ADDR_LOG_ADDR_FILTER = 0x0150, /* RW - 4.6., p. 71 - 5.3., p. 86 */
CS8900_PP_ADDR_MAC_ADDR = 0x0158, /* # RW - 4.6., p. 71 - 5.3., p. 86 */
/* 0x015E - 0x03FF: reserved */
CS8900_PP_ADDR_RXSTATUS = 0x0400, /* R- - 4.7., p. 72 - 5.2., p. 78 */
CS8900_PP_ADDR_RXLENGTH = 0x0402, /* R- - 4.7., p. 72 - 5.2., p. 78 */
CS8900_PP_ADDR_RX_FRAMELOC = 0x0404, /* R- - 4.7., p. 72 - 5.2., p. 78 */
CS8900_PP_ADDR_RXSTATUS = 0x0400, /* R- - 4.7., p. 72 - 5.2., p. 78 */
CS8900_PP_ADDR_RXLENGTH = 0x0402, /* R- - 4.7., p. 72 - 5.2., p. 78 */
CS8900_PP_ADDR_RX_FRAMELOC = 0x0404, /* R- - 4.7., p. 72 - 5.2., p. 78 */
/* here, the received frame is stored */
CS8900_PP_ADDR_TX_FRAMELOC = 0x0A00, /* -W - 4.7., p. 72 - 5.7., p. 98 */
CS8900_PP_ADDR_TX_FRAMELOC = 0x0A00, /* -W - 4.7., p. 72 - 5.7., p. 98 */
/* here, the frame to transmit is stored */
CS8900_PP_ADDR_END = 0x1000, /* memory to CS8900_PP_ADDR_END-1 is used */
CS8900_PP_ADDR_END = 0x1000, /* memory to CS8900_PP_ADDR_END-1 is used */
/* CS8900_PP_ADDR_CONF_CTRL is subdivided: */
CS8900_PP_ADDR_CC_RXCFG = 0x0102, /* # RW - 4.4.6., p. 52 - 0003 */
CS8900_PP_ADDR_CC_RXCTL = 0x0104, /* # RW - 4.4.8., p. 54 - 0005 */
CS8900_PP_ADDR_CC_TXCFG = 0x0106, /* RW - 4.4.9., p. 55 - 0007 */
CS8900_PP_ADDR_CC_TXCMD = 0x0108, /* R- - 4.4.11., p. 57 - 0009 */
CS8900_PP_ADDR_CC_BUFCFG = 0x010A, /* RW - 4.4.12., p. 58 - 000B */
CS8900_PP_ADDR_CC_LINECTL = 0x0112, /* # RW - 4.4.16., p. 62 - 0013 */
CS8900_PP_ADDR_CC_SELFCTL = 0x0114, /* RW - 4.4.18., p. 64 - 0015 */
CS8900_PP_ADDR_CC_BUSCTL = 0x0116, /* RW - 4.4.20., p. 66 - 0017 */
CS8900_PP_ADDR_CC_TESTCTL = 0x0118, /* RW - 4.4.22., p. 68 - 0019 */
CS8900_PP_ADDR_CC_RXCFG = 0x0102, /* # RW - 4.4.6., p. 52 - 0003 */
CS8900_PP_ADDR_CC_RXCTL = 0x0104, /* # RW - 4.4.8., p. 54 - 0005 */
CS8900_PP_ADDR_CC_TXCFG = 0x0106, /* RW - 4.4.9., p. 55 - 0007 */
CS8900_PP_ADDR_CC_TXCMD = 0x0108, /* R- - 4.4.11., p. 57 - 0009 */
CS8900_PP_ADDR_CC_BUFCFG = 0x010A, /* RW - 4.4.12., p. 58 - 000B */
CS8900_PP_ADDR_CC_LINECTL = 0x0112, /* # RW - 4.4.16., p. 62 - 0013 */
CS8900_PP_ADDR_CC_SELFCTL = 0x0114, /* RW - 4.4.18., p. 64 - 0015 */
CS8900_PP_ADDR_CC_BUSCTL = 0x0116, /* RW - 4.4.20., p. 66 - 0017 */
CS8900_PP_ADDR_CC_TESTCTL = 0x0118, /* RW - 4.4.22., p. 68 - 0019 */
/* CS8900_PP_ADDR_STATUS_EVENT is subdivided: */
CS8900_PP_ADDR_SE_ISQ = 0x0120, /* R- - 4.4.5., p. 51 - 0000 */
CS8900_PP_ADDR_SE_RXEVENT = 0x0124, /* # R- - 4.4.7., p. 53 - 0004 */
CS8900_PP_ADDR_SE_TXEVENT = 0x0128, /* R- - 4.4.10., p. 56 - 0008 */
CS8900_PP_ADDR_SE_BUFEVENT = 0x012C, /* R- - 4.4.13., p. 59 - 000C */
CS8900_PP_ADDR_SE_RXMISS = 0x0130, /* R- - 4.4.14., p. 60 - 0010 */
CS8900_PP_ADDR_SE_TXCOL = 0x0132, /* R- - 4.4.15., p. 61 - 0012 */
CS8900_PP_ADDR_SE_LINEST = 0x0134, /* R- - 4.4.17., p. 63 - 0014 */
CS8900_PP_ADDR_SE_SELFST = 0x0136, /* R- - 4.4.19., p. 65 - 0016 */
CS8900_PP_ADDR_SE_BUSST = 0x0138, /* # R- - 4.4.21., p. 67 - 0018 */
CS8900_PP_ADDR_SE_TDR = 0x013C /* R- - 4.4.23., p. 69 - 001C */
CS8900_PP_ADDR_SE_ISQ = 0x0120, /* R- - 4.4.5., p. 51 - 0000 */
CS8900_PP_ADDR_SE_RXEVENT = 0x0124, /* # R- - 4.4.7., p. 53 - 0004 */
CS8900_PP_ADDR_SE_TXEVENT = 0x0128, /* R- - 4.4.10., p. 56 - 0008 */
CS8900_PP_ADDR_SE_BUFEVENT = 0x012C, /* R- - 4.4.13., p. 59 - 000C */
CS8900_PP_ADDR_SE_RXMISS = 0x0130, /* R- - 4.4.14., p. 60 - 0010 */
CS8900_PP_ADDR_SE_TXCOL = 0x0132, /* R- - 4.4.15., p. 61 - 0012 */
CS8900_PP_ADDR_SE_LINEST = 0x0134, /* R- - 4.4.17., p. 63 - 0014 */
CS8900_PP_ADDR_SE_SELFST = 0x0136, /* R- - 4.4.19., p. 65 - 0016 */
CS8900_PP_ADDR_SE_BUSST = 0x0138, /* # R- - 4.4.21., p. 67 - 0018 */
CS8900_PP_ADDR_SE_TDR = 0x013C /* R- - 4.4.23., p. 69 - 001C */
};
enum tx_rx_min_max_e : u16 {
@ -209,21 +209,21 @@ enum tx_rx_min_max_e : u16 {
};
enum cs8900_tx_state_e : u8 {
CS8900_TX_IDLE = 0,
CS8900_TX_GOT_CMD = 1,
CS8900_TX_GOT_LEN = 2,
CS8900_TX_READ_BUSST = 3
CS8900_TX_IDLE = 0,
CS8900_TX_GOT_CMD = 1,
CS8900_TX_GOT_LEN = 2,
CS8900_TX_READ_BUSST = 3
};
enum cs8900_rx_state_e : u8 {
CS8900_RX_IDLE = 0,
CS8900_RX_GOT_FRAME = 1
CS8900_RX_IDLE = 0,
CS8900_RX_GOT_FRAME = 1
};
enum pp_ptr_masks_e : u16 {
PP_PTR_AUTO_INCR_FLAG = 0x8000, /* auto increment flag in package pointer */
PP_PTR_FLAG_MASK = 0xf000, /* is always : x y 1 1 (with x=auto incr) */
PP_PTR_ADDR_MASK = 0x0fff /* address portion of packet page pointer */
PP_PTR_AUTO_INCR_FLAG = 0x8000, /* auto increment flag in package pointer */
PP_PTR_FLAG_MASK = 0xf000, /* is always : x y 1 1 (with x=auto incr) */
PP_PTR_ADDR_MASK = 0x0fff /* address portion of packet page pointer */
};
#define LO_BYTE(x) (u8)((x)& 0xff)
@ -255,10 +255,10 @@ void cs8900a_device::cs8900_set_tx_status(int ready, int error)
u16 new_status = old_status & ~0x180;
if (ready)
new_status |= 0x100; /* set Rdy4TxNOW */
new_status |= 0x100; /* set Rdy4TxNOW */
if (error)
new_status |= 0x080; /* set TxBidErr */
new_status |= 0x080; /* set TxBidErr */
if (new_status != old_status)
{
@ -301,39 +301,39 @@ void cs8900a_device::device_reset()
SET_PP_16(CS8900_PP_ADDR_DMA_CHAN, 0x0003); /* xxxx xxxx xxxx xx11b */
/* according to descriptions of the registers, see definitions of
CS8900_PP_ADDR_CC_... and CS8900_PP_ADDR_SE_... above! */
CS8900_PP_ADDR_CC_... and CS8900_PP_ADDR_SE_... above! */
SET_PP_16(CS8900_PP_ADDR_CC_RXCFG, 0x0003);
SET_PP_16(CS8900_PP_ADDR_CC_RXCTL, 0x0005);
SET_PP_16(CS8900_PP_ADDR_CC_TXCFG, 0x0007);
SET_PP_16(CS8900_PP_ADDR_CC_TXCMD, 0x0009);
SET_PP_16(CS8900_PP_ADDR_CC_BUFCFG, 0x000B);
SET_PP_16(CS8900_PP_ADDR_CC_LINECTL, 0x0013);
SET_PP_16(CS8900_PP_ADDR_CC_SELFCTL, 0x0015);
SET_PP_16(CS8900_PP_ADDR_CC_BUSCTL, 0x0017);
SET_PP_16(CS8900_PP_ADDR_CC_TESTCTL, 0x0019);
SET_PP_16(CS8900_PP_ADDR_CC_RXCFG, 0x0003);
SET_PP_16(CS8900_PP_ADDR_CC_RXCTL, 0x0005);
SET_PP_16(CS8900_PP_ADDR_CC_TXCFG, 0x0007);
SET_PP_16(CS8900_PP_ADDR_CC_TXCMD, 0x0009);
SET_PP_16(CS8900_PP_ADDR_CC_BUFCFG, 0x000B);
SET_PP_16(CS8900_PP_ADDR_CC_LINECTL, 0x0013);
SET_PP_16(CS8900_PP_ADDR_CC_SELFCTL, 0x0015);
SET_PP_16(CS8900_PP_ADDR_CC_BUSCTL, 0x0017);
SET_PP_16(CS8900_PP_ADDR_CC_TESTCTL, 0x0019);
SET_PP_16(CS8900_PP_ADDR_SE_ISQ, 0x0000);
SET_PP_16(CS8900_PP_ADDR_SE_RXEVENT, 0x0004);
SET_PP_16(CS8900_PP_ADDR_SE_TXEVENT, 0x0008);
SET_PP_16(CS8900_PP_ADDR_SE_BUFEVENT, 0x000C);
SET_PP_16(CS8900_PP_ADDR_SE_RXMISS, 0x0010);
SET_PP_16(CS8900_PP_ADDR_SE_TXCOL, 0x0012);
SET_PP_16(CS8900_PP_ADDR_SE_LINEST, 0x0014);
SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0016);
SET_PP_16(CS8900_PP_ADDR_SE_BUSST, 0x0018);
SET_PP_16(CS8900_PP_ADDR_SE_TDR, 0x001C);
SET_PP_16(CS8900_PP_ADDR_SE_ISQ, 0x0000);
SET_PP_16(CS8900_PP_ADDR_SE_RXEVENT, 0x0004);
SET_PP_16(CS8900_PP_ADDR_SE_TXEVENT, 0x0008);
SET_PP_16(CS8900_PP_ADDR_SE_BUFEVENT, 0x000C);
SET_PP_16(CS8900_PP_ADDR_SE_RXMISS, 0x0010);
SET_PP_16(CS8900_PP_ADDR_SE_TXCOL, 0x0012);
SET_PP_16(CS8900_PP_ADDR_SE_LINEST, 0x0014);
SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0016);
SET_PP_16(CS8900_PP_ADDR_SE_BUSST, 0x0018);
SET_PP_16(CS8900_PP_ADDR_SE_TDR, 0x001C);
SET_PP_16(CS8900_PP_ADDR_TXCMD, 0x0009);
SET_PP_16(CS8900_PP_ADDR_TXCMD, 0x0009);
/* 4.4.19 Self Status Register, p. 65
Important: set INITD (Bit 7) to signal device is ready */
SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0896);
Important: set INITD (Bit 7) to signal device is ready */
SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0896);
cs8900_recv_control = GET_PP_16(CS8900_PP_ADDR_CC_RXCTL);
/* spec: mac address is undefined after reset.
real HW: keeps the last set address. */
real HW: keeps the last set address. */
for (int i = 0; i < 6; i++)
SET_PP_8(CS8900_PP_ADDR_MAC_ADDR + i, cs8900_ia_mac[i]);
@ -380,13 +380,13 @@ cs8900a_device::cs8900a_device(const machine_config& mconfig, device_type type,
, device_network_interface(mconfig, *this, 10.0f)
, cs8900_ia_mac{0, 0, 0, 0, 0, 0}
, cs8900_packetpage_ptr(0)
, cs8900_recv_control(0) /* copy of CC_RXCTL (contains all bits below) */
, cs8900_recv_broadcast(false) /* broadcast */
, cs8900_recv_mac(false) /* individual address (IA) */
, cs8900_recv_multicast(false) /* multicast if address passes the hash filter */
, cs8900_recv_correct(false) /* accept correct frames */
, cs8900_recv_promiscuous(false) /* promiscuous mode */
, cs8900_recv_hashfilter(false) /* accept if IA passes the hash filter */
, cs8900_recv_control(0) /* copy of CC_RXCTL (contains all bits below) */
, cs8900_recv_broadcast(false) /* broadcast */
, cs8900_recv_mac(false) /* individual address (IA) */
, cs8900_recv_multicast(false) /* multicast if address passes the hash filter */
, cs8900_recv_correct(false) /* accept correct frames */
, cs8900_recv_promiscuous(false) /* promiscuous mode */
, cs8900_recv_hashfilter(false) /* accept if IA passes the hash filter */
, tx_buffer(CS8900_PP_ADDR_TX_FRAMELOC)
, rx_buffer(CS8900_PP_ADDR_RXSTATUS)
, tx_count(0)
@ -405,8 +405,8 @@ cs8900a_device::cs8900a_device(machine_config const& mconfig, char const *tag, d
{}
/*
This is a helper for cs8900_receive() to determine if the received frame should be accepted
according to the settings.
This is a helper for cs8900_receive() to determine if the received frame should be accepted
according to the settings.
*/
bool cs8900a_device::cs8900_should_accept(unsigned char *buffer, int length, bool *phashed, int *phash_index,
bool *pcorrect_mac, bool *pbroadcast, bool *pmulticast)
@ -419,8 +419,8 @@ bool cs8900a_device::cs8900_should_accept(unsigned char *buffer, int length, boo
*phashed = false;
*phash_index = 0;
*pcorrect_mac = false;
*pbroadcast = false;
*pmulticast = false;
*pbroadcast = false;
*pmulticast = false;
LOGMASKED(CS8900_DEBUG_FRAMES, "cs8900_should_accept called with %02X:%02X:%02X:%02X:%02X:%02X, length=%4u",
cs8900_ia_mac[0], cs8900_ia_mac[1], cs8900_ia_mac[2],
@ -496,8 +496,8 @@ u16 cs8900a_device::cs8900_receive()
u8 buffer[MAX_RXLENGTH];
int len;
bool hashed = false;
int hash_index = 0;
bool hashed = false;
int hash_index = 0;
bool rx_ok = false;
bool correct_mac = false;
bool broadcast = false;
@ -536,7 +536,7 @@ u16 cs8900a_device::cs8900_receive()
{
/* we already know the type of frame: Trust it! */
LOGMASKED(CS8900_DEBUG_FRAMES, "+++ cs8900_receive(): *** hashed=%u, correct_mac=%u, "
"broadcast=%u", hashed, correct_mac, broadcast);
"broadcast=%u", hashed, correct_mac, broadcast);
}
else
{
@ -619,21 +619,21 @@ u16 cs8900a_device::cs8900_receive()
}
/* ------------------------------------------------------------------------- */
/* reading and writing IO register functions */
/* reading and writing IO register functions */
/*
These registers are currently fully or partially supported:
These registers are currently fully or partially supported:
CS8900_PP_ADDR_CC_RXCFG 0x0102 * # RW - 4.4.6., p. 52 - 0003 *
CS8900_PP_ADDR_CC_RXCTL 0x0104 * # RW - 4.4.8., p. 54 - 0005 *
CS8900_PP_ADDR_CC_LINECTL 0x0112 * # RW - 4.4.16., p. 62 - 0013 *
CS8900_PP_ADDR_SE_RXEVENT 0x0124 * # R- - 4.4.7., p. 53 - 0004 *
CS8900_PP_ADDR_SE_BUSST 0x0138 * # R- - 4.4.21., p. 67 - 0018 *
CS8900_PP_ADDR_TXCMD 0x0144 * # -W - 4.5., p. 70 - 5.7., p. 98 *
CS8900_PP_ADDR_TXLENGTH 0x0146 * # -W - 4.5., p. 70 - 5.7., p. 98 *
CS8900_PP_ADDR_MAC_ADDR 0x0158 * # RW - 4.6., p. 71 - 5.3., p. 86 *
0x015a
0x015c
CS8900_PP_ADDR_CC_RXCFG 0x0102 * # RW - 4.4.6., p. 52 - 0003 *
CS8900_PP_ADDR_CC_RXCTL 0x0104 * # RW - 4.4.8., p. 54 - 0005 *
CS8900_PP_ADDR_CC_LINECTL 0x0112 * # RW - 4.4.16., p. 62 - 0013 *
CS8900_PP_ADDR_SE_RXEVENT 0x0124 * # R- - 4.4.7., p. 53 - 0004 *
CS8900_PP_ADDR_SE_BUSST 0x0138 * # R- - 4.4.21., p. 67 - 0018 *
CS8900_PP_ADDR_TXCMD 0x0144 * # -W - 4.5., p. 70 - 5.7., p. 98 *
CS8900_PP_ADDR_TXLENGTH 0x0146 * # -W - 4.5., p. 70 - 5.7., p. 98 *
CS8900_PP_ADDR_MAC_ADDR 0x0158 * # RW - 4.6., p. 71 - 5.3., p. 86 *
0x015a
0x015c
*/
/* ------------------------------------------------------------------------- */
@ -674,7 +674,7 @@ void cs8900a_device::cs8900_write_tx_buffer(u8 value, int odd_address)
/* full frame transmitted? */
if (tx_count == tx_length)
{
LOGMASKED(CS8900_DEBUG_FRAMES, "cs8900_arch_transmit() called with: "
LOGMASKED(CS8900_DEBUG_FRAMES, "cs8900_arch_transmit() called with:\t\t\t\t\t\t\t\t\t"
"length=%4u and buffer %s", tx_length,
debug_outbuffer(tx_length, &cs8900_packetpage[CS8900_PP_ADDR_TX_FRAMELOC])
);
@ -714,19 +714,19 @@ u8 cs8900a_device::cs8900_read_rx_buffer(int odd_address)
else
{
/*
According to the CS8900 spec, the handling is the following:
first read H, then L (RX_STATUS), then H, then L (RX_LENGTH).
Inside the RX frame data, we always get L then H, until the end is reached.
According to the CS8900 spec, the handling is the following:
first read H, then L (RX_STATUS), then H, then L (RX_LENGTH).
Inside the RX frame data, we always get L then H, until the end is reached.
even odd
CS8900_PP_ADDR_RXSTATUS: - proceed
CS8900_PP_ADDR_RXLENGTH: - proceed
CS8900_PP_ADDR_RX_FRAMELOC: - -
CS8900_PP_ADDR_RX_FRAMELOC+2: proceed -
CS8900_PP_ADDR_RX_FRAMELOC+4: proceed -
even odd
CS8900_PP_ADDR_RXSTATUS: - proceed
CS8900_PP_ADDR_RXLENGTH: - proceed
CS8900_PP_ADDR_RX_FRAMELOC: - -
CS8900_PP_ADDR_RX_FRAMELOC+2: proceed -
CS8900_PP_ADDR_RX_FRAMELOC+4: proceed -
*/
u16 addr = odd_address ? 1 : 0;
u8 value;
u8 value;
/* read RXSTATUS or RX_LENGTH */
if (rx_count < 4)
@ -769,7 +769,7 @@ u8 cs8900a_device::cs8900_read_rx_buffer(int odd_address)
/* handle side-effects of read and write operations */
/*
This is called *after* the relevant octets are written
This is called *after* the relevant octets are written
*/
void cs8900a_device::cs8900_sideeffects_write_pp(u16 ppaddress, int odd_address)
{
@ -934,7 +934,7 @@ void cs8900a_device::cs8900_sideeffects_write_pp(u16 ppaddress, int odd_address)
}
/*
This is called *before* the relevant octets are read
This is called *before* the relevant octets are read
*/
void cs8900a_device::cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address)
{
@ -946,10 +946,10 @@ void cs8900a_device::cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address)
{
int access_mask = (odd_address) ? 1 : 2;
/* update the status register only if the full word of the last
status was read! unfortunately different access patterns are
possible: either the status is read LH, LH, LH...
or HL, HL, HL, or even L, L, L or H, H, H */
/* update the status register only if the full word of the last
status was read! unfortunately different access patterns are
possible: either the status is read LH, LH, LH...
or HL, HL, HL, or even L, L, L or H, H, H */
if ((access_mask & rxevent_read_mask) != 0)
{
/* receiver is not enabled */
@ -962,8 +962,8 @@ void cs8900a_device::cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address)
/* perform frame reception */
u16 ret_val = cs8900_receive();
/* RXSTATUS and RXEVENT are the same, except that RXSTATUS buffers
the old value while RXEVENT sets a new value whenever it is called
/* RXSTATUS and RXEVENT are the same, except that RXSTATUS buffers
the old value while RXEVENT sets a new value whenever it is called
*/
SET_PP_16(CS8900_PP_ADDR_RXSTATUS, ret_val);
SET_PP_16(CS8900_PP_ADDR_SE_RXEVENT, ret_val);
@ -1399,11 +1399,11 @@ void cs8900a_device::cs8900_store(u16 io_address, u8 var)
if (reg_base == CS8900_ADDR_PP_PTR)
{
/* cv: we store the full package pointer in cs8900_packetpage_ptr variable.
this includes the mask area (0xf000) and the addr range (0x0fff).
we ensure that the bits 0x3000 are always set (as in real HW).
odd values of the pointer are valid and supported.
only register read and write have to be mapped to word boundary. */
/* cv: we store the full package pointer in cs8900_packetpage_ptr variable.
this includes the mask area (0xf000) and the addr range (0x0fff).
we ensure that the bits 0x3000 are always set (as in real HW).
odd values of the pointer are valid and supported.
only register read and write have to be mapped to word boundary. */
word_value |= 0x3000;
cs8900_packetpage_ptr = word_value;
LOGMASKED(CS8900_DEBUG_STORE, "set PP Ptr to $%04X.\n", cs8900_packetpage_ptr);

26
src/devices/machine/cs8900a.h
View File

@ -3,11 +3,11 @@
/*************************************************************************
CS8900A ethernet controller implementation
CS8900A ethernet controller implementation
by Rhett Aultman <roadriverrail@gmail.com>
ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/)
VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de>
by Rhett Aultman <roadriverrail@gmail.com>
ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/)
VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de>
**************************************************************************/
@ -19,7 +19,7 @@
#include <queue>
/***************************************************************************
TYPE DEFINITIONS
TYPE DEFINITIONS
***************************************************************************/
class cs8900a_device : public device_t, public device_network_interface {
@ -57,13 +57,13 @@ private:
u16 cs8900_packetpage_ptr;
/* reveiver setup */
u16 cs8900_recv_control; /* copy of CC_RXCTL (contains all bits below) */
bool cs8900_recv_broadcast; /* broadcast */
bool cs8900_recv_mac; /* individual address (IA) */
bool cs8900_recv_multicast; /* multicast if address passes the hash filter */
bool cs8900_recv_correct; /* accept correct frames */
bool cs8900_recv_promiscuous; /* promiscuous mode */
bool cs8900_recv_hashfilter; /* accept if IA passes the hash filter */
u16 cs8900_recv_control; /* copy of CC_RXCTL (contains all bits below) */
bool cs8900_recv_broadcast; /* broadcast */
bool cs8900_recv_mac; /* individual address (IA) */
bool cs8900_recv_multicast; /* multicast if address passes the hash filter */
bool cs8900_recv_correct; /* accept correct frames */
bool cs8900_recv_promiscuous; /* promiscuous mode */
bool cs8900_recv_hashfilter; /* accept if IA passes the hash filter */
u16 tx_buffer;
u16 rx_buffer;
@ -90,7 +90,7 @@ private:
void cs8900_set_transmitter(int enabled);
bool cs8900_should_accept(unsigned char *buffer, int length, bool *phashed, int *phash_index, bool *pcorrect_mac, bool *pbroadcast, bool *pmulticast);
u16 cs8900_receive(void);
void cs8900_write_tx_buffer(u8 value, int odd_address);
void cs8900_write_tx_buffer(u8 value, int odd_address);
u8 cs8900_read_rx_buffer(int odd_address);
void cs8900_sideeffects_write_pp(u16 ppaddress, int odd_address);
void cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address);

4
src/devices/machine/generalplus_gpl16250soc.cpp
View File

@ -219,12 +219,12 @@ void sunplus_gcm394_base_device::trigger_systemm_dma(int channel)
// mem.write_word(0x4d8d4, 0x4841); // golden tee IRQ? wait hack
//if (mem.read_word(0x3510f) == 0x4845)
// mem.write_word(0x3510f, 0x4840); // camp rock force service mode
// mem.write_word(0x3510f, 0x4840); // camp rock force service mode
if (mem.read_word(0x4abe7) == 0x4840)
mem.write_word(0x4abe7, 0x4841); // camp rock IRQ? wait hack
// clear params after operation
m_dma_params[0][channel] = m_dma_params[0][channel] & 0x00f7;

4
src/devices/sound/gaelco.cpp
View File

@ -181,8 +181,8 @@ void gaelco_gae1_device::sound_stream_update(sound_stream &stream, std::vector<r
outputs[1].put_int(j, output_r, 32768);
}
// if (wavraw)
// wav_add_data_buffer(wavraw, outputs[0], outputs[1]);
// if (wavraw)
// wav_add_data_buffer(wavraw, outputs[0], outputs[1]);
}
/*============================================================================

8
src/devices/sound/hc55516.cpp
View File

@ -188,10 +188,10 @@ void hc55516_device::process_digit()
m_next_sample = temp;
/* compress the sample range to fit better in a 16-bit word */
/* if (temp < 0)
m_next_sample = (int)(temp / (-temp * (1.0 / 32768.0) + 1.0));
else
m_next_sample = (int)(temp / (temp * (1.0 / 32768.0) + 1.0));*/
/* if (temp < 0)
m_next_sample = (int)(temp / (-temp * (1.0 / 32768.0) + 1.0));
else
m_next_sample = (int)(temp / (temp * (1.0 / 32768.0) + 1.0));*/
}
void hc55516_device::clock_w(int state)

2
src/devices/sound/votrax.cpp
View File

@ -489,7 +489,7 @@ void votrax_sc01_device::chip_update()
m_noise = ((m_noise << 1) & 0x7ffe) | inp;
m_cur_noise = !(((m_noise >> 14) ^ (m_noise >> 13)) & 1);
// logerror("%s tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", machine().time().to_string(), m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 3, m_pitch & 7, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure);
// logerror("%s tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", machine().time().to_string(), m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 3, m_pitch & 7, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure);
}
void votrax_sc01_device::filters_commit(bool force)

2
src/devices/video/ppu2c0x.cpp
View File

@ -419,7 +419,7 @@ void ppu2c0x_device::init_palette_tables()
m_nespens[entry] = (uint32_t)col;
entry++;
}
}
}

2
src/devices/video/ppu2c0x_sh6578.cpp
View File

@ -174,7 +174,7 @@ void ppu_sh6578_device::draw_background(uint8_t* line_priority)
{
color_mask = 0xff;
}
/* cache the background pen */
pen_t back_pen = m_nespens[m_back_color & color_mask];

16
src/devices/video/ppu2c0x_vt.cpp
View File

@ -146,7 +146,7 @@ void ppu_vt03_device::init_vtxx_rgb555_palette_tables()
{
for (int palval = 0; palval < 0x8000; palval++)
{
// uint16_t rgbval = (m_palette_ram[i & 0x7f] & 0xff) | ((m_palette_ram[(i & 0x7f) + 0x80] & 0xff) << 8);
// uint16_t rgbval = (m_palette_ram[i & 0x7f] & 0xff) | ((m_palette_ram[(i & 0x7f) + 0x80] & 0xff) << 8);
uint8_t blue = (palval & 0x001f) << 3;
uint8_t green = (palval & 0x3e0) >> 2;
uint8_t red = (palval & 0x7C00) >> 7;
@ -364,7 +364,7 @@ void ppu_vt03_device::draw_sprite_pixel(int sprite_xpos, int color, int pixel, u
if (!is16pix)
{
uint8_t pen = pixel_data + (4 * color);
draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel));
draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel));
}
else
{
@ -374,13 +374,13 @@ void ppu_vt03_device::draw_sprite_pixel(int sprite_xpos, int color, int pixel, u
if ((pixel_data & 0x03) != 0)
{
uint8_t pen = (pixel_data & 0x03) + (4 * color);
draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel));
draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel));
}
if (((pixel_data >> 5) & 0x03) != 0)
{
uint8_t pen = ((pixel_data >> 5) & 0x03) + (4 * color);
draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel + 8));
draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel + 8));
}
//ppu2c0x_device::draw_sprite_pixel(sprite_xpos, color, pixel, pixel_data & 0x03, bitmap);
//ppu2c0x_device::draw_sprite_pixel(sprite_xpos, color, pixel + 8, (pixel_data >> 5) & 0x03, bitmap);
@ -450,7 +450,7 @@ void ppu_vt03_device::draw_tile_pixel_inner(uint8_t pen, uint32_t *dest)
// does grayscale mode exist here? (we haven't calculated any colours for it)
//if (m_regs[PPU_CONTROL1] & PPU_CONTROL1_DISPLAY_MONO)
// palval &= 0x30;
// palval &= 0x30;
// apply colour emphasis (does it really exist here?) (we haven't calculated any colours for it, so ths has no effect)
palval |= ((m_regs[PPU_CONTROL1] & PPU_CONTROL1_COLOR_EMPHASIS) << 10);
@ -466,7 +466,7 @@ void ppu_vt03_device::draw_tile_pixel_inner(uint8_t pen, uint32_t *dest)
// does grayscale mode exist here? (we haven't calculated any colours for it)
//if (m_regs[PPU_CONTROL1] & PPU_CONTROL1_DISPLAY_MONO)
// palval &= 0x30;
// palval &= 0x30;
// apply colour emphasis (does it really exist here?) (we haven't calculated any colours for it, so ths has no effect)
palval |= ((m_regs[PPU_CONTROL1] & PPU_CONTROL1_COLOR_EMPHASIS) << 7);
@ -482,7 +482,7 @@ void ppu_vt03_device::draw_tile_pixel_inner(uint8_t pen, uint32_t *dest)
// does grayscale mode exist here? (we haven't calculated any colours for it)
//if (m_regs[PPU_CONTROL1] & PPU_CONTROL1_DISPLAY_MONO)
// palval &= 0x30;
// palval &= 0x30;
// apply colour emphasis (does it really exist here?) (we calculate values for it when building the palette lookup)
palval |= ((m_regs[PPU_CONTROL1] & PPU_CONTROL1_COLOR_EMPHASIS) << 7);
@ -539,7 +539,7 @@ void ppu_vt03_device::draw_tile_pixel(uint8_t pix, int color, uint32_t back_pen,
pen = 0; // back_pen; // fixme backpen logic probably differs on vt03 due to extra colours
}
draw_tile_pixel_inner(pen, dest);
draw_tile_pixel_inner(pen, dest);
}
}

2
src/emu/disound.h
View File

@ -138,7 +138,7 @@ protected:
// internal state
u8 m_outputs; // number of outputs
std::vector<u8> m_outputmap; // map of inputs to outputs
std::vector<bool> m_output_clear; // flag for tracking cleared buffers
std::vector<bool> m_output_clear; // flag for tracking cleared buffers
sound_stream *m_mixer_stream; // mixing stream
};

2
src/emu/sound.cpp
View File

@ -393,7 +393,7 @@ void sound_stream_output::init(sound_stream &stream, u32 index, char const *tag)
#if (LOG_OUTPUT_WAV)
std::string filename = stream.device().machine().basename();
filename += stream.device().tag();
filename += stream.device().tag();
for (int index = 0; index < filename.size(); index++)
if (filename[index] == ':')
filename[index] = '_';

72
src/emu/sound.h
View File

@ -8,47 +8,47 @@
****************************************************************************
In MAME, sound is represented as a graph of sound "streams". Each
stream has a fixed number of inputs and outputs, and is responsible
for producing sound on demand.
In MAME, sound is represented as a graph of sound "streams". Each
stream has a fixed number of inputs and outputs, and is responsible
for producing sound on demand.
The graph is driven from the outputs, which are speaker devices.
These devices are updated on a regular basis (~50 times per second),
and when an update occurs, the graph is walked from the speaker
through each input, until all connected streams are up to date.
The graph is driven from the outputs, which are speaker devices.
These devices are updated on a regular basis (~50 times per second),
and when an update occurs, the graph is walked from the speaker
through each input, until all connected streams are up to date.
Individual streams can also be updated manually. This is important
for sound chips and CPU-driven devices, who should force any
affected streams to update prior to making changes.
Individual streams can also be updated manually. This is important
for sound chips and CPU-driven devices, who should force any
affected streams to update prior to making changes.
Sound streams are *not* part of the device execution model. This is
very important to understand. If the process of producing the ouput
stream affects state that might be consumed by an executing device
(e.g., a CPU), then care must be taken to ensure that the stream is
updated frequently enough
Sound streams are *not* part of the device execution model. This is
very important to understand. If the process of producing the ouput
stream affects state that might be consumed by an executing device
(e.g., a CPU), then care must be taken to ensure that the stream is
updated frequently enough
The model for timing sound samples is very important and explained
here. Each stream source has a clock (aka sample rate). Each clock
edge represents a sample that is held for the duration of one clock
period. This model has interesting effects:
The model for timing sound samples is very important and explained
here. Each stream source has a clock (aka sample rate). Each clock
edge represents a sample that is held for the duration of one clock
period. This model has interesting effects:
For example, if you have a 10Hz clock, and call stream.update() at
t=0.91, it will compute 10 samples (for clock edges 0.0, 0.1, 0.2,
..., 0.7, 0.8, and 0.9). And then if you ask the stream what its
current end time is (via stream.sample_time()), it will say t=1.0,
which is in the future, because it knows it will hold that last
sample until 1.0s.
For example, if you have a 10Hz clock, and call stream.update() at
t=0.91, it will compute 10 samples (for clock edges 0.0, 0.1, 0.2,
..., 0.7, 0.8, and 0.9). And then if you ask the stream what its
current end time is (via stream.sample_time()), it will say t=1.0,
which is in the future, because it knows it will hold that last
sample until 1.0s.
Sound generation callbacks are presented with a std::vector of inputs
and outputs. The vectors contain objects of read_stream_view and
write_stream_view respectively, which wrap access to a circular buffer
of samples. Sound generation callbacks are expected to fill all the
samples described by the outputs' write_stream_view objects. At the
moment, all outputs have the same sample rate, so the number of samples
that need to be generated will be consistent across all outputs.
Sound generation callbacks are presented with a std::vector of inputs
and outputs. The vectors contain objects of read_stream_view and
write_stream_view respectively, which wrap access to a circular buffer
of samples. Sound generation callbacks are expected to fill all the
samples described by the outputs' write_stream_view objects. At the
moment, all outputs have the same sample rate, so the number of samples
that need to be generated will be consistent across all outputs.
By default, the inputs will have been resampled to match the output
sample rate, unless otherwise specified.
By default, the inputs will have been resampled to match the output
sample rate, unless otherwise specified.
***************************************************************************/
@ -81,7 +81,11 @@ constexpr u32 SAMPLE_RATE_MINIMUM = 50;
//**************************************************************************
// turn this on to enable aggressive assertions and other checks
#ifdef MAME_DEBUG
#define SOUND_DEBUG (1)
#else
#define SOUND_DEBUG (0)
#endif
// if SOUND_DEBUG is on, make assertions fire regardless of MAME_DEBUG
#if (SOUND_DEBUG)

54
src/lib/formats/p2000t_cas.cpp
View File

@ -153,7 +153,7 @@ struct P2000T_Header
std::ostream &operator<<(std::ostream &os, P2000T_Header const &hdr)
{
return os << "File: " << std::string(hdr.file_name, 8) << '.'
<< std::string(hdr.ext, 3) << " " << hdr.file_length;
<< std::string(hdr.ext, 3) << " " << hdr.file_length;
}
static cassette_image::error p2000t_cas_identify(cassette_image *cass, struct CassetteOptions *opts)
@ -189,27 +189,27 @@ void update_chksum(uint16_t *de, bool bit)
}
/*
A transition on a clock boundary from low to high is a 1.
A transition on a clock boundary from high to low is a 0
An intermediate transition halfway between the clock boundary
can occur when there are consecutive 0s or 1s. See the example
below where the clock is marked by a |
A transition on a clock boundary from low to high is a 1.
A transition on a clock boundary from high to low is a 0
An intermediate transition halfway between the clock boundary
can occur when there are consecutive 0s or 1s. See the example
below where the clock is marked by a |
1 0 1 1 0 0
RDA: _|----|____|--__|----|__--|__--
RDC: _|-___|-___|-___|-___|-___|-___
^ ^
|-- clock signal |-- intermediate transition.
1 0 1 1 0 0
RDA: _|----|____|--__|----|__--|__--
RDC: _|-___|-___|-___|-___|-___|-___
^ ^
|-- clock signal |-- intermediate transition.
This signal can be written by a simple algorithm where the first bit
is always false (transition to low, half clock). Now only one bit is needed
to determine what the next partial clock should look like.
This signal can be written by a simple algorithm where the first bit
is always false (transition to low, half clock). Now only one bit is needed
to determine what the next partial clock should look like.
This works because we are always guaranteed that a block starts with 0xAA,
and hence will ALWAYS find a signal like this on tape: _-- (low, high, high)
after a gap. This is guaranteed when the tape is moving forward as well as
backwards.
This works because we are always guaranteed that a block starts with 0xAA,
and hence will ALWAYS find a signal like this on tape: _-- (low, high, high)
after a gap. This is guaranteed when the tape is moving forward as well as
backwards.
*/
cassette_image::error p2000t_put_bit(cassette_image *cass, double *time_index, bool bit)
{
@ -263,17 +263,17 @@ static cassette_image::error p2000t_cas_load(cassette_image *cassette)
constexpr int CAS_BLOCK = 1280;
/*
The cas format is pretty simple. it consists of a sequence of blocks,
where a block consists of the following:
The cas format is pretty simple. it consists of a sequence of blocks,
where a block consists of the following:
[0-256] P2000 memory address 0x6000 - 0x6100
.... Nonsense (keyboard status etc.)
0x30 P200T_Header
0x50
... Nonsense..
[0-1024] Data block
[0-256] P2000 memory address 0x6000 - 0x6100
.... Nonsense (keyboard status etc.)
0x30 P200T_Header
0x50
... Nonsense..
[0-1024] Data block
This means that one block gets stored in 1280 bytes.
This means that one block gets stored in 1280 bytes.
*/
if (image_size % CAS_BLOCK != 0)
{

2
src/lib/formats/vg5k_cas.cpp
View File

@ -234,5 +234,5 @@ static const struct CassetteFormat vg5k_k7_format =
CASSETTE_FORMATLIST_START(vg5k_cassette_formats)
CASSETTE_FORMAT(vg5k_k7_format)
CASSETTE_FORMAT(wavfile_format)
CASSETTE_FORMAT(wavfile_format)
CASSETTE_FORMATLIST_END

4
src/lib/netlist/core/nets.h
View File

@ -21,7 +21,7 @@
// no action will be taken. This is academically cleaner, but slower than
// allowing this to happen and filter it during during "process".
#define AVOID_NOOP_QUEUE_PUSHES (0)
#define AVOID_NOOP_QUEUE_PUSHES (0)
namespace netlist
{
@ -160,7 +160,7 @@ namespace netlist
if (m_in_queue == queue_status::DELAYED_DUE_TO_INACTIVE)
{
#if (AVOID_NOOP_QUEUE_PUSHES)
if (m_next_scheduled_time > exec().time()
if (m_next_scheduled_time > exec().time()
&& (m_cur_Q != m_new_Q))
#else
if (m_next_scheduled_time > exec().time())

18
src/lib/netlist/macro/nlm_cd4xxx_lib.cpp
View File

@ -490,15 +490,15 @@ static NETLIST_START(CD4049_DIP)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
//DIPPINS( /* +--------------+ */
// A.VDD, /* VCC |1 ++ 16| NC */ NC.I,
// A.G, /*G=/A |2 15| L=/F*/ F.L,
// A.A, /* A |3 14| F */ F.F,
// B.H, /*H=/B |4 13| NC */ NC.I,
// B.B, /* B |5 4049 12| K=/E*/ E.K,
// C.I, /*I=/C |6 11| E */ E.E,
// C.C, /* C |7 10| J=/D*/ D.J,
// A.VSS, /* VSS |8 9| D */ D.D
// /* +--------------+ */
// A.VDD, /* VCC |1 ++ 16| NC */ NC.I,
// A.G, /*G=/A |2 15| L=/F*/ F.L,
// A.A, /* A |3 14| F */ F.F,
// B.H, /*H=/B |4 13| NC */ NC.I,
// B.B, /* B |5 4049 12| K=/E*/ E.K,
// C.I, /*I=/C |6 11| E */ E.E,
// C.C, /* C |7 10| J=/D*/ D.J,
// A.VSS, /* VSS |8 9| D */ D.D
// /* +--------------+ */
//)
DIPPINS( /* +--------------+ */
A.VDD, /* VCC |1 ++ 16| NC */ NC.I,

4
src/lib/netlist/plib/gmres.h
View File

@ -288,7 +288,7 @@ namespace plib
}
else
//rho_delta = accuracy * plib::sqrt(vec_mult2<FT>(n, rhs))
// + 1e-4 * std::sqrt(n);
// + 1e-4 * std::sqrt(n);
rho_delta = accuracy * plib::sqrt(narrow_cast<FT>(n));
//
@ -399,7 +399,7 @@ namespace plib
}
//for (std::size_t i = 0; i <= k; i++)
// vec_add_mult_scalar(n, x, m_v[i], m_y[i]);
// vec_add_mult_scalar(n, x, m_v[i], m_y[i]);
return true;
}
return false;

2
src/lib/netlist/plib/ptimed_queue.h
View File

@ -341,4 +341,4 @@ namespace plib {
} // namespace plib
#endif // PTIMED_QUEUE_H_
#include <cstdlib>
#include <cstdlib>

40
src/mame/audio/nl_astrob.cpp
View File

@ -61,26 +61,26 @@
// Define some random factors (5%)
#define FRND1 1.023
#define FRND2 1.017
#define FRND3 1.005
#define FRND4 1.014
#define FRND5 1.049
#define FRND6 1.044
#define FRND7 1.016
#define FRND8 1.037
#define FRND9 1.030
#define FRND10 1.001
#define FRND11 1.034
#define FRND12 1.043
#define FRND13 1.011
#define FRND14 1.016
#define FRND15 1.011
#define FRND16 1.006
#define FRND17 1.009
#define FRND18 1.007
#define FRND19 1.035
#define FRND20 1.004
#define FRND1 1.023
#define FRND2 1.017
#define FRND3 1.005
#define FRND4 1.014
#define FRND5 1.049
#define FRND6 1.044
#define FRND7 1.016
#define FRND8 1.037
#define FRND9 1.030
#define FRND10 1.001
#define FRND11 1.034
#define FRND12 1.043
#define FRND13 1.011
#define FRND14 1.016
#define FRND15 1.011
#define FRND16 1.006
#define FRND17 1.009
#define FRND18 1.007
#define FRND19 1.035
#define FRND20 1.004
//
// Main netlist

2
src/mame/audio/sente6vb.cpp
View File

@ -127,7 +127,7 @@ void sente6vb_device::device_add_mconfig(machine_config &config)
SPEAKER(config, "mono").front_center();
mm5837_stream_device &noise(MM5837_STREAM(config, "noise", 0));
// noise.set_vdd(-6.5); // seems too low -- possible the mapping in mm5837 is wrong
// noise.set_vdd(-6.5); // seems too low -- possible the mapping in mm5837 is wrong
noise.set_vdd(-8.0);
for (auto &cem_device : m_cem_device)

24
src/mame/drivers/abc1600.cpp
View File

@ -34,20 +34,20 @@
TODO:
- sas/format/format in abcenix tries to access the SASI card using a memory location mapped for task 0, when the process is run as task 1
- sas/format/format in abcenix tries to access the SASI card using a memory location mapped for task 0, when the process is run as task 1
[:mac] ':3f' (0009E) ff800:4f TASK 0 SEGMENT 15 PAGE 15 MEM 7f800-7ffff 1ff800
[:mac] ':3f' (0009E) ff801:ff TASK 0 SEGMENT 15 PAGE 15 MEM 7f800-7ffff 1ff800
[:mac] ':3f' (0009E) ff000:4f TASK 0 SEGMENT 15 PAGE 14 MEM 7f000-7f7ff 1ff000
[:mac] ':3f' (0009E) ff001:fe TASK 0 SEGMENT 15 PAGE 14 MEM 7f000-7f7ff 1ff000
[:mac] ':3f' (0009E) fe800:4f TASK 0 SEGMENT 15 PAGE 13 MEM 7e800-7efff 1fe800
[:mac] ':3f' (0009E) fe801:fd TASK 0 SEGMENT 15 PAGE 13 MEM 7e800-7efff 1fe800
[:mac] ':3f' (0009E) fe000:4f TASK 0 SEGMENT 15 PAGE 12 MEM 7e000-7e7ff 1fe000
[:mac] ':3f' (0009E) fe001:fc TASK 0 SEGMENT 15 PAGE 12 MEM 7e000-7e7ff 1fe000
[:mac] ':3f' (0009E) ff800:4f TASK 0 SEGMENT 15 PAGE 15 MEM 7f800-7ffff 1ff800
[:mac] ':3f' (0009E) ff801:ff TASK 0 SEGMENT 15 PAGE 15 MEM 7f800-7ffff 1ff800
[:mac] ':3f' (0009E) ff000:4f TASK 0 SEGMENT 15 PAGE 14 MEM 7f000-7f7ff 1ff000
[:mac] ':3f' (0009E) ff001:fe TASK 0 SEGMENT 15 PAGE 14 MEM 7f000-7f7ff 1ff000
[:mac] ':3f' (0009E) fe800:4f TASK 0 SEGMENT 15 PAGE 13 MEM 7e800-7efff 1fe800
[:mac] ':3f' (0009E) fe801:fd TASK 0 SEGMENT 15 PAGE 13 MEM 7e800-7efff 1fe800
[:mac] ':3f' (0009E) fe000:4f TASK 0 SEGMENT 15 PAGE 12 MEM 7e000-7e7ff 1fe000
[:mac] ':3f' (0009E) fe001:fc TASK 0 SEGMENT 15 PAGE 12 MEM 7e000-7e7ff 1fe000
[:mac] ':3f' (08A98) MAC 7e4a2:0004a2 (SEGA 02f SEGD 09 PGA 09c PGD 8000 NONX 1 WP 0 TASK 1 FC 1)
should be
[:mac] ':3f' (089A8) MAC 7e4a2:1fe4a2 (SEGA 00f SEGD 0f PGA 0fc PGD 43fc NONX 0 WP 1 TASK 0 FC 5)
[:mac] ':3f' (08A98) MAC 7e4a2:0004a2 (SEGA 02f SEGD 09 PGA 09c PGD 8000 NONX 1 WP 0 TASK 1 FC 1)
should be
[:mac] ':3f' (089A8) MAC 7e4a2:1fe4a2 (SEGA 00f SEGD 0f PGA 0fc PGD 43fc NONX 0 WP 1 TASK 0 FC 5)
- short/long reset (RSTBUT)
- CIO

2
src/mame/drivers/bagman.cpp
View File

@ -748,7 +748,7 @@ ROM_START( bagnardi ) // 1983
ROM_REGION (0x104, "plds", 0)
ROM_LOAD( "lebag_itisa_pal16r6cn.p6", 0x000, 0x104, CRC(13f14bbf) SHA1(b8c4ddf61609465f3a3699dd42796f15a7b17979) )
ROM_END
ROM_START( bagnardio ) // 1982, based on bagnard set with mods for license text

2
src/mame/drivers/clickstart.cpp
View File

@ -9,7 +9,7 @@
mouse optical sensor is a N2163, probably from Agilent.
ClickStart cartridges pinout:
1 N/C 2 GND
3 GND 4 VCC
5 GND 6 VCC

2
src/mame/drivers/cps1bl_5205.cpp
View File

@ -1082,7 +1082,7 @@ ROM_START( knightsb3 )
== |
| 1 5 6 |
|________________________|
#1 palce20v8h secured, bruteforce ok
#2 palce16v8h secured, bruteforce ok
#3 palce16v8h secured, registered

2
src/mame/drivers/cps1bl_pic.cpp
View File

@ -1319,7 +1319,7 @@ ROM_START( jurassic99 )
U98G ATF16V8B-15PC 8 secured, registered
U99G ATF16V8B-15PC 8 secured, registered
U134G ATF16V8B-15PC 8? secured, registered
3rd column numbers are what's hand-written on each chip
? = hard to read or rubbed off
the #8 pals appear to be just 74LS298 equivalents, can be replaced with real 74LS298 (additional 16-pin footprints underneath each chip) or hand-crafted jed

4
src/mame/drivers/dpb7000.cpp
View File

@ -47,8 +47,8 @@
#define LOG_SIZE_CARD (1 << 14)
#define LOG_FILTER_CARD (1 << 15)
#define LOG_KEYBC (1 << 16)
#define LOG_TDS (1 << 17)
#define LOG_TABLET (1 << 18)
#define LOG_TDS (1 << 17)
#define LOG_TABLET (1 << 18)
#define LOG_ALL (LOG_UNKNOWN | LOG_CSR | LOG_CTRLBUS | LOG_SYS_CTRL | LOG_FDC_CTRL | LOG_FDC_PORT | LOG_FDC_CMD | LOG_FDC_MECH | LOG_BRUSH_ADDR | \
LOG_STORE_ADDR | LOG_COMBINER | LOG_SIZE_CARD | LOG_FILTER_CARD)

4
src/mame/drivers/elan_eu3a05.cpp
View File

@ -247,7 +247,7 @@ public:
void init_sudelan();
void init_sudelan3();
protected:
// driver_device overrides
virtual void machine_start() override;
@ -869,7 +869,7 @@ void elan_eu3a05_pvwwcas_state::pvwwcas(machine_config& config)
m_screen->set_refresh_hz(50);
m_sys->set_pal(); // TODO: also set PAL clocks
m_gpio->read_2_callback().set(FUNC(elan_eu3a05_pvwwcas_state::pvwwc_portc_r));
m_gpio->read_2_callback().set(FUNC(elan_eu3a05_pvwwcas_state::pvwwc_portc_r));
m_gpio->write_2_callback().set(FUNC(elan_eu3a05_pvwwcas_state::pvwwc_portc_w));
}

4
src/mame/drivers/generalplus_gpl32612.cpp
View File

@ -62,7 +62,7 @@ private:
uint32_t unk_d000003c_r(offs_t offset, uint32_t mem_mask);
uint32_t unk_d0800018_r(offs_t offset, uint32_t mem_mask);
uint32_t unk_d0900140_r(offs_t offset, uint32_t mem_mask);
uint32_t unk_d0900153_r(offs_t offset, uint32_t mem_mask);
uint32_t unk_d0900153_r(offs_t offset, uint32_t mem_mask);
};
uint32_t generalplus_gpl32612_game_state::unk_d000003c_r(offs_t offset, uint32_t mem_mask)
@ -90,7 +90,7 @@ void generalplus_gpl32612_game_state::arm_map(address_map &map)
map(0x00000000, 0x03ffffff).ram();
map(0xd000003c, 0xd000003f).r(FUNC(generalplus_gpl32612_game_state::unk_d000003c_r));
map(0xd0800018, 0xd080001b).r(FUNC(generalplus_gpl32612_game_state::unk_d0800018_r));
map(0xd0900140, 0xd0900143).r(FUNC(generalplus_gpl32612_game_state::unk_d0900140_r));

8
src/mame/drivers/ginganin.cpp
View File

@ -82,7 +82,7 @@ f5d6 print 7 digit BCD number: d0.l to (a1)+ color $3000
void ginganin_state::main_map(address_map &map)
{
// PC=0x408 ROM area 10000-13fff is written at POST with: 0000 0000 0000 0001,
// PC=0x408 ROM area 10000-13fff is written at POST with: 0000 0000 0000 0001,
// looks a debugging left-over for GFX patching (causes state garbage if hooked as RAM write mirror)
map(0x000000, 0x01ffff).rom().nopw();
map(0x020000, 0x023fff).ram();
@ -360,10 +360,10 @@ void ginganin_state::init_ginganin()
{
// pending full removal of this patch ...
/* main cpu patches */
// u16 *rom = (u16 *)memregion("maincpu")->base();
// u16 *rom = (u16 *)memregion("maincpu")->base();
/* avoid writes to rom getting to the log */
// rom[0x408 / 2] = 0x6000;
// rom[0x40a / 2] = 0x001c;
// rom[0x408 / 2] = 0x6000;
// rom[0x40a / 2] = 0x001c;
}

10
src/mame/drivers/informer_207_100.cpp
View File

@ -8,15 +8,15 @@
Hardware:
- HD68B09EP
- 3x HM6116LP-4 (+ 3 empty sockets), 2x TC5517BPL-20
- 3x HM6116LP-4 (+ 3 empty sockets), 2x TC5517BPL-20
- R6545-1AP CRTC
- MC2681P DUART
- MC2681P DUART
- MC68B50P ACIA
- M58321 RTC
- 19.7184 MHz XTAL, 3.6864 MHz XTAL
- 19.7184 MHz XTAL, 3.6864 MHz XTAL
TODO:
- Redump ROM 207_100_2.bin
- Redump ROM 207_100_2.bin
***************************************************************************/
@ -112,7 +112,7 @@ MC6845_UPDATE_ROW( informer_207_100_state::crtc_update_row )
for (int x = 0; x < x_count; x++)
{
// uint8_t attr = m_ram[ma + x * 2 + 0];
// uint8_t attr = m_ram[ma + x * 2 + 0];
uint8_t code = m_ram[ma + x * 2 + 1];
uint8_t data = m_chargen[(code << 4) + ra];

10
src/mame/drivers/informer_207_376.cpp
View File

@ -8,17 +8,17 @@
Hardware:
- M6809
- 8253 PIT
- 8253 PIT
- Z80SCC 8530
- 2x 6850 ACIA (up to 4)
- 2x X2212P NOVRAM
TODO:
- Dump keyboard controller and emulate it (currently HLE'd)
- Problably needs improvements to at least the Z80SCC to
properly support synchrous modes
- Dump keyboard controller and emulate it (currently HLE'd)
- Problably needs improvements to at least the Z80SCC to
properly support synchrous modes
- Figure out the unknown bits at 0x8400
- Verify clock speeds
- Verify clock speeds
Notes:
- Thanks to charcole and his zmachine3270 project at

18
src/mame/drivers/informer_213.cpp
View File

@ -3,18 +3,18 @@
/***************************************************************************
Informer 213 (IBM 374/SNA V.22)
Informer 213 AE (VT-100)
Informer 213 AE (VT-100)
Hardware:
- EF68B09EP
- 2x TC5564PL-15 [8k] (next to CG ROM)
- 1x TC5565APL-15 [8k] + 2x TMS4464-15NL [32k] (next to CPU)
- Z0853006PSC SCC
- ASIC (INFORMER 44223)
- 18.432 MHz XTAL
- 2x TC5564PL-15 [8k] (next to CG ROM)
- 1x TC5565APL-15 [8k] + 2x TMS4464-15NL [32k] (next to CPU)
- Z0853006PSC SCC
- ASIC (INFORMER 44223)
- 18.432 MHz XTAL
TODO:
- Figure out the ASIC and how it's connected
- Figure out the ASIC and how it's connected
***************************************************************************/
@ -136,7 +136,7 @@ INPUT_PORTS_END
uint32_t informer_213_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
offs_t chargen_base = (m_chargen.bytes() == 0x4000) ? 0x2000 : 0;
// line at which vram splits into two windows
int split = 24 - ((m_vram_start_addr2 - m_vram_start_addr) / 80);
@ -389,7 +389,7 @@ void informer_213_state::informer_213(machine_config &config)
m_screen->set_visarea_full();
m_screen->set_refresh_hz(60);
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(2500)); // not accurate
// m_screen->set_raw(18.432_MHz_XTAL, 0, 0, 0, 0, 0, 0);
// m_screen->set_raw(18.432_MHz_XTAL, 0, 0, 0, 0, 0, 0);
m_screen->set_screen_update(FUNC(informer_213_state::screen_update));
m_screen->screen_vblank().set(FUNC(informer_213_state::vblank_w));

16
src/mame/drivers/m72.cpp
View File

@ -597,16 +597,16 @@ static const u8 airduelm72_crc[CRC_LEN] = { 0x54,0x81,0xe6,0x8a, 0xc9,0x12,0
// Actual MCU is dumped, information for Air Duel (Japan, M72 hardware) for reference:
static const u8 airduelm72_code[CODE_LEN] =
{
0x68,0x00,0xd0, // push 0d000h
0x1f, // pop ds
// the game checks for
// "This game can only be played in Japan..." message in the video text buffer
// the message is nowhere to be found in the ROMs, so has to be displayed by the mcu
0xc6,0x06,0xc0,0x1c,0x57, // mov [1cc0h], byte 057h
0xea,0x69,0x0b,0x00,0x00 // jmp 0000:$0b69
0x68,0x00,0xd0, // push 0d000h
0x1f, // pop ds
// the game checks for
// "This game can only be played in Japan..." message in the video text buffer
// the message is nowhere to be found in the ROMs, so has to be displayed by the mcu
0xc6,0x06,0xc0,0x1c,0x57, // mov [1cc0h], byte 057h
0xea,0x69,0x0b,0x00,0x00 // jmp 0000:$0b69
};
static const u8 airduelm72j_crc[CRC_LEN] = { 0x72,0x9c,0xca,0x85, 0xc9,0x12,0xcc,0xea,
0x00,0x00 };
0x00,0x00 };
*/
/* Daiku no Gensan */

14
src/mame/drivers/mac.cpp
View File

@ -41,13 +41,13 @@
when the PC hits GetCPUID, the move.l (a2), d0 at PC = 0x10000 will cause an MMU fault (jump to 0xFFF00300). why?
a2 = 0x5ffffffc (the CPU ID register). MMU is unable to resolve this; defect in the MMU emulation probable.
TODO:
- SE and Classic to own driver
- Portable and PowerBook 100 to own driver
- Remaining PowerBooks to own driver
- Quadra 700 to own driver
- V8 and friends to own driver
- LC3 / LC520 / IIvx / IIvi to own driver
TODO:
- SE and Classic to own driver
- Portable and PowerBook 100 to own driver
- Remaining PowerBooks to own driver
- Quadra 700 to own driver
- V8 and friends to own driver
- LC3 / LC520 / IIvx / IIvi to own driver
****************************************************************************/

8
src/mame/drivers/mac128.cpp
View File

@ -6,8 +6,8 @@
Original-style Macintosh family emulation
The cutoff here is Macs with 128k-style video and audio.
We also include the SE and Classic, which are basically cost-reduced Mac Pluses with ADB
instead of the original keyboard/mouse hardware.
We also include the SE and Classic, which are basically cost-reduced Mac Pluses with ADB
instead of the original keyboard/mouse hardware.
Nate Woods, Raphael Nabet, R. Belmont
@ -379,7 +379,7 @@ void mac128_state::field_interrupts()
take_interrupt = 1;
}
// printf("field_interrupts: take %d\n", take_interrupt);
// printf("field_interrupts: take %d\n", take_interrupt);
if (m_last_taken_interrupt > -1)
{
@ -757,7 +757,7 @@ uint8_t mac128_state::mac_via_in_b()
val |= m_rtc->data_r();
// printf("%s VIA1 IN_B = %02x\n", machine().describe_context().c_str(), val);
// printf("%s VIA1 IN_B = %02x\n", machine().describe_context().c_str(), val);
return val;
}

10
src/mame/drivers/msisaac.cpp
View File

@ -6,11 +6,11 @@
driver by Jarek Burczynski
TODO:
- complete MCU simulation, several gameplay elements not properly right;
- sprites are probably banked differently (no way to be sure until MCU dump is available)
- TA7630 emulation needs filter support (characteristics depend on the frequency)
- TA7630 volume table is hand tuned to match the sample, but still slightly off.
TODO:
- complete MCU simulation, several gameplay elements not properly right;
- sprites are probably banked differently (no way to be sure until MCU dump is available)
- TA7630 emulation needs filter support (characteristics depend on the frequency)
- TA7630 volume table is hand tuned to match the sample, but still slightly off.
****************************************************************************/

10
src/mame/drivers/nes_vt.cpp
View File

@ -2353,13 +2353,13 @@ CONS( 2016, fcpocket, 0, 0, nes_vt_fp_4x16mb, nes_vt_fp, nes_vt_hh_state, e
/****************************************************************************************************************
Things below seem on heavily enhanced hardware of unknown VT type
Things below seem on heavily enhanced hardware of unknown VT type
It's possible some of these are the same as some of the ones above (sy889, rminitv, dgun2573 etc.) but with
more features used.
It's possible some of these are the same as some of the ones above (sy889, rminitv, dgun2573 etc.) but with
more features used.
In some cases these might be almost entirely different, and it is likely a number don't belong in this
driver at all.
In some cases these might be almost entirely different, and it is likely a number don't belong in this
driver at all.
****************************************************************************************************************/

2
src/mame/drivers/photoply.cpp
View File

@ -340,7 +340,7 @@ ROM_START(photoply98sp)
ROM_REGION(0x20000, "bios", 0) // Motherboard BIOS
ROM_LOAD("funworld_award_486e_w83787.bin", 0x000000, 0x20000, CRC(af7ff1d4) SHA1(72eeecf798a03817ce7ba4d65cd4128ed3ef7e68) ) // 486E 96/7/19 W83787 PLUG & PLAY BIOS, AT27C010, Funworld sticker: Sept 1998
ROM_REGION(0x8000, "ex_bios", ROMREGION_ERASE00 ) // Multifunction board with a ESS AudioDrive chip, Funworld sticker: Sept 1998
ROM_REGION(0x8000, "ex_bios", ROMREGION_ERASE00 ) // Multifunction board with a ESS AudioDrive chip, Funworld sticker: Sept 1998
ROM_LOAD("enhanced_bios_centos.bin", 0x000000, 0x8000, CRC(ee8ad003) SHA1(4814385117599a98da02155785d1e3fce4e485bd) ) // Centos CI-8000/PP2000 ROM BIOS Version 1.06, 27C256B
ROM_REGION(0x8000, "video_bios", 0 )

2
src/mame/drivers/quickpick5.cpp
View File

@ -488,7 +488,7 @@ static INPUT_PORTS_START( quickpick5 )
INPUT_PORTS_END
// Control panel buttons layout:
// Payout 1 2 1-2 1-3 1-4
// Payout 1 2 1-2 1-3 1-4
// 3 4 2-3 2-4 3-4 Start
static INPUT_PORTS_START( waijockey )
PORT_START("IN1")

14
src/mame/drivers/seibucats.cpp
View File

@ -12,7 +12,7 @@
- mahjong keyboard inputs (and JAMMA adapter for some games);
- emulate YMF721-S or at least do something about MIDI sound;
- verify interrupt table;
- verify coin inputs;
- verify coin inputs;
- Any other port lingering in the 0x400-0x7ff area?
===========================================================================================================================
@ -38,14 +38,14 @@
ROM:
- Program ROMs: MX27C40000C-12 or MBM27C4001-12Z or TMS27C040-10 x4 (U011, U015-U017 = "PRG0-PRG3" on ROM board)
- Sprite ROMs: MX29F8100MC-12 or "MX29F1610" x4 (U0231-U0234 = "OBJ1-OBJ4" on ROM board).
Only three ROMs appear to be populated on any game.
This means sprites should be 6bpp, even though they could potentially have been 8bpp.
Only three ROMs appear to be populated on any game.
This means sprites should be 6bpp, even though they could potentially have been 8bpp.
EEPROM/NVRAM:
- ST93C46AF Serial EEPROM (U0512; towards left center of board)
- Toshiba TC55257DFL-70L (U0144 on ROM board) with Maxell CR2032 battery (BT011 on ROM board).
The ROM board type used by Marumie Network lacks NVRAM and RTC;
their locations are not populated on Pakkun Ball TV.
The ROM board type used by Marumie Network lacks NVRAM and RTC;
their locations are not populated on Pakkun Ball TV.
RTC:
- JRC 6355E/NJU6355 Real Time Clock (U0513, above YMF721)
@ -54,8 +54,8 @@
Serial ports:
- NEC uPD71051GB USART x2 (U1133, U1134; lined up with DB9 ports)
- MAXZ32 Serial Line Driver x2 (U1138, U1141; between USARTs and DB9 ports)
- Two DB9 ports, one marked "DVD" and the other "Touch Panel."
The latter also uses a separate 2-pin Molex power connector (CN114).
- Two DB9 ports, one marked "DVD" and the other "Touch Panel."
The latter also uses a separate 2-pin Molex power connector (CN114).
Sound and linear miscellany:
- Yamaha YMF721-S General MIDI OPL4-ML2 (U0274; to right of USARTs)

6
src/mame/drivers/snesb.cpp
View File

@ -324,7 +324,7 @@ uint8_t snesb_state::wldgunsb_722262_r()
{
// PC 2e2f6
return 0x2b;
}
}
uint8_t snesb_state::wldgunsb_723364_r()
{
@ -1412,7 +1412,7 @@ void snesb_state::init_wldgunsb()
static uint8_t address_tab_high[0x20] = {
0x0b, 0x1d, 0x05, 0x15, 0x09, 0x19, 0x04, 0x13, 0x02, 0x1f, 0x07, 0x17, 0x0d, 0x11, 0x0a, 0x1a,
0x14, 0x0e, 0x18, 0x06, 0x1e, 0x01, 0x10, 0x0c, 0x1b, 0x0f, 0x16, 0x00, 0x12, 0x08, 0x1c, 0x03
0x14, 0x0e, 0x18, 0x06, 0x1e, 0x01, 0x10, 0x0c, 0x1b, 0x0f, 0x16, 0x00, 0x12, 0x08, 0x1c, 0x03
};
static uint8_t address_tab_low[0x40] = {
@ -1465,7 +1465,7 @@ void snesb_state::init_wldgunsb()
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770071, 0x770071, read8smo_delegate(*this, FUNC(snesb_state::snesb_dsw1_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770072, 0x770072, read8smo_delegate(*this, FUNC(snesb_state::snesb_dsw2_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770079, 0x770079, read8smo_delegate(*this, FUNC(snesb_state::snesb_coin_r)));
// protection overlays
// counter (PC=0x2dfe7 / 0x2dfee)
m_maincpu->space(AS_PROGRAM).install_read_handler(0x7bf45b, 0x7bf45b, read8smo_delegate(*this, FUNC(snesb_state::sb2b_75bd37_r)));

14
src/mame/drivers/spg2xx.cpp
View File

@ -1039,13 +1039,13 @@ static INPUT_PORTS_START( hotwheels )
PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("P2")
PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_BUTTON1 )
PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_BUTTON1 )
PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_CONFNAME( 0x0080, 0x0000, "Player 1 Controller Type" )
PORT_CONFSETTING( 0x0000, "Bling" )
PORT_CONFSETTING( 0x0080, "Rally" )
@ -1059,7 +1059,7 @@ static INPUT_PORTS_START( hotwheels )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0xe000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("P3") // never read?

14
src/mame/drivers/spg2xx_wiwi.cpp
View File

@ -6,10 +6,10 @@
The WiWi could also run NES games; SunPlus hardware was in the cartridge, it was a 'fake' system.
---
---
some of these are just checking a external timer on a port, I think this is one of the SPG features
so might need making more generic.
some of these are just checking a external timer on a port, I think this is one of the SPG features
so might need making more generic.
*/
@ -90,9 +90,9 @@ public:
protected:
// virtual uint16_t portb_r();
// virtual uint16_t portb_r();
virtual void porta_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) override;
// virtual void portb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) override;
// virtual void portb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) override;
};
@ -212,10 +212,10 @@ void spg2xx_game_ddmsup_state::ddmsup(machine_config &config)
{
spg2xx(config);
// m_maincpu->portb_in().set(FUNC(spg2xx_game_ddmsup_state::portb_r));
// m_maincpu->portb_in().set(FUNC(spg2xx_game_ddmsup_state::portb_r));
m_maincpu->porta_in().set(FUNC(spg2xx_game_ddmsup_state::porta_r));
m_maincpu->porta_out().set(FUNC(spg2xx_game_ddmsup_state::porta_w));
// m_maincpu->portb_out().set(FUNC(spg2xx_game_ddmsup_state::portb_w));
// m_maincpu->portb_out().set(FUNC(spg2xx_game_ddmsup_state::portb_w));
}

6
src/mame/drivers/spg2xx_zone_32bit.cpp
View File

@ -651,10 +651,10 @@ INPUT_PORTS_END
static INPUT_PORTS_START( mywicogt )
PORT_START("P1")
PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_START("P2")
PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_START("P3")
PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("Green / Left")
@ -666,7 +666,7 @@ static INPUT_PORTS_START( mywicogt )
PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Start / Pause / Menu")
PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("Back")
PORT_BIT( 0xfe00, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0xfe00, IP_ACTIVE_HIGH, IPT_UNUSED )
INPUT_PORTS_END

20
src/mame/drivers/startouch.cpp
View File

@ -2,16 +2,16 @@
// copyright-holders:
/*******************************************************************************
Skeleton driver for "EuroByte Electronics & Multimedia IASA" PC-based touch
games, sold in Spain by Sleic / Petaco.
-----+----------------------------+------+----------------------------------
Dump | Game | Year | Notes
-----+----------------------------+------+----------------------------------
NO | Superchip | 1999 |
NO | Star Touch | 2000 |
YES | Star Touch / EuroPlay 2001 | 2001 | Original Game: http://www.eurobyte.com.gr/gb_europlay.htm
Skeleton driver for "EuroByte Electronics & Multimedia IASA" PC-based touch
games, sold in Spain by Sleic / Petaco.
-----+----------------------------+------+----------------------------------
Dump | Game | Year | Notes
-----+----------------------------+------+----------------------------------
NO | Superchip | 1999 |
NO | Star Touch | 2000 |
YES | Star Touch / EuroPlay 2001 | 2001 | Original Game: http://www.eurobyte.com.gr/gb_europlay.htm
Hardware overview:
MB Soyo M5EH or similar (e.g. Biostar M5ATD)
16384 KB RAM

48
src/mame/drivers/vg5k.cpp
View File

@ -82,7 +82,7 @@ public:
void init_vg5k();
DECLARE_INPUT_CHANGED_MEMBER(delta_button);
DECLARE_INPUT_CHANGED_MEMBER(delta_button);
private:
required_device<z80_device> m_maincpu;
@ -114,12 +114,12 @@ private:
void vg5k_state::z80_m1_w(uint8_t data)
{
// Leverage the refresh callback of the Z80 emulator to pretend
// the second T state of the M1 cycle didn't happen.
// This simulates the WAIT line asserted at that moment, as
// the current implementation of the Z80 doesn't handle the WAIT
// line at that moment.
m_maincpu->adjust_icount(-1);
// Leverage the refresh callback of the Z80 emulator to pretend
// the second T state of the M1 cycle didn't happen.
// This simulates the WAIT line asserted at that moment, as
// the current implementation of the Z80 doesn't handle the WAIT
// line at that moment.
m_maincpu->adjust_icount(-1);
}
uint8_t vg5k_state::printer_r()
@ -163,17 +163,17 @@ uint8_t vg5k_state::cassette_r()
void vg5k_state::cassette_w(uint8_t data)
{
m_dac->write(BIT(data, 3));
m_cassette->change_state(BIT(data, 1) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED , CASSETTE_MASK_MOTOR);
m_cassette->change_state(BIT(data, 1) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED , CASSETTE_MASK_MOTOR);
if (BIT(data, 1)) {
if (BIT(data, 0)) {
m_cassette->output(+1);
} else {
m_cassette->output(-1);
}
} else {
m_cassette->output(0);
}
if (BIT(data, 1)) {
if (BIT(data, 0)) {
m_cassette->output(+1);
} else {
m_cassette->output(-1);
}
} else {
m_cassette->output(0);
}
}
@ -308,8 +308,8 @@ static INPUT_PORTS_START( vg5k )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("direct")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_END) PORT_NAME("DELTA") PORT_CHANGED_MEMBER(DEVICE_SELF, vg5k_state, delta_button, 0)
PORT_START("direct")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_END) PORT_NAME("DELTA") PORT_CHANGED_MEMBER(DEVICE_SELF, vg5k_state, delta_button, 0)
INPUT_PORTS_END
@ -333,10 +333,10 @@ TIMER_DEVICE_CALLBACK_MEMBER(vg5k_state::vg5k_scanline)
INPUT_CHANGED_MEMBER(vg5k_state::delta_button)
{
// The yellow Delta key on the keyboard is wired so that it asserts directly the NMI line of the Z80.
if (!newval) {
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
// The yellow Delta key on the keyboard is wired so that it asserts directly the NMI line of the Z80.
if (!newval) {
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
}
@ -398,7 +398,7 @@ void vg5k_state::vg5k(machine_config &config)
Z80(config, m_maincpu, XTAL(4'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &vg5k_state::vg5k_mem);
m_maincpu->set_addrmap(AS_IO, &vg5k_state::vg5k_io);
m_maincpu->refresh_cb().set(FUNC(vg5k_state::z80_m1_w));
m_maincpu->refresh_cb().set(FUNC(vg5k_state::z80_m1_w));
TIMER(config, "vg5k_scanline").configure_scanline(FUNC(vg5k_state::vg5k_scanline), "screen", 0, 10);

70
src/mame/drivers/votrhv.cpp
View File

@ -7,46 +7,46 @@
*
******************************************************************************/
/*
The HC-110 and HC-120 both consist of 3 boards:
1. An 'embedded system' 6800 board with two output latches, one input
latch, and two 'resume/reset' latches which pull the 6800 is out of
reset on a rising edge, as a form of power saving. (pcb 1816?)
2. A keyboard handler pcb; this is different on the HC-110 (where it is
made by a 3rd party company for the 128-key input) and the HC-120
(where it was made by votrax/phonic mirror, pcb 1817?)
3. The voice synthesizer pcb 1818c, encased in epoxy. It is a discrete
synthesizer roughly equivalent to an SC-01 or VSK, it has external
pins to allow control of speech pitch and rate in addition to the
typical 2 inflection pins.
The HC-110 and HC-120 both consist of 3 boards:
1. An 'embedded system' 6800 board with two output latches, one input
latch, and two 'resume/reset' latches which pull the 6800 is out of
reset on a rising edge, as a form of power saving. (pcb 1816?)
2. A keyboard handler pcb; this is different on the HC-110 (where it is
made by a 3rd party company for the 128-key input) and the HC-120
(where it was made by votrax/phonic mirror, pcb 1817?)
3. The voice synthesizer pcb 1818c, encased in epoxy. It is a discrete
synthesizer roughly equivalent to an SC-01 or VSK, it has external
pins to allow control of speech pitch and rate in addition to the
typical 2 inflection pins.
Notes: Electronic Arrays, Inc. who made the EA8316 CMOS mask ROMs was
bought out by NEC in 1978.
Notes: Electronic Arrays, Inc. who made the EA8316 CMOS mask ROMs was
bought out by NEC in 1978.
TODO: 1818c discrete speech synth device
TODO: 1818c discrete speech synth device
The 1818C SYNTHESIZER BOARD is mentioned as one of two speech
synthesizers described in US Patent 4,130,730 in figures 3, 4a and 4b
(the Votrax VSK/VSL is the other device, described in figures 1, 2a,
and 2b)
The 1818C uses three Motorola MCM14524 256x4 CMOS MASK ROMs to hold
the phoneme parameters.
(This is mentioned in 4,130,730 column 11 line 31.)
The 1818C SYNTHESIZER BOARD is mentioned as one of two speech
synthesizers described in US Patent 4,130,730 in figures 3, 4a and 4b
(the Votrax VSK/VSL is the other device, described in figures 1, 2a,
and 2b)
The 1818C uses three Motorola MCM14524 256x4 CMOS MASK ROMs to hold
the phoneme parameters.
(This is mentioned in 4,130,730 column 11 line 31.)
Motorola MCM14524:
+---..---+
/CLK -> | 1 16 | -- VDD (up to 18v)
CE -> | 2 15 | <- A0
B0 <- | 3 14 | <- A1
B1 <- | 4 13 | <- A7
B2 <- | 5 12 | <- A6
B3 <- | 6 11 | <- A5
A2 -> | 7 10 | <- A4
(0v)VSS -- | 8 9 | <- A3
+--------+
see http://bitsavers.org/components/motorola/_dataBooks/1978_Motorola_CMOS_Data_Book.pdf
page 488
Motorola MCM14524:
+---..---+
/CLK -> | 1 16 | -- VDD (up to 18v)
CE -> | 2 15 | <- A0
B0 <- | 3 14 | <- A1
B1 <- | 4 13 | <- A7
B2 <- | 5 12 | <- A6
B3 <- | 6 11 | <- A5
A2 -> | 7 10 | <- A4
(0v)VSS -- | 8 9 | <- A3
+--------+
see http://bitsavers.org/components/motorola/_dataBooks/1978_Motorola_CMOS_Data_Book.pdf
page 488
TODO: make the two latcha/b flops combine together using input_merger
TODO: make the two latcha/b flops combine together using input_merger
*/
/* Core includes */

6
src/mame/drivers/vt1682.cpp
View File

@ -6236,12 +6236,12 @@ CONS( 200?, dance555, 0, 0, vt1682_exsportp, dance555, vt1682_exsport_state
// manual explicitly states it has NTSC output only (unit can be connected to a TV) and both Ranning Horse + Explosion (Bomberman) are the NTSC versions
// has 21.477 Mhz XTAL
CONS( 200?, njp60in1, 0, 0, vt1682_lxts3, njp60in1, vt1682_lxts3_state, njp60in1_init, "<unknown>", "NJ Pocket 60-in-1 handheld 'X zero' (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // RNG + linescroll issues
CONS( 200?, njp60in1, 0, 0, vt1682_lxts3, njp60in1, vt1682_lxts3_state, njp60in1_init, "<unknown>", "NJ Pocket 60-in-1 handheld 'X zero' (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // RNG + linescroll issues
// this appears to be related to the NJ Pocket, claims 101-in-1 but has some duplicates.
// Like the 'Wow Wireless gaming' it incorrectly mixes the PAL version of 'Ranning Horse' with the NTSC version of 'Bomberman', it has no TV output.
// has 26.6017 Mhz (6xPAL) XTAL
CONS( 200?, unk1682, 0, 0, vt1682_unk1682, lxts3, vt1682_lxts3_state, unk1682_init, "<unknown>", "unknown VT1682-based 101-in-1 handheld (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // RNG + linescroll issues
CONS( 200?, unk1682, 0, 0, vt1682_unk1682, lxts3, vt1682_lxts3_state, unk1682_init, "<unknown>", "unknown VT1682-based 101-in-1 handheld (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // RNG + linescroll issues
CONS( 2010, lxts3, 0, 0, vt1682_lxts3, lxts3, vt1682_lxts3_state, regular_init, "Lexibook", "Toy Story 3 (Lexibook)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // RNG + linescroll issues
CONS( 2010, lxts3, 0, 0, vt1682_lxts3, lxts3, vt1682_lxts3_state, regular_init, "Lexibook", "Toy Story 3 (Lexibook)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // RNG + linescroll issues

2
src/mame/drivers/williams.cpp
View File

@ -2345,7 +2345,7 @@ Stargate ROM labels are in this format:
+--------------------+
Solid Yellow (Black print) 3002-1 through 3002-12 - ROM type A, 2532
Solid Yellow (Green print) 3002-13 through 3002-24 - ROM type B, 2732
Solid Yellow (Green print) 3002-13 through 3002-24 - ROM type B, 2732
| Black print | Green print
Part Number | ROM# Number | ROM# Number

10
src/mame/drivers/wswan.cpp
View File

@ -27,8 +27,8 @@
interesting issues:
- mirror of smaller <64KBYTE/512kbit SRAM sizes
- banking when using 1M or 2M sram sizes
- The units likely came with the name "WONDERSWAN" configured in the
internal EEPOM
- The units likely came with the name "WONDERSWAN" configured in the
internal EEPOM
***************************************************************************/
@ -90,8 +90,8 @@ protected:
static const u8 WSWAN_INT_VBL = 6;
static const u8 WSWAN_INT_HBLTMR = 7;
static const u32 INTERNAL_EEPROM_SIZE = 1024; // 16kbit on WSC
static const u32 INTERNAL_EEPROM_SIZE_WS = 64; // 1kbit on WS
static const u32 INTERNAL_EEPROM_SIZE = 1024; // 16kbit on WSC
static const u32 INTERNAL_EEPROM_SIZE_WS = 64; // 1kbit on WS
enum enum_system { TYPE_WSWAN=0, TYPE_WSC };
@ -727,7 +727,7 @@ void wswan_state::port_w(offs_t offset, u8 data)
// Bit 4-7 - Unknown
m_sound->port_w(offset, data);
break;
case 0x9E: // WSC volume setting (0, 1, 2, 3)
case 0x9E: // WSC volume setting (0, 1, 2, 3)
break;
case 0xa0: // Hardware type/system control
// Bit 0 - Enable cartridge slot and/or disable bios

2
src/mame/drivers/zeebo_qualcomm_adreno130.cpp
View File

@ -120,7 +120,7 @@ uint32_t zeebo_game_state::screen_update(screen_device &screen, bitmap_rgb32 &bi
void zeebo_game_state::zeebo(machine_config &config)
{
ARM11(config, m_maincpu, 528000000); // 528 MHz ARM11 based SoC
ARM11(config, m_maincpu, 528000000); // 528 MHz ARM11 based SoC
m_maincpu->set_addrmap(AS_PROGRAM, &zeebo_game_state::zeebo_arm11_map);
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));

2
src/mame/includes/p2000t.h
View File

@ -54,7 +54,7 @@ protected:
required_device<cpu_device> m_maincpu;
required_device<speaker_sound_device> m_speaker;
required_device<mdcr_device> m_mdcr;
required_device<mdcr_device> m_mdcr;
private:
required_ioport_array<10> m_keyboard;

8
src/mame/layout/v4dbltak.lay
View File

@ -7,7 +7,7 @@ license:CC0
<!-- this adds support for combining outputs to make an aggregated output--><script>
local layout = {}
local ledlamps = { { 88, 89, 90, 91, 92, 93, 94, -1 },
local ledlamps = { { 88, 89, 90, 91, 92, 93, 94, -1 },
{ 80, 81, 82, 83, 84, 85, 86, 87 },
{ 72, 73, 74, 75, 76, 77, 78, -1 },
{ 64, 65, 66, 67, 68, 69, 70, -1 } }
@ -125,7 +125,7 @@ return layout, "v4dbltak"
<bounds x="0" y="0.1" width="1" height="0.8" />
</text>
</element>
<element name="SELECT">
<rect state="1">
<color red="1.0" green="0.5" blue="0.0" />
@ -138,7 +138,7 @@ return layout, "v4dbltak"
<bounds x="0" y="0.1" width="1" height="0.8" />
</text>
</element>
<element name="DEAL">
<rect state="1">
<color red="1.0" green="0.5" blue="0.0" />
@ -158,7 +158,7 @@ return layout, "v4dbltak"
<bounds x="0" y="0.1" width="1" height="0.8" />
</text>
</element>
<view name="Monitor and Lamps">
<screen index="0">
<bounds x="0" y="0" width="504" height="296" />

8
src/mame/machine/abc1600mac.cpp
View File

@ -440,7 +440,7 @@ void abc1600_mac_device::task_w(offs_t offset, uint8_t data)
m_task = data ^ 0xff;
if (LOG) logerror("%s TASK %05x:%02x (TASK %u BOOTE %u MAGIC %u)\n", machine().describe_context(), offset, data,
if (LOG) logerror("%s TASK %05x:%02x (TASK %u BOOTE %u MAGIC %u)\n", machine().describe_context(), offset, data,
get_current_task(offset), BOOTE, MAGIC);
}
@ -498,7 +498,7 @@ void abc1600_mac_device::segment_w(offs_t offset, uint8_t data)
m_segment_ram[sega] = data & 0x7f;
if (LOG) logerror("%s %05x:%02x TASK %u SEGMENT %u MEM %05x-%05x\n", machine().describe_context(), offset, data,
if (LOG) logerror("%s %05x:%02x TASK %u SEGMENT %u MEM %05x-%05x\n", machine().describe_context(), offset, data,
get_current_task(offset), sega & 0x1f, (sega & 0x1f) * 0x8000, ((sega & 0x1f) * 0x8000) + 0x7fff);
}
@ -604,8 +604,8 @@ void abc1600_mac_device::page_w(offs_t offset, uint8_t data)
m_page_ram[pga] = ((data & 0xc3) << 8) | (m_page_ram[pga] & 0xff);
}
if (LOG) logerror("%s %05x:%02x TASK %u SEGMENT %u PAGE %u MEM %05x-%05x %06x\n", machine().describe_context(), offset, data,
get_current_task(offset), sega & 0x1f, ((offset >> 11) & 0x0f), ((sega & 0x1f) * 0x8000) + ((offset >> 11) & 0x0f) * 0x800,
if (LOG) logerror("%s %05x:%02x TASK %u SEGMENT %u PAGE %u MEM %05x-%05x %06x\n", machine().describe_context(), offset, data,
get_current_task(offset), sega & 0x1f, ((offset >> 11) & 0x0f), ((sega & 0x1f) * 0x8000) + ((offset >> 11) & 0x0f) * 0x800,
((sega & 0x1f) * 0x8000) + (((offset >> 11) & 0x0f) * 0x800) + 0x7ff, (m_page_ram[pga] & 0x3ff) << 11);
}

2
src/mame/machine/bacta_datalogger.cpp
View File

@ -53,7 +53,7 @@ void bacta_datalogger_device::device_reset()
int startbits = 1;
int databits = 8;
parity_t parity = device_serial_interface::PARITY_ODD;
stop_bits_t stopbits = device_serial_interface::STOP_BITS_1;
stop_bits_t stopbits = device_serial_interface::STOP_BITS_1;
set_data_frame(startbits, databits, parity, stopbits);

16
src/mame/machine/egret.cpp
View File

@ -113,14 +113,14 @@ void egret_device::send_port(uint8_t offset, uint8_t data)
{
m_adb_dtime = (int)(machine().time().as_ticks(1000000) - last_adb_time);
/*
if (data & 0x80)
{
printf("EG ADB: 1->0 time %d\n", m_adb_dtime);
}
else
{
printf("EG ADB: 0->1 time %d\n", m_adb_dtime);
}
if (data & 0x80)
{
printf("EG ADB: 1->0 time %d\n", m_adb_dtime);
}
else
{
printf("EG ADB: 0->1 time %d\n", m_adb_dtime);
}
*/
// allow the linechange handler to override us
adb_in = (data & 0x80) ? true : false;

2
src/mame/machine/informer_207_376_kbd.cpp
View File

@ -121,7 +121,7 @@ static INPUT_PORTS_START( keyboard )
PORT_START("row_5")
PORT_BIT(0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD) /* 50 */ PORT_CODE(KEYCODE_F2) PORT_NAME("Cursor Sel Clear")
PORT_BIT(0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD) /* 51 */ PORT_CODE(KEYCODE_F1) // X + human? ATTN?
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_UNKNOWN) /* 52 */
PORT_BIT(0x0004, IP_ACTIVE_HIGH, IPT_UNKNOWN) /* 52 */
PORT_BIT(0x0008, IP_ACTIVE_HIGH, IPT_UNKNOWN) /* 53 */
PORT_BIT(0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD) /* 54 */ PORT_CODE(KEYCODE_F3) PORT_NAME("Cursor Blink Alt Cursor")
PORT_BIT(0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD) /* 55 */ PORT_CODE(KEYCODE_END) PORT_NAME("Erase EOF")

4
src/mame/machine/informer_207_376_kbd.h
View File

@ -22,8 +22,8 @@
// ======================> informer_207_376_kbd_hle_device
class informer_207_376_kbd_hle_device : public device_t,
public device_buffered_serial_interface<16>,
protected device_matrix_keyboard_interface<8>
public device_buffered_serial_interface<16>,
protected device_matrix_keyboard_interface<8>
{
public:
// construction/destruction

2
src/mame/machine/informer_213_kbd.h
View File

@ -22,7 +22,7 @@
// ======================> informer_213_kbd_hle_device
class informer_213_kbd_hle_device : public device_t,
protected device_matrix_keyboard_interface<9>
protected device_matrix_keyboard_interface<9>
{
public:
// construction/destruction

24
src/mame/machine/macadb.cpp
View File

@ -195,7 +195,7 @@ static INPUT_PORTS_START( macadb )
INPUT_PORTS_END
macadb_device::macadb_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, MACADB, tag, owner, clock),
: device_t(mconfig, MACADB, tag, owner, clock),
m_mouse0(*this, "MOUSE0"),
m_mouse1(*this, "MOUSE1"),
m_mouse2(*this, "MOUSE2"),
@ -212,7 +212,7 @@ macadb_device::macadb_device(const machine_config &mconfig, const char *tag, dev
ioport_constructor macadb_device::device_input_ports() const
{
return INPUT_PORTS_NAME(macadb);
return INPUT_PORTS_NAME(macadb);
}
void macadb_device::device_start()
@ -796,12 +796,12 @@ TIMER_CALLBACK_MEMBER(macadb_device::mac_adb_tick)
set_adb_line(CLEAR_LINE);
if (m_adb_buffer[m_adb_stream_ptr] & 0x80)
{
//printf("1 ");
//printf("1 ");
m_adb_timer->adjust(attotime::from_ticks(adb_short, adb_timebase));
}
else
{
//printf("0 ");
//printf("0 ");
m_adb_timer->adjust(attotime::from_ticks(adb_long, adb_timebase));
}
m_adb_linestate++;
@ -1499,14 +1499,14 @@ WRITE_LINE_MEMBER(macadb_device::adb_linechange_w)
int dtime = (int)(machine().time().as_ticks(adb_timebase) - m_last_adb_time);
m_last_adb_time = machine().time().as_ticks(adb_timebase);
/*if (m_adb_linestate <= 12)
{
printf("linechange: %d -> %d, time %d (state %d = %s)\n", state^1, state, dtime, m_adb_linestate, states[m_adb_linestate]);
}
else
{
printf("linechange: %d -> %d, time %d (state %d)\n", state^1, state, dtime, m_adb_linestate);
}*/
/*if (m_adb_linestate <= 12)
{
printf("linechange: %d -> %d, time %d (state %d = %s)\n", state^1, state, dtime, m_adb_linestate, states[m_adb_linestate]);
}
else
{
printf("linechange: %d -> %d, time %d (state %d)\n", state^1, state, dtime, m_adb_linestate);
}*/
if ((m_adb_direction) && (m_adb_linestate == LST_TSTOP))
{

2
src/mame/machine/macadb.h
View File

@ -47,7 +47,7 @@ public:
protected:
// device-level overrides
virtual ioport_constructor device_input_ports() const override;
virtual ioport_constructor device_input_ports() const override;
virtual void device_start() override;
virtual void device_reset() override;

50
src/mame/machine/p2000t.cpp
View File

@ -44,19 +44,19 @@
*/
uint8_t p2000t_state::p2000t_port_000f_r(offs_t offset)
{
if (m_port_101f & P2000M_101F_KEYINT)
{
return (m_keyboard[0]->read() & m_keyboard[1]->read() & m_keyboard[2]->read()
& m_keyboard[3]->read() & m_keyboard[4]->read() & m_keyboard[5]->read()
& m_keyboard[6]->read() & m_keyboard[7]->read() & m_keyboard[8]->read()
& m_keyboard[9]->read());
}
else if (offset < 10)
{
return m_keyboard[offset]->read();
}
else
return 0xff;
if (m_port_101f & P2000M_101F_KEYINT)
{
return (m_keyboard[0]->read() & m_keyboard[1]->read() & m_keyboard[2]->read()
& m_keyboard[3]->read() & m_keyboard[4]->read() & m_keyboard[5]->read()
& m_keyboard[6]->read() & m_keyboard[7]->read() & m_keyboard[8]->read()
& m_keyboard[9]->read());
}
else if (offset < 10)
{
return m_keyboard[offset]->read();
}
else
return 0xff;
}
/*
@ -75,13 +75,13 @@ uint8_t p2000t_state::p2000t_port_000f_r(offs_t offset)
*/
uint8_t p2000t_state::p2000t_port_202f_r()
{
uint8_t data = 0x00;
data |= !m_mdcr->wen() << 3;
data |= !m_mdcr->cip() << 4;
data |= !m_mdcr->bet() << 5;
data |= m_mdcr->rdc() << 6;
data |= !m_mdcr->rda() << 7;
return data;
uint8_t data = 0x00;
data |= !m_mdcr->wen() << 3;
data |= !m_mdcr->cip() << 4;
data |= !m_mdcr->bet() << 5;
data |= m_mdcr->rdc() << 6;
data |= !m_mdcr->rda() << 7;
return data;
}
@ -99,11 +99,11 @@ uint8_t p2000t_state::p2000t_port_202f_r()
*/
void p2000t_state::p2000t_port_101f_w(uint8_t data)
{
m_port_101f = data;
m_mdcr->wda(BIT(data, 0));
m_mdcr->wdc(BIT(data, 1));
m_mdcr->rev(BIT(data, 2));
m_mdcr->fwd(BIT(data, 3));
m_port_101f = data;
m_mdcr->wda(BIT(data, 0));
m_mdcr->wdc(BIT(data, 1));
m_mdcr->rev(BIT(data, 2));
m_mdcr->fwd(BIT(data, 3));
}
/*

6
src/mame/machine/p2000t_mdcr.cpp
View File

@ -87,7 +87,7 @@ void mdcr_device::device_add_mconfig(machine_config &config)
{
CASSETTE(config, m_cassette);
m_cassette->set_default_state(CASSETTE_STOPPED | CASSETTE_MOTOR_DISABLED |
CASSETTE_SPEAKER_MUTED);
CASSETTE_SPEAKER_MUTED);
m_cassette->set_interface("p2000_cass");
m_cassette->set_formats(p2000t_cassette_formats);
}
@ -199,7 +199,7 @@ bool mdcr_device::tape_start_or_end()
{
auto pos = m_cassette->get_position();
auto bet = m_cassette->motor_on() &&
(pos <= 0 || pos >= m_cassette->get_length());
(pos <= 0 || pos >= m_cassette->get_length());
// Reset phase decoder at tape start/end.
if (bet)
@ -239,7 +239,7 @@ bool mdcr_device::phase_decoder::signal(bool state, double delay)
if (state == m_last_signal)
{
if (m_needs_sync == 0 && m_current_clock > m_clock_period &&
!within_tolerance(m_current_clock, m_clock_period))
!within_tolerance(m_current_clock, m_clock_period))
{
// We might be at the last bit in a sequence, meaning we
// are only getting the reference signal for a while.

2
src/mame/video/wswan.cpp
View File

@ -10,7 +10,7 @@
TODO:
- remove the redundant parts of m_regs
- split the Color VDP from the Mono VDP
- Add support for WSC high/low contrast (register 14, bit 1)
- Add support for WSC high/low contrast (register 14, bit 1)
***************************************************************************/